drm: brainlcd: load MAC config from device tree
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70d8eee4b7
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@ -103,24 +103,14 @@ static const struct {
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{ 0x02, 1, 0 },
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{ 0xbb, 0, 0 }, /* ? */
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{ 0x14, 1, 0 }, { 0x55, 1, 0 },
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{ 0x36, 0, 0 }, /* Memory Access Control */
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{ 0x28, 1, 0 },
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{ 0x3a, 0, 0 }, /* Interface Pixel Format */
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{ 0x55, 1, 0 },
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{ 0x21, 0, 0 }, /* Display Inversion On */
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{ 0xb6, 0, 0 }, /* MCU/RGB Interface Select */
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{ 0x01, 1, 0 }, { 0x80, 1, 0 }, { 0x8f, 1, 0 },
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{ 0x44, 0, 0 }, /* Write Tear Scan Line? */
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{ 0x00, 1, 0 }, { 0x00, 1, 0 },
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{ 0x35, 0, 0 }, /* Tearing Effect Line On */
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{ 0x00, 1, 0 },
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{ 0x11, 0, 120 }, /* Sleep Out */
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{ 0x29, 0, 20 }, /* Display On */
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{ 0x2a, 0, 0 }, /* Column Address Set */
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{ 0x00, 1, 0 }, { 0x00, 1, 0 }, { 0x03, 1, 0 }, { 0x1f, 1, 0 },
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{ 0x2b, 0, 0 }, /* Page Address Set */
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{ 0x00, 1, 0 }, { 0x00, 1, 0 }, { 0x01, 1, 0 }, { 0xdf, 1, 0 },
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{ 0x2c, 0, 0 }, /* Memory Write*/
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};
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@ -262,6 +252,7 @@ static void brain_enable(struct drm_simple_display_pipe *pipe,
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struct drm_display_mode *m = &crtc_state->adjusted_mode;
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int i, ret, idx;
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u32 valid;
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u8 mac = 0;
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ili = pipe_to_brain_drm_private(pipe);
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m = &ili->pipe.crtc.state->adjusted_mode;
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@ -301,6 +292,53 @@ static void brain_enable(struct drm_simple_display_pipe *pipe,
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mdelay(lcd_regs[i].delay);
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}
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if (of_property_read_bool(ili->pdev->dev.of_node, "sharp,mac-flip-x")) {
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mac |= ILI9805_MADCTL_MX;
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}
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if (of_property_read_bool(ili->pdev->dev.of_node, "sharp,mac-flip-y")) {
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mac |= ILI9805_MADCTL_MY;
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}
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if (of_property_read_bool(ili->pdev->dev.of_node, "sharp,mac-flip-y-gs")) {
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mac |= ILI9805_MADCTL_GS;
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}
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if (of_property_read_bool(ili->pdev->dev.of_node, "sharp,mac-transpose")) {
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mac |= ILI9805_MADCTL_MV;
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}
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if (of_property_read_bool(ili->pdev->dev.of_node, "sharp,mac-bgr")) {
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mac |= ILI9805_MADCTL_BGR;
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}
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brain_write_byte(ili, 0x36, 0); /* Memory Access Control */
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brain_write_byte(ili, mac, 1);
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if (of_property_read_bool(ili->pdev->dev.of_node, "sharp,mac-inversion")) {
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brain_write_byte(ili, 0x21, 0); /* Display Inversion On */
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}
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brain_write_byte(ili, 0x11, 0); /* Sleep Out */
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mdelay(120);
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brain_write_byte(ili, 0x29, 0); /* Display On */
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mdelay(120);
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brain_write_byte(ili, 0x2a, 0); /* Column Address Set */
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brain_write_byte(ili, 0x00, 1); /* Start Column in 2 Bytes */
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brain_write_byte(ili, 0x00, 1);
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brain_write_byte(ili, (m->hdisplay & 0xff00) >> 8, 1); /* End Column in 2 Bytes */
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brain_write_byte(ili, (m->hdisplay & 0x00ff) >> 0, 1);
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brain_write_byte(ili, 0x2b, 0); /* Page Address Set */
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brain_write_byte(ili, 0x00, 1); /* Start Page in 2 Bytes */
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brain_write_byte(ili, 0x00, 1);
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brain_write_byte(ili, (m->vdisplay & 0xff00) >> 8, 1); /* End Page in 2 Bytes */
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brain_write_byte(ili, (m->vdisplay & 0x00ff) >> 0, 1);
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brain_write_byte(ili, 0x2c, 0); /* Memory Write */
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writel(CTRL1_SET_BYTE_PACKAGING(0xf), ili->base + LCDC_CTRL1 + REG_CLR);
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writel(CTRL1_SET_BYTE_PACKAGING(valid), ili->base + LCDC_CTRL1 + REG_SET);
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