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drm/amd/display: use min disp and dpp clk debug option for dcn2
This allows to set a minimum display and dpp clock on dcn2+ HW by adjusting clocks used for dml calculations. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -344,6 +344,7 @@ struct dc_debug_options {
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bool disable_pplib_wm_range;
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enum wm_report_mode pplib_wm_report_mode;
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unsigned int min_disp_clk_khz;
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unsigned int min_dpp_clk_khz;
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int sr_exit_time_dpm0_ns;
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int sr_enter_plus_exit_time_dpm0_ns;
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int sr_exit_time_ns;
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@ -2170,10 +2170,6 @@ bool dcn20_fast_validate_bw(
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}
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if (force_split && context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] == 1)
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context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] /= 2;
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if (dc->config.forced_clocks == true) {
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context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] =
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context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
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}
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if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
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hsplit_pipe = find_idle_secondary_pipe(&context->res_ctx, dc->res_pool, pipe);
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ASSERT(hsplit_pipe);
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@ -2293,6 +2289,10 @@ void dcn20_calculate_wm(
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pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
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pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
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}
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if (dc->debug.min_disp_clk_khz > pipes[pipe_cnt].clks_cfg.dispclk_mhz * 1000)
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pipes[pipe_cnt].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
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if (dc->debug.min_dpp_clk_khz > pipes[pipe_cnt].clks_cfg.dppclk_mhz * 1000)
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pipes[pipe_cnt].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
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pipe_cnt++;
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}
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