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i.MX arm64 device tree update for 5.4: 

- New board support: i.MX8MQ Nitrogen8m, Hummingboard Pulse,
    PICO-PI-IMX8M, i.MX8QXP AI_ML, and LS1046A FRWY board.
  - Add gpio-ranges for GPIO devices on i.MX8MQ and i.MX8MM.
  - Update OPP table according to latest data sheet and add opp-suspend
    to OPP table for i.MX8MQ and i.MX8MM.
  - Add IDEL states for i.MX8MM SoC.
  - Correct I2C clock divider for Layerscape SoCs.
  - Add series alias and LPUART baud clock for i.MX8QXP SoC.
  - Add MIPI D-PHY device for i.MX8MQ and enable it on imx8mq-librem5
    board.
  - Enable USB1 and Type-C support for i.MX8MM EVK board.
  - Add Thermal Monitor Unit support for LS1028A SoC.
  - Misc small update and correction on Layerscape and i.MX8 support.
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Merge tag 'imx-dt64-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt

i.MX arm64 device tree update for 5.4:
 - New board support: i.MX8MQ Nitrogen8m, Hummingboard Pulse,
   PICO-PI-IMX8M, i.MX8QXP AI_ML, and LS1046A FRWY board.
 - Add gpio-ranges for GPIO devices on i.MX8MQ and i.MX8MM.
 - Update OPP table according to latest data sheet and add opp-suspend
   to OPP table for i.MX8MQ and i.MX8MM.
 - Add IDEL states for i.MX8MM SoC.
 - Correct I2C clock divider for Layerscape SoCs.
 - Add series alias and LPUART baud clock for i.MX8QXP SoC.
 - Add MIPI D-PHY device for i.MX8MQ and enable it on imx8mq-librem5
   board.
 - Enable USB1 and Type-C support for i.MX8MM EVK board.
 - Add Thermal Monitor Unit support for LS1028A SoC.
 - Misc small update and correction on Layerscape and i.MX8 support.

* tag 'imx-dt64-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (41 commits)
  arm64: dts: imx8mq: Add mux controller to iomuxc_gpr
  arm64: dts: fsl: add support for Hummingboard Pulse
  arm64: dts: ls1088a: update gpio compatible
  arm64: dts: imx: Add i.mx8mq nitrogen8m basic dts support
  arm64: dts: ls1088a-qds: Add the spi-flash nodes under the DSPI controller
  arm64: dts: ls1088a: Add the DSPI controller node
  arm64: dts: imx8mm: Enable cpu-idle driver
  arm64: dts: ls1028a: Add esdhc node in dts
  arm64: dts: ls1028a: Add properties node for Display output pixel clock
  arm64: dts: lx2160a: Fix incorrect I2C clock divider
  arm64: dts: ls1028a: Fix incorrect I2C clock divider
  arm64: dts: ls1012a: Fix incorrect I2C clock divider
  arm64: dts: ls1088a: Fix incorrect I2C clock divider
  arm64: dts: ls1028a: fix gpio nodes
  arm64: dts: ls1028a: Add Thermal Monitor Unit node
  arm64: dts: imx8mq-evk: Unbypass audio_pll1
  arm64: dts: imx8mm: Add opp-suspend property to OPP table
  arm64: dts: imx8mq: Add opp-suspend property to OPP table
  arm64: dts: ls1088a: Revise gpio registers to little-endian
  arm64: dts: add the console node for DPAA2 platforms
  ...

Link: https://lore.kernel.org/r/20190825153237.28829-6-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2019-09-03 16:10:52 +02:00
parent a0a4c25fba 215701807e
commit e8e39a2026
22 changed files with 2241 additions and 84 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
arch/arm64/boot/dts/freescale/Makefile
View File

@ -8,6 +8,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-frwy.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-qds.dtb
@ -23,7 +24,11 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-hummingboard-pulse.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-nitrogen.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-pico-pi.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb

4
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
View File

@ -323,7 +323,7 @@
#size-cells = <0>;
reg = <0x0 0x2180000 0x0 0x10000>;
interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 0>;
clocks = <&clockgen 4 3>;
status = "disabled";
};
@ -333,7 +333,7 @@
#size-cells = <0>;
reg = <0x0 0x2190000 0x0 0x10000>;
interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 0>;
clocks = <&clockgen 4 3>;
status = "disabled";
};

8
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
View File

@ -95,6 +95,14 @@
status = "okay";
};
&esdhc {
status = "okay";
};
&esdhc1 {
status = "okay";
};
&i2c0 {
status = "okay";

13
arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
View File

@ -83,6 +83,19 @@
};
};
&esdhc {
sd-uhs-sdr104;
sd-uhs-sdr50;
sd-uhs-sdr25;
sd-uhs-sdr12;
status = "okay";
};
&esdhc1 {
mmc-hs200-1_8v;
status = "okay";
};
&i2c0 {
status = "okay";

151
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
View File

@ -29,6 +29,7 @@
clocks = <&clockgen 1 0>;
next-level-cache = <&l2>;
cpu-idle-states = <&CPU_PW20>;
#cooling-cells = <2>;
};
cpu1: cpu@1 {
@ -39,6 +40,7 @@
clocks = <&clockgen 1 0>;
next-level-cache = <&l2>;
cpu-idle-states = <&CPU_PW20>;
#cooling-cells = <2>;
};
l2: l2-cache {
@ -70,11 +72,18 @@
clock-output-names = "sysclk";
};
dpclk: clock-dp {
osc_27m: clock-osc-27m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
clock-output-names= "dpclk";
clock-output-names = "phy_27m";
};
dpclk: clock-controller@f1f0000 {
compatible = "fsl,ls1028a-plldig";
reg = <0x0 0xf1f0000 0x0 0xffff>;
#clock-cells = <1>;
clocks = <&osc_27m>;
};
aclk: clock-axi {
@ -171,7 +180,7 @@
#size-cells = <0>;
reg = <0x0 0x2000000 0x0 0x10000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 1>;
clocks = <&clockgen 4 3>;
status = "disabled";
};
@ -181,7 +190,7 @@
#size-cells = <0>;
reg = <0x0 0x2010000 0x0 0x10000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 1>;
clocks = <&clockgen 4 3>;
status = "disabled";
};
@ -191,7 +200,7 @@
#size-cells = <0>;
reg = <0x0 0x2020000 0x0 0x10000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 1>;
clocks = <&clockgen 4 3>;
status = "disabled";
};
@ -201,7 +210,7 @@
#size-cells = <0>;
reg = <0x0 0x2030000 0x0 0x10000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 1>;
clocks = <&clockgen 4 3>;
status = "disabled";
};
@ -211,7 +220,7 @@
#size-cells = <0>;
reg = <0x0 0x2040000 0x0 0x10000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 1>;
clocks = <&clockgen 4 3>;
status = "disabled";
};
@ -221,7 +230,7 @@
#size-cells = <0>;
reg = <0x0 0x2050000 0x0 0x10000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 1>;
clocks = <&clockgen 4 3>;
status = "disabled";
};
@ -231,7 +240,7 @@
#size-cells = <0>;
reg = <0x0 0x2060000 0x0 0x10000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 1>;
clocks = <&clockgen 4 3>;
status = "disabled";
};
@ -241,7 +250,34 @@
#size-cells = <0>;
reg = <0x0 0x2070000 0x0 0x10000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 1>;
clocks = <&clockgen 4 3>;
status = "disabled";
};
esdhc: mmc@2140000 {
compatible = "fsl,ls1028a-esdhc", "fsl,esdhc";
reg = <0x0 0x2140000 0x0 0x10000>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <0>; /* fixed up by bootloader */
clocks = <&clockgen 2 1>;
voltage-ranges = <1800 1800 3300 3300>;
sdhci,auto-cmd12;
little-endian;
bus-width = <4>;
status = "disabled";
};
esdhc1: mmc@2150000 {
compatible = "fsl,ls1028a-esdhc", "fsl,esdhc";
reg = <0x0 0x2150000 0x0 0x10000>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <0>; /* fixed up by bootloader */
clocks = <&clockgen 2 1>;
voltage-ranges = <1800 1800 3300 3300>;
sdhci,auto-cmd12;
broken-cd;
little-endian;
bus-width = <4>;
status = "disabled";
};
@ -277,33 +313,36 @@
};
gpio1: gpio@2300000 {
compatible = "fsl,qoriq-gpio";
compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
reg = <0x0 0x2300000 0x0 0x10000>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
little-endian;
};
gpio2: gpio@2310000 {
compatible = "fsl,qoriq-gpio";
compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
reg = <0x0 0x2310000 0x0 0x10000>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
little-endian;
};
gpio3: gpio@2320000 {
compatible = "fsl,qoriq-gpio";
compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
reg = <0x0 0x2320000 0x0 0x10000>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
little-endian;
};
usb0: usb@3100000 {
@ -503,6 +542,89 @@
status = "disabled";
};
tmu: tmu@1f00000 {
compatible = "fsl,qoriq-tmu";
reg = <0x0 0x1f80000 0x0 0x10000>;
interrupts = <0 23 0x4>;
fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
fsl,tmu-calibration = <0x00000000 0x00000024
0x00000001 0x0000002b
0x00000002 0x00000031
0x00000003 0x00000038
0x00000004 0x0000003f
0x00000005 0x00000045
0x00000006 0x0000004c
0x00000007 0x00000053
0x00000008 0x00000059
0x00000009 0x00000060
0x0000000a 0x00000066
0x0000000b 0x0000006d
0x00010000 0x0000001c
0x00010001 0x00000024
0x00010002 0x0000002c
0x00010003 0x00000035
0x00010004 0x0000003d
0x00010005 0x00000045
0x00010006 0x0000004d
0x00010007 0x00000045
0x00010008 0x0000005e
0x00010009 0x00000066
0x0001000a 0x0000006e
0x00020000 0x00000018
0x00020001 0x00000022
0x00020002 0x0000002d
0x00020003 0x00000038
0x00020004 0x00000043
0x00020005 0x0000004d
0x00020006 0x00000058
0x00020007 0x00000063
0x00020008 0x0000006e
0x00030000 0x00000010
0x00030001 0x0000001c
0x00030002 0x00000029
0x00030003 0x00000036
0x00030004 0x00000042
0x00030005 0x0000004f
0x00030006 0x0000005b
0x00030007 0x00000068>;
little-endian;
#thermal-sensor-cells = <1>;
};
thermal-zones {
core-cluster {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 0>;
trips {
core_cluster_alert: core-cluster-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
core_cluster_crit: core-cluster-crit {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&core_cluster_alert>;
cooling-device =
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
pcie@1f0000000 { /* Integrated Endpoint Root Complex */
compatible = "pci-host-ecam-generic";
reg = <0x01 0xf0000000 0x0 0x100000>;
@ -551,9 +673,10 @@
interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
<0 223 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "DE", "SE";
clocks = <&dpclk>, <&aclk>, <&aclk>, <&pclk>;
clocks = <&dpclk 0>, <&aclk>, <&aclk>, <&pclk>;
clock-names = "pxlclk", "mclk", "aclk", "pclk";
arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
arm,malidp-arqos-value = <0xd000d000>;
port {
dp0_out: endpoint {

155
arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy.dts Normal file
View File

@ -0,0 +1,155 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
*
* Copyright 2019 NXP.
*
*/
/dts-v1/;
#include "fsl-ls1046a.dtsi"
/ {
model = "LS1046A FRWY Board";
compatible = "fsl,ls1046a-frwy", "fsl,ls1046a";
aliases {
serial0 = &duart0;
serial1 = &duart1;
serial2 = &duart2;
serial3 = &duart3;
};
chosen {
stdout-path = "serial0:115200n8";
};
sb_3v3: regulator-sb3v3 {
compatible = "regulator-fixed";
regulator-name = "LT8642SEV-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
&duart0 {
status = "okay";
};
&duart1 {
status = "okay";
};
&duart2 {
status = "okay";
};
&duart3 {
status = "okay";
};
&i2c0 {
status = "okay";
i2c-mux@77 {
compatible = "nxp,pca9546";
reg = <0x77>;
#address-cells = <1>;
#size-cells = <0>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
power-monitor@40 {
compatible = "ti,ina220";
reg = <0x40>;
shunt-resistor = <1000>;
};
temperature-sensor@4c {
compatible = "nxp,sa56004";
reg = <0x4c>;
vcc-supply = <&sb_3v3>;
};
rtc@51 {
compatible = "nxp,pcf2129";
reg = <0x51>;
};
eeprom@52 {
compatible = "atmel,24c512";
reg = <0x52>;
};
eeprom@53 {
compatible = "atmel,24c512";
reg = <0x53>;
};
};
};
};
&ifc {
#address-cells = <2>;
#size-cells = <1>;
/* NAND Flash */
ranges = <0x0 0x0 0x0 0x7e800000 0x00010000>;
status = "okay";
nand@0,0 {
compatible = "fsl,ifc-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0 0x0 0x10000>;
};
};
#include "fsl-ls1046-post.dtsi"
&fman0 {
ethernet@e0000 {
phy-handle = <&qsgmii_phy4>;
phy-connection-type = "qsgmii";
};
ethernet@e8000 {
phy-handle = <&qsgmii_phy2>;
phy-connection-type = "qsgmii";
};
ethernet@ea000 {
phy-handle = <&qsgmii_phy1>;
phy-connection-type = "qsgmii";
};
ethernet@f2000 {
phy-handle = <&qsgmii_phy3>;
phy-connection-type = "qsgmii";
};
mdio@fd000 {
qsgmii_phy1: ethernet-phy@1c {
reg = <0x1c>;
};
qsgmii_phy2: ethernet-phy@1d {
reg = <0x1d>;
};
qsgmii_phy3: ethernet-phy@1e {
reg = <0x1e>;
};
qsgmii_phy4: ethernet-phy@1f {
reg = <0x1f>;
};
};
};

33
arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts
View File

@ -17,6 +17,39 @@
compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
};
&dspi {
bus-num = <0>;
status = "okay";
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <1000000>;
};
flash@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-cpol;
spi-cpha;
spi-max-frequency = <3500000>;
reg = <1>;
};
flash@2 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-cpol;
spi-cpha;
spi-max-frequency = <3500000>;
reg = <2>;
};
};
&i2c0 {
status = "okay";

38
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
View File

@ -252,6 +252,19 @@
#thermal-sensor-cells = <1>;
};
dspi: spi@2100000 {
compatible = "fsl,ls1088a-dspi",
"fsl,ls1021a-v1.0-dspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2100000 0x0 0x10000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "dspi";
clocks = <&clockgen 4 1>;
spi-num-chipselects = <6>;
status = "disabled";
};
duart0: serial@21c0500 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x0 0x21c0500 0x0 0x100>;
@ -269,9 +282,10 @@
};
gpio0: gpio@2300000 {
compatible = "fsl,qoriq-gpio";
compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2300000 0x0 0x10000>;
interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
little-endian;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@ -279,9 +293,10 @@
};
gpio1: gpio@2310000 {
compatible = "fsl,qoriq-gpio";
compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2310000 0x0 0x10000>;
interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
little-endian;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@ -289,9 +304,10 @@
};
gpio2: gpio@2320000 {
compatible = "fsl,qoriq-gpio";
compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2320000 0x0 0x10000>;
interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
little-endian;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@ -299,9 +315,10 @@
};
gpio3: gpio@2330000 {
compatible = "fsl,qoriq-gpio";
compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2330000 0x0 0x10000>;
interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
little-endian;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@ -324,7 +341,7 @@
#size-cells = <0>;
reg = <0x0 0x2000000 0x0 0x10000>;
interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 3>;
clocks = <&clockgen 4 7>;
status = "disabled";
};
@ -334,7 +351,7 @@
#size-cells = <0>;
reg = <0x0 0x2010000 0x0 0x10000>;
interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 3>;
clocks = <&clockgen 4 7>;
status = "disabled";
};
@ -344,7 +361,7 @@
#size-cells = <0>;
reg = <0x0 0x2020000 0x0 0x10000>;
interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 3>;
clocks = <&clockgen 4 7>;
status = "disabled";
};
@ -354,7 +371,7 @@
#size-cells = <0>;
reg = <0x0 0x2030000 0x0 0x10000>;
interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 3>;
clocks = <&clockgen 4 7>;
status = "disabled";
};
@ -609,6 +626,11 @@
<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
};
console@8340020 {
compatible = "fsl,dpaa2-console";
reg = <0x00000000 0x08340020 0 0x2>;
};
ptp-timer@8b95000 {
compatible = "fsl,dpaa2-ptp";
reg = <0x0 0x8b95000 0x0 0x100>;

5
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
View File

@ -321,6 +321,11 @@
};
};
console@8340020 {
compatible = "fsl,dpaa2-console";
reg = <0x00000000 0x08340020 0 0x2>;
};
ptp-timer@8b95000 {
compatible = "fsl,dpaa2-ptp";
reg = <0x0 0x8b95000 0x0 0x100>;

21
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
View File

@ -485,7 +485,7 @@
reg = <0x0 0x2000000 0x0 0x10000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
clocks = <&clockgen 4 7>;
clocks = <&clockgen 4 15>;
scl-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
@ -497,7 +497,7 @@
reg = <0x0 0x2010000 0x0 0x10000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
clocks = <&clockgen 4 7>;
clocks = <&clockgen 4 15>;
status = "disabled";
};
@ -508,7 +508,7 @@
reg = <0x0 0x2020000 0x0 0x10000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
clocks = <&clockgen 4 7>;
clocks = <&clockgen 4 15>;
status = "disabled";
};
@ -519,7 +519,7 @@
reg = <0x0 0x2030000 0x0 0x10000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
clocks = <&clockgen 4 7>;
clocks = <&clockgen 4 15>;
status = "disabled";
};
@ -530,7 +530,7 @@
reg = <0x0 0x2040000 0x0 0x10000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
clocks = <&clockgen 4 7>;
clocks = <&clockgen 4 15>;
scl-gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
@ -542,7 +542,7 @@
reg = <0x0 0x2050000 0x0 0x10000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
clocks = <&clockgen 4 7>;
clocks = <&clockgen 4 15>;
status = "disabled";
};
@ -553,7 +553,7 @@
reg = <0x0 0x2060000 0x0 0x10000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
clocks = <&clockgen 4 7>;
clocks = <&clockgen 4 15>;
status = "disabled";
};
@ -564,7 +564,7 @@
reg = <0x0 0x2070000 0x0 0x10000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
clocks = <&clockgen 4 7>;
clocks = <&clockgen 4 15>;
status = "disabled";
};
@ -848,6 +848,11 @@
dma-coherent;
};
console@8340020 {
compatible = "fsl,dpaa2-console";
reg = <0x00000000 0x08340020 0 0x2>;
};
ptp-timer@8b95000 {
compatible = "fsl,dpaa2-ptp";
reg = <0x0 0x8b95000 0x0 0x100>;

68
arch/arm64/boot/dts/freescale/imx8mm-evk.dts
View File

@ -5,6 +5,7 @@
/dts-v1/;
#include <dt-bindings/usb/pd.h>
#include "imx8mm.dtsi"
/ {
@ -89,9 +90,6 @@
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
at803x,led-act-blind-workaround;
at803x,eee-okay;
at803x,vddio-1p8v;
};
};
};
@ -115,6 +113,21 @@
status = "okay";
};
&usbotg1 {
dr_mode = "otg";
hnp-disable;
srp-disable;
adp-disable;
usb-role-switch;
status = "okay";
port {
usb1_drd_sw: endpoint {
remote-endpoint = <&typec1_dr_sw>;
};
};
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
@ -257,6 +270,42 @@
};
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
ptn5110: tcpc@50 {
compatible = "nxp,ptn5110";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_typec1>;
reg = <0x50>;
interrupt-parent = <&gpio2>;
interrupts = <11 8>;
status = "okay";
port {
typec1_dr_sw: endpoint {
remote-endpoint = <&usb1_drd_sw>;
};
};
typec1_con: connector {
compatible = "usb-c-connector";
label = "USB-C";
power-role = "dual";
data-role = "dual";
try-power-role = "sink";
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
PDO_VAR(5000, 20000, 3000)>;
op-sink-microwatt = <15000000>;
self-powered;
};
};
};
&iomuxc {
pinctrl-names = "default";
@ -299,6 +348,13 @@
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
>;
};
pinctrl_pmic: pmicirq {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
@ -320,6 +376,12 @@
>;
};
pinctrl_typec1: typec1grp {
fsl,pins = <
MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140

61
arch/arm64/boot/dts/freescale/imx8mm.dtsi
View File

@ -44,6 +44,19 @@
#address-cells = <1>;
#size-cells = <0>;
idle-states {
entry-method = "psci";
cpu_pd_wait: cpu-pd-wait {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0010033>;
local-timer-stop;
entry-latency-us = <1000>;
exit-latency-us = <700>;
min-residency-us = <2700>;
};
};
A53_0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
@ -55,6 +68,7 @@
operating-points-v2 = <&a53_opp_table>;
nvmem-cells = <&cpu_speed_grade>;
nvmem-cell-names = "speed_grade";
cpu-idle-states = <&cpu_pd_wait>;
};
A53_1: cpu@1 {
@ -66,6 +80,7 @@
enable-method = "psci";
next-level-cache = <&A53_L2>;
operating-points-v2 = <&a53_opp_table>;
cpu-idle-states = <&cpu_pd_wait>;
};
A53_2: cpu@2 {
@ -77,6 +92,7 @@
enable-method = "psci";
next-level-cache = <&A53_L2>;
operating-points-v2 = <&a53_opp_table>;
cpu-idle-states = <&cpu_pd_wait>;
};
A53_3: cpu@3 {
@ -88,6 +104,7 @@
enable-method = "psci";
next-level-cache = <&A53_L2>;
operating-points-v2 = <&a53_opp_table>;
cpu-idle-states = <&cpu_pd_wait>;
};
A53_L2: l2-cache0 {
@ -104,6 +121,7 @@
opp-microvolt = <850000>;
opp-supported-hw = <0xe>, <0x7>;
clock-latency-ns = <150000>;
opp-suspend;
};
opp-1600000000 {
@ -111,14 +129,15 @@
opp-microvolt = <900000>;
opp-supported-hw = <0xc>, <0x7>;
clock-latency-ns = <150000>;
opp-suspend;
};
opp-1800000000 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <1000000>;
/* Consumer only but rely on speed grading */
opp-supported-hw = <0x8>, <0x7>;
opp-supported-hw = <0x8>, <0x3>;
clock-latency-ns = <150000>;
opp-suspend;
};
};
@ -295,6 +314,7 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 10 30>;
};
gpio2: gpio@30210000 {
@ -307,6 +327,7 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 40 21>;
};
gpio3: gpio@30220000 {
@ -319,6 +340,7 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 61 26>;
};
gpio4: gpio@30230000 {
@ -331,6 +353,7 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 87 32>;
};
gpio5: gpio@30240000 {
@ -343,6 +366,7 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 119 30>;
};
wdog1: watchdog@30280000 {
@ -451,10 +475,22 @@
<&clk_ext3>, <&clk_ext4>;
clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
"clk_ext3", "clk_ext4";
assigned-clocks = <&clk IMX8MM_CLK_NOC>,
<&clk IMX8MM_CLK_AUDIO_AHB>,
<&clk IMX8MM_CLK_IPG_AUDIO_ROOT>,
<&clk IMX8MM_SYS_PLL3>,
<&clk IMX8MM_VIDEO_PLL1>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL3_OUT>,
<&clk IMX8MM_SYS_PLL1_800M>;
assigned-clock-rates = <0>,
<400000000>,
<400000000>,
<750000000>,
<594000000>;
};
src: reset-controller@30390000 {
compatible = "fsl,imx8mm-src", "syscon";
compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon";
reg = <0x30390000 0x10000>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
#reset-cells = <1>;
@ -743,10 +779,8 @@
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
clock-names = "usb1_ctrl_root_clk";
assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>,
<&clk IMX8MM_CLK_USB_CORE_REF>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>,
<&clk IMX8MM_SYS_PLL1_100M>;
assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
fsl,usbphy = <&usbphynop1>;
fsl,usbmisc = <&usbmisc1 0>;
status = "disabled";
@ -764,10 +798,8 @@
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
clock-names = "usb1_ctrl_root_clk";
assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>,
<&clk IMX8MM_CLK_USB_CORE_REF>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>,
<&clk IMX8MM_SYS_PLL1_100M>;
assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
fsl,usbphy = <&usbphynop2>;
fsl,usbmisc = <&usbmisc2 0>;
status = "disabled";
@ -818,5 +850,12 @@
interrupt-controller;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
ddr-pmu@3d800000 {
compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu";
reg = <0x3d800000 0x400000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
};
};
};

6
arch/arm64/boot/dts/freescale/imx8mq-evk.dts
View File

@ -118,9 +118,9 @@
&sai2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai2>;
assigned-clocks = <&clk IMX8MQ_CLK_SAI2>;
assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, <&clk IMX8MQ_CLK_SAI2>;
assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL1_OUT>;
assigned-clock-rates = <0>, <24576000>;
status = "okay";
};

256
arch/arm64/boot/dts/freescale/imx8mq-hummingboard-pulse.dts Normal file
View File

@ -0,0 +1,256 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2018 Jon Nettleton <jon@solid-run.com>
*/
/dts-v1/;
#include "dt-bindings/usb/pd.h"
#include "imx8mq-sr-som.dtsi"
/ {
model = "SolidRun i.MX8MQ HummingBoard Pulse";
compatible = "solidrun,hummingboard-pulse", "fsl,imx8mq";
chosen {
stdout-path = &uart1;
};
reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 13 GPIO_ACTIVE_LOW>;
};
reg_v_5v0: regulator-v-5v0 {
compatible = "regulator-fixed";
regulator-name = "v_5v0";
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
regulator-always-on;
};
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clock-frequency = <100000>;
status = "okay";
typec_ptn5100: usb-typec@50 {
compatible = "nxp,ptn5110";
reg = <0x50>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_typec>;
interrupt-parent = <&gpio1>;
interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
connector {
compatible = "usb-c-connector";
label = "USB-C";
data-role = "dual";
power-role = "dual";
try-power-role = "sink";
source-pdos = <PDO_FIXED(5000, 2000,
PDO_FIXED_USB_COMM |
PDO_FIXED_SUSPEND |
PDO_FIXED_EXTPOWER)>;
sink-pdos = <PDO_FIXED(5000, 2000,
PDO_FIXED_USB_COMM |
PDO_FIXED_SUSPEND |
PDO_FIXED_EXTPOWER)
PDO_FIXED(9000, 2000,
PDO_FIXED_USB_COMM |
PDO_FIXED_SUSPEND |
PDO_FIXED_EXTPOWER)>;
op-sink-microwatt = <9000000>;
port {
typec1_dr_sw: endpoint {
remote-endpoint = <&usb1_drd_sw>;
};
};
};
};
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clock-frequency = <100000>;
status = "okay";
rtc@69 {
compatible = "abracon,ab1805";
reg = <0x69>;
abracon,tc-diode = "schottky";
abracon,tc-resistor = <3>;
};
};
&uart2 { /* J35 header */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
assigned-clocks = <&clk IMX8MQ_CLK_UART2>;
assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
status = "okay";
};
&uart3 { /* Mikrobus */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
assigned-clocks = <&clk IMX8MQ_CLK_UART3>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
uart-has-rtscts;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
&usb_dwc3_0 {
dr_mode = "otg";
status = "okay";
port {
usb1_drd_sw: endpoint {
remote-endpoint = <&typec1_dr_sw>;
};
};
};
&usb_dwc3_1 {
dr_mode = "host";
status = "okay";
};
&usb3_phy0 {
status = "okay";
};
&usb3_phy1 {
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_hog: hoggrp {
fsl,pins = <
/* MikroBus Analog */
MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x41
/* MikroBus Reset */
MX8MQ_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x41
/*
* The following 2 pins need to be commented out and
* reconfigured to enable RTS/CTS on UART3
*/
/* MikroBus PWM */
MX8MQ_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x41
/* MikroBus INT */
MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x41
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f
MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f
>;
};
pinctrl_typec: typecgrp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x16
MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x17059
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49
MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49
MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49
/*
* These pins are by default GPIO on the Mikro Bus
* Header. To use RTS/CTS on UART3 comment them out
* of the hoggrp and enable them here
*/
/* MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x49 */
/* MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x49 */
>;
};
pinctrl_usdhc2_gpio: usdhc2grpgpio {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
>;
};
pinctrl_usdhc2_vmmc: usdhc2vmmcgpio {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x41
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
};

4
arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
View File

@ -174,6 +174,10 @@
assigned-clock-rates = <786432000>, <722534400>;
};
&dphy {
status = "okay";
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;

405
arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts Normal file
View File

@ -0,0 +1,405 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2018 Boundary Devices
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "imx8mq.dtsi"
/ {
model = "Boundary Devices i.MX8MQ Nitrogen8M";
compatible = "boundary,imx8mq-nitrogen8m", "fsl,imx8mq";
chosen {
stdout-path = "serial0:115200n8";
};
memory@40000000 {
device_type = "memory";
reg = <0x00000000 0x40000000 0 0x80000000>;
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
power {
label = "Power Button";
gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
wakeup-source;
};
};
reg_vref_0v9: regulator-vref-0v9 {
compatible = "regulator-fixed";
regulator-name = "vref-0v9";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
};
reg_vref_1v8: regulator-vref-1v8 {
compatible = "regulator-fixed";
regulator-name = "vref-1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
reg_vref_2v5: regulator-vref-2v5 {
compatible = "regulator-fixed";
regulator-name = "vref-2v5";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
};
reg_vref_3v3: regulator-vref-3v3 {
compatible = "regulator-fixed";
regulator-name = "vref-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_vref_5v: regulator-vref-5v {
compatible = "regulator-fixed";
regulator-name = "vref-5v";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <4>;
interrupts-extended = <&gpio1 11 IRQ_TYPE_LEVEL_LOW>;
};
};
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
i2cmux@70 {
compatible = "nxp,pca9546";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_pca9546>;
reg = <0x70>;
reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
#address-cells = <1>;
#size-cells = <0>;
i2c1a: i2c1@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
reg_arm_dram: regulator@60 {
compatible = "fcs,fan53555";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_arm_dram>;
reg = <0x60>;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
vsel-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
};
};
i2c1b: i2c1@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
reg_dram_1p1v: regulator@60 {
compatible = "fcs,fan53555";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_dram_1p1v>;
reg = <0x60>;
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
vsel-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>;
};
};
i2c1c: i2c1@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
reg_soc_gpu_vpu: regulator@60 {
compatible = "fcs,fan53555";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_soc_gpu_vpu>;
reg = <0x60>;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
vsel-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
};
};
i2c1d: i2c1@3 {
reg = <3>;
#address-cells = <1>;
#size-cells = <0>;
rtc@68 {
compatible = "microcrystal,rv4162";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1d_rv4162>;
reg = <0x68>;
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_LOW>;
wakeup-source;
};
};
};
};
&uart1 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
assigned-clocks = <&clk IMX8MQ_CLK_UART2>;
assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
status = "okay";
};
&usdhc1 {
bus-width = <8>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
non-removable;
vmmc-supply = <&reg_vref_1v8>;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_hog: hoggrp {
fsl,pins = <
/* J17 connector, odd */
MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x19 /* Pin 19 */
MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1 0x19 /* Pin 21 */
MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x19 /* Pin 23 */
MX8MQ_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x19 /* Pin 25 */
MX8MQ_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x19 /* Pin 27 */
MX8MQ_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x19 /* Pin 29 */
MX8MQ_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x19 /* Pin 31 */
MX8MQ_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x19 /* Pin 33 */
MX8MQ_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x19 /* Pin 35 */
MX8MQ_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x19 /* Pin 39 */
MX8MQ_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x19 /* Pin 41 */
MX8MQ_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x19 /* Pin 43 */
MX8MQ_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19 /* Pin 45 */
MX8MQ_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x19 /* Pin 47 */
MX8MQ_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 /* Pin 49 */
MX8MQ_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 /* Pin 51 */
/* J17 connector, even */
MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 /* Pin 44 */
MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19 /* Pin 48 */
MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* Pin 50 */
MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 /* Pin 54 */
MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* Pin 56 */
/* J18 connector, odd */
MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 /* Pin 41 */
MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 /* Pin 43 */
MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 /* Pin 45 */
MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x19 /* Pin 47 */
MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x19 /* Pin 49 */
MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x19 /* Pin 53 */
/* J18 connector, even */
MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x19 /* Pin 32 */
MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x19 /* Pin 36 */
MX8MQ_IOMUXC_NAND_DATA00_GPIO3_IO6 0x19 /* Pin 38 */
MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x19 /* Pin 40 */
MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x19 /* Pin 42 */
MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 /* Pin 44 */
MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x19 /* Pin 46 */
/* J13 Pin 2, WL_WAKE */
MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0xd6
/* J13 Pin 4, WL_IRQ, not needed for Silex */
MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21 0xd6
/* J13 pin 9, unused */
MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19
/* J13 Pin 41, BT_CLK_REQ */
MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0xd6
/* J13 Pin 42, BT_HOST_WAKE */
MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0xd6
/* Clock for both CSI1 and CSI2 */
MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x07
/* test points */
MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0xc1 /* TP87 */
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x59
>;
};
pinctrl_gpio_keys: gpio-keysgrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
>;
};
pinctrl_i2c1_pca9546: i2c1-pca9546grp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x49
>;
};
pinctrl_i2c1d_rv4162: i2c1d-rv4162grp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x49
>;
};
pinctrl_reg_arm_dram: reg-arm-dramgrp {
fsl,pins = <
MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x16
>;
};
pinctrl_reg_dram_1p1v: reg-dram-1p1vgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_STROBE_GPIO2_IO11 0x16
>;
};
pinctrl_reg_soc_gpu_vpu: reg-soc-gpu-vpugrp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x16
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x45
MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x45
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x45
MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x45
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
};

413
arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts Normal file
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@ -0,0 +1,413 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 Wandboard, Org.
* Copyright 2017 NXP
*
* Author: Richard Hu <hakahu@gmail.com>
*/
/dts-v1/;
#include "imx8mq.dtsi"
/ {
model = "TechNexion PICO-PI-8M";
compatible = "technexion,pico-pi-imx8m", "fsl,imx8mq";
chosen {
stdout-path = &uart1;
};
pmic_osc: clock-pmic {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "pmic_osc";
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_otg_vbus>;
compatible = "regulator-fixed";
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 14 GPIO_ACTIVE_LOW>;
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1 &pinctrl_enet_3v3>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pmic: pmic@4b {
reg = <0x4b>;
compatible = "rohm,bd71837";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
clocks = <&pmic_osc>;
clock-names = "osc";
clock-output-names = "pmic_clk";
interrupt-parent = <&gpio1>;
interrupts = <3 GPIO_ACTIVE_LOW>;
interrupt-names = "irq";
regulators {
buck1: BUCK1 {
regulator-name = "buck1";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-ramp-delay = <1250>;
rohm,dvs-run-voltage = <900000>;
rohm,dvs-idle-voltage = <850000>;
rohm,dvs-suspend-voltage = <800000>;
};
buck2: BUCK2 {
regulator-name = "buck2";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-ramp-delay = <1250>;
rohm,dvs-run-voltage = <1000000>;
rohm,dvs-idle-voltage = <900000>;
};
buck3: BUCK3 {
regulator-name = "buck3";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
rohm,dvs-run-voltage = <1000000>;
};
buck4: BUCK4 {
regulator-name = "buck4";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
rohm,dvs-run-voltage = <1000000>;
};
buck5: BUCK5 {
regulator-name = "buck5";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1350000>;
regulator-boot-on;
};
buck6: BUCK6 {
regulator-name = "buck6";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
};
buck7: BUCK7 {
regulator-name = "buck7";
regulator-min-microvolt = <1605000>;
regulator-max-microvolt = <1995000>;
regulator-boot-on;
};
buck8: BUCK8 {
regulator-name = "buck8";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
regulator-boot-on;
};
ldo1: LDO1 {
regulator-name = "ldo1";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo2: LDO2 {
regulator-name = "ldo2";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-boot-on;
regulator-always-on;
};
ldo3: LDO3 {
regulator-name = "ldo3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
};
ldo4: LDO4 {
regulator-name = "ldo4";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
};
ldo5: LDO5 {
regulator-name = "ldo5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
};
ldo6: LDO6 {
regulator-name = "ldo6";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
};
ldo7: LDO7 {
regulator-name = "ldo7";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
};
};
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
};
&uart1 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
bus-width = <4>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
status = "okay";
};
&usb3_phy0 {
status = "okay";
};
&usb3_phy1 {
status = "okay";
};
&usb_dwc3_1 {
dr_mode = "host";
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_enet_3v3: enet3v3grp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x19
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
>;
};
pinctrl_otg_vbus: otgvbusgrp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x19 /* USB OTG VBUS Enable */
>;
};
pinctrl_pmic: pmicirq {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49
MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49
MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x49
MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x49
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87
>;
};
pinctrl_usdhc2_gpio: usdhc2grpgpio {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
};

309
arch/arm64/boot/dts/freescale/imx8mq-sr-som.dtsi Normal file
View File

@ -0,0 +1,309 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2018 Jon Nettleton <jon@solid-run.com>
*/
#include "imx8mq.dtsi"
/ {
reg_vdd_3v3: regulator-vdd-3v3 {
compatible = "regulator-fixed";
regulator-always-on;
regulator-name = "vdd_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
phy-reset-duration = <2>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <4>;
};
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clock-frequency = <400000>;
status = "okay";
pmic: pmic@8 {
compatible = "fsl,pfuze100";
reg = <0x08>;
regulators {
sw1a_reg: sw1ab {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
};
sw1c_reg: sw1c {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
};
sw2_reg: sw2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
sw3a_reg: sw3ab {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
regulator-always-on;
};
sw4_reg: sw4 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
swbst_reg: swbst {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
};
snvs_reg: vsnvs {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
};
vref_reg: vrefddr {
regulator-always-on;
};
vgen1_reg: vgen1 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
};
vgen2_reg: vgen2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
regulator-always-on;
};
vgen3_reg: vgen3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen4_reg: vgen4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen5_reg: vgen5 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen6_reg: vgen6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
};
};
};
&pgc_gpu{
power-supply = <&sw1a_reg>;
};
&pgc_vpu {
power-supply = <&sw1c_reg>;
};
&qspi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi>;
status = "okay";
/* SPI flash; not assembled by default */
spi_flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
compatible = "micron,n25q256a", "jedec,spi-nor";
spi-max-frequency = <29000000>;
status = "disabled";
};
};
&uart1 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
assigned-clock-rates = <25000000>;
status = "okay";
};
&uart4 { /* ublox BT */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
assigned-clocks = <&clk IMX8MQ_CLK_UART4>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
assigned-clock-rates = <80000000>;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
>;
};
pinctrl_pcie0: pcie0grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x74
MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x16
MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x16
>;
};
pinctrl_qspi: qspigrp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX 0x49
MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX 0x49
MX8MQ_IOMUXC_SAI3_TXD_GPIO5_IO1 0x19
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
};

46
arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi
View File

@ -68,18 +68,6 @@
regulator-always-on;
};
reg_5p0_user_usb: regulator-5p0-user-usb {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_user_usb>;
vin-supply = <&reg_5p0_main>;
regulator-name = "5V_USER_USB";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 12 GPIO_ACTIVE_LOW>;
startup-delay-us = <1000>;
};
reg_usdhc2_vmmc: regulator-vsd-3v3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2>;
@ -244,6 +232,13 @@
line-name = "usb-mode1";
};
usb-pwr {
gpio-hog;
gpios = <12 GPIO_ACTIVE_LOW>;
output-high;
line-name = "usb-pwr-ctrl-en-n";
};
usb-mode2 {
gpio-hog;
gpios = <13 GPIO_ACTIVE_HIGH>;
@ -257,6 +252,17 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
ucs1002: charger@32 {
compatible = "microchip,ucs1002";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ucs1002>;
reg = <0x32>;
interrupt-parent = <&gpio3>;
interrupts = <17 IRQ_TYPE_EDGE_BOTH>,
<18 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "a_det", "alert";
};
};
&i2c2 {
@ -428,7 +434,7 @@
};
&usb3_phy0 {
vbus-supply = <&reg_5p0_user_usb>;
vbus-supply = <&ucs1002>;
status = "okay";
};
@ -532,6 +538,7 @@
fsl,pins = <
MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x6
MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x6
MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x6
MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x6
>;
};
@ -597,12 +604,6 @@
>;
};
pinctrl_reg_user_usb: reguserusbgrp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x6
>;
};
pinctrl_switch_irq: switchgrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41
@ -630,6 +631,13 @@
>;
};
pinctrl_ucs1002: ucs1002grp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x41
MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x41
>;
};
pinctrl_usbhub: usbhubgrp {
fsl,pins = <
MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x41

52
arch/arm64/boot/dts/freescale/imx8mq.dtsi
View File

@ -156,6 +156,7 @@
/* Industrial only */
opp-supported-hw = <0xf>, <0x4>;
clock-latency-ns = <150000>;
opp-suspend;
};
opp-1000000000 {
@ -164,21 +165,23 @@
/* Consumer only */
opp-supported-hw = <0xe>, <0x3>;
clock-latency-ns = <150000>;
opp-suspend;
};
opp-1300000000 {
opp-hz = /bits/ 64 <1300000000>;
opp-microvolt = <1000000>;
opp-supported-hw = <0xc>, <0x7>;
opp-supported-hw = <0xc>, <0x4>;
clock-latency-ns = <150000>;
opp-suspend;
};
opp-1500000000 {
opp-hz = /bits/ 64 <1500000000>;
opp-microvolt = <1000000>;
/* Consumer only but rely on speed grading */
opp-supported-hw = <0x8>, <0x7>;
opp-supported-hw = <0x8>, <0x3>;
clock-latency-ns = <150000>;
opp-suspend;
};
};
@ -288,6 +291,7 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 10 30>;
};
gpio2: gpio@30210000 {
@ -300,6 +304,7 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 40 21>;
};
gpio3: gpio@30220000 {
@ -312,6 +317,7 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 61 26>;
};
gpio4: gpio@30230000 {
@ -324,6 +330,7 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 87 32>;
};
gpio5: gpio@30240000 {
@ -336,12 +343,14 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 119 30>;
};
tmu: tmu@30260000 {
compatible = "fsl,imx8mq-tmu";
reg = <0x30260000 0x10000>;
interrupt = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_TMU_ROOT>;
little-endian;
fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
fsl,tmu-calibration = <0x00000000 0x00000023
@ -431,8 +440,15 @@
};
iomuxc_gpr: syscon@30340000 {
compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon";
compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr",
"syscon", "simple-mfd";
reg = <0x30340000 0x10000>;
mux: mux-controller {
compatible = "mmio-mux";
#mux-control-cells = <1>;
mux-reg-masks = <0x34 0x00000004>; /* MIPI_MUX_SEL */
};
};
ocotp: ocotp-ctrl@30350000 {
@ -727,6 +743,19 @@
status = "disabled";
};
dphy: dphy@30a00300 {
compatible = "fsl,imx8mq-mipi-dphy";
reg = <0x30a00300 0x100>;
clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
clock-names = "phy_ref";
assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>;
assigned-clock-rates = <24000000>;
#phy-cells = <0>;
power-domains = <&pgc_mipi>;
status = "disabled";
};
i2c1: i2c@30a20000 {
compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
reg = <0x30a20000 0x10000>;
@ -900,9 +929,9 @@
usb_dwc3_0: usb@38100000 {
compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
reg = <0x38100000 0x10000>;
clocks = <&clk IMX8MQ_CLK_USB_BUS>,
clocks = <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>,
<&clk IMX8MQ_CLK_USB_CORE_REF>,
<&clk IMX8MQ_CLK_USB1_CTRL_ROOT>;
<&clk IMX8MQ_CLK_32K>;
clock-names = "bus_early", "ref", "suspend";
assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
<&clk IMX8MQ_CLK_USB_CORE_REF>;
@ -932,9 +961,9 @@
usb_dwc3_1: usb@38200000 {
compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
reg = <0x38200000 0x10000>;
clocks = <&clk IMX8MQ_CLK_USB_BUS>,
clocks = <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>,
<&clk IMX8MQ_CLK_USB_CORE_REF>,
<&clk IMX8MQ_CLK_USB2_CTRL_ROOT>;
<&clk IMX8MQ_CLK_32K>;
clock-names = "bus_early", "ref", "suspend";
assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
<&clk IMX8MQ_CLK_USB_CORE_REF>;
@ -1032,5 +1061,12 @@
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
};
ddr-pmu@3d800000 {
compatible = "fsl,imx8mq-ddr-pmu", "fsl,imx8m-ddr-pmu";
reg = <0x3d800000 0x400000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
};
};
};

249
arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts Normal file
View File

@ -0,0 +1,249 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 Einfochips
* Copyright 2019 Linaro Ltd.
*/
/dts-v1/;
#include "imx8qxp.dtsi"
/ {
model = "Einfochips i.MX8QXP AI_ML";
compatible = "einfochips,imx8qxp-ai_ml", "fsl,imx8qxp";
aliases {
serial1 = &adma_lpuart1;
serial2 = &adma_lpuart2;
serial3 = &adma_lpuart3;
};
chosen {
stdout-path = &adma_lpuart2;
};
memory@80000000 {
device_type = "memory";
reg = <0x00000000 0x80000000 0 0x80000000>;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_leds>;
user-led1 {
label = "green:user1";
gpios = <&lsio_gpio4 16 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
user-led2 {
label = "green:user2";
gpios = <&lsio_gpio0 6 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "none";
};
user-led3 {
label = "green:user3";
gpios = <&lsio_gpio0 7 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc1";
default-state = "off";
};
user-led4 {
label = "green:user4";
gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>;
panic-indicator;
linux,default-trigger = "none";
};
wlan-active-led {
label = "yellow:wlan";
gpios = <&lsio_gpio4 17 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy0tx";
default-state = "off";
};
bt-active-led {
label = "blue:bt";
gpios = <&lsio_gpio4 18 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "hci0-power";
default-state = "off";
};
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wifi_reg_on>;
reset-gpios = <&lsio_gpio3 24 GPIO_ACTIVE_LOW>;
};
};
/* BT */
&adma_lpuart0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart0>;
uart-has-rtscts;
status = "okay";
};
/* LS-UART0 */
&adma_lpuart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart1>;
status = "okay";
};
/* Debug */
&adma_lpuart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart2>;
status = "okay";
};
/* PCI-E UART */
&adma_lpuart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart3>;
status = "okay";
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
};
};
/* WiFi */
&usdhc1 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
bus-width = <4>;
no-sd;
non-removable;
mmc-pwrseq = <&sdio_pwrseq>;
status = "okay";
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
};
/* SD */
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
bus-width = <4>;
cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>;
status = "okay";
};
&iomuxc {
pinctrl_fec1: fec1grp {
fsl,pins = <
IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020
IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020
IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020
IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020
IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020
IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020
IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020
IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020
IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020
IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020
IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020
IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020
IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020
>;
};
pinctrl_leds: ledsgrp{
fsl,pins = <
IMX8QXP_ESAI0_TX2_RX3_LSIO_GPIO0_IO06 0x00000021
IMX8QXP_ESAI0_TX3_RX2_LSIO_GPIO0_IO07 0x00000021
IMX8QXP_EMMC0_DATA7_LSIO_GPIO4_IO16 0x00000021
IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x00000021
IMX8QXP_EMMC0_STROBE_LSIO_GPIO4_IO17 0x00000021
IMX8QXP_EMMC0_RESET_B_LSIO_GPIO4_IO18 0x00000021
>;
};
pinctrl_lpuart0: lpuart0grp {
fsl,pins = <
IMX8QXP_UART0_RX_ADMA_UART0_RX 0X06000020
IMX8QXP_UART0_TX_ADMA_UART0_TX 0X06000020
IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B 0x06000020
IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B 0x06000020
>;
};
pinctrl_lpuart1: lpuart1grp {
fsl,pins = <
IMX8QXP_UART1_RX_ADMA_UART1_RX 0X06000020
IMX8QXP_UART1_TX_ADMA_UART1_TX 0X06000020
>;
};
pinctrl_lpuart2: lpuart2grp {
fsl,pins = <
IMX8QXP_UART2_RX_ADMA_UART2_RX 0X06000020
IMX8QXP_UART2_TX_ADMA_UART2_TX 0X06000020
>;
};
pinctrl_lpuart3: lpuart3grp {
fsl,pins = <
IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0X06000020
IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0X06000020
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000021
>;
};
pinctrl_wifi_reg_on: wifiregongrp {
fsl,pins = <
IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24 0x00000021
>;
};
};

23
arch/arm64/boot/dts/freescale/imx8qxp.dtsi
View File

@ -30,6 +30,9 @@
mmc2 = &usdhc3;
mu1 = &lsio_mu1;
serial0 = &adma_lpuart0;
serial1 = &adma_lpuart1;
serial2 = &adma_lpuart2;
serial3 = &adma_lpuart3;
};
cpus {
@ -241,8 +244,9 @@
reg = <0x5a060000 0x1000>;
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&adma_lpcg IMX_ADMA_LPCG_UART0_BAUD_CLK>;
clock-names = "ipg";
clocks = <&adma_lpcg IMX_ADMA_LPCG_UART0_IPG_CLK>,
<&adma_lpcg IMX_ADMA_LPCG_UART0_BAUD_CLK>;
clock-names = "ipg", "baud";
power-domains = <&pd IMX_SC_R_UART_0>;
status = "disabled";
};
@ -252,8 +256,9 @@
reg = <0x5a070000 0x1000>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&adma_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>;
clock-names = "ipg";
clocks = <&adma_lpcg IMX_ADMA_LPCG_UART1_IPG_CLK>,
<&adma_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>;
clock-names = "ipg", "baud";
power-domains = <&pd IMX_SC_R_UART_1>;
status = "disabled";
};
@ -263,8 +268,9 @@
reg = <0x5a080000 0x1000>;
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&adma_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK>;
clock-names = "ipg";
clocks = <&adma_lpcg IMX_ADMA_LPCG_UART2_IPG_CLK>,
<&adma_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK>;
clock-names = "ipg", "baud";
power-domains = <&pd IMX_SC_R_UART_2>;
status = "disabled";
};
@ -274,8 +280,9 @@
reg = <0x5a090000 0x1000>;
interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&adma_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK>;
clock-names = "ipg";
clocks = <&adma_lpcg IMX_ADMA_LPCG_UART3_IPG_CLK>,
<&adma_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK>;
clock-names = "ipg", "baud";
power-domains = <&pd IMX_SC_R_UART_3>;
status = "disabled";
};