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arm: imx: Add low power idle for imx6ull
Add low power idle support for i.MX6ULL. Signed-off-by: Jacky Bai <ping.bai@nxp.com>
This commit is contained in:
parent
9d8cacc997
commit
e6d26ea852
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@ -32,7 +32,8 @@ obj-$(CONFIG_SOC_IMX6SLL) += cpuidle-imx6sll.o imx6sll_low_power_idle.o
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obj-$(CONFIG_SOC_IMX6SX) += cpuidle-imx6sx.o imx6sx_low_power_idle.o
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AFLAGS_imx6sx_low_power_idle.o :=-Wa,-march=armv7-a
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AFLAGS_imx6ul_low_power_idle.o :=-Wa,-march=armv7-a
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obj-$(CONFIG_SOC_IMX6UL) += cpuidle-imx6ul.o imx6ul_low_power_idle.o
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AFLAGS_imx6ull_low_power_idle.o :=-Wa,-march=armv7-a
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obj-$(CONFIG_SOC_IMX6UL) += cpuidle-imx6ul.o imx6ul_low_power_idle.o imx6ull_low_power_idle.o
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obj-$(CONFIG_SOC_IMX7ULP) += cpuidle-imx7ulp.o
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AFLAGS_imx7d_low_power_idle.o :=-Wa,-march=armv7-a
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obj-$(CONFIG_SOC_IMX7D_CA7) += cpuidle-imx7d.o imx7d_low_power_idle.o
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@ -144,11 +144,6 @@ void imx6_up_ddr3_freq_change(struct imx6_busfreq_info *busfreq_info) {}
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void imx6_up_lpddr2_freq_change(u32 freq, int bus_freq_mode) {}
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#endif
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#if !defined(CONFIG_SOC_IMX6ULL)
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u32 mx6ull_lpm_wfi_start, mx6ull_lpm_wfi_end;
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void imx6ull_low_power_idle(void) {}
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#endif
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#if !defined(CONFIG_SOC_IMX6Q)
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u32 mx6_ddr3_freq_change_start, mx6_ddr3_freq_change_end;
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u32 mx6q_lpddr2_freq_change_start, mx6q_lpddr2_freq_change_end;
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@ -146,6 +146,7 @@ void imx6sl_low_power_idle(void);
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void imx6sll_low_power_idle(void);
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void imx6sx_low_power_idle(void);
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void imx6ul_low_power_idle(void);
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void imx6ull_low_power_idle(void);
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void imx7d_low_power_idle(void);
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#ifdef CONFIG_HAVE_IMX_MMDC
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int imx_mmdc_get_ddr_type(void);
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@ -253,10 +253,17 @@ int __init imx6ul_cpuidle_init(void)
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cpuidle_pm_info->mmdc_io_val[i][0] = mmdc_offset_array[i];
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/* calculate the wfi code size */
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wfi_code_size = (&mx6ul_lpm_wfi_end -&mx6ul_lpm_wfi_start) *4;
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if (cpu_is_imx6ul()) {
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wfi_code_size = (&mx6ul_lpm_wfi_end -&mx6ul_lpm_wfi_start) *4;
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imx6ul_wfi_in_iram_fn = (void *)fncpy(wfi_iram_base + sizeof(*cpuidle_pm_info),
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&imx6ul_low_power_idle, wfi_code_size);
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imx6ul_wfi_in_iram_fn = (void *)fncpy(wfi_iram_base + sizeof(*cpuidle_pm_info),
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&imx6ul_low_power_idle, wfi_code_size);
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} else {
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wfi_code_size = (&mx6ull_lpm_wfi_end -&mx6ull_lpm_wfi_start) *4;
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imx6ul_wfi_in_iram_fn = (void *)fncpy(wfi_iram_base + sizeof(*cpuidle_pm_info),
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&imx6ull_low_power_idle, wfi_code_size);
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}
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#endif
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imx6_set_int_mem_clk_lpm(true);
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764
arch/arm/mach-imx/imx6ull_low_power_idle.S
Normal file
764
arch/arm/mach-imx/imx6ull_low_power_idle.S
Normal file
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@ -0,0 +1,764 @@
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/linkage.h>
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#define PM_INFO_PBASE_OFFSET 0x0
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#define PM_INFO_RESUME_ADDR_OFFSET 0x4
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#define PM_INFO_PM_INFO_SIZE_OFFSET 0x8
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#define PM_INFO_PM_INFO_TTBR_OFFSET 0xc
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#define PM_INFO_MX6Q_MMDC_P_OFFSET 0x10
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#define PM_INFO_MX6Q_MMDC_V_OFFSET 0x14
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#define PM_INFO_MX6Q_IOMUXC_P_OFFSET 0x18
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#define PM_INFO_MX6Q_IOMUXC_V_OFFSET 0x1c
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#define PM_INFO_MX6Q_CCM_P_OFFSET 0x20
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#define PM_INFO_MX6Q_CCM_V_OFFSET 0x24
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#define PM_INFO_MX6Q_GPC_P_OFFSET 0x28
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#define PM_INFO_MX6Q_GPC_V_OFFSET 0x2c
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#define PM_INFO_MX6Q_ANATOP_P_OFFSET 0x30
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#define PM_INFO_MX6Q_ANATOP_V_OFFSET 0x34
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#define PM_INFO_MX6Q_SRC_P_OFFSET 0x38
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#define PM_INFO_MX6Q_SRC_V_OFFSET 0x3c
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#define PM_INFO_MMDC_IO_NUM_OFFSET 0x40
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#define PM_INFO_MMDC_IO_VAL_OFFSET 0x44
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#define MX6Q_MMDC_MAPSR 0x404
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#define MX6Q_MMDC_MPDGCTRL0 0x83c
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#define MX6Q_SRC_GPR1 0x20
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#define MX6Q_SRC_GPR2 0x24
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#define MX6Q_GPC_IMR1 0x08
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#define MX6Q_GPC_IMR2 0x0c
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#define MX6Q_GPC_IMR3 0x10
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#define MX6Q_GPC_IMR4 0x14
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#define MX6Q_CCM_CCR 0x0
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.globl mx6ull_lpm_wfi_start
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.globl mx6ull_lpm_wfi_end
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.macro pll_do_wait_lock
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1:
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ldr r7, [r10, r8]
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ands r7, #0x80000000
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beq 1b
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.endm
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.macro ccm_do_wait
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2:
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ldr r7, [r10, #0x48]
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cmp r7, #0x0
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bne 2b
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.endm
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.macro ccm_enter_idle
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ldr r10, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET]
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/* set ahb to 3MHz */
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ldr r7, [r10, #0x14]
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orr r7, r7, #0x1c00
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str r7, [r10, #0x14]
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/* set perclk to 6MHz */
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ldr r7, [r10, #0x1c]
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bic r7, r7, #0x3f
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orr r7, r7, #0x3
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str r7, [r10, #0x1c]
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/* set mmdc to 1MHz, periph2_clk2 need to be @8MHz */
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ldr r7, [r10, #0x14]
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orr r7, r7, #0x2
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orr r7, r7, #(0x7 << 3)
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str r7, [r10, #0x14]
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ccm_do_wait
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ldr r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET]
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/*
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* disable pll2, suppose when system enter low
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* power idle mode, only 396MHz pfd needs pll2,
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* now we switch arm clock to OSC, we can disable
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* pll2 now, gate pll2_pfd2 first.
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*/
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ldr r7, [r10, #0x100]
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orr r7, #0x800000
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str r7, [r10, #0x100]
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ldr r7, [r10, #0x30]
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orr r7, r7, #0x1000
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bic r7, r7, #0x2000
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str r7, [r10, #0x30]
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.endm
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.macro ccm_exit_idle
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cmp r5, #0x0
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ldreq r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET]
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ldrne r10, [r0, #PM_INFO_MX6Q_ANATOP_P_OFFSET]
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/* enable pll2 and pll2_pfd2 */
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ldr r7, [r10, #0x30]
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bic r7, r7, #0x1000
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orr r7, r7, #0x2000
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str r7, [r10, #0x30]
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ldr r8, =0x30
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pll_do_wait_lock
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ldr r7, [r10, #0x100]
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bic r7, #0x800000
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str r7, [r10, #0x100]
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cmp r5, #0x0
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ldreq r10, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET]
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ldrne r10, [r0, #PM_INFO_MX6Q_CCM_P_OFFSET]
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/* set perclk back to 24MHz */
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ldr r7, [r10, #0x1c]
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bic r7, r7, #0x3f
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str r7, [r10, #0x1c]
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/* set mmdc back to 24MHz */
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ldr r7, [r10, #0x14]
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bic r7, r7, #0x7
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bic r7, r7, #(0x7 << 3)
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str r7, [r10, #0x14]
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/* set ahb div back to 24MHz */
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ldr r7, [r10, #0x14]
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bic r7, r7, #0x1c00
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str r7, [r10, #0x14]
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ccm_do_wait
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.endm
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.macro anatop_enter_idle
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ldr r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET]
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/*
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* check whether any PLL is enabled, as only when
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* there is no PLLs enabled, 2P5 and 1P1 can be
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* off and only enable weak ones.
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*/
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/* arm pll1 */
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ldr r7, [r10, #0]
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ands r7, r7, #(1 << 31)
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bne 10f
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/* sys pll2 */
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ldr r7, [r10, #0x30]
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ands r7, r7, #(1 << 31)
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bne 10f
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/* usb pll3 */
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ldr r7, [r10, #0x10]
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ands r7, r7, #(1 << 31)
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bne 10f
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/* audio pll4 */
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ldr r7, [r10, #0x70]
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ands r7, r7, #(1 << 31)
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bne 10f
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/* vidio pll5 */
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ldr r7, [r10, #0xa0]
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ands r7, r7, #(1 << 31)
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bne 10f
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/* enet pll6 */
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ldr r7, [r10, #0xe0]
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ands r7, r7, #(1 << 31)
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bne 10f
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/* usb host pll7 */
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ldr r7, [r10, #0x20]
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ands r7, r7, #(1 << 31)
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bne 10f
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/* enable weak 2P5 and turn off regular 2P5 */
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ldr r7, [r10, #0x130]
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orr r7, r7, #0x40000
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str r7, [r10, #0x130]
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bic r7, r7, #0x1
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str r7, [r10, #0x130]
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/* enable weak 1p1 and turn off regular 1P1 */
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ldr r7, [r10, #0x110]
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orr r7, r7, #0x40000
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str r7, [r10, #0x110]
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bic r7, r7, #0x1
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str r7, [r10, #0x110]
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/* check whether ARM LDO is bypassed */
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ldr r7, [r10, #0x140]
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and r7, r7, #0x1f
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cmp r7, #0x1f
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bne 10f
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/* low power band gap enable */
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ldr r7, [r10, #0x270]
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orr r7, r7, #0x20
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str r7, [r10, #0x270]
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/* turn off the bias current from the regular bandgap */
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ldr r7, [r10, #0x270]
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orr r7, r7, #0x80
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str r7, [r10, #0x270]
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/*
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* clear the REFTOP_SELFBIASOFF,
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* self-bias circuit of the band gap.
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* Per RM, should be cleared when
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* band gap is powered down.
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*/
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ldr r7, [r10, #0x150]
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bic r7, r7, #0x8
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str r7, [r10, #0x150]
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/* turn off regular bandgap */
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ldr r7, [r10, #0x150]
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orr r7, r7, #0x1
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str r7, [r10, #0x150]
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10:
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/* switch to RC-OSC */
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ldr r7, [r10, #0x270]
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orr r7, r7, #0x10
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str r7, [r10, #0x270]
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/* turn off XTAL-OSC */
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ldr r7, [r10, #0x150]
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orr r7, r7, #0x40000000
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str r7, [r10, #0x150]
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/* lower OSC current by 37.5% */
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ldr r7, [r10, #0x150]
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orr r7, r7, #0x6000
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str r7, [r10, #0x150]
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/* disconnect vdd_high_in and vdd_snvs_in */
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ldr r7, [r10, #0x150]
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orr r7, r7, #0x1000
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str r7, [r10, #0x150]
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.endm
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.macro anatop_exit_idle
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cmp r5, #0x0
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ldreq r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET]
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ldrne r10, [r0, #PM_INFO_MX6Q_ANATOP_P_OFFSET]
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/* increase OSC current to normal */
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ldr r7, [r10, #0x150]
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bic r7, r7, #0x6000
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str r7, [r10, #0x150]
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/* turn on XTAL-OSC and detector */
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ldr r7, [r10, #0x150]
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bic r7, r7, #0x40000000
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orr r7, r7, #0x10000
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str r7, [r10, #0x150]
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/* wait for XTAL stable */
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14:
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ldr r7, [r10, #0x150]
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ands r7, r7, #0x8000
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beq 14b
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/* switch to XTAL-OSC */
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ldr r7, [r10, #0x270]
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bic r7, r7, #0x10
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str r7, [r10, #0x270]
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/* turn off XTAL-OSC detector */
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ldr r7, [r10, #0x150]
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bic r7, r7, #0x10000
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str r7, [r10, #0x150]
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15:
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/* check whether we need to enable 2P5/1P1 */
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ldr r7, [r10, #0x110]
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ands r7, r7, #0x40000
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beq 11f
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/* check whether ARM LDO is bypassed */
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ldr r7, [r10, #0x140]
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and r7, r7, #0x1f
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cmp r7, #0x1f
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bne 12f
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/* turn on regular bandgap and wait for stable */
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ldr r7, [r10, #0x150]
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bic r7, r7, #0x1
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str r7, [r10, #0x150]
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13:
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ldr r7, [r10, #0x150]
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ands r7, #0x80
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beq 13b
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/*
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* set the REFTOP_SELFBIASOFF,
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* self-bias circuit of the band gap.
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*/
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ldr r7, [r10, #0x150]
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orr r7, r7, #0x8
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str r7, [r10, #0x150]
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/* turn on the bias current from the regular bandgap */
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ldr r7, [r10, #0x270]
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bic r7, r7, #0x80
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str r7, [r10, #0x270]
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/* low power band gap disable */
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ldr r7, [r10, #0x270]
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bic r7, r7, #0x20
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str r7, [r10, #0x270]
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12:
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/* enable regular 2P5 and turn off weak 2P5 */
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ldr r7, [r10, #0x130]
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orr r7, r7, #0x1
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str r7, [r10, #0x130]
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/* Ensure the 2P5 is up. */
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3:
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ldr r7, [r10, #0x130]
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ands r7, r7, #0x20000
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beq 3b
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ldr r7, [r10, #0x130]
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bic r7, r7, #0x40000
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str r7, [r10, #0x130]
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/* enable regular 1p1 and turn off weak 1P1 */
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ldr r7, [r10, #0x110]
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orr r7, r7, #0x1
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str r7, [r10, #0x110]
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4:
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ldr r7, [r10, #0x110]
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ands r7, r7, #0x20000
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beq 4b
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ldr r7, [r10, #0x110]
|
||||
bic r7, r7, #0x40000
|
||||
str r7, [r10, #0x110]
|
||||
11:
|
||||
.endm
|
||||
|
||||
.macro disable_l1_dcache
|
||||
|
||||
/*
|
||||
* Flush all data from the L1 data cache before disabling
|
||||
* SCTLR.C bit.
|
||||
*/
|
||||
push {r0 - r10, lr}
|
||||
ldr r7, =v7_flush_dcache_all
|
||||
mov lr, pc
|
||||
mov pc, r7
|
||||
pop {r0 - r10, lr}
|
||||
|
||||
/* disable d-cache */
|
||||
mrc p15, 0, r7, c1, c0, 0
|
||||
bic r7, r7, #(1 << 2)
|
||||
mcr p15, 0, r7, c1, c0, 0
|
||||
dsb
|
||||
isb
|
||||
|
||||
push {r0 - r10, lr}
|
||||
ldr r7, =v7_flush_dcache_all
|
||||
mov lr, pc
|
||||
mov pc, r7
|
||||
pop {r0 - r10, lr}
|
||||
|
||||
.endm
|
||||
|
||||
.macro mmdc_enter_dvfs_mode
|
||||
|
||||
/* disable automatic power savings. */
|
||||
ldr r7, [r10, #MX6Q_MMDC_MAPSR]
|
||||
orr r7, r7, #0x1
|
||||
str r7, [r10, #MX6Q_MMDC_MAPSR]
|
||||
|
||||
/* disable power down timer */
|
||||
ldr r7, [r10, #0x4]
|
||||
bic r7, r7, #0xff00
|
||||
str r7, [r10, #0x4]
|
||||
|
||||
/* make the DDR explicitly enter self-refresh. */
|
||||
ldr r7, [r10, #MX6Q_MMDC_MAPSR]
|
||||
orr r7, r7, #(1 << 21)
|
||||
str r7, [r10, #MX6Q_MMDC_MAPSR]
|
||||
5:
|
||||
ldr r7, [r10, #MX6Q_MMDC_MAPSR]
|
||||
ands r7, r7, #(1 << 25)
|
||||
beq 5b
|
||||
|
||||
.endm
|
||||
|
||||
.macro resume_mmdc
|
||||
|
||||
/* restore MMDC IO */
|
||||
cmp r5, #0x0
|
||||
ldreq r10, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET]
|
||||
ldrne r10, [r0, #PM_INFO_MX6Q_IOMUXC_P_OFFSET]
|
||||
|
||||
ldr r6, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET]
|
||||
ldr r7, =PM_INFO_MMDC_IO_VAL_OFFSET
|
||||
add r7, r7, r0
|
||||
6:
|
||||
ldr r8, [r7], #0x4
|
||||
ldr r9, [r7], #0x4
|
||||
str r9, [r10, r8]
|
||||
subs r6, r6, #0x1
|
||||
bne 6b
|
||||
|
||||
cmp r5, #0x0
|
||||
ldreq r10, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET]
|
||||
ldrne r10, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET]
|
||||
|
||||
/* reset read FIFO, RST_RD_FIFO */
|
||||
ldr r7, =MX6Q_MMDC_MPDGCTRL0
|
||||
ldr r6, [r10, r7]
|
||||
orr r6, r6, #(1 << 31)
|
||||
str r6, [r10, r7]
|
||||
7:
|
||||
ldr r6, [r10, r7]
|
||||
ands r6, r6, #(1 << 31)
|
||||
bne 7b
|
||||
|
||||
/* reset FIFO a second time */
|
||||
ldr r6, [r10, r7]
|
||||
orr r6, r6, #(1 << 31)
|
||||
str r6, [r10, r7]
|
||||
8:
|
||||
ldr r6, [r10, r7]
|
||||
ands r6, r6, #(1 << 31)
|
||||
bne 8b
|
||||
|
||||
/* let DDR out of self-refresh */
|
||||
ldr r7, [r10, #MX6Q_MMDC_MAPSR]
|
||||
bic r7, r7, #(1 << 21)
|
||||
str r7, [r10, #MX6Q_MMDC_MAPSR]
|
||||
9:
|
||||
ldr r7, [r10, #MX6Q_MMDC_MAPSR]
|
||||
ands r7, r7, #(1 << 25)
|
||||
bne 9b
|
||||
|
||||
/* enable power down timer */
|
||||
ldr r7, [r10, #0x4]
|
||||
orr r7, r7, #0x5500
|
||||
str r7, [r10, #0x4]
|
||||
|
||||
/* enable DDR auto power saving */
|
||||
ldr r7, [r10, #MX6Q_MMDC_MAPSR]
|
||||
bic r7, r7, #0x1
|
||||
str r7, [r10, #MX6Q_MMDC_MAPSR]
|
||||
|
||||
.endm
|
||||
|
||||
.macro tlb_set_to_ocram
|
||||
|
||||
/* save ttbr */
|
||||
mrc p15, 0, r7, c2, c0, 1
|
||||
str r7, [r0, #PM_INFO_PM_INFO_TTBR_OFFSET]
|
||||
|
||||
/*
|
||||
* To ensure no page table walks occur in DDR, we
|
||||
* have a another page table stored in IRAM that only
|
||||
* contains entries pointing to IRAM, AIPS1 and AIPS2.
|
||||
* We need to set the TTBR1 to the new IRAM TLB.
|
||||
* Do the following steps:
|
||||
* 1. Flush the Branch Target Address Cache (BTAC)
|
||||
* 2. Set TTBR1 to point to IRAM page table.
|
||||
* 3. Disable page table walks in TTBR0 (PD0 = 1)
|
||||
* 4. Set TTBR0.N=1, implying 0-2G is translated by TTBR0
|
||||
* and 2-4G is translated by TTBR1.
|
||||
*/
|
||||
|
||||
ldr r6, =iram_tlb_phys_addr
|
||||
ldr r7, [r6]
|
||||
|
||||
/* Flush the BTAC. */
|
||||
ldr r6, =0x0
|
||||
mcr p15, 0, r6, c7, c1, 6
|
||||
|
||||
/* Disable Branch Prediction, Z bit in SCTLR. */
|
||||
mrc p15, 0, r6, c1, c0, 0
|
||||
bic r6, r6, #0x800
|
||||
mcr p15, 0, r6, c1, c0, 0
|
||||
|
||||
dsb
|
||||
isb
|
||||
|
||||
/* Store the IRAM table in TTBR1 */
|
||||
mcr p15, 0, r7, c2, c0, 1
|
||||
|
||||
/* Read TTBCR and set PD0=1, N = 1 */
|
||||
mrc p15, 0, r6, c2, c0, 2
|
||||
orr r6, r6, #0x11
|
||||
mcr p15, 0, r6, c2, c0, 2
|
||||
|
||||
dsb
|
||||
isb
|
||||
|
||||
/* flush the TLB */
|
||||
ldr r6, =0x0
|
||||
mcr p15, 0, r6, c8, c3, 0
|
||||
|
||||
.endm
|
||||
|
||||
.macro tlb_back_to_ddr
|
||||
|
||||
/* Restore the TTBCR */
|
||||
|
||||
dsb
|
||||
isb
|
||||
|
||||
/* Read TTBCR and set PD0=0, N = 0 */
|
||||
mrc p15, 0, r6, c2, c0, 2
|
||||
bic r6, r6, #0x11
|
||||
mcr p15, 0, r6, c2, c0, 2
|
||||
|
||||
dsb
|
||||
isb
|
||||
|
||||
/* flush the TLB */
|
||||
ldr r6, =0x0
|
||||
mcr p15, 0, r6, c8, c3, 0
|
||||
|
||||
dsb
|
||||
isb
|
||||
|
||||
/* Enable Branch Prediction, Z bit in SCTLR. */
|
||||
mrc p15, 0, r6, c1, c0, 0
|
||||
orr r6, r6, #0x800
|
||||
mcr p15, 0, r6, c1, c0, 0
|
||||
|
||||
/* Flush the Branch Target Address Cache (BTAC) */
|
||||
ldr r6, =0x0
|
||||
mcr p15, 0, r6, c7, c1, 6
|
||||
|
||||
/* restore ttbr */
|
||||
ldr r7, [r0, #PM_INFO_PM_INFO_TTBR_OFFSET]
|
||||
mcr p15, 0, r7, c2, c0, 1
|
||||
|
||||
.endm
|
||||
|
||||
.extern iram_tlb_phys_addr
|
||||
|
||||
/* imx6ull_low_power_idle */
|
||||
|
||||
.align 3
|
||||
ENTRY(imx6ull_low_power_idle)
|
||||
mx6ull_lpm_wfi_start:
|
||||
push {r4 - r10}
|
||||
|
||||
/* get necessary info from pm_info */
|
||||
ldr r1, [r0, #PM_INFO_PBASE_OFFSET]
|
||||
ldr r2, [r0, #PM_INFO_PM_INFO_SIZE_OFFSET]
|
||||
|
||||
/*
|
||||
* counting the resume address in iram
|
||||
* to set it in SRC register.
|
||||
*/
|
||||
ldr r5, =imx6ull_low_power_idle
|
||||
ldr r6, =wakeup
|
||||
sub r6, r6, r5
|
||||
add r8, r1, r2
|
||||
add r3, r8, r6
|
||||
|
||||
/* store physical resume addr and pm_info address. */
|
||||
ldr r10, [r0, #PM_INFO_MX6Q_SRC_V_OFFSET]
|
||||
str r3, [r10, #0x20]
|
||||
str r1, [r10, #0x24]
|
||||
|
||||
/* set ARM power to be gated */
|
||||
ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
|
||||
ldr r7, =0x1
|
||||
str r7, [r10, #0x2a0]
|
||||
|
||||
disable_l1_dcache
|
||||
|
||||
tlb_set_to_ocram
|
||||
|
||||
/* make sure MMDC in self-refresh */
|
||||
ldr r10, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET]
|
||||
mmdc_enter_dvfs_mode
|
||||
|
||||
/* save DDR IO settings */
|
||||
ldr r10, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET]
|
||||
ldr r6, =0x0
|
||||
ldr r7, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET]
|
||||
ldr r8, =PM_INFO_MMDC_IO_VAL_OFFSET
|
||||
add r8, r8, r0
|
||||
save_and_set_mmdc_io_lpm:
|
||||
ldr r9, [r8], #0x4
|
||||
ldr r5, [r10, r9]
|
||||
str r6, [r10, r9]
|
||||
str r5, [r8], #0x4
|
||||
subs r7, r7, #0x1
|
||||
bne save_and_set_mmdc_io_lpm
|
||||
|
||||
mov r5, #0x0
|
||||
ccm_enter_idle
|
||||
anatop_enter_idle
|
||||
|
||||
/*
|
||||
* mask all GPC interrupts before
|
||||
* enabling the RBC counters to
|
||||
* avoid the counter starting too
|
||||
* early if an interupt is already
|
||||
* pending.
|
||||
*/
|
||||
ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
|
||||
ldr r4, [r10, #MX6Q_GPC_IMR1]
|
||||
ldr r5, [r10, #MX6Q_GPC_IMR2]
|
||||
ldr r6, [r10, #MX6Q_GPC_IMR3]
|
||||
ldr r7, [r10, #MX6Q_GPC_IMR4]
|
||||
|
||||
ldr r3, =0xffffffff
|
||||
str r3, [r10, #MX6Q_GPC_IMR1]
|
||||
str r3, [r10, #MX6Q_GPC_IMR2]
|
||||
str r3, [r10, #MX6Q_GPC_IMR3]
|
||||
str r3, [r10, #MX6Q_GPC_IMR4]
|
||||
|
||||
/*
|
||||
* enable the RBC bypass counter here
|
||||
* to hold off the interrupts. RBC counter
|
||||
* = 4 (120us). With this setting, the latency
|
||||
* from wakeup interrupt to ARM power up
|
||||
* is ~130uS.
|
||||
*/
|
||||
ldr r10, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET]
|
||||
ldr r3, [r10, #MX6Q_CCM_CCR]
|
||||
bic r3, r3, #(0x3f << 21)
|
||||
orr r3, r3, #(0x4 << 21)
|
||||
str r3, [r10, #MX6Q_CCM_CCR]
|
||||
|
||||
/* enable the counter. */
|
||||
ldr r3, [r10, #MX6Q_CCM_CCR]
|
||||
orr r3, r3, #(0x1 << 27)
|
||||
str r3, [r10, #MX6Q_CCM_CCR]
|
||||
|
||||
/* unmask all the GPC interrupts. */
|
||||
ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
|
||||
str r4, [r10, #MX6Q_GPC_IMR1]
|
||||
str r5, [r10, #MX6Q_GPC_IMR2]
|
||||
str r6, [r10, #MX6Q_GPC_IMR3]
|
||||
str r7, [r10, #MX6Q_GPC_IMR4]
|
||||
|
||||
/*
|
||||
* now delay for a short while (3usec)
|
||||
* ARM is at 24MHz at this point
|
||||
* so a short loop should be enough.
|
||||
* this delay is required to ensure that
|
||||
* the RBC counter can start counting in
|
||||
* case an interrupt is already pending
|
||||
* or in case an interrupt arrives just
|
||||
* as ARM is about to assert DSM_request.
|
||||
*/
|
||||
ldr r4, =50
|
||||
rbc_loop:
|
||||
subs r4, r4, #0x1
|
||||
bne rbc_loop
|
||||
|
||||
wfi
|
||||
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
|
||||
mov r5, #0x0
|
||||
anatop_exit_idle
|
||||
ccm_exit_idle
|
||||
|
||||
/* clear ARM power gate setting */
|
||||
ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
|
||||
ldr r7, =0x0
|
||||
str r7, [r10, #0x2a0]
|
||||
|
||||
resume_mmdc
|
||||
/* enable d-cache */
|
||||
mrc p15, 0, r7, c1, c0, 0
|
||||
orr r7, r7, #(1 << 2)
|
||||
mcr p15, 0, r7, c1, c0, 0
|
||||
|
||||
tlb_back_to_ddr
|
||||
|
||||
/* Restore registers */
|
||||
pop {r4 - r10}
|
||||
mov pc, lr
|
||||
|
||||
wakeup:
|
||||
/* invalidate L1 I-cache first */
|
||||
mov r1, #0x0
|
||||
mcr p15, 0, r1, c7, c5, 0
|
||||
mcr p15, 0, r1, c7, c5, 0
|
||||
mcr p15, 0, r1, c7, c5, 6
|
||||
/* enable the Icache and branch prediction */
|
||||
mov r1, #0x1800
|
||||
mcr p15, 0, r1, c1, c0, 0
|
||||
isb
|
||||
|
||||
/* get physical resume address from pm_info. */
|
||||
ldr lr, [r0, #PM_INFO_RESUME_ADDR_OFFSET]
|
||||
/* clear core0's entry and parameter */
|
||||
ldr r10, [r0, #PM_INFO_MX6Q_SRC_P_OFFSET]
|
||||
mov r7, #0x0
|
||||
str r7, [r10, #MX6Q_SRC_GPR1]
|
||||
str r7, [r10, #MX6Q_SRC_GPR2]
|
||||
|
||||
/* clear ARM power gate setting */
|
||||
ldr r10, [r0, #PM_INFO_MX6Q_GPC_P_OFFSET]
|
||||
ldr r7, =0x0
|
||||
str r7, [r10, #0x2a0]
|
||||
|
||||
mov r5, #0x1
|
||||
anatop_exit_idle
|
||||
ccm_exit_idle
|
||||
resume_mmdc
|
||||
|
||||
/* Restore registers */
|
||||
mov pc, lr
|
||||
.ltorg
|
||||
mx6ull_lpm_wfi_end:
|
Loading…
Reference in New Issue
Block a user