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clk: at91: master: Add sam9x60 support 

The sam9x60 cpu clock is located at a different offset but is otherwise
similar to the master clock.

Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Alexandre Belloni 2019-04-02 14:50:53 +02:00 committed by Stephen Boyd
parent 2423eeaead
commit e5be537064
3 changed files with 8 additions and 3 deletions
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8
drivers/clk/at91/clk-master.c
View File

@ -29,6 +29,7 @@ struct clk_master {
struct regmap *regmap;
const struct clk_master_layout *layout;
const struct clk_master_characteristics *characteristics;
u32 mckr;
};
static inline bool clk_master_ready(struct regmap *regmap)
@ -69,7 +70,7 @@ static unsigned long clk_master_recalc_rate(struct clk_hw *hw,
master->characteristics;
unsigned int mckr;
regmap_read(master->regmap, AT91_PMC_MCKR, &mckr);
regmap_read(master->regmap, master->layout->offset, &mckr);
mckr &= layout->mask;
pres = (mckr >> layout->pres_shift) & MASTER_PRES_MASK;
@ -95,7 +96,7 @@ static u8 clk_master_get_parent(struct clk_hw *hw)
struct clk_master *master = to_clk_master(hw);
unsigned int mckr;
regmap_read(master->regmap, AT91_PMC_MCKR, &mckr);
regmap_read(master->regmap, master->layout->offset, &mckr);
return mckr & AT91_PMC_CSS;
}
@ -147,13 +148,14 @@ at91_clk_register_master(struct regmap *regmap,
return hw;
}
const struct clk_master_layout at91rm9200_master_layout = {
.mask = 0x31F,
.pres_shift = 2,
.offset = AT91_PMC_MCKR,
};
const struct clk_master_layout at91sam9x5_master_layout = {
.mask = 0x373,
.pres_shift = 4,
.offset = AT91_PMC_MCKR,
};

1
drivers/clk/at91/pmc.h
View File

@ -38,6 +38,7 @@ struct clk_range {
#define CLK_RANGE(MIN, MAX) {.min = MIN, .max = MAX,}
struct clk_master_layout {
u32 offset;
u32 mask;
u8 pres_shift;
};

2
include/linux/clk/at91_pmc.h
View File

@ -74,6 +74,8 @@
#define AT91_PMC_USBDIV_4 (2 << 28)
#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
#define AT91_PMC_CPU_CKR 0x28 /* CPU Clock Register */
#define AT91_PMC_MCKR 0x30 /* Master Clock Register */
#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */
#define AT91_PMC_CSS_SLOW (0 << 0)