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drm/amd/display: move signal type out of otg dlg params 

It makes no logical sense being there

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Dmytro Laktyushkin 2019-04-08 15:04:43 -04:00 committed by Alex Deucher
parent 052fa7e8c9
commit db819940b0
3 changed files with 5 additions and 6 deletions
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3
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
View File

@ -663,7 +663,7 @@ static enum dc_status dcn10_enable_stream_timing(
pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset;
pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width;
pipe_ctx->stream_res.tg->dlg_otg_param.signal = pipe_ctx->stream->signal;
pipe_ctx->stream_res.tg->signal = pipe_ctx->stream->signal;
pipe_ctx->stream_res.tg->funcs->program_timing(
pipe_ctx->stream_res.tg,
@ -2283,7 +2283,6 @@ static void program_all_pipe_in_tree(
pipe_ctx->stream_res.tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start;
pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset;
pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width;
pipe_ctx->stream_res.tg->dlg_otg_param.signal = pipe_ctx->stream->signal;
pipe_ctx->stream_res.tg->funcs->program_global_sync(
pipe_ctx->stream_res.tg);

6
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
View File

@ -243,9 +243,9 @@ void optc1_program_timing(
OTG_V_SYNC_A_POL, v_sync_polarity);
v_init = asic_blank_start;
if (optc->dlg_otg_param.signal == SIGNAL_TYPE_DISPLAY_PORT ||
optc->dlg_otg_param.signal == SIGNAL_TYPE_DISPLAY_PORT_MST ||
optc->dlg_otg_param.signal == SIGNAL_TYPE_EDP) {
if (optc->signal == SIGNAL_TYPE_DISPLAY_PORT ||
optc->signal == SIGNAL_TYPE_DISPLAY_PORT_MST ||
optc->signal == SIGNAL_TYPE_EDP) {
start_point = 1;
if (patched_crtc_timing.flags.INTERLACE == 1)
field_num = 1;

2
drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
View File

@ -75,7 +75,6 @@ struct _dlg_otg_param {
int vupdate_offset;
int vupdate_width;
int vready_offset;
enum signal_type signal;
};
struct vupdate_keepout_params {
@ -127,6 +126,7 @@ struct timing_generator {
struct dc_bios *bp;
struct dc_context *ctx;
struct _dlg_otg_param dlg_otg_param;
enum signal_type signal;
int inst;
};