brain-hackers_pepepper-mirror
/
linux-brain
mirror of https://github.com/brain-hackers/linux-brain.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge pull request #61 from toradex/4.14-2.3.x-imx 

4.14 2.3.x imx: net: sch_generic compilation fix, rel_imx_4.14.98_2.3.1_patch and v4.14.170 stable
This commit is contained in:
Otavio Salvador 2020-03-08 14:05:33 -03:00 committed by GitHub
parent 6da05a37e7 f2c1392ff3
commit cd7c926fa6
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
678 changed files with 6718 additions and 4206 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/ABI/testing/sysfs-bus-mei
View File

@ -4,7 +4,7 @@ KernelVersion: 3.10
Contact: Samuel Ortiz <sameo@linux.intel.com>
linux-mei@linux.intel.com
Description: Stores the same MODALIAS value emitted by uevent
Format: mei:<mei device name>:<device uuid>:
Format: mei:<mei device name>:<device uuid>:<protocol version>
What: /sys/bus/mei/devices/.../name
Date: May 2015

7
Documentation/ABI/testing/sysfs-class-devfreq
View File

@ -7,6 +7,13 @@ Description:
The name of devfreq object denoted as ... is same as the
name of device using devfreq.
What: /sys/class/devfreq/.../name
Date: November 2019
Contact: Chanwoo Choi <cw00.choi@samsung.com>
Description:
The /sys/class/devfreq/.../name shows the name of device
of the corresponding devfreq object.
What: /sys/class/devfreq/.../governor
Date: September 2011
Contact: MyungJoo Ham <myungjoo.ham@samsung.com>

6
Documentation/admin-guide/kernel-parameters.txt
View File

@ -1845,6 +1845,12 @@
Built with CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF=y,
the default is off.
kpti= [ARM64] Control page table isolation of user
and kernel address spaces.
Default: enabled on cores which need mitigation.
0: force disabled
1: force enabled
kvm.ignore_msrs=[KVM] Ignore guest accesses to unhandled MSRs.
Default is 0 (don't ignore, but inject #GP)

6
Makefile
View File

@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
VERSION = 4
PATCHLEVEL = 14
SUBLEVEL = 164
SUBLEVEL = 170
EXTRAVERSION =
NAME = Petit Gorille
@ -971,6 +971,7 @@ ifdef CONFIG_STACK_VALIDATION
endif
endif
PHONY += prepare0
ifeq ($(KBUILD_EXTMOD),)
core-y += kernel/ certs/ mm/ fs/ ipc/ security/ crypto/ block/
@ -1065,8 +1066,7 @@ include/config/kernel.release: include/config/auto.conf FORCE
# archprepare is used in arch Makefiles and when processed asm symlink,
# version.h and scripts_basic is processed / created.
# Listed in dependency order
PHONY += prepare archprepare prepare0 prepare1 prepare2 prepare3
PHONY += prepare archprepare prepare1 prepare2 prepare3
# prepare3 is used to check if we are building in a separate output directory,
# and if so do:

2
arch/arc/plat-eznps/Kconfig
View File

@ -7,7 +7,7 @@
menuconfig ARC_PLAT_EZNPS
bool "\"EZchip\" ARC dev platform"
select CPU_BIG_ENDIAN
select CLKSRC_NPS
select CLKSRC_NPS if !PHYS_ADDR_T_64BIT
select EZNPS_GIC
select EZCHIP_NPS_MANAGEMENT_ENET if ETHERNET
help

5
arch/arm/boot/dts/am335x-boneblack-common.dtsi
View File

@ -131,6 +131,11 @@
};
/ {
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x20000000>; /* 512 MB */
};
clk_mcasp0_fixed: clk_mcasp0_fixed {
#clock-cells = <0>;
compatible = "fixed-clock";

2
arch/arm/boot/dts/am571x-idk.dts
View File

@ -93,7 +93,7 @@
&pcie1_rc {
status = "okay";
gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
};
&pcie1_ep {

21
arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
View File

@ -32,6 +32,27 @@
reg = <0x0 0x80000000 0x0 0x80000000>;
};
main_12v0: fixedregulator-main_12v0 {
/* main supply */
compatible = "regulator-fixed";
regulator-name = "main_12v0";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-always-on;
regulator-boot-on;
};
evm_5v0: fixedregulator-evm_5v0 {
/* Output of TPS54531D */
compatible = "regulator-fixed";
regulator-name = "evm_5v0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&main_12v0>;
regulator-always-on;
regulator-boot-on;
};
vdd_3v3: fixedregulator-vdd_3v3 {
compatible = "regulator-fixed";
regulator-name = "vdd_3v3";

4
arch/arm/boot/dts/lpc3250-phy3250.dts
View File

@ -49,8 +49,8 @@
sd_reg: regulator@2 {
compatible = "regulator-fixed";
regulator-name = "sd_reg";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio 5 5 0>;
enable-active-high;
};

10
arch/arm/boot/dts/lpc32xx.dtsi
View File

@ -139,11 +139,11 @@
};
clcd: clcd@31040000 {
compatible = "arm,pl110", "arm,primecell";
compatible = "arm,pl111", "arm,primecell";
reg = <0x31040000 0x1000>;
interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk LPC32XX_CLK_LCD>;
clock-names = "apb_pclk";
clocks = <&clk LPC32XX_CLK_LCD>, <&clk LPC32XX_CLK_LCD>;
clock-names = "clcdclk", "apb_pclk";
status = "disabled";
};
@ -462,7 +462,9 @@
key: key@40050000 {
compatible = "nxp,lpc3220-key";
reg = <0x40050000 0x1000>;
interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk LPC32XX_CLK_KEY>;
interrupt-parent = <&sic1>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};

9
arch/arm/boot/dts/ls1021a-twr.dts
View File

@ -143,7 +143,7 @@
};
&enet0 {
tbi-handle = <&tbi1>;
tbi-handle = <&tbi0>;
phy-handle = <&sgmii_phy2>;
phy-connection-type = "sgmii";
status = "okay";
@ -222,6 +222,13 @@
sgmii_phy2: ethernet-phy@2 {
reg = <0x2>;
};
tbi0: tbi-phy@1f {
reg = <0x1f>;
device_type = "tbi-phy";
};
};
&mdio1 {
tbi1: tbi-phy@1f {
reg = <0x1f>;
device_type = "tbi-phy";

11
arch/arm/boot/dts/ls1021a.dtsi
View File

@ -562,13 +562,22 @@
};
mdio0: mdio@2d24000 {
compatible = "gianfar";
compatible = "fsl,etsec2-mdio";
device_type = "mdio";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2d24000 0x0 0x4000>;
};
mdio1: mdio@2d64000 {
compatible = "fsl,etsec2-mdio";
device_type = "mdio";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2d64000 0x0 0x4000>,
<0x0 0x2d50030 0x0 0x4>;
};
ptp_clock@2d10e00 {
compatible = "fsl,etsec-ptp";
reg = <0x0 0x2d10e00 0x0 0xb0>;

1
arch/arm/boot/dts/stm32h743i-eval.dts
View File

@ -71,6 +71,7 @@
};
&adc_12 {
vdda-supply = <&vdda>;
vref-supply = <&vdda>;
status = "okay";
adc1: adc@0 {

2
arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
View File

@ -90,7 +90,7 @@
initial-mode = <1>; /* initialize in HUB mode */
disabled-ports = <1>;
intn-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
reset-gpios = <&pio 4 16 GPIO_ACTIVE_HIGH>; /* PE16 */
reset-gpios = <&pio 4 16 GPIO_ACTIVE_LOW>; /* PE16 */
connect-gpios = <&pio 4 17 GPIO_ACTIVE_HIGH>; /* PE17 */
refclk-frequency = <19200000>;
};

4
arch/arm/boot/dts/sun8i-h3-beelink-x2.dts
View File

@ -79,6 +79,8 @@
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
clocks = <&rtc 1>;
clock-names = "ext_clock";
};
sound_spdif {
@ -128,6 +130,8 @@
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins_a>;
vmmc-supply = <&reg_vcc3v3>;
vqmmc-supply = <&reg_vcc3v3>;
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
non-removable;
status = "okay";

2
arch/arm/common/mcpm_entry.c
View File

@ -379,7 +379,7 @@ static int __init nocache_trampoline(unsigned long _arg)
unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
phys_reset_t phys_reset;
mcpm_set_entry_vector(cpu, cluster, cpu_resume);
mcpm_set_entry_vector(cpu, cluster, cpu_resume_no_hyp);
setup_mm_for_reboot();
__mcpm_cpu_going_down(cpu, cluster);

1
arch/arm/include/asm/suspend.h
View File

@ -10,6 +10,7 @@ struct sleep_save_sp {
};
extern void cpu_resume(void);
extern void cpu_resume_no_hyp(void);
extern void cpu_resume_arm(void);
extern int cpu_suspend(unsigned long, int (*)(unsigned long));

11
arch/arm/kernel/hyp-stub.S
View File

@ -159,10 +159,9 @@ ARM_BE8(orr r7, r7, #(1 << 25)) @ HSCTLR.EE
#if !defined(ZIMAGE) && defined(CONFIG_ARM_ARCH_TIMER)
@ make CNTP_* and CNTPCT accessible from PL1
mrc p15, 0, r7, c0, c1, 1 @ ID_PFR1
lsr r7, #16
and r7, #0xf
cmp r7, #1
bne 1f
ubfx r7, r7, #16, #4
teq r7, #0
beq 1f
mrc p15, 4, r7, c14, c1, 0 @ CNTHCTL
orr r7, r7, #3 @ PL1PCEN | PL1PCTEN
mcr p15, 4, r7, c14, c1, 0 @ CNTHCTL
@ -180,8 +179,8 @@ ARM_BE8(orr r7, r7, #(1 << 25)) @ HSCTLR.EE
@ Check whether GICv3 system registers are available
mrc p15, 0, r7, c0, c1, 1 @ ID_PFR1
ubfx r7, r7, #28, #4
cmp r7, #1
bne 2f
teq r7, #0
beq 2f
@ Enable system register accesses
mrc p15, 4, r7, c12, c9, 5 @ ICC_HSRE

12
arch/arm/kernel/sleep.S
View File

@ -120,6 +120,14 @@ ENDPROC(cpu_resume_after_mmu)
.text
.align
#ifdef CONFIG_MCPM
.arm
THUMB( .thumb )
ENTRY(cpu_resume_no_hyp)
ARM_BE8(setend be) @ ensure we are in BE mode
b no_hyp
#endif
#ifdef CONFIG_MMU
.arm
ENTRY(cpu_resume_arm)
@ -135,6 +143,7 @@ ARM_BE8(setend be) @ ensure we are in BE mode
bl __hyp_stub_install_secondary
#endif
safe_svcmode_maskall r1
no_hyp:
mov r1, #0
ALT_SMP(mrc p15, 0, r0, c0, c0, 5)
ALT_UP_B(1f)
@ -163,6 +172,9 @@ ENDPROC(cpu_resume)
#ifdef CONFIG_MMU
ENDPROC(cpu_resume_arm)
#endif
#ifdef CONFIG_MCPM
ENDPROC(cpu_resume_no_hyp)
#endif
.align 2

2
arch/arm/mach-omap2/omap_hwmod.c
View File

@ -2530,7 +2530,7 @@ static void _setup_iclk_autoidle(struct omap_hwmod *oh)
*/
static int _setup_reset(struct omap_hwmod *oh)
{
int r;
int r = 0;
if (oh->_state != _HWMOD_STATE_INITIALIZED)
return -EINVAL;

3
arch/arm/mach-rpc/irq.c
View File

@ -118,7 +118,7 @@ extern unsigned char rpc_default_fiq_start, rpc_default_fiq_end;
void __init rpc_init_irq(void)
{
unsigned int irq, clr, set = 0;
unsigned int irq, clr, set;
iomd_writeb(0, IOMD_IRQMASKA);
iomd_writeb(0, IOMD_IRQMASKB);
@ -130,6 +130,7 @@ void __init rpc_init_irq(void)
for (irq = 0; irq < NR_IRQS; irq++) {
clr = IRQ_NOREQUEST;
set = 0;
if (irq <= 6 || (irq >= 9 && irq <= 15))
clr |= IRQ_NOPROBE;

6
arch/arm/plat-pxa/ssp.c
View File

@ -230,18 +230,12 @@ static int pxa_ssp_probe(struct platform_device *pdev)
static int pxa_ssp_remove(struct platform_device *pdev)
{
struct resource *res;
struct ssp_device *ssp;
ssp = platform_get_drvdata(pdev);
if (ssp == NULL)
return -ENODEV;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
release_mem_region(res->start, resource_size(res));
clk_put(ssp->clk);
mutex_lock(&ssp_lock);
list_del(&ssp->node);
mutex_unlock(&ssp_lock);

2
arch/arm64/boot/Makefile
View File

@ -16,7 +16,7 @@
OBJCOPYFLAGS_Image :=-O binary -R .note -R .note.gnu.build-id -R .comment -S
targets := Image Image.gz
targets := Image Image.bz2 Image.gz Image.lz4 Image.lzma Image.lzo
$(obj)/Image: vmlinux FORCE
$(call if_changed,objcopy)

3
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
View File

@ -274,7 +274,8 @@
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu 58>;
clocks = <&ccu 58>, <&osc24M>, <&rtc 0>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
#gpio-cells = <3>;
interrupt-controller;

8
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
View File

@ -56,10 +56,10 @@
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <0 120 8>,
<0 121 8>,
<0 122 8>,
<0 123 8>;
interrupts = <0 170 4>,
<0 171 4>,
<0 172 4>,
<0 173 4>;
interrupt-affinity = <&cpu0>,
<&cpu1>,
<&cpu2>,

4
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
View File

@ -33,11 +33,9 @@
gpio-keys-polled {
compatible = "gpio-keys-polled";
#address-cells = <1>;
#size-cells = <0>;
poll-interval = <100>;
button@0 {
power-button {
label = "power";
linux,code = <KEY_POWER>;
gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>;

1
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
View File

@ -226,7 +226,6 @@
cap-mmc-highspeed;
mmc-ddr-3_3v;
max-frequency = <50000000>;
non-removable;
disable-wp;
mmc-pwrseq = <&emmc_pwrseq>;

1
arch/arm64/boot/dts/arm/juno-base.dtsi
View File

@ -5,7 +5,6 @@
/*
* Devices shared by all Juno boards
*/
dma-ranges = <0 0 0 0 0x100 0>;
memtimer: timer@2a810000 {
compatible = "arm,armv7-timer-mem";

4
arch/arm64/boot/dts/arm/juno-clocks.dtsi
View File

@ -8,10 +8,10 @@
*/
/ {
/* SoC fixed clocks */
soc_uartclk: refclk7273800hz {
soc_uartclk: refclk7372800hz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <7273800>;
clock-frequency = <7372800>;
clock-output-names = "juno:uartclk";
};

10
arch/arm64/boot/dts/freescale/Makefile
View File

@ -92,6 +92,16 @@ dtb-$(CONFIG_ARCH_FSL_IMX8QXP) += fsl-imx8qxp-lpddr4-arm2.dtb \
fsl-imx8qxp-ddr3l-val.dtb \
fsl-imx8dx-17x17-val.dtb \
fsl-imx8dx-lpddr4-arm2.dtb \
fsl-imx8dx-mek.dtb \
fsl-imx8dx-mek-rpmsg.dtb \
fsl-imx8dx-mek-dsp.dtb \
fsl-imx8dx-mek-enet2-tja1100.dtb \
fsl-imx8dx-mek-ov5640.dtb \
fsl-imx8dx-mek-dsi-rm67191.dtb \
fsl-imx8dx-mek-it6263-lvds0-dual-channel.dtb \
fsl-imx8dx-mek-it6263-lvds1-dual-channel.dtb \
fsl-imx8dx-mek-jdi-wuxga-lvds0-panel.dtb \
fsl-imx8dx-mek-jdi-wuxga-lvds1-panel.dtb \
fsl-imx8dxp-lpddr4-arm2.dtb
dtb-$(CONFIG_ARCH_FSL_IMX8MQ) += fsl-imx8mq-ddr3l-arm2.dtb \
fsl-imx8mq-ddr4-arm2.dtb \

63
arch/arm64/boot/dts/freescale/fsl-imx8dx-mek-dsi-rm67191.dts Normal file
View File

@ -0,0 +1,63 @@
/*
* Copyright 2020 NXP
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "fsl-imx8dx-mek.dts"
&mipi_dsi_bridge1 {
status = "okay";
panel@0 {
compatible = "raydium,rm67191";
reg = <0>;
reset-gpio = <&pca9557_a 6 GPIO_ACTIVE_HIGH>;
dsi-lanes = <4>;
panel-width-mm = <68>;
panel-height-mm = <121>;
port {
panel1_in: endpoint {
remote-endpoint = <&mipi_bridge1_out>;
};
};
};
port@2 {
mipi_bridge1_out: endpoint {
remote-endpoint = <&panel1_in>;
};
};
};
&mipi_dsi_bridge2 {
status = "okay";
panel@0 {
compatible = "raydium,rm67191";
reg = <0>;
reset-gpio = <&pca9557_b 7 GPIO_ACTIVE_HIGH>;
dsi-lanes = <4>;
panel-width-mm = <68>;
panel-height-mm = <121>;
port {
panel2_in: endpoint {
remote-endpoint = <&mipi_bridge2_out>;
};
};
};
port@2 {
mipi_bridge2_out: endpoint {
remote-endpoint = <&panel2_in>;
};
};
};

232
arch/arm64/boot/dts/freescale/fsl-imx8dx-mek-dsp.dts Normal file
View File

@ -0,0 +1,232 @@
// SPDX-License-Identifier: GPL-2.0+
// Copyright NXP 2018
#include "fsl-imx8dx-mek-rpmsg.dts"
/ {
sound-cs42888 {
status = "disabled";
};
sound {
status = "disabled";
};
dspaudio: dspaudio {
compatible = "fsl,dsp-audio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esai0>;
status = "okay";
};
sound-dsp {
compatible = "fsl,imx-dsp-audio";
model = "dsp-audio";
cpu-dai = <&dspaudio>;
audio-codec = <&cs42888>;
audio-platform = <&dsp>;
};
};
&edma0 {
compatible = "fsl,imx8qm-edma";
reg = <0x0 0x59280000 0x0 0x10000>, /* spdif0 rx */
<0x0 0x59290000 0x0 0x10000>, /* spdif0 tx */
<0x0 0x592c0000 0x0 0x10000>, /* sai0 rx */
<0x0 0x592d0000 0x0 0x10000>, /* sai0 tx */
<0x0 0x592e0000 0x0 0x10000>, /* sai1 rx */
<0x0 0x592f0000 0x0 0x10000>, /* sai1 tx */
<0x0 0x59300000 0x0 0x10000>, /* sai2 rx */
<0x0 0x59310000 0x0 0x10000>;
#dma-cells = <3>;
shared-interrupt;
dma-channels = <8>;
interrupts = <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */
<GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma0-chan8-rx", "edma0-chan9-tx", /* spdif0 */
"edma0-chan12-rx", "edma0-chan13-tx", /* sai0 */
"edma0-chan14-rx", "edma0-chan15-tx", /* sai1 */
"edma0-chan16-rx", /* sai2 */
"edma0-chan17-rx"; /* sai3 */
pdomains = <&pd_dma0_chan8>, <&pd_dma0_chan9>, /* spdif0 */
<&pd_dma0_chan12>, <&pd_dma0_chan13>, /* sai0 */
<&pd_dma0_chan14>, <&pd_dma0_chan15>, /* sai1 */
<&pd_dma0_chan16>, /* sai2 rx */
<&pd_dma0_chan17>; /* sai3 rx */
status = "okay";
};
&dsp {
compatible = "fsl,imx8qxp-dsp";
reserved-region = <&dsp_reserved>;
reg = <0x0 0x596e8000 0x0 0x88000>;
clocks = <&clk IMX8QXP_AUD_ESAI_0_IPG>,
<&clk IMX8QXP_AUD_ESAI_0_EXTAL_IPG>,
<&clk IMX8QXP_AUD_ASRC_0_IPG>,
<&clk IMX8QXP_CLK_DUMMY>,
<&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>,
<&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK>,
<&clk IMX8QXP_ACM_AUD_CLK0_SEL>,
<&clk IMX8QXP_ACM_AUD_CLK1_SEL>;
clock-names = "esai_ipg", "esai_mclk", "asrc_ipg", "asrc_mem",
"asrck_0", "asrck_1", "asrck_2", "asrck_3";
assigned-clocks = <&clk IMX8QXP_ACM_ESAI0_MCLK_SEL>,
<&clk IMX8QXP_AUD_PLL0_DIV>,
<&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>,
<&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>,
<&clk IMX8QXP_AUD_ESAI_0_EXTAL_IPG>;
assigned-clock-parents = <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>;
assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>;
fsl,dsp-firmware = "imx/dsp/hifi4.bin";
power-domains = <&pd_dsp>;
};
/delete-node/ &pd_dma0_chan0;
/delete-node/ &pd_dma0_chan1;
/delete-node/ &pd_dma0_chan2;
/delete-node/ &pd_dma0_chan3;
/delete-node/ &pd_dma0_chan4;
/delete-node/ &pd_dma0_chan5;
/delete-node/ &pd_dma0_chan6;
/delete-node/ &pd_dma0_chan7;
/delete-node/ &pd_dsp_mu_A;
/delete-node/ &pd_esai0;
&pd_asrc0 {
reg = <SC_R_ASRC_0>;
power-domains =<&pd_audio_clk1>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_dma0_chan0: PD_ASRC_0_RXA {
reg = <SC_R_DMA_0_CH0>;
power-domains =<&pd_asrc0>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_dma0_chan1: PD_ASRC_0_RXB {
reg = <SC_R_DMA_0_CH1>;
power-domains =<&pd_dma0_chan0>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_dma0_chan2: PD_ASRC_0_RXC {
reg = <SC_R_DMA_0_CH2>;
power-domains =<&pd_dma0_chan1>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_dma0_chan3: PD_ASRC_0_TXA {
reg = <SC_R_DMA_0_CH3>;
power-domains =<&pd_dma0_chan2>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_dma0_chan4: PD_ASRC_0_TXB {
reg = <SC_R_DMA_0_CH4>;
power-domains =<&pd_dma0_chan3>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_dma0_chan5: PD_ASRC_0_TXC {
reg = <SC_R_DMA_0_CH5>;
power-domains =<&pd_dma0_chan4>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_dma0_chan6: PD_ESAI_0_RX {
reg = <SC_R_DMA_0_CH6>;
power-domains =<&pd_dma0_chan5>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_dma0_chan7: PD_ESAI_0_TX {
reg = <SC_R_DMA_0_CH7>;
power-domains =<&pd_dma0_chan6>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_esai0: PD_AUD_ESAI_0 {
reg = <SC_R_ESAI_0>;
#power-domain-cells = <0>;
power-domains =<&pd_dma0_chan7>;
#address-cells = <1>;
#size-cells = <0>;
pd_dsp_mu_A: PD_DSP_MU_A {
reg = <SC_R_MU_13A>;
#power-domain-cells = <0>;
power-domains =<&pd_esai0>;
#address-cells = <1>;
#size-cells = <0>;
pd_dsp_mu_B: PD_DSP_MU_B {
reg = <SC_R_MU_13B>;
#power-domain-cells = <0>;
power-domains =<&pd_dsp_mu_A>;
#address-cells = <1>;
#size-cells = <0>;
pd_dsp_ram: PD_AUD_OCRAM {
reg = <SC_R_DSP_RAM>;
#power-domain-cells = <0>;
power-domains =<&pd_dsp_mu_B>;
#address-cells = <1>;
#size-cells = <0>;
pd_dsp: PD_AUD_DSP {
reg = <SC_R_DSP>;
#power-domain-cells = <0>;
power-domains =<&pd_dsp_ram>;
};
};
};
};
};
};
};
};
};
};
};
};
};
};
&esai0 {
status = "disabled";
};
&asrc0 {
status = "disabled";
};
&sai1 {
status = "disabled";
};
&wm8960 {
status = "disabled";
};
&cs42888 {
assigned-clocks = <&clk IMX8QXP_AUD_PLL0_DIV>,
<&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>,
<&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>,
<&clk IMX8QXP_AUD_MCLKOUT0>;
assigned-clock-rates = <786432000>, <49152000>, <24576000>, <12288000>;
};

28
arch/arm64/boot/dts/freescale/fsl-imx8dx-mek-enet2-tja1100.dts Normal file
View File

@ -0,0 +1,28 @@
/*
* Copyright 2020 NXP
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "fsl-imx8dx-mek.dts"
#include "fsl-imx8qxp-enet2-tja1100.dtsi"
&esai0 {
status = "disabled";
};
&ethphy1 {
status = "okay";
};
&fec2 {
status = "okay";
};

30
arch/arm64/boot/dts/freescale/fsl-imx8dx-mek-it6263-lvds0-dual-channel.dts Executable file
View File

@ -0,0 +1,30 @@
/*
* Copyright 2020 NXP
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "fsl-imx8dx-mek.dts"
&i2c0_mipi_lvds0 {
lvds-to-hdmi-bridge@4c {
split-mode;
};
};
&ldb1 {
fsl,dual-channel;
power-domains = <&pd_mipi_dsi_0_dual_lvds>;
};
&ldb2 {
status = "disabled";
};

30
arch/arm64/boot/dts/freescale/fsl-imx8dx-mek-it6263-lvds1-dual-channel.dts Executable file
View File

@ -0,0 +1,30 @@
/*
* Copyright 2020 NXP
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "fsl-imx8dx-mek.dts"
&i2c0_mipi_lvds1 {
lvds-to-hdmi-bridge@4c {
split-mode;
};
};
&ldb1 {
status = "disabled";
};
&ldb2 {
fsl,dual-channel;
power-domains = <&pd_mipi_dsi_1_dual_lvds>;
};

50
arch/arm64/boot/dts/freescale/fsl-imx8dx-mek-jdi-wuxga-lvds0-panel.dts Normal file
View File

@ -0,0 +1,50 @@
/*
* Copyright 2020 NXP
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "fsl-imx8dx-mek.dts"
/ {
lvds0_panel {
compatible = "jdi,tx26d202vm0bwa";
backlight = <&lvds_backlight1>;
port {
panel_lvds0_in: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
};
};
&ldb1 {
fsl,dual-channel;
power-domains = <&pd_mipi_dsi_0_dual_lvds>;
lvds-channel@0 {
fsl,data-mapping = "spwg";
fsl,data-width = <24>;
port@1 {
reg = <1>;
lvds0_out: endpoint {
remote-endpoint = <&panel_lvds0_in>;
};
};
};
};
&ldb2 {
status = "disabled";
};

50
arch/arm64/boot/dts/freescale/fsl-imx8dx-mek-jdi-wuxga-lvds1-panel.dts Normal file
View File

@ -0,0 +1,50 @@
/*
* Copyright 2020 NXP
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "fsl-imx8dx-mek.dts"
/ {
lvds1_panel {
compatible = "jdi,tx26d202vm0bwa";
backlight = <&lvds_backlight0>;
port {
panel_lvds1_in: endpoint {
remote-endpoint = <&lvds1_out>;
};
};
};
};
&ldb2 {
fsl,dual-channel;
power-domains = <&pd_mipi_dsi_1_dual_lvds>;
lvds-channel@0 {
fsl,data-mapping = "spwg";
fsl,data-width = <24>;
port@1 {
reg = <1>;
lvds1_out: endpoint {
remote-endpoint = <&panel_lvds1_in>;
};
};
};
};
&ldb1 {
status = "disabled";
};

27
arch/arm64/boot/dts/freescale/fsl-imx8dx-mek-ov5640.dts Normal file
View File

@ -0,0 +1,27 @@
// SPDX-License-Identifier: GPL-2.0+
// Copyright NXP 2020
#include "fsl-imx8dx-mek.dts"
#include "fsl-imx8dx-mek-ov5640.dtsi"
&i2c0_cm40 {
ov5640: ov5640@3c {
compatible = "ovti,ov5640_v3";
reg = <0x3c>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_parallel_csi>;
clocks = <&clk IMX8QXP_PARALLEL_CSI_MISC0_CLK>;
clock-names = "csi_mclk";
pwn-gpios = <&gpio3 2 GPIO_ACTIVE_LOW>;
rst-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>;
csi_id = <0>;
mclk = <24000000>;
mclk_source = <0>;
status = "okay";
port {
ov5640_ep: endpoint {
remote-endpoint = <&parallel_csi_ep>;
};
};
};
};

126
arch/arm64/boot/dts/freescale/fsl-imx8dx-mek-ov5640.dtsi Normal file
View File

@ -0,0 +1,126 @@
&iomuxc {
imx8qxp-mek {
pinctrl_mipi_csi0: mipicsi0grp{
fsl,pins = <
SC_P_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT 0xC0000041
SC_P_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07 0xC0000041
SC_P_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08 0xC0000041
>;
};
pinctrl_parallel_csi: parallelcsigrp {
fsl,pins = <
SC_P_CSI_D00_CI_PI_D02 0xC0000041
SC_P_CSI_D01_CI_PI_D03 0xC0000041
SC_P_CSI_D02_CI_PI_D04 0xC0000041
SC_P_CSI_D03_CI_PI_D05 0xC0000041
SC_P_CSI_D04_CI_PI_D06 0xC0000041
SC_P_CSI_D05_CI_PI_D07 0xC0000041
SC_P_CSI_D06_CI_PI_D08 0xC0000041
SC_P_CSI_D07_CI_PI_D09 0xC0000041
SC_P_CSI_MCLK_CI_PI_MCLK 0xC0000041
SC_P_CSI_PCLK_CI_PI_PCLK 0xC0000041
SC_P_CSI_HSYNC_CI_PI_HSYNC 0xC0000041
SC_P_CSI_VSYNC_CI_PI_VSYNC 0xC0000041
SC_P_CSI_EN_LSIO_GPIO3_IO02 0xC0000041
SC_P_CSI_RESET_LSIO_GPIO3_IO03 0xC0000041
>;
};
};
};
&isi_0 {
interface = <6 0 2>; /* INPUT: 6-PARALLEL CSI */
parallel_csi;
status = "okay";
};
&cameradev {
parallel_csi;
status = "okay";
};
&parallel_csi {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
port@0 {
reg = <0>;
parallel_csi_ep: endpoint {
remote-endpoint = <&ov5640_ep>;
};
};
};
&isi_2 {
interface = <2 0 2>;
status = "okay";
};
&isi_1 {
status = "disabled";
};
&isi_3 {
status = "disabled";
};
&isi_4 {
status = "disabled";
};
&isi_5 {
status = "disabled";
};
&isi_6 {
status = "disabled";
};
&isi_7 {
status = "disabled";
};
&i2c0_csi0 {
clock-frequency = <100000>;
status = "okay";
ov5640_mipi: ov5640_mipi@3c {
compatible = "ovti,ov5640_mipi_v3";
reg = <0x3c>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mipi_csi0>;
clocks = <&clk IMX8QXP_24MHZ>;
clock-names = "csi_mclk";
csi_id = <0>;
pwn-gpios = <&gpio3 7 GPIO_ACTIVE_LOW>;
rst-gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>;
mclk = <24000000>;
mclk_source = <0>;
mipi_csi;
status = "okay";
port {
ov5640_mipi_ep: endpoint {
remote-endpoint = <&mipi_csi0_ep>;
};
};
};
max9286_mipi@6A {
status = "disabled";
};
};
&mipi_csi_0 {
/delete-property/virtual-channel;
status = "okay";
port@0 {
reg = <0>;
mipi_csi0_ep: endpoint {
remote-endpoint = <&ov5640_mipi_ep>;
data-lanes = <1 2>;
};
};
};

17
arch/arm64/boot/dts/freescale/fsl-imx8dx-mek-rpmsg.dts Normal file
View File

@ -0,0 +1,17 @@
/*
* Copyright 2020 NXP
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/dts-v1/;
#include "fsl-imx8dx-mek-rpmsg.dtsi"

20
arch/arm64/boot/dts/freescale/fsl-imx8dx-mek-rpmsg.dtsi Normal file
View File

@ -0,0 +1,20 @@
/*
* Copyright 2020 NXP
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "fsl-imx8dx-mek.dtsi"
#include "fsl-imx8x-mek-rpmsg.dtsi"
&typec_ptn5110 {
/delete-property/ ss-sel-gpios;
/delete-property/ reset-gpios;
};

17
arch/arm64/boot/dts/freescale/fsl-imx8dx-mek.dts Normal file
View File

@ -0,0 +1,17 @@
/*
* Copyright 2020 NXP
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/dts-v1/;
#include "fsl-imx8dx-mek.dtsi"

41
arch/arm64/boot/dts/freescale/fsl-imx8dx-mek.dtsi Normal file
View File

@ -0,0 +1,41 @@
/*
* Copyright 2020 NXP
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "fsl-imx8dx.dtsi"
#include "fsl-imx8x-mek.dtsi"
/ {
model = "Freescale i.MX8DX MEK";
compatible = "fsl,imx8dx-mek", "fsl,imx8dx", "fsl,imx8qxp";
reserved-memory {
linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0 0x14000000>;
alloc-ranges = <0 0x96000000 0 0x14000000>;
linux,cma-default;
};
};
};
&typec_ptn5110 {
/delete-property/ ss-sel-gpios;
/delete-property/ reset-gpios;
};
&imx8_gpu_ss{
reg = <0x0 0x80000000 0x0 0x40000000>, <0x0 0x0 0x0 0x08000000>;
reg-names = "phys_baseaddr", "contiguous_mem";
};

2
arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi
View File

@ -2712,7 +2712,7 @@
clocks = <&clk IMX8QXP_GPU0_CORE_CLK>, <&clk IMX8QXP_GPU0_SHADER_CLK>;
clock-names = "core", "shader";
assigned-clocks = <&clk IMX8QXP_GPU0_CORE_CLK>, <&clk IMX8QXP_GPU0_SHADER_CLK>;
assigned-clock-rates = <700000000>, <850000000>;
assigned-clock-rates = <372000000>, <372000000>;
power-domains = <&pd_gpu0>;
status = "disabled";
};

24
arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi
View File

@ -490,24 +490,24 @@
#address-cells = <1>;
#size-cells = <0>;
pd_pcie1: PD_HSIO_PCIE_B {
reg = <SC_R_PCIE_B>;
pd_serdes1: PD_HSIO_SERDES_1 {
reg = <SC_R_SERDES_1>;
#power-domain-cells = <0>;
power-domains =<&pd_pcie0>;
#address-cells = <1>;
#size-cells = <0>;
pd_serdes1: PD_HSIO_SERDES_1 {
reg = <SC_R_SERDES_1>;
#power-domain-cells = <0>;
power-domains =<&pd_pcie1>;
#address-cells = <1>;
#size-cells = <0>;
pd_sata0: PD_HSIO_SATA_0 {
reg = <SC_R_SATA_0>;
pd_pcie1: PD_HSIO_PCIE_B {
reg = <SC_R_PCIE_B>;
#power-domain-cells = <0>;
power-domains =<&pd_serdes1>;
#address-cells = <1>;
#size-cells = <0>;
pd_sata0: PD_HSIO_SATA_0 {
reg = <SC_R_SATA_0>;
#power-domain-cells = <0>;
power-domains =<&pd_pcie1>;
};
};
};
@ -4118,7 +4118,7 @@
<0 0 0 2 &gic 0 74 4>,
<0 0 0 3 &gic 0 75 4>,
<0 0 0 4 &gic 0 76 4>;
power-domains = <&pd_pcie1>;
power-domains = <&pd_pcie0>;
fsl,max-link-speed = <3>;
hsio-cfg = <PCIEAX1PCIEBX1SATA>;
hsio = <&hsio>;

198
arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-rpmsg.dtsi Executable file → Normal file
View File

@ -13,200 +13,4 @@
*/
#include "fsl-imx8qxp-mek.dtsi"
/delete-node/ &i2c0_cm40;
/delete-node/ &i2c1;
&i2c_rpbus_1 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
typec_ptn5110: typec@50 {
compatible = "usb,tcpci";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_typec>;
reg = <0x50>;
interrupt-parent = <&gpio1>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
ss-sel-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
reset-gpios = <&pca9557_a 7 GPIO_ACTIVE_HIGH>;
src-pdos = <0x380190c8 0x3803c0c8>;
port-type = "drp";
sink-disable;
default-role = "source";
status = "okay";
};
};
&i2c_rpbus_5 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
wm8960: wm8960@1a {
compatible = "wlf,wm8960";
reg = <0x1a>;
clocks = <&clk IMX8QXP_AUD_MCLKOUT0>;
clock-names = "mclk";
wlf,shared-lrclk;
power-domains = <&pd_mclk_out0>;
assigned-clocks = <&clk IMX8QXP_AUD_PLL0_DIV>,
<&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>,
<&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>,
<&clk IMX8QXP_AUD_MCLKOUT0>;
assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>;
};
pca6416: gpio@20 {
compatible = "ti,tca6416";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
cs42888: cs42888@48 {
compatible = "cirrus,cs42888";
reg = <0x48>;
clocks = <&clk IMX8QXP_AUD_MCLKOUT0>;
clock-names = "mclk";
VA-supply = <&reg_audio>;
VD-supply = <&reg_audio>;
VLS-supply = <&reg_audio>;
VLC-supply = <&reg_audio>;
reset-gpio = <&pca9557_b 1 1>;
power-domains = <&pd_mclk_out0>;
assigned-clocks = <&clk IMX8QXP_AUD_PLL0_DIV>,
<&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>,
<&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>,
<&clk IMX8QXP_AUD_MCLKOUT0>;
assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>;
fsl,txs-rxm;
status = "okay";
};
ov5640: ov5640@3c {
compatible = "ovti,ov5640_v3";
reg = <0x3c>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_parallel_csi>;
clocks = <&clk IMX8QXP_PARALLEL_CSI_MISC0_CLK>;
clock-names = "csi_mclk";
pwn-gpios = <&gpio3 2 GPIO_ACTIVE_LOW>;
rst-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>;
csi_id = <0>;
mclk = <24000000>;
mclk_source = <0>;
status = "okay";
port {
ov5640_ep: endpoint {
remote-endpoint = <&parallel_csi_ep>;
};
};
};
};
&i2c_rpbus_12 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
max7322: gpio@68 {
compatible = "maxim,max7322";
reg = <0x68>;
gpio-controller;
#gpio-cells = <2>;
};
};
&i2c_rpbus_14 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
fxos8700@1e {
compatible = "fsl,fxos8700";
reg = <0x1e>;
interrupt-open-drain;
};
fxas2100x@21 {
compatible = "fsl,fxas2100x";
reg = <0x21>;
interrupt-open-drain;
};
mpl3115@60 {
compatible = "fsl,mpl3115";
reg = <0x60>;
interrupt-open-drain;
};
};
&i2c_rpbus_15 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
pca9557_a: gpio@1a {
compatible = "nxp,pca9557";
reg = <0x1a>;
gpio-controller;
#gpio-cells = <2>;
};
pca9557_b: gpio@1d {
compatible = "nxp,pca9557";
reg = <0x1d>;
gpio-controller;
#gpio-cells = <2>;
};
isl29023@44 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_isl29023>;
compatible = "fsl,isl29023";
reg = <0x44>;
rext = <499>;
interrupt-parent = <&gpio1>;
interrupts = <2 2>;
};
};
&rpmsg{
/*
* 64K for one rpmsg instance:
*/
vdev-nums = <2>;
reg = <0x0 0x90000000 0x0 0x20000>;
status = "okay";
};
&reg_can_en {
status = "disabled";
};
&reg_can_stby {
status = "disabled";
};
&intmux_cm40 {
status = "disabled";
};
&flexcan1 {
status = "disabled";
};
&flexcan2 {
status = "disabled";
};
&flexspi0 {
status = "disabled";
};
&lpuart3 {
status = "disabled";
};
#include "fsl-imx8x-mek-rpmsg.dtsi"

1376
arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dtsi Executable file → Normal file
View File

File diff suppressed because it is too large Load Diff

210
arch/arm64/boot/dts/freescale/fsl-imx8x-mek-rpmsg.dtsi Normal file
View File

@ -0,0 +1,210 @@
/*
* Copyright 2020 NXP
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/delete-node/ &i2c0_cm40;
/delete-node/ &i2c1;
&i2c_rpbus_1 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
typec_ptn5110: typec@50 {
compatible = "usb,tcpci";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_typec>;
reg = <0x50>;
interrupt-parent = <&gpio1>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
ss-sel-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
reset-gpios = <&pca9557_a 7 GPIO_ACTIVE_HIGH>;
src-pdos = <0x380190c8 0x3803c0c8>;
port-type = "drp";
sink-disable;
default-role = "source";
status = "okay";
};
};
&i2c_rpbus_5 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
wm8960: wm8960@1a {
compatible = "wlf,wm8960";
reg = <0x1a>;
clocks = <&clk IMX8QXP_AUD_MCLKOUT0>;
clock-names = "mclk";
wlf,shared-lrclk;
power-domains = <&pd_mclk_out0>;
assigned-clocks = <&clk IMX8QXP_AUD_PLL0_DIV>,
<&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>,
<&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>,
<&clk IMX8QXP_AUD_MCLKOUT0>;
assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>;
};
pca6416: gpio@20 {
compatible = "ti,tca6416";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
cs42888: cs42888@48 {
compatible = "cirrus,cs42888";
reg = <0x48>;
clocks = <&clk IMX8QXP_AUD_MCLKOUT0>;
clock-names = "mclk";
VA-supply = <&reg_audio>;
VD-supply = <&reg_audio>;
VLS-supply = <&reg_audio>;
VLC-supply = <&reg_audio>;
reset-gpio = <&pca9557_b 1 1>;
power-domains = <&pd_mclk_out0>;
assigned-clocks = <&clk IMX8QXP_AUD_PLL0_DIV>,
<&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>,
<&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>,
<&clk IMX8QXP_AUD_MCLKOUT0>;
assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>;
fsl,txs-rxm;
status = "okay";
};
ov5640: ov5640@3c {
compatible = "ovti,ov5640_v3";
reg = <0x3c>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_parallel_csi>;
clocks = <&clk IMX8QXP_PARALLEL_CSI_MISC0_CLK>;
clock-names = "csi_mclk";
pwn-gpios = <&gpio3 2 GPIO_ACTIVE_LOW>;
rst-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>;
csi_id = <0>;
mclk = <24000000>;
mclk_source = <0>;
status = "okay";
port {
ov5640_ep: endpoint {
remote-endpoint = <&parallel_csi_ep>;
};
};
};
};
&i2c_rpbus_12 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
max7322: gpio@68 {
compatible = "maxim,max7322";
reg = <0x68>;
gpio-controller;
#gpio-cells = <2>;
};
};
&i2c_rpbus_14 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
fxos8700@1e {
compatible = "fsl,fxos8700";
reg = <0x1e>;
interrupt-open-drain;
};
fxas2100x@21 {
compatible = "fsl,fxas2100x";
reg = <0x21>;
interrupt-open-drain;
};
mpl3115@60 {
compatible = "fsl,mpl3115";
reg = <0x60>;
interrupt-open-drain;
};
};
&i2c_rpbus_15 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
pca9557_a: gpio@1a {
compatible = "nxp,pca9557";
reg = <0x1a>;
gpio-controller;
#gpio-cells = <2>;
};
pca9557_b: gpio@1d {
compatible = "nxp,pca9557";
reg = <0x1d>;
gpio-controller;
#gpio-cells = <2>;
};
isl29023@44 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_isl29023>;
compatible = "fsl,isl29023";
reg = <0x44>;
rext = <499>;
interrupt-parent = <&gpio1>;
interrupts = <2 2>;
};
};
&rpmsg{
/*
* 64K for one rpmsg instance:
*/
vdev-nums = <2>;
reg = <0x0 0x90000000 0x0 0x20000>;
status = "okay";
};
&reg_can_en {
status = "disabled";
};
&reg_can_stby {
status = "disabled";
};
&intmux_cm40 {
status = "disabled";
};
&flexcan1 {
status = "disabled";
};
&flexcan2 {
status = "disabled";
};
&flexspi0 {
status = "disabled";
};
&lpuart3 {
status = "disabled";
};

1388
arch/arm64/boot/dts/freescale/fsl-imx8x-mek.dtsi Normal file
View File

File diff suppressed because it is too large Load Diff

2
arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
View File

@ -458,6 +458,8 @@
l11 {
regulator-min-microvolt = <1750000>;
regulator-max-microvolt = <3337000>;
regulator-allow-set-load;
regulator-system-load = <200000>;
};
l12 {

2
arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
View File

@ -262,6 +262,8 @@
l21 {
regulator-min-microvolt = <2950000>;
regulator-max-microvolt = <2950000>;
regulator-allow-set-load;
regulator-system-load = <200000>;
};
l22 {
regulator-min-microvolt = <3300000>;

5
arch/arm64/include/asm/kvm_mmu.h
View File

@ -296,6 +296,11 @@ static inline bool __kvm_cpu_uses_extended_idmap(void)
return __cpu_uses_extended_idmap();
}
/*
* Can't use pgd_populate here, because the extended idmap adds an extra level
* above CONFIG_PGTABLE_LEVELS (which is 2 or 3 if we're using the extended
* idmap), and pgd_populate is only available if CONFIG_PGTABLE_LEVELS = 4.
*/
static inline void __kvm_extend_hypmap(pgd_t *boot_hyp_pgd,
pgd_t *hyp_pgd,
pgd_t *merged_hyp_pgd,

1
arch/arm64/include/asm/pgtable.h
View File

@ -343,6 +343,7 @@ static inline int pmd_protnone(pmd_t pmd)
#define pud_write(pud) pte_write(pud_pte(pud))
#define pud_pfn(pud) (((pud_val(pud) & PUD_MASK) & PHYS_MASK) >> PAGE_SHIFT)
#define pfn_pud(pfn,prot) (__pud(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)))
#define set_pmd_at(mm, addr, pmdp, pmd) set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd))

17
arch/arm64/kernel/cpufeature.c
View File

@ -799,11 +799,6 @@ static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int _
MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
}
static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
{
return is_kernel_in_hyp_mode();
}
static bool hyp_offset_low(const struct arm64_cpu_capabilities *entry,
int __unused)
{
@ -841,6 +836,7 @@ static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
{ /* sentinel */ }
};
char const *str = "kpti command line option";
bool meltdown_safe;
@ -937,6 +933,12 @@ static int __init parse_kpti(char *str)
}
early_param("kpti", parse_kpti);
#ifdef CONFIG_ARM64_VHE
static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
{
return is_kernel_in_hyp_mode();
}
static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
{
/*
@ -950,6 +952,7 @@ static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
if (!alternatives_applied)
write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
}
#endif
#ifdef CONFIG_ARM64_SSBD
static int ssbs_emulation_handler(struct pt_regs *regs, u32 instr)
@ -1275,9 +1278,9 @@ static void __update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
static void update_cpu_capabilities(u16 scope_mask)
{
__update_cpu_capabilities(arm64_features, scope_mask, "detected:");
__update_cpu_capabilities(arm64_errata, scope_mask,
"enabling workaround for");
__update_cpu_capabilities(arm64_features, scope_mask, "detected:");
}
static int __enable_cpu_capability(void *arg)
@ -1332,8 +1335,8 @@ __enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
static void __init enable_cpu_capabilities(u16 scope_mask)
{
__enable_cpu_capabilities(arm64_features, scope_mask);
__enable_cpu_capabilities(arm64_errata, scope_mask);
__enable_cpu_capabilities(arm64_features, scope_mask);
}
/*

3
arch/arm64/kernel/hibernate.c
View File

@ -246,8 +246,7 @@ static int create_safe_exec_page(void *src_start, size_t length,
}
pte = pte_offset_kernel(pmd, dst_addr);
set_pte(pte, __pte(virt_to_phys((void *)dst) |
pgprot_val(PAGE_KERNEL_EXEC)));
set_pte(pte, pfn_pte(virt_to_pfn(dst), PAGE_KERNEL_EXEC));
/*
* Load our new page tables. A strict BBM approach requires that we

32
arch/arm64/mm/mmu.c
View File

@ -605,8 +605,8 @@ static void __init map_kernel(pgd_t *pgd)
* entry instead.
*/
BUG_ON(!IS_ENABLED(CONFIG_ARM64_16K_PAGES));
set_pud(pud_set_fixmap_offset(pgd, FIXADDR_START),
__pud(__pa_symbol(bm_pmd) | PUD_TYPE_TABLE));
pud_populate(&init_mm, pud_set_fixmap_offset(pgd, FIXADDR_START),
lm_alias(bm_pmd));
pud_clear_fixmap();
} else {
BUG();
@ -721,7 +721,7 @@ int __meminit vmemmap_populate(unsigned long start, unsigned long end, int node)
if (!p)
return -ENOMEM;
set_pmd(pmd, __pmd(__pa(p) | PROT_SECT_NORMAL));
pmd_set_huge(pmd, __pa(p), __pgprot(PROT_SECT_NORMAL));
} else
vmemmap_verify((pte_t *)pmd, node, addr, next);
} while (addr = next, addr != end);
@ -913,17 +913,35 @@ int __init arch_ioremap_pmd_supported(void)
return !IS_ENABLED(CONFIG_ARM64_PTDUMP_DEBUGFS);
}
int pud_set_huge(pud_t *pud, phys_addr_t phys, pgprot_t prot)
int pud_set_huge(pud_t *pudp, phys_addr_t phys, pgprot_t prot)
{
pgprot_t sect_prot = __pgprot(PUD_TYPE_SECT |
pgprot_val(mk_sect_prot(prot)));
pud_t new_pud = pfn_pud(__phys_to_pfn(phys), sect_prot);
/* Only allow permission changes for now */
if (!pgattr_change_is_safe(READ_ONCE(pud_val(*pudp)),
pud_val(new_pud)))
return 0;
BUG_ON(phys & ~PUD_MASK);
set_pud(pud, __pud(phys | PUD_TYPE_SECT | pgprot_val(mk_sect_prot(prot))));
set_pud(pudp, new_pud);
return 1;
}
int pmd_set_huge(pmd_t *pmd, phys_addr_t phys, pgprot_t prot)
int pmd_set_huge(pmd_t *pmdp, phys_addr_t phys, pgprot_t prot)
{
pgprot_t sect_prot = __pgprot(PMD_TYPE_SECT |
pgprot_val(mk_sect_prot(prot)));
pmd_t new_pmd = pfn_pmd(__phys_to_pfn(phys), sect_prot);
/* Only allow permission changes for now */
if (!pgattr_change_is_safe(READ_ONCE(pmd_val(*pmdp)),
pmd_val(new_pmd)))
return 0;
BUG_ON(phys & ~PMD_MASK);
set_pmd(pmd, __pmd(phys | PMD_TYPE_SECT | pgprot_val(mk_sect_prot(prot))));
set_pmd(pmdp, new_pmd);
return 1;
}

8
arch/hexagon/include/asm/atomic.h
View File

@ -105,7 +105,7 @@ static inline void atomic_##op(int i, atomic_t *v) \
"1: %0 = memw_locked(%1);\n" \
" %0 = "#op "(%0,%2);\n" \
" memw_locked(%1,P3)=%0;\n" \
" if !P3 jump 1b;\n" \
" if (!P3) jump 1b;\n" \
: "=&r" (output) \
: "r" (&v->counter), "r" (i) \
: "memory", "p3" \
@ -121,7 +121,7 @@ static inline int atomic_##op##_return(int i, atomic_t *v) \
"1: %0 = memw_locked(%1);\n" \
" %0 = "#op "(%0,%2);\n" \
" memw_locked(%1,P3)=%0;\n" \
" if !P3 jump 1b;\n" \
" if (!P3) jump 1b;\n" \
: "=&r" (output) \
: "r" (&v->counter), "r" (i) \
: "memory", "p3" \
@ -138,7 +138,7 @@ static inline int atomic_fetch_##op(int i, atomic_t *v) \
"1: %0 = memw_locked(%2);\n" \
" %1 = "#op "(%0,%3);\n" \
" memw_locked(%2,P3)=%1;\n" \
" if !P3 jump 1b;\n" \
" if (!P3) jump 1b;\n" \
: "=&r" (output), "=&r" (val) \
: "r" (&v->counter), "r" (i) \
: "memory", "p3" \
@ -187,7 +187,7 @@ static inline int __atomic_add_unless(atomic_t *v, int a, int u)
" }"
" memw_locked(%2, p3) = %1;"
" {"
" if !p3 jump 1b;"
" if (!p3) jump 1b;"
" }"
"2:"
: "=&r" (__oldval), "=&r" (tmp)

8
arch/hexagon/include/asm/bitops.h
View File

@ -52,7 +52,7 @@ static inline int test_and_clear_bit(int nr, volatile void *addr)
"1: R12 = memw_locked(R10);\n"
" { P0 = tstbit(R12,R11); R12 = clrbit(R12,R11); }\n"
" memw_locked(R10,P1) = R12;\n"
" {if !P1 jump 1b; %0 = mux(P0,#1,#0);}\n"
" {if (!P1) jump 1b; %0 = mux(P0,#1,#0);}\n"
: "=&r" (oldval)
: "r" (addr), "r" (nr)
: "r10", "r11", "r12", "p0", "p1", "memory"
@ -76,7 +76,7 @@ static inline int test_and_set_bit(int nr, volatile void *addr)
"1: R12 = memw_locked(R10);\n"
" { P0 = tstbit(R12,R11); R12 = setbit(R12,R11); }\n"
" memw_locked(R10,P1) = R12;\n"
" {if !P1 jump 1b; %0 = mux(P0,#1,#0);}\n"
" {if (!P1) jump 1b; %0 = mux(P0,#1,#0);}\n"
: "=&r" (oldval)
: "r" (addr), "r" (nr)
: "r10", "r11", "r12", "p0", "p1", "memory"
@ -102,7 +102,7 @@ static inline int test_and_change_bit(int nr, volatile void *addr)
"1: R12 = memw_locked(R10);\n"
" { P0 = tstbit(R12,R11); R12 = togglebit(R12,R11); }\n"
" memw_locked(R10,P1) = R12;\n"
" {if !P1 jump 1b; %0 = mux(P0,#1,#0);}\n"
" {if (!P1) jump 1b; %0 = mux(P0,#1,#0);}\n"
: "=&r" (oldval)
: "r" (addr), "r" (nr)
: "r10", "r11", "r12", "p0", "p1", "memory"
@ -237,7 +237,7 @@ static inline int ffs(int x)
int r;
asm("{ P0 = cmp.eq(%1,#0); %0 = ct0(%1);}\n"
"{ if P0 %0 = #0; if !P0 %0 = add(%0,#1);}\n"
"{ if (P0) %0 = #0; if (!P0) %0 = add(%0,#1);}\n"
: "=&r" (r)
: "r" (x)
: "p0");

2
arch/hexagon/include/asm/cmpxchg.h
View File

@ -44,7 +44,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
__asm__ __volatile__ (
"1: %0 = memw_locked(%1);\n" /* load into retval */
" memw_locked(%1,P0) = %2;\n" /* store into memory */
" if !P0 jump 1b;\n"
" if (!P0) jump 1b;\n"
: "=&r" (retval)
: "r" (ptr), "r" (x)
: "memory", "p0"

6
arch/hexagon/include/asm/futex.h
View File

@ -16,7 +16,7 @@
/* For example: %1 = %4 */ \
insn \
"2: memw_locked(%3,p2) = %1;\n" \
" if !p2 jump 1b;\n" \
" if (!p2) jump 1b;\n" \
" %1 = #0;\n" \
"3:\n" \
".section .fixup,\"ax\"\n" \
@ -84,10 +84,10 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, u32 oldval,
"1: %1 = memw_locked(%3)\n"
" {\n"
" p2 = cmp.eq(%1,%4)\n"
" if !p2.new jump:NT 3f\n"
" if (!p2.new) jump:NT 3f\n"
" }\n"
"2: memw_locked(%3,p2) = %5\n"
" if !p2 jump 1b\n"
" if (!p2) jump 1b\n"
"3:\n"
".section .fixup,\"ax\"\n"
"4: %0 = #%6\n"

20
arch/hexagon/include/asm/spinlock.h
View File

@ -44,9 +44,9 @@ static inline void arch_read_lock(arch_rwlock_t *lock)
__asm__ __volatile__(
"1: R6 = memw_locked(%0);\n"
" { P3 = cmp.ge(R6,#0); R6 = add(R6,#1);}\n"
" { if !P3 jump 1b; }\n"
" { if (!P3) jump 1b; }\n"
" memw_locked(%0,P3) = R6;\n"
" { if !P3 jump 1b; }\n"
" { if (!P3) jump 1b; }\n"
:
: "r" (&lock->lock)
: "memory", "r6", "p3"
@ -60,7 +60,7 @@ static inline void arch_read_unlock(arch_rwlock_t *lock)
"1: R6 = memw_locked(%0);\n"
" R6 = add(R6,#-1);\n"
" memw_locked(%0,P3) = R6\n"
" if !P3 jump 1b;\n"
" if (!P3) jump 1b;\n"
:
: "r" (&lock->lock)
: "memory", "r6", "p3"
@ -75,7 +75,7 @@ static inline int arch_read_trylock(arch_rwlock_t *lock)
__asm__ __volatile__(
" R6 = memw_locked(%1);\n"
" { %0 = #0; P3 = cmp.ge(R6,#0); R6 = add(R6,#1);}\n"
" { if !P3 jump 1f; }\n"
" { if (!P3) jump 1f; }\n"
" memw_locked(%1,P3) = R6;\n"
" { %0 = P3 }\n"
"1:\n"
@ -102,9 +102,9 @@ static inline void arch_write_lock(arch_rwlock_t *lock)
__asm__ __volatile__(
"1: R6 = memw_locked(%0)\n"
" { P3 = cmp.eq(R6,#0); R6 = #-1;}\n"
" { if !P3 jump 1b; }\n"
" { if (!P3) jump 1b; }\n"
" memw_locked(%0,P3) = R6;\n"
" { if !P3 jump 1b; }\n"
" { if (!P3) jump 1b; }\n"
:
: "r" (&lock->lock)
: "memory", "r6", "p3"
@ -118,7 +118,7 @@ static inline int arch_write_trylock(arch_rwlock_t *lock)
__asm__ __volatile__(
" R6 = memw_locked(%1)\n"
" { %0 = #0; P3 = cmp.eq(R6,#0); R6 = #-1;}\n"
" { if !P3 jump 1f; }\n"
" { if (!P3) jump 1f; }\n"
" memw_locked(%1,P3) = R6;\n"
" %0 = P3;\n"
"1:\n"
@ -141,9 +141,9 @@ static inline void arch_spin_lock(arch_spinlock_t *lock)
__asm__ __volatile__(
"1: R6 = memw_locked(%0);\n"
" P3 = cmp.eq(R6,#0);\n"
" { if !P3 jump 1b; R6 = #1; }\n"
" { if (!P3) jump 1b; R6 = #1; }\n"
" memw_locked(%0,P3) = R6;\n"
" { if !P3 jump 1b; }\n"
" { if (!P3) jump 1b; }\n"
:
: "r" (&lock->lock)
: "memory", "r6", "p3"
@ -163,7 +163,7 @@ static inline unsigned int arch_spin_trylock(arch_spinlock_t *lock)
__asm__ __volatile__(
" R6 = memw_locked(%1);\n"
" P3 = cmp.eq(R6,#0);\n"
" { if !P3 jump 1f; R6 = #1; %0 = #0; }\n"
" { if (!P3) jump 1f; R6 = #1; %0 = #0; }\n"
" memw_locked(%1,P3) = R6;\n"
" %0 = P3;\n"
"1:\n"

4
arch/hexagon/kernel/stacktrace.c
View File

@ -24,8 +24,6 @@
#include <linux/thread_info.h>
#include <linux/module.h>
register unsigned long current_frame_pointer asm("r30");
struct stackframe {
unsigned long fp;
unsigned long rets;
@ -43,7 +41,7 @@ void save_stack_trace(struct stack_trace *trace)
low = (unsigned long)task_stack_page(current);
high = low + THREAD_SIZE;
fp = current_frame_pointer;
fp = (unsigned long)__builtin_frame_address(0);
while (fp >= low && fp <= (high - sizeof(*frame))) {
frame = (struct stackframe *)fp;

2
arch/hexagon/kernel/vm_entry.S
View File

@ -382,7 +382,7 @@ ret_from_fork:
R26.L = #LO(do_work_pending);
R0 = #VM_INT_DISABLE;
}
if P0 jump check_work_pending
if (P0) jump check_work_pending
{
R0 = R25;
callr R24

9
arch/m68k/amiga/cia.c
View File

@ -88,10 +88,19 @@ static irqreturn_t cia_handler(int irq, void *dev_id)
struct ciabase *base = dev_id;
int mach_irq;
unsigned char ints;
unsigned long flags;
/* Interrupts get disabled while the timer irq flag is cleared and
* the timer interrupt serviced.
*/
mach_irq = base->cia_irq;
local_irq_save(flags);
ints = cia_set_irq(base, CIA_ICR_ALL);
amiga_custom.intreq = base->int_mask;
if (ints & 1)
generic_handle_irq(mach_irq);
local_irq_restore(flags);
mach_irq++, ints >>= 1;
for (; ints; mach_irq++, ints >>= 1) {
if (ints & 1)
generic_handle_irq(mach_irq);

4
arch/m68k/atari/ataints.c
View File

@ -142,7 +142,7 @@ struct mfptimerbase {
.name = "MFP Timer D"
};
static irqreturn_t mfptimer_handler(int irq, void *dev_id)
static irqreturn_t mfp_timer_d_handler(int irq, void *dev_id)
{
struct mfptimerbase *base = dev_id;
int mach_irq;
@ -344,7 +344,7 @@ void __init atari_init_IRQ(void)
st_mfp.tim_ct_cd = (st_mfp.tim_ct_cd & 0xf0) | 0x6;
/* request timer D dispatch handler */
if (request_irq(IRQ_MFP_TIMD, mfptimer_handler, IRQF_SHARED,
if (request_irq(IRQ_MFP_TIMD, mfp_timer_d_handler, IRQF_SHARED,
stmfp_base.name, &stmfp_base))
pr_err("Couldn't register %s interrupt\n", stmfp_base.name);

15
arch/m68k/atari/time.c
View File

@ -24,6 +24,18 @@
DEFINE_SPINLOCK(rtc_lock);
EXPORT_SYMBOL_GPL(rtc_lock);
static irqreturn_t mfp_timer_c_handler(int irq, void *dev_id)
{
irq_handler_t timer_routine = dev_id;
unsigned long flags;
local_irq_save(flags);
timer_routine(0, NULL);
local_irq_restore(flags);
return IRQ_HANDLED;
}
void __init
atari_sched_init(irq_handler_t timer_routine)
{
@ -32,7 +44,8 @@ atari_sched_init(irq_handler_t timer_routine)
/* start timer C, div = 1:100 */
st_mfp.tim_ct_cd = (st_mfp.tim_ct_cd & 15) | 0x60;
/* install interrupt service routine for MFP Timer C */
if (request_irq(IRQ_MFP_TIMC, timer_routine, 0, "timer", timer_routine))
if (request_irq(IRQ_MFP_TIMC, mfp_timer_c_handler, 0, "timer",
timer_routine))
pr_err("Couldn't register timer interrupt\n");
}

20
arch/m68k/bvme6000/config.c
View File

@ -45,11 +45,6 @@ extern int bvme6000_set_clock_mmss (unsigned long);
extern void bvme6000_reset (void);
void bvme6000_set_vectors (void);
/* Save tick handler routine pointer, will point to xtime_update() in
* kernel/timer/timekeeping.c, called via bvme6000_process_int() */
static irq_handler_t tick_handler;
int __init bvme6000_parse_bootinfo(const struct bi_record *bi)
{
@ -159,12 +154,18 @@ irqreturn_t bvme6000_abort_int (int irq, void *dev_id)
static irqreturn_t bvme6000_timer_int (int irq, void *dev_id)
{
irq_handler_t timer_routine = dev_id;
unsigned long flags;
volatile RtcPtr_t rtc = (RtcPtr_t)BVME_RTC_BASE;
unsigned char msr = rtc->msr & 0xc0;
unsigned char msr;
local_irq_save(flags);
msr = rtc->msr & 0xc0;
rtc->msr = msr | 0x20; /* Ack the interrupt */
timer_routine(0, NULL);
local_irq_restore(flags);
return tick_handler(irq, dev_id);
return IRQ_HANDLED;
}
/*
@ -183,9 +184,8 @@ void bvme6000_sched_init (irq_handler_t timer_routine)
rtc->msr = 0; /* Ensure timer registers accessible */
tick_handler = timer_routine;
if (request_irq(BVME_IRQ_RTC, bvme6000_timer_int, 0,
"timer", bvme6000_timer_int))
if (request_irq(BVME_IRQ_RTC, bvme6000_timer_int, 0, "timer",
timer_routine))
panic ("Couldn't register timer int");
rtc->t1cr_omr = 0x04; /* Mode 2, ext clk */

10
arch/m68k/hp300/time.c
View File

@ -38,13 +38,19 @@
static irqreturn_t hp300_tick(int irq, void *dev_id)
{
irq_handler_t timer_routine = dev_id;
unsigned long flags;
unsigned long tmp;
irq_handler_t vector = dev_id;
local_irq_save(flags);
in_8(CLOCKBASE + CLKSR);
asm volatile ("movpw %1@(5),%0" : "=d" (tmp) : "a" (CLOCKBASE));
timer_routine(0, NULL);
local_irq_restore(flags);
/* Turn off the network and SCSI leds */
blinken_leds(0, 0xe0);
return vector(irq, NULL);
return IRQ_HANDLED;
}
u32 hp300_gettimeoffset(void)

119
arch/m68k/mac/via.c
View File

@ -54,16 +54,6 @@ static __u8 rbv_clear;
static int gIER,gIFR,gBufA,gBufB;
/*
* Timer defs.
*/
#define TICK_SIZE 10000
#define MAC_CLOCK_TICK (783300/HZ) /* ticks per HZ */
#define MAC_CLOCK_LOW (MAC_CLOCK_TICK&0xFF)
#define MAC_CLOCK_HIGH (MAC_CLOCK_TICK>>8)
/*
* On Macs with a genuine VIA chip there is no way to mask an individual slot
* interrupt. This limitation also seems to apply to VIA clone logic cores in
@ -278,22 +268,6 @@ void __init via_init(void)
}
}
/*
* Start the 100 Hz clock
*/
void __init via_init_clock(irq_handler_t func)
{
via1[vACR] |= 0x40;
via1[vT1LL] = MAC_CLOCK_LOW;
via1[vT1LH] = MAC_CLOCK_HIGH;
via1[vT1CL] = MAC_CLOCK_LOW;
via1[vT1CH] = MAC_CLOCK_HIGH;
if (request_irq(IRQ_MAC_TIMER_1, func, 0, "timer", func))
pr_err("Couldn't register %s interrupt\n", "timer");
}
/*
* Debugging dump, used in various places to see what's going on.
*/
@ -321,29 +295,6 @@ void via_debug_dump(void)
}
}
/*
* This is always executed with interrupts disabled.
*
* TBI: get time offset between scheduling timer ticks
*/
u32 mac_gettimeoffset(void)
{
unsigned long ticks, offset = 0;
/* read VIA1 timer 2 current value */
ticks = via1[vT1CL] | (via1[vT1CH] << 8);
/* The probability of underflow is less than 2% */
if (ticks > MAC_CLOCK_TICK - MAC_CLOCK_TICK / 50)
/* Check for pending timer interrupt in VIA1 IFR */
if (via1[vIFR] & 0x40) offset = TICK_SIZE;
ticks = MAC_CLOCK_TICK - ticks;
ticks = ticks * 10000L / MAC_CLOCK_TICK;
return (ticks + offset) * 1000;
}
/*
* Flush the L2 cache on Macs that have it by flipping
* the system into 24-bit mode for an instant.
@ -447,6 +398,8 @@ void via_nubus_irq_shutdown(int irq)
* via6522.c :-), disable/pending masks added.
*/
#define VIA_TIMER_1_INT BIT(6)
void via1_irq(struct irq_desc *desc)
{
int irq_num;
@ -456,6 +409,21 @@ void via1_irq(struct irq_desc *desc)
if (!events)
return;
irq_num = IRQ_MAC_TIMER_1;
irq_bit = VIA_TIMER_1_INT;
if (events & irq_bit) {
unsigned long flags;
local_irq_save(flags);
via1[vIFR] = irq_bit;
generic_handle_irq(irq_num);
local_irq_restore(flags);
events &= ~irq_bit;
if (!events)
return;
}
irq_num = VIA1_SOURCE_BASE;
irq_bit = 1;
do {
@ -612,3 +580,56 @@ int via2_scsi_drq_pending(void)
return via2[gIFR] & (1 << IRQ_IDX(IRQ_MAC_SCSIDRQ));
}
EXPORT_SYMBOL(via2_scsi_drq_pending);
/* timer and clock source */
#define VIA_CLOCK_FREQ 783360 /* VIA "phase 2" clock in Hz */
#define VIA_TIMER_INTERVAL (1000000 / HZ) /* microseconds per jiffy */
#define VIA_TIMER_CYCLES (VIA_CLOCK_FREQ / HZ) /* clock cycles per jiffy */
#define VIA_TC (VIA_TIMER_CYCLES - 2) /* including 0 and -1 */
#define VIA_TC_LOW (VIA_TC & 0xFF)
#define VIA_TC_HIGH (VIA_TC >> 8)
void __init via_init_clock(irq_handler_t timer_routine)
{
if (request_irq(IRQ_MAC_TIMER_1, timer_routine, 0, "timer", NULL)) {
pr_err("Couldn't register %s interrupt\n", "timer");
return;
}
via1[vT1LL] = VIA_TC_LOW;
via1[vT1LH] = VIA_TC_HIGH;
via1[vT1CL] = VIA_TC_LOW;
via1[vT1CH] = VIA_TC_HIGH;
via1[vACR] |= 0x40;
}
u32 mac_gettimeoffset(void)
{
unsigned long flags;
u8 count_high;
u16 count, offset = 0;
/*
* Timer counter wrap-around is detected with the timer interrupt flag
* but reading the counter low byte (vT1CL) would reset the flag.
* Also, accessing both counter registers is essentially a data race.
* These problems are avoided by ignoring the low byte. Clock accuracy
* is 256 times worse (error can reach 0.327 ms) but CPU overhead is
* reduced by avoiding slow VIA register accesses.
*/
local_irq_save(flags);
count_high = via1[vT1CH];
if (count_high == 0xFF)
count_high = 0;
if (count_high > 0 && (via1[vIFR] & VIA_TIMER_1_INT))
offset = VIA_TIMER_CYCLES;
local_irq_restore(flags);
count = count_high << 8;
count = VIA_TIMER_CYCLES - count + offset;
return ((count * VIA_TIMER_INTERVAL) / VIA_TIMER_CYCLES) * 1000;
}

18
arch/m68k/mvme147/config.c
View File

@ -46,11 +46,6 @@ extern void mvme147_reset (void);
static int bcd2int (unsigned char b);
/* Save tick handler routine pointer, will point to xtime_update() in
* kernel/time/timekeeping.c, called via mvme147_process_int() */
irq_handler_t tick_handler;
int __init mvme147_parse_bootinfo(const struct bi_record *bi)
{
@ -106,16 +101,23 @@ void __init config_mvme147(void)
static irqreturn_t mvme147_timer_int (int irq, void *dev_id)
{
irq_handler_t timer_routine = dev_id;
unsigned long flags;
local_irq_save(flags);
m147_pcc->t1_int_cntrl = PCC_TIMER_INT_CLR;
m147_pcc->t1_int_cntrl = PCC_INT_ENAB|PCC_LEVEL_TIMER1;
return tick_handler(irq, dev_id);
timer_routine(0, NULL);
local_irq_restore(flags);
return IRQ_HANDLED;
}
void mvme147_sched_init (irq_handler_t timer_routine)
{
tick_handler = timer_routine;
if (request_irq(PCC_IRQ_TIMER1, mvme147_timer_int, 0, "timer 1", NULL))
if (request_irq(PCC_IRQ_TIMER1, mvme147_timer_int, 0, "timer 1",
timer_routine))
pr_err("Couldn't register timer interrupt\n");
/* Init the clock with a value */

21
arch/m68k/mvme16x/config.c
View File

@ -51,11 +51,6 @@ extern void mvme16x_reset (void);
int bcd2int (unsigned char b);
/* Save tick handler routine pointer, will point to xtime_update() in
* kernel/time/timekeeping.c, called via mvme16x_process_int() */
static irq_handler_t tick_handler;
unsigned short mvme16x_config;
EXPORT_SYMBOL(mvme16x_config);
@ -354,8 +349,15 @@ static irqreturn_t mvme16x_abort_int (int irq, void *dev_id)
static irqreturn_t mvme16x_timer_int (int irq, void *dev_id)
{
*(volatile unsigned char *)0xfff4201b |= 8;
return tick_handler(irq, dev_id);
irq_handler_t timer_routine = dev_id;
unsigned long flags;
local_irq_save(flags);
*(volatile unsigned char *)0xfff4201b |= 8;
timer_routine(0, NULL);
local_irq_restore(flags);
return IRQ_HANDLED;
}
void mvme16x_sched_init (irq_handler_t timer_routine)
@ -363,14 +365,13 @@ void mvme16x_sched_init (irq_handler_t timer_routine)
uint16_t brdno = be16_to_cpu(mvme_bdid.brdno);
int irq;
tick_handler = timer_routine;
/* Using PCCchip2 or MC2 chip tick timer 1 */
*(volatile unsigned long *)0xfff42008 = 0;
*(volatile unsigned long *)0xfff42004 = 10000; /* 10ms */
*(volatile unsigned char *)0xfff42017 |= 3;
*(volatile unsigned char *)0xfff4201b = 0x16;
if (request_irq(MVME16x_IRQ_TIMER, mvme16x_timer_int, 0,
"timer", mvme16x_timer_int))
if (request_irq(MVME16x_IRQ_TIMER, mvme16x_timer_int, 0, "timer",
timer_routine))
panic ("Couldn't register timer int");
if (brdno == 0x0162 || brdno == 0x172)

19
arch/m68k/q40/q40ints.c
View File

@ -127,10 +127,10 @@ void q40_mksound(unsigned int hz, unsigned int ticks)
sound_ticks = ticks << 1;
}
static irq_handler_t q40_timer_routine;
static irqreturn_t q40_timer_int (int irq, void * dev)
static irqreturn_t q40_timer_int(int irq, void *dev_id)
{
irq_handler_t timer_routine = dev_id;
ql_ticks = ql_ticks ? 0 : 1;
if (sound_ticks) {
unsigned char sval=(sound_ticks & 1) ? 128-SVOL : 128+SVOL;
@ -139,8 +139,13 @@ static irqreturn_t q40_timer_int (int irq, void * dev)
*DAC_RIGHT=sval;
}
if (!ql_ticks)
q40_timer_routine(irq, dev);
if (!ql_ticks) {
unsigned long flags;
local_irq_save(flags);
timer_routine(0, NULL);
local_irq_restore(flags);
}
return IRQ_HANDLED;
}
@ -148,11 +153,9 @@ void q40_sched_init (irq_handler_t timer_routine)
{
int timer_irq;
q40_timer_routine = timer_routine;
timer_irq = Q40_IRQ_FRAME;
if (request_irq(timer_irq, q40_timer_int, 0,
"timer", q40_timer_int))
if (request_irq(timer_irq, q40_timer_int, 0, "timer", timer_routine))
panic("Couldn't register timer int");
master_outb(-1, FRAME_CLEAR_REG);

3
arch/m68k/sun3/sun3ints.c
View File

@ -61,8 +61,10 @@ static irqreturn_t sun3_int7(int irq, void *dev_id)
static irqreturn_t sun3_int5(int irq, void *dev_id)
{
unsigned long flags;
unsigned int cnt;
local_irq_save(flags);
#ifdef CONFIG_SUN3
intersil_clear();
#endif
@ -76,6 +78,7 @@ static irqreturn_t sun3_int5(int irq, void *dev_id)
cnt = kstat_irqs_cpu(irq, 0);
if (!(cnt % 20))
sun3_leds(led_pattern[cnt % 160 / 20]);
local_irq_restore(flags);
return IRQ_HANDLED;
}

16
arch/m68k/sun3x/time.c
View File

@ -78,15 +78,19 @@ u32 sun3x_gettimeoffset(void)
}
#if 0
static void sun3x_timer_tick(int irq, void *dev_id, struct pt_regs *regs)
static irqreturn_t sun3x_timer_tick(int irq, void *dev_id)
{
void (*vector)(int, void *, struct pt_regs *) = dev_id;
irq_handler_t timer_routine = dev_id;
unsigned long flags;
/* Clear the pending interrupt - pulse the enable line low */
disable_irq(5);
enable_irq(5);
local_irq_save(flags);
/* Clear the pending interrupt - pulse the enable line low */
disable_irq(5);
enable_irq(5);
timer_routine(0, NULL);
local_irq_restore(flags);
vector(irq, NULL, regs);
return IRQ_HANDLED;
}
#endif

6
arch/mips/bcm63xx/Makefile
View File

@ -1,8 +1,8 @@
# SPDX-License-Identifier: GPL-2.0
obj-y += clk.o cpu.o cs.o gpio.o irq.o nvram.o prom.o reset.o \
setup.o timer.o dev-dsp.o dev-enet.o dev-flash.o \
dev-pcmcia.o dev-rng.o dev-spi.o dev-hsspi.o dev-uart.o \
dev-wdt.o dev-usb-usbd.o
setup.o timer.o dev-enet.o dev-flash.o dev-pcmcia.o \
dev-rng.o dev-spi.o dev-hsspi.o dev-uart.o dev-wdt.o \
dev-usb-usbd.o
obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
obj-y += boards/

20
arch/mips/bcm63xx/boards/board_bcm963xx.c
View File

@ -23,7 +23,6 @@
#include <bcm63xx_nvram.h>
#include <bcm63xx_dev_pci.h>
#include <bcm63xx_dev_enet.h>
#include <bcm63xx_dev_dsp.h>
#include <bcm63xx_dev_flash.h>
#include <bcm63xx_dev_hsspi.h>
#include <bcm63xx_dev_pcmcia.h>
@ -289,14 +288,6 @@ static struct board_info __initdata board_96348gw_10 = {
.has_pccard = 1,
.has_ehci0 = 1,
.has_dsp = 1,
.dsp = {
.gpio_rst = 6,
.gpio_int = 34,
.cs = 2,
.ext_irq = 2,
},
.leds = {
{
.name = "adsl-fail",
@ -401,14 +392,6 @@ static struct board_info __initdata board_96348gw = {
.has_ohci0 = 1,
.has_dsp = 1,
.dsp = {
.gpio_rst = 6,
.gpio_int = 34,
.ext_irq = 2,
.cs = 2,
},
.leds = {
{
.name = "adsl-fail",
@ -898,9 +881,6 @@ int __init board_register_devices(void)
if (board.has_usbd)
bcm63xx_usbd_register(&board.usbd);
if (board.has_dsp)
bcm63xx_dsp_register(&board.dsp);
/* Generate MAC address for WLAN and register our SPROM,
* do this after registering enet devices
*/

56
arch/mips/bcm63xx/dev-dsp.c
View File

@ -1,56 +0,0 @@
/*
* Broadcom BCM63xx VoIP DSP registration
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <bcm63xx_cpu.h>
#include <bcm63xx_dev_dsp.h>
#include <bcm63xx_regs.h>
#include <bcm63xx_io.h>
static struct resource voip_dsp_resources[] = {
{
.start = -1, /* filled at runtime */
.end = -1, /* filled at runtime */
.flags = IORESOURCE_MEM,
},
{
.start = -1, /* filled at runtime */
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device bcm63xx_voip_dsp_device = {
.name = "bcm63xx-voip-dsp",
.id = -1,
.num_resources = ARRAY_SIZE(voip_dsp_resources),
.resource = voip_dsp_resources,
};
int __init bcm63xx_dsp_register(const struct bcm63xx_dsp_platform_data *pd)
{
struct bcm63xx_dsp_platform_data *dpd;
u32 val;
/* Get the memory window */
val = bcm_mpi_readl(MPI_CSBASE_REG(pd->cs - 1));
val &= MPI_CSBASE_BASE_MASK;
voip_dsp_resources[0].start = val;
voip_dsp_resources[0].end = val + 0xFFFFFFF;
voip_dsp_resources[1].start = pd->ext_irq;
/* copy given platform data */
dpd = bcm63xx_voip_dsp_device.dev.platform_data;
memcpy(dpd, pd, sizeof (*pd));
return platform_device_register(&bcm63xx_voip_dsp_device);
}

3
arch/mips/boot/compressed/Makefile
View File

@ -29,6 +29,9 @@ KBUILD_AFLAGS := $(KBUILD_AFLAGS) -D__ASSEMBLY__ \
-DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE) \
-DKERNEL_ENTRY=$(VMLINUX_ENTRY_ADDRESS)
# Prevents link failures: __sanitizer_cov_trace_pc() is not linked in.
KCOV_INSTRUMENT := n
# decompressor objects (linked with vmlinuz)
vmlinuzobjs-y := $(obj)/head.o $(obj)/decompress.o $(obj)/string.o

14
arch/mips/include/asm/io.h
View File

@ -60,21 +60,11 @@
* instruction, so the lower 16 bits must be zero. Should be true on
* on any sane architecture; generic code does not use this assumption.
*/
extern const unsigned long mips_io_port_base;
extern unsigned long mips_io_port_base;
/*
* Gcc will generate code to load the value of mips_io_port_base after each
* function call which may be fairly wasteful in some cases. So we don't
* play quite by the book. We tell gcc mips_io_port_base is a long variable
* which solves the code generation issue. Now we need to violate the
* aliasing rules a little to make initialization possible and finally we
* will need the barrier() to fight side effects of the aliasing chat.
* This trickery will eventually collapse under gcc's optimizer. Oh well.
*/
static inline void set_io_port_base(unsigned long base)
{
* (unsigned long *) &mips_io_port_base = base;
barrier();
mips_io_port_base = base;
}
/*

14
arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_dsp.h
View File

@ -1,14 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __BCM63XX_DSP_H
#define __BCM63XX_DSP_H
struct bcm63xx_dsp_platform_data {
unsigned gpio_rst;
unsigned gpio_int;
unsigned cs;
unsigned ext_irq;
};
int __init bcm63xx_dsp_register(const struct bcm63xx_dsp_platform_data *pd);
#endif /* __BCM63XX_DSP_H */

5
arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
View File

@ -7,7 +7,6 @@
#include <linux/leds.h>
#include <bcm63xx_dev_enet.h>
#include <bcm63xx_dev_usb_usbd.h>
#include <bcm63xx_dev_dsp.h>
/*
* flash mapping
@ -31,7 +30,6 @@ struct board_info {
unsigned int has_ohci0:1;
unsigned int has_ehci0:1;
unsigned int has_usbd:1;
unsigned int has_dsp:1;
unsigned int has_uart0:1;
unsigned int has_uart1:1;
@ -43,9 +41,6 @@ struct board_info {
/* USB config */
struct bcm63xx_usbd_platform_data usbd;
/* DSP config */
struct bcm63xx_dsp_platform_data dsp;
/* GPIO LEDs */
struct gpio_led leds[5];

27
arch/mips/kernel/cacheinfo.c
View File

@ -61,6 +61,25 @@ static int __init_cache_level(unsigned int cpu)
return 0;
}
static void fill_cpumask_siblings(int cpu, cpumask_t *cpu_map)
{
int cpu1;
for_each_possible_cpu(cpu1)
if (cpus_are_siblings(cpu, cpu1))
cpumask_set_cpu(cpu1, cpu_map);
}
static void fill_cpumask_cluster(int cpu, cpumask_t *cpu_map)
{
int cpu1;
int cluster = cpu_cluster(&cpu_data[cpu]);
for_each_possible_cpu(cpu1)
if (cpu_cluster(&cpu_data[cpu1]) == cluster)
cpumask_set_cpu(cpu1, cpu_map);
}
static int __populate_cache_leaves(unsigned int cpu)
{
struct cpuinfo_mips *c = &current_cpu_data;
@ -68,14 +87,20 @@ static int __populate_cache_leaves(unsigned int cpu)
struct cacheinfo *this_leaf = this_cpu_ci->info_list;
if (c->icache.waysize) {
/* L1 caches are per core */
fill_cpumask_siblings(cpu, &this_leaf->shared_cpu_map);
populate_cache(dcache, this_leaf, 1, CACHE_TYPE_DATA);
fill_cpumask_siblings(cpu, &this_leaf->shared_cpu_map);
populate_cache(icache, this_leaf, 1, CACHE_TYPE_INST);
} else {
populate_cache(dcache, this_leaf, 1, CACHE_TYPE_UNIFIED);
}
if (c->scache.waysize)
if (c->scache.waysize) {
/* L2 cache is per cluster */
fill_cpumask_cluster(cpu, &this_leaf->shared_cpu_map);
populate_cache(scache, this_leaf, 2, CACHE_TYPE_UNIFIED);
}
if (c->tcache.waysize)
populate_cache(tcache, this_leaf, 3, CACHE_TYPE_UNIFIED);

2
arch/mips/kernel/setup.c
View File

@ -75,7 +75,7 @@ static char __initdata builtin_cmdline[COMMAND_LINE_SIZE] = CONFIG_CMDLINE;
* mips_io_port_base is the begin of the address space to which x86 style
* I/O ports are mapped.
*/
const unsigned long mips_io_port_base = -1;
unsigned long mips_io_port_base = -1;
EXPORT_SYMBOL(mips_io_port_base);
static struct resource code_resource = { .name = "Kernel code", };

12
arch/nios2/kernel/nios2_ksyms.c
View File

@ -9,12 +9,20 @@
#include <linux/export.h>
#include <linux/string.h>
#include <asm/cacheflush.h>
#include <asm/pgtable.h>
/* string functions */
EXPORT_SYMBOL(memcpy);
EXPORT_SYMBOL(memset);
EXPORT_SYMBOL(memmove);
/* memory management */
EXPORT_SYMBOL(empty_zero_page);
EXPORT_SYMBOL(flush_icache_range);
/*
* libgcc functions - functions that are used internally by the
* compiler... (prototypes are not correct though, but that
@ -31,3 +39,7 @@ DECLARE_EXPORT(__udivsi3);
DECLARE_EXPORT(__umoddi3);
DECLARE_EXPORT(__umodsi3);
DECLARE_EXPORT(__muldi3);
DECLARE_EXPORT(__ucmpdi2);
DECLARE_EXPORT(__lshrdi3);
DECLARE_EXPORT(__ashldi3);
DECLARE_EXPORT(__ashrdi3);

2
arch/powerpc/Makefile
View File

@ -385,7 +385,9 @@ vdso_install:
ifeq ($(CONFIG_PPC64),y)
$(Q)$(MAKE) $(build)=arch/$(ARCH)/kernel/vdso64 $@
endif
ifdef CONFIG_VDSO32
$(Q)$(MAKE) $(build)=arch/$(ARCH)/kernel/vdso32 $@
endif
archclean:
$(Q)$(MAKE) $(clean)=$(boot)

1
arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0-best-effort.dtsi
View File

@ -63,6 +63,7 @@ fman@400000 {
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xe1000 0x1000>;
fsl,erratum-a011043; /* must ignore read errors */
pcsphy0: ethernet-phy@0 {
reg = <0x0>;

1
arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi
View File

@ -60,6 +60,7 @@ fman@400000 {
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xf1000 0x1000>;
fsl,erratum-a011043; /* must ignore read errors */
pcsphy6: ethernet-phy@0 {
reg = <0x0>;

1
arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1-best-effort.dtsi
View File

@ -63,6 +63,7 @@ fman@400000 {
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xe3000 0x1000>;
fsl,erratum-a011043; /* must ignore read errors */
pcsphy1: ethernet-phy@0 {
reg = <0x0>;

1
arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi
View File

@ -60,6 +60,7 @@ fman@400000 {
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xf3000 0x1000>;
fsl,erratum-a011043; /* must ignore read errors */
pcsphy7: ethernet-phy@0 {
reg = <0x0>;

1
arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-0.dtsi
View File

@ -59,6 +59,7 @@ fman@400000 {
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xe1000 0x1000>;
fsl,erratum-a011043; /* must ignore read errors */
pcsphy0: ethernet-phy@0 {
reg = <0x0>;

1
arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-1.dtsi
View File

@ -59,6 +59,7 @@ fman@400000 {
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xe3000 0x1000>;
fsl,erratum-a011043; /* must ignore read errors */
pcsphy1: ethernet-phy@0 {
reg = <0x0>;

1
arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-2.dtsi
View File

@ -59,6 +59,7 @@ fman@400000 {
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xe5000 0x1000>;
fsl,erratum-a011043; /* must ignore read errors */
pcsphy2: ethernet-phy@0 {
reg = <0x0>;

1
arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-3.dtsi
View File

@ -59,6 +59,7 @@ fman@400000 {
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xe7000 0x1000>;
fsl,erratum-a011043; /* must ignore read errors */
pcsphy3: ethernet-phy@0 {
reg = <0x0>;

1
arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-4.dtsi
View File

@ -59,6 +59,7 @@ fman@400000 {
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xe9000 0x1000>;
fsl,erratum-a011043; /* must ignore read errors */
pcsphy4: ethernet-phy@0 {
reg = <0x0>;

1
arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-5.dtsi
View File

@ -59,6 +59,7 @@ fman@400000 {
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xeb000 0x1000>;
fsl,erratum-a011043; /* must ignore read errors */
pcsphy5: ethernet-phy@0 {
reg = <0x0>;

1
arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-0.dtsi
View File

@ -60,6 +60,7 @@ fman@500000 {
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xf1000 0x1000>;
fsl,erratum-a011043; /* must ignore read errors */
pcsphy14: ethernet-phy@0 {
reg = <0x0>;

1
arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-1.dtsi
View File

@ -60,6 +60,7 @@ fman@500000 {
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xf3000 0x1000>;
fsl,erratum-a011043; /* must ignore read errors */
pcsphy15: ethernet-phy@0 {
reg = <0x0>;

1
arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-0.dtsi
View File

@ -59,6 +59,7 @@ fman@500000 {
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xe1000 0x1000>;
fsl,erratum-a011043; /* must ignore read errors */
pcsphy8: ethernet-phy@0 {
reg = <0x0>;

1
arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-1.dtsi
View File

@ -59,6 +59,7 @@ fman@500000 {
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xe3000 0x1000>;
fsl,erratum-a011043; /* must ignore read errors */
pcsphy9: ethernet-phy@0 {
reg = <0x0>;

1
arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-2.dtsi
View File

@ -59,6 +59,7 @@ fman@500000 {
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xe5000 0x1000>;
fsl,erratum-a011043; /* must ignore read errors */
pcsphy10: ethernet-phy@0 {
reg = <0x0>;

Some files were not shown because too many files have changed in this diff Show More