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ARM: sunxi: Add the missing clocks to the pinctrl nodes
The pin controllers also use the two oscillators for debouncing. Add them to the DTs. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Chen-Yu Tsai <wens@csie.org>
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@ -967,7 +967,8 @@
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compatible = "allwinner,sun4i-a10-pinctrl";
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reg = <0x01c20800 0x400>;
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interrupts = <28>;
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clocks = <&apb0_gates 5>;
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clocks = <&apb0_gates 5>, <&osc24M>, <&osc32k>;
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clock-names = "apb", "hosc", "losc";
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <3>;
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@ -547,7 +547,8 @@
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pio: pinctrl@01c20800 {
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reg = <0x01c20800 0x400>;
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interrupts = <28>;
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clocks = <&apb0_gates 5>;
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clocks = <&apb0_gates 5>, <&osc24M>, <&osc32k>;
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clock-names = "apb", "hosc", "losc";
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <3>;
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@ -471,7 +471,8 @@
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<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_APB1_PIO>;
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clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&osc32k>;
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clock-names = "apb", "hosc", "losc";
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <3>;
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@ -1064,7 +1065,8 @@
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reg = <0x01f02c00 0x400>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&apb0_gates 0>;
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clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>;
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clock-names = "apb", "hosc", "losc";
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resets = <&apb0_rst 0>;
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gpio-controller;
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interrupt-controller;
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@ -1085,7 +1085,8 @@
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compatible = "allwinner,sun7i-a20-pinctrl";
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reg = <0x01c20800 0x400>;
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interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&apb0_gates 5>;
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clocks = <&apb0_gates 5>, <&osc24M>, <&osc32k>;
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clock-names = "apb", "hosc", "losc";
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <3>;
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@ -266,7 +266,8 @@
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/* compatible gets set in SoC specific dtsi file */
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reg = <0x01c20800 0x400>;
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/* interrupts get set in SoC specific dtsi file */
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clocks = <&ccu CLK_BUS_PIO>;
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clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
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clock-names = "apb", "hosc", "losc";
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <3>;
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@ -575,7 +576,8 @@
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compatible = "allwinner,sun8i-a23-r-pinctrl";
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reg = <0x01f02c00 0x400>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&apb0_gates 0>;
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clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>;
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clock-names = "apb", "hosc", "losc";
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resets = <&apb0_rst 0>;
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gpio-controller;
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interrupt-controller;
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@ -321,7 +321,8 @@
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reg = <0x01c20800 0x400>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_PIO>;
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clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
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clock-names = "apb", "hosc", "losc";
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gpio-controller;
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#gpio-cells = <3>;
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interrupt-controller;
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@ -614,7 +615,8 @@
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compatible = "allwinner,sun8i-h3-r-pinctrl";
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reg = <0x01f02c00 0x400>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&apb0_gates 0>;
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clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>;
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clock-names = "apb", "hosc", "losc";
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resets = <&apb0_reset 0>;
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gpio-controller;
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#gpio-cells = <3>;
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@ -678,7 +678,8 @@
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<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&apb0_gates 5>;
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clocks = <&apb0_gates 5>, <&osc24M>, <&osc32k>;
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clock-names = "apb", "hosc", "losc";
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <3>;
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@ -902,7 +903,8 @@
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reg = <0x08002c00 0x400>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&apbs_gates 0>;
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clocks = <&apbs_gates 0>, <&osc24M>, <&osc32k>;
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clock-names = "apb", "hosc", "losc";
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resets = <&apbs_rst 0>;
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gpio-controller;
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interrupt-controller;
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