drm/amdgpu: remove old CI DPM implementation
The power smu7 powerplay code is much more robust and has been the default for a while now. Remove the old code. Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher
parent
089888c468
commit
bc4b539e38
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@ -57,7 +57,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
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# add asic specific block
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amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \
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ci_smc.o ci_dpm.o dce_v8_0.o gfx_v7_0.o cik_sdma.o uvd_v4_2.o vce_v2_0.o
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dce_v8_0.o gfx_v7_0.o cik_sdma.o uvd_v4_2.o vce_v2_0.o
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amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce_v6_0.o si_dpm.o si_smc.o
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File diff suppressed because it is too large
Load Diff
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@ -1,349 +0,0 @@
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/*
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* Copyright 2013 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __CI_DPM_H__
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#define __CI_DPM_H__
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#include "amdgpu_atombios.h"
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#include "ppsmc.h"
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#define SMU__NUM_SCLK_DPM_STATE 8
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#define SMU__NUM_MCLK_DPM_LEVELS 6
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#define SMU__NUM_LCLK_DPM_LEVELS 8
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#define SMU__NUM_PCIE_DPM_LEVELS 8
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#include "smu7_discrete.h"
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#define CISLANDS_MAX_HARDWARE_POWERLEVELS 2
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#define CISLANDS_UNUSED_GPIO_PIN 0x7F
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struct ci_pl {
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u32 mclk;
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u32 sclk;
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enum amdgpu_pcie_gen pcie_gen;
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u16 pcie_lane;
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};
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struct ci_ps {
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u16 performance_level_count;
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bool dc_compatible;
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u32 sclk_t;
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struct ci_pl performance_levels[CISLANDS_MAX_HARDWARE_POWERLEVELS];
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};
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struct ci_dpm_level {
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bool enabled;
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u32 value;
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u32 param1;
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};
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#define CISLAND_MAX_DEEPSLEEP_DIVIDER_ID 5
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#define MAX_REGULAR_DPM_NUMBER 8
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#define CISLAND_MINIMUM_ENGINE_CLOCK 800
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struct ci_single_dpm_table {
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u32 count;
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struct ci_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];
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};
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struct ci_dpm_table {
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struct ci_single_dpm_table sclk_table;
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struct ci_single_dpm_table mclk_table;
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struct ci_single_dpm_table pcie_speed_table;
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struct ci_single_dpm_table vddc_table;
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struct ci_single_dpm_table vddci_table;
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struct ci_single_dpm_table mvdd_table;
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};
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struct ci_mc_reg_entry {
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u32 mclk_max;
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u32 mc_data[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
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};
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struct ci_mc_reg_table {
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u8 last;
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u8 num_entries;
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u16 valid_flag;
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struct ci_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES];
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SMU7_Discrete_MCRegisterAddress mc_reg_address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
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};
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struct ci_ulv_parm
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{
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bool supported;
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u32 cg_ulv_parameter;
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u32 volt_change_delay;
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struct ci_pl pl;
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};
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#define CISLANDS_MAX_LEAKAGE_COUNT 8
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struct ci_leakage_voltage {
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u16 count;
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u16 leakage_id[CISLANDS_MAX_LEAKAGE_COUNT];
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u16 actual_voltage[CISLANDS_MAX_LEAKAGE_COUNT];
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};
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struct ci_dpm_level_enable_mask {
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u32 uvd_dpm_enable_mask;
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u32 vce_dpm_enable_mask;
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u32 acp_dpm_enable_mask;
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u32 samu_dpm_enable_mask;
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u32 sclk_dpm_enable_mask;
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u32 mclk_dpm_enable_mask;
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u32 pcie_dpm_enable_mask;
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};
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struct ci_vbios_boot_state
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{
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u16 mvdd_bootup_value;
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u16 vddc_bootup_value;
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u16 vddci_bootup_value;
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u32 sclk_bootup_value;
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u32 mclk_bootup_value;
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u16 pcie_gen_bootup_value;
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u16 pcie_lane_bootup_value;
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};
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struct ci_clock_registers {
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u32 cg_spll_func_cntl;
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u32 cg_spll_func_cntl_2;
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u32 cg_spll_func_cntl_3;
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u32 cg_spll_func_cntl_4;
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u32 cg_spll_spread_spectrum;
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u32 cg_spll_spread_spectrum_2;
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u32 dll_cntl;
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u32 mclk_pwrmgt_cntl;
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u32 mpll_ad_func_cntl;
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u32 mpll_dq_func_cntl;
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u32 mpll_func_cntl;
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u32 mpll_func_cntl_1;
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u32 mpll_func_cntl_2;
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u32 mpll_ss1;
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u32 mpll_ss2;
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};
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struct ci_thermal_temperature_setting {
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s32 temperature_low;
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s32 temperature_high;
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s32 temperature_shutdown;
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};
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struct ci_pcie_perf_range {
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u16 max;
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u16 min;
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};
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enum ci_pt_config_reg_type {
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CISLANDS_CONFIGREG_MMR = 0,
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CISLANDS_CONFIGREG_SMC_IND,
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CISLANDS_CONFIGREG_DIDT_IND,
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CISLANDS_CONFIGREG_CACHE,
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CISLANDS_CONFIGREG_MAX
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};
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#define POWERCONTAINMENT_FEATURE_BAPM 0x00000001
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#define POWERCONTAINMENT_FEATURE_TDCLimit 0x00000002
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#define POWERCONTAINMENT_FEATURE_PkgPwrLimit 0x00000004
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struct ci_pt_config_reg {
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u32 offset;
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u32 mask;
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u32 shift;
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u32 value;
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enum ci_pt_config_reg_type type;
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};
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struct ci_pt_defaults {
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u8 svi_load_line_en;
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u8 svi_load_line_vddc;
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u8 tdc_vddc_throttle_release_limit_perc;
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u8 tdc_mawt;
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u8 tdc_waterfall_ctl;
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u8 dte_ambient_temp_base;
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u32 display_cac;
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u32 bapm_temp_gradient;
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u16 bapmti_r[SMU7_DTE_ITERATIONS * SMU7_DTE_SOURCES * SMU7_DTE_SINKS];
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u16 bapmti_rc[SMU7_DTE_ITERATIONS * SMU7_DTE_SOURCES * SMU7_DTE_SINKS];
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};
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#define DPMTABLE_OD_UPDATE_SCLK 0x00000001
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#define DPMTABLE_OD_UPDATE_MCLK 0x00000002
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#define DPMTABLE_UPDATE_SCLK 0x00000004
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#define DPMTABLE_UPDATE_MCLK 0x00000008
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struct ci_power_info {
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struct ci_dpm_table dpm_table;
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struct ci_dpm_table golden_dpm_table;
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u32 voltage_control;
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u32 mvdd_control;
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u32 vddci_control;
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u32 active_auto_throttle_sources;
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struct ci_clock_registers clock_registers;
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u16 acpi_vddc;
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u16 acpi_vddci;
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enum amdgpu_pcie_gen force_pcie_gen;
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enum amdgpu_pcie_gen acpi_pcie_gen;
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struct ci_leakage_voltage vddc_leakage;
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struct ci_leakage_voltage vddci_leakage;
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u16 max_vddc_in_pp_table;
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u16 min_vddc_in_pp_table;
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u16 max_vddci_in_pp_table;
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u16 min_vddci_in_pp_table;
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u32 mclk_strobe_mode_threshold;
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u32 mclk_stutter_mode_threshold;
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u32 mclk_edc_enable_threshold;
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u32 mclk_edc_wr_enable_threshold;
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struct ci_vbios_boot_state vbios_boot_state;
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/* smc offsets */
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u32 sram_end;
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u32 dpm_table_start;
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u32 soft_regs_start;
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u32 mc_reg_table_start;
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u32 fan_table_start;
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u32 arb_table_start;
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/* smc tables */
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SMU7_Discrete_DpmTable smc_state_table;
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SMU7_Discrete_MCRegisters smc_mc_reg_table;
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SMU7_Discrete_PmFuses smc_powertune_table;
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/* other stuff */
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struct ci_mc_reg_table mc_reg_table;
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struct atom_voltage_table vddc_voltage_table;
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struct atom_voltage_table vddci_voltage_table;
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struct atom_voltage_table mvdd_voltage_table;
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struct ci_ulv_parm ulv;
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u32 power_containment_features;
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const struct ci_pt_defaults *powertune_defaults;
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u32 dte_tj_offset;
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bool vddc_phase_shed_control;
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struct ci_thermal_temperature_setting thermal_temp_setting;
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struct ci_dpm_level_enable_mask dpm_level_enable_mask;
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u32 need_update_smu7_dpm_table;
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u32 sclk_dpm_key_disabled;
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u32 mclk_dpm_key_disabled;
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u32 pcie_dpm_key_disabled;
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u32 thermal_sclk_dpm_enabled;
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struct ci_pcie_perf_range pcie_gen_performance;
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struct ci_pcie_perf_range pcie_lane_performance;
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struct ci_pcie_perf_range pcie_gen_powersaving;
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struct ci_pcie_perf_range pcie_lane_powersaving;
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u32 activity_target[SMU7_MAX_LEVELS_GRAPHICS];
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u32 mclk_activity_target;
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u32 low_sclk_interrupt_t;
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u32 last_mclk_dpm_enable_mask;
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u32 sys_pcie_mask;
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/* caps */
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bool caps_power_containment;
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bool caps_cac;
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bool caps_sq_ramping;
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bool caps_db_ramping;
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bool caps_td_ramping;
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bool caps_tcp_ramping;
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bool caps_fps;
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bool caps_sclk_ds;
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bool caps_sclk_ss_support;
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bool caps_mclk_ss_support;
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bool caps_uvd_dpm;
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bool caps_vce_dpm;
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bool caps_samu_dpm;
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bool caps_acp_dpm;
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bool caps_automatic_dc_transition;
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bool caps_sclk_throttle_low_notification;
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bool caps_dynamic_ac_timing;
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bool caps_od_fuzzy_fan_control_support;
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/* flags */
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bool thermal_protection;
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bool pcie_performance_request;
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bool dynamic_ss;
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bool dll_default_on;
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bool cac_enabled;
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bool uvd_enabled;
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bool battery_state;
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bool pspp_notify_required;
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bool enable_bapm_feature;
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bool enable_tdc_limit_feature;
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bool enable_pkg_pwr_tracking_feature;
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bool use_pcie_performance_levels;
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bool use_pcie_powersaving_levels;
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bool uvd_power_gated;
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/* driver states */
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struct amdgpu_ps current_rps;
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struct ci_ps current_ps;
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struct amdgpu_ps requested_rps;
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struct ci_ps requested_ps;
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/* fan control */
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bool fan_ctrl_is_in_default_mode;
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bool fan_is_controlled_by_smc;
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u32 t_min;
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u32 fan_ctrl_default_mode;
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};
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#define CISLANDS_VOLTAGE_CONTROL_NONE 0x0
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#define CISLANDS_VOLTAGE_CONTROL_BY_GPIO 0x1
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#define CISLANDS_VOLTAGE_CONTROL_BY_SVID2 0x2
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#define CISLANDS_Q88_FORMAT_CONVERSION_UNIT 256
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#define CISLANDS_VRC_DFLT0 0x3FFFC000
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#define CISLANDS_VRC_DFLT1 0x000400
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#define CISLANDS_VRC_DFLT2 0xC00080
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#define CISLANDS_VRC_DFLT3 0xC00200
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#define CISLANDS_VRC_DFLT4 0xC01680
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#define CISLANDS_VRC_DFLT5 0xC00033
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#define CISLANDS_VRC_DFLT6 0xC00033
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#define CISLANDS_VRC_DFLT7 0x3FFFC000
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#define CISLANDS_CGULVPARAMETER_DFLT 0x00040035
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#define CISLAND_TARGETACTIVITY_DFLT 30
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#define CISLAND_MCLK_TARGETACTIVITY_DFLT 10
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#define PCIE_PERF_REQ_REMOVE_REGISTRY 0
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#define PCIE_PERF_REQ_FORCE_LOWPOWER 1
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#define PCIE_PERF_REQ_PECI_GEN1 2
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#define PCIE_PERF_REQ_PECI_GEN2 3
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#define PCIE_PERF_REQ_PECI_GEN3 4
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#define CISLANDS_SSTU_DFLT 0
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#define CISLANDS_SST_DFLT 0x00C8
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/* XXX are these ok? */
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#define CISLANDS_TEMP_RANGE_MIN (90 * 1000)
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#define CISLANDS_TEMP_RANGE_MAX (120 * 1000)
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int amdgpu_ci_copy_bytes_to_smc(struct amdgpu_device *adev,
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u32 smc_start_address,
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const u8 *src, u32 byte_count, u32 limit);
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void amdgpu_ci_start_smc(struct amdgpu_device *adev);
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void amdgpu_ci_reset_smc(struct amdgpu_device *adev);
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int amdgpu_ci_program_jump_on_start(struct amdgpu_device *adev);
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void amdgpu_ci_stop_smc_clock(struct amdgpu_device *adev);
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void amdgpu_ci_start_smc_clock(struct amdgpu_device *adev);
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bool amdgpu_ci_is_smc_running(struct amdgpu_device *adev);
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PPSMC_Result amdgpu_ci_send_msg_to_smc(struct amdgpu_device *adev, PPSMC_Msg msg);
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PPSMC_Result amdgpu_ci_wait_for_smc_inactive(struct amdgpu_device *adev);
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int amdgpu_ci_load_smc_ucode(struct amdgpu_device *adev, u32 limit);
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int amdgpu_ci_read_smc_sram_dword(struct amdgpu_device *adev,
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u32 smc_address, u32 *value, u32 limit);
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int amdgpu_ci_write_smc_sram_dword(struct amdgpu_device *adev,
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u32 smc_address, u32 value, u32 limit);
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#endif
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@ -1,279 +0,0 @@
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/*
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* Copyright 2011 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
|
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* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Alex Deucher
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*/
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#include <linux/firmware.h>
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#include <drm/drmP.h>
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#include "amdgpu.h"
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#include "cikd.h"
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#include "ppsmc.h"
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#include "amdgpu_ucode.h"
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#include "ci_dpm.h"
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#include "smu/smu_7_0_1_d.h"
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#include "smu/smu_7_0_1_sh_mask.h"
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static int ci_set_smc_sram_address(struct amdgpu_device *adev,
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u32 smc_address, u32 limit)
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{
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if (smc_address & 3)
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return -EINVAL;
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if ((smc_address + 3) > limit)
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return -EINVAL;
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WREG32(mmSMC_IND_INDEX_0, smc_address);
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WREG32_P(mmSMC_IND_ACCESS_CNTL, 0, ~SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK);
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return 0;
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}
|
||||
|
||||
int amdgpu_ci_copy_bytes_to_smc(struct amdgpu_device *adev,
|
||||
u32 smc_start_address,
|
||||
const u8 *src, u32 byte_count, u32 limit)
|
||||
{
|
||||
unsigned long flags;
|
||||
u32 data, original_data;
|
||||
u32 addr;
|
||||
u32 extra_shift;
|
||||
int ret = 0;
|
||||
|
||||
if (smc_start_address & 3)
|
||||
return -EINVAL;
|
||||
if ((smc_start_address + byte_count) > limit)
|
||||
return -EINVAL;
|
||||
|
||||
addr = smc_start_address;
|
||||
|
||||
spin_lock_irqsave(&adev->smc_idx_lock, flags);
|
||||
while (byte_count >= 4) {
|
||||
/* SMC address space is BE */
|
||||
data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3];
|
||||
|
||||
ret = ci_set_smc_sram_address(adev, addr, limit);
|
||||
if (ret)
|
||||
goto done;
|
||||
|
||||
WREG32(mmSMC_IND_DATA_0, data);
|
||||
|
||||
src += 4;
|
||||
byte_count -= 4;
|
||||
addr += 4;
|
||||
}
|
||||
|
||||
/* RMW for the final bytes */
|
||||
if (byte_count > 0) {
|
||||
data = 0;
|
||||
|
||||
ret = ci_set_smc_sram_address(adev, addr, limit);
|
||||
if (ret)
|
||||
goto done;
|
||||
|
||||
original_data = RREG32(mmSMC_IND_DATA_0);
|
||||
|
||||
extra_shift = 8 * (4 - byte_count);
|
||||
|
||||
while (byte_count > 0) {
|
||||
data = (data << 8) + *src++;
|
||||
byte_count--;
|
||||
}
|
||||
|
||||
data <<= extra_shift;
|
||||
|
||||
data |= (original_data & ~((~0UL) << extra_shift));
|
||||
|
||||
ret = ci_set_smc_sram_address(adev, addr, limit);
|
||||
if (ret)
|
||||
goto done;
|
||||
|
||||
WREG32(mmSMC_IND_DATA_0, data);
|
||||
}
|
||||
|
||||
done:
|
||||
spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
void amdgpu_ci_start_smc(struct amdgpu_device *adev)
|
||||
{
|
||||
u32 tmp = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL);
|
||||
|
||||
tmp &= ~SMC_SYSCON_RESET_CNTL__rst_reg_MASK;
|
||||
WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, tmp);
|
||||
}
|
||||
|
||||
void amdgpu_ci_reset_smc(struct amdgpu_device *adev)
|
||||
{
|
||||
u32 tmp = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL);
|
||||
|
||||
tmp |= SMC_SYSCON_RESET_CNTL__rst_reg_MASK;
|
||||
WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, tmp);
|
||||
}
|
||||
|
||||
int amdgpu_ci_program_jump_on_start(struct amdgpu_device *adev)
|
||||
{
|
||||
static u8 data[] = { 0xE0, 0x00, 0x80, 0x40 };
|
||||
|
||||
return amdgpu_ci_copy_bytes_to_smc(adev, 0x0, data, 4, sizeof(data)+1);
|
||||
}
|
||||
|
||||
void amdgpu_ci_stop_smc_clock(struct amdgpu_device *adev)
|
||||
{
|
||||
u32 tmp = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
|
||||
|
||||
tmp |= SMC_SYSCON_CLOCK_CNTL_0__ck_disable_MASK;
|
||||
|
||||
WREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0, tmp);
|
||||
}
|
||||
|
||||
void amdgpu_ci_start_smc_clock(struct amdgpu_device *adev)
|
||||
{
|
||||
u32 tmp = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
|
||||
|
||||
tmp &= ~SMC_SYSCON_CLOCK_CNTL_0__ck_disable_MASK;
|
||||
|
||||
WREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0, tmp);
|
||||
}
|
||||
|
||||
bool amdgpu_ci_is_smc_running(struct amdgpu_device *adev)
|
||||
{
|
||||
u32 clk = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
|
||||
u32 pc_c = RREG32_SMC(ixSMC_PC_C);
|
||||
|
||||
if (!(clk & SMC_SYSCON_CLOCK_CNTL_0__ck_disable_MASK) && (0x20100 <= pc_c))
|
||||
return true;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
PPSMC_Result amdgpu_ci_send_msg_to_smc(struct amdgpu_device *adev, PPSMC_Msg msg)
|
||||
{
|
||||
u32 tmp;
|
||||
int i;
|
||||
|
||||
if (!amdgpu_ci_is_smc_running(adev))
|
||||
return PPSMC_Result_Failed;
|
||||
|
||||
WREG32(mmSMC_MESSAGE_0, msg);
|
||||
|
||||
for (i = 0; i < adev->usec_timeout; i++) {
|
||||
tmp = RREG32(mmSMC_RESP_0);
|
||||
if (tmp != 0)
|
||||
break;
|
||||
udelay(1);
|
||||
}
|
||||
tmp = RREG32(mmSMC_RESP_0);
|
||||
|
||||
return (PPSMC_Result)tmp;
|
||||
}
|
||||
|
||||
PPSMC_Result amdgpu_ci_wait_for_smc_inactive(struct amdgpu_device *adev)
|
||||
{
|
||||
u32 tmp;
|
||||
int i;
|
||||
|
||||
if (!amdgpu_ci_is_smc_running(adev))
|
||||
return PPSMC_Result_OK;
|
||||
|
||||
for (i = 0; i < adev->usec_timeout; i++) {
|
||||
tmp = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
|
||||
if ((tmp & SMC_SYSCON_CLOCK_CNTL_0__cken_MASK) == 0)
|
||||
break;
|
||||
udelay(1);
|
||||
}
|
||||
|
||||
return PPSMC_Result_OK;
|
||||
}
|
||||
|
||||
int amdgpu_ci_load_smc_ucode(struct amdgpu_device *adev, u32 limit)
|
||||
{
|
||||
const struct smc_firmware_header_v1_0 *hdr;
|
||||
unsigned long flags;
|
||||
u32 ucode_start_address;
|
||||
u32 ucode_size;
|
||||
const u8 *src;
|
||||
u32 data;
|
||||
|
||||
if (!adev->pm.fw)
|
||||
return -EINVAL;
|
||||
|
||||
hdr = (const struct smc_firmware_header_v1_0 *)adev->pm.fw->data;
|
||||
amdgpu_ucode_print_smc_hdr(&hdr->header);
|
||||
|
||||
adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
|
||||
ucode_start_address = le32_to_cpu(hdr->ucode_start_addr);
|
||||
ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes);
|
||||
src = (const u8 *)
|
||||
(adev->pm.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
|
||||
|
||||
if (ucode_size & 3)
|
||||
return -EINVAL;
|
||||
|
||||
spin_lock_irqsave(&adev->smc_idx_lock, flags);
|
||||
WREG32(mmSMC_IND_INDEX_0, ucode_start_address);
|
||||
WREG32_P(mmSMC_IND_ACCESS_CNTL, SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK,
|
||||
~SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK);
|
||||
while (ucode_size >= 4) {
|
||||
/* SMC address space is BE */
|
||||
data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3];
|
||||
|
||||
WREG32(mmSMC_IND_DATA_0, data);
|
||||
|
||||
src += 4;
|
||||
ucode_size -= 4;
|
||||
}
|
||||
WREG32_P(mmSMC_IND_ACCESS_CNTL, 0, ~SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK);
|
||||
spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int amdgpu_ci_read_smc_sram_dword(struct amdgpu_device *adev,
|
||||
u32 smc_address, u32 *value, u32 limit)
|
||||
{
|
||||
unsigned long flags;
|
||||
int ret;
|
||||
|
||||
spin_lock_irqsave(&adev->smc_idx_lock, flags);
|
||||
ret = ci_set_smc_sram_address(adev, smc_address, limit);
|
||||
if (ret == 0)
|
||||
*value = RREG32(mmSMC_IND_DATA_0);
|
||||
spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int amdgpu_ci_write_smc_sram_dword(struct amdgpu_device *adev,
|
||||
u32 smc_address, u32 value, u32 limit)
|
||||
{
|
||||
unsigned long flags;
|
||||
int ret;
|
||||
|
||||
spin_lock_irqsave(&adev->smc_idx_lock, flags);
|
||||
ret = ci_set_smc_sram_address(adev, smc_address, limit);
|
||||
if (ret == 0)
|
||||
WREG32(mmSMC_IND_DATA_0, value);
|
||||
spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -2070,10 +2070,7 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
|
|||
amdgpu_device_ip_block_add(adev, &cik_ih_ip_block);
|
||||
amdgpu_device_ip_block_add(adev, &gfx_v7_2_ip_block);
|
||||
amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block);
|
||||
if (amdgpu_dpm == -1)
|
||||
amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
|
||||
else
|
||||
amdgpu_device_ip_block_add(adev, &ci_smu_ip_block);
|
||||
amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
|
||||
if (adev->enable_virtual_display)
|
||||
amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
|
||||
#if defined(CONFIG_DRM_AMD_DC)
|
||||
|
|
@ -2091,10 +2088,7 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
|
|||
amdgpu_device_ip_block_add(adev, &cik_ih_ip_block);
|
||||
amdgpu_device_ip_block_add(adev, &gfx_v7_3_ip_block);
|
||||
amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block);
|
||||
if (amdgpu_dpm == -1)
|
||||
amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
|
||||
else
|
||||
amdgpu_device_ip_block_add(adev, &ci_smu_ip_block);
|
||||
amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
|
||||
if (adev->enable_virtual_display)
|
||||
amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
|
||||
#if defined(CONFIG_DRM_AMD_DC)
|
||||
|
|
|
|||
|
|
@ -24,7 +24,6 @@
|
|||
#ifndef __CIK_DPM_H__
|
||||
#define __CIK_DPM_H__
|
||||
|
||||
extern const struct amdgpu_ip_block_version ci_smu_ip_block;
|
||||
extern const struct amdgpu_ip_block_version kv_smu_ip_block;
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue