kbuild: remove empty rules for makefiles

The previous commit made 'MAKEFLAGS += -rR' effective in the top
Makefile regardless of O= option, GNU Make versions.

The top Makefile does not need to cancel implicit rules for makefiles.

There is still one place where an empty rule is useful. Since -rR is
effective only after sub-make, GNU Make would try implicit rules to
update the top Makefile. Although it is not a big overhead, cancel it
just in case.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This commit is contained in:
Masahiro Yamada 2019-02-22 16:40:08 +09:00
parent 3812b8c5c5
commit b999923c29

View File

@ -37,6 +37,10 @@ ifneq ($(sub-make-done),1)
# (this increases performance and avoids hard-to-debug behaviour)
MAKEFLAGS += -rR
# 'MAKEFLAGS += -rR' does not become immediately effective for old
# GNU Make versions. Cancel implicit rules for this Makefile.
$(lastword $(MAKEFILE_LIST)): ;
# Avoid funny character set dependencies
unexport LC_ALL
LC_COLLATE=C
@ -120,9 +124,6 @@ ifeq ("$(origin O)", "command line")
KBUILD_OUTPUT := $(O)
endif
# Cancel implicit rules on top Makefile
$(CURDIR)/Makefile Makefile: ;
ifneq ($(words $(subst :, ,$(CURDIR))), 1)
$(error main directory cannot contain spaces nor colons)
endif
@ -303,8 +304,6 @@ __build_one_by_one:
else
# We need some generic definitions (do not try to remake the file).
scripts/Kbuild.include: ;
include scripts/Kbuild.include
# Read KERNELRELEASE from include/config/kernel.release (if it exists)
@ -1760,9 +1759,7 @@ cmd_crmodverdir = $(Q)mkdir -p $(MODVERDIR) \
# read saved command lines for existing targets
existing-targets := $(wildcard $(sort $(targets)))
cmd_files := $(foreach f,$(existing-targets),$(dir $(f)).$(notdir $(f)).cmd)
$(cmd_files): ; # Do not try to update included dependency files
-include $(cmd_files)
-include $(foreach f,$(existing-targets),$(dir $(f)).$(notdir $(f)).cmd)
endif # ifeq ($(config-targets),1)
endif # ifeq ($(mixed-targets),1)