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ARM: dts: ls1021a: update the clockgen node
qoriq clock driver has been updated to parse the clock configuration information defined in driver itself not in dts. Since the new implementation and the bindings have been merged, it is time to update the clock related node and remove redundent clock configuration information from the dts. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Yuantian Tang
Shawn Guo
parent
ad8046a56d
commit
b6f5e70193
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@ -75,7 +75,7 @@
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0xf00>;
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clocks = <&cluster1_clk>;
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clocks = <&clockgen 1 0>;
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#cooling-cells = <2>;
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};
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@ -83,10 +83,17 @@
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0xf01>;
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clocks = <&cluster1_clk>;
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clocks = <&clockgen 1 0>;
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};
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};
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sysclk: sysclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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clock-output-names = "sysclk";
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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@ -165,7 +172,7 @@
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<0x0 0x20220520 0x0 0x4>;
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reg-names = "ahci", "sata-ecc";
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interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&platform_clk 1>;
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clocks = <&clockgen 4 1>;
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dma-coherent;
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status = "disabled";
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};
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@ -216,41 +223,10 @@
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};
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clockgen: clocking@1ee1000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x1ee1000 0x10000>;
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sysclk: sysclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-output-names = "sysclk";
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};
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cga_pll1: pll@800 {
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compatible = "fsl,qoriq-core-pll-2.0";
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#clock-cells = <1>;
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reg = <0x800 0x10>;
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clocks = <&sysclk>;
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clock-output-names = "cga-pll1", "cga-pll1-div2",
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"cga-pll1-div4";
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};
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platform_clk: pll@c00 {
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compatible = "fsl,qoriq-core-pll-2.0";
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#clock-cells = <1>;
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reg = <0xc00 0x10>;
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clocks = <&sysclk>;
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clock-output-names = "platform-clk", "platform-clk-div2";
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};
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cluster1_clk: clk0c0@0 {
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compatible = "fsl,qoriq-core-mux-2.0";
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#clock-cells = <0>;
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reg = <0x0 0x10>;
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clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4";
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clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>;
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clock-output-names = "cluster1-clk";
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};
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compatible = "fsl,ls1021a-clockgen";
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reg = <0x0 0x1ee1000 0x0 0x1000>;
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#clock-cells = <2>;
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clocks = <&sysclk>;
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};
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tmu: tmu@1f00000 {
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@ -338,7 +314,7 @@
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reg = <0x0 0x2100000 0x0 0x10000>;
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "dspi";
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clocks = <&platform_clk 1>;
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clocks = <&clockgen 4 1>;
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spi-num-chipselects = <6>;
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big-endian;
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status = "disabled";
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@ -351,7 +327,7 @@
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reg = <0x0 0x2110000 0x0 0x10000>;
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interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "dspi";
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clocks = <&platform_clk 1>;
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clocks = <&clockgen 4 1>;
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spi-num-chipselects = <6>;
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big-endian;
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status = "disabled";
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@ -364,7 +340,7 @@
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reg = <0x0 0x2180000 0x0 0x10000>;
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interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "i2c";
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clocks = <&platform_clk 1>;
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clocks = <&clockgen 4 1>;
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status = "disabled";
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};
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@ -375,7 +351,7 @@
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reg = <0x0 0x2190000 0x0 0x10000>;
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interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "i2c";
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clocks = <&platform_clk 1>;
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clocks = <&clockgen 4 1>;
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status = "disabled";
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};
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@ -386,7 +362,7 @@
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reg = <0x0 0x21a0000 0x0 0x10000>;
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interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "i2c";
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clocks = <&platform_clk 1>;
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clocks = <&clockgen 4 1>;
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status = "disabled";
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};
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@ -479,7 +455,7 @@
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compatible = "fsl,ls1021a-lpuart";
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reg = <0x0 0x2960000 0x0 0x1000>;
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interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&platform_clk 1>;
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clocks = <&clockgen 4 1>;
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clock-names = "ipg";
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status = "disabled";
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};
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@ -488,7 +464,7 @@
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compatible = "fsl,ls1021a-lpuart";
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reg = <0x0 0x2970000 0x0 0x1000>;
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interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&platform_clk 1>;
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clocks = <&clockgen 4 1>;
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clock-names = "ipg";
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status = "disabled";
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};
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@ -497,7 +473,7 @@
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compatible = "fsl,ls1021a-lpuart";
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reg = <0x0 0x2980000 0x0 0x1000>;
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&platform_clk 1>;
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clocks = <&clockgen 4 1>;
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clock-names = "ipg";
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status = "disabled";
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};
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@ -506,7 +482,7 @@
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compatible = "fsl,ls1021a-lpuart";
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reg = <0x0 0x2990000 0x0 0x1000>;
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interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&platform_clk 1>;
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clocks = <&clockgen 4 1>;
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clock-names = "ipg";
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status = "disabled";
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};
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@ -515,7 +491,7 @@
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compatible = "fsl,ls1021a-lpuart";
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reg = <0x0 0x29a0000 0x0 0x1000>;
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interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&platform_clk 1>;
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clocks = <&clockgen 4 1>;
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clock-names = "ipg";
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status = "disabled";
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};
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@ -524,7 +500,7 @@
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compatible = "fsl,imx21-wdt";
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reg = <0x0 0x2ad0000 0x0 0x10000>;
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interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&platform_clk 1>;
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clocks = <&clockgen 4 1>;
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clock-names = "wdog-en";
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big-endian;
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};
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@ -534,8 +510,8 @@
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compatible = "fsl,vf610-sai";
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reg = <0x0 0x2b50000 0x0 0x10000>;
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interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&platform_clk 1>, <&platform_clk 1>,
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<&platform_clk 1>, <&platform_clk 1>;
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clocks = <&clockgen 4 1>, <&clockgen 4 1>,
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<&clockgen 4 1>, <&clockgen 4 1>;
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clock-names = "bus", "mclk1", "mclk2", "mclk3";
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dma-names = "tx", "rx";
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dmas = <&edma0 1 47>,
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@ -548,8 +524,8 @@
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compatible = "fsl,vf610-sai";
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reg = <0x0 0x2b60000 0x0 0x10000>;
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interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&platform_clk 1>, <&platform_clk 1>,
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<&platform_clk 1>, <&platform_clk 1>;
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clocks = <&clockgen 4 1>, <&clockgen 4 1>,
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<&clockgen 4 1>, <&clockgen 4 1>;
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clock-names = "bus", "mclk1", "mclk2", "mclk3";
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dma-names = "tx", "rx";
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dmas = <&edma0 1 45>,
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@ -569,16 +545,16 @@
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dma-channels = <32>;
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big-endian;
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clock-names = "dmamux0", "dmamux1";
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clocks = <&platform_clk 1>,
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<&platform_clk 1>;
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clocks = <&clockgen 4 1>,
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<&clockgen 4 1>;
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};
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dcu: dcu@2ce0000 {
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compatible = "fsl,ls1021a-dcu";
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reg = <0x0 0x2ce0000 0x0 0x10000>;
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interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&platform_clk 0>,
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<&platform_clk 0>;
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clocks = <&clockgen 4 0>,
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<&clockgen 4 0>;
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clock-names = "dcu", "pix";
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big-endian;
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status = "disabled";
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