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https://github.com/brain-hackers/linux-brain.git
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gpio: Add a driver for Sodaville GPIO controller
Sodaville has GPIO controller behind the PCI bus. To my suprissed it is not the same as on PXA. The interrupt & gpio chip can be referenced from the device tree like from any other driver. Unfortunately the driver which uses the gpio interrupt has to use irq_of_parse_and_map() instead of platform_get_irq(). The problem is that the platform device (which is created from the device tree) is most likely created before the interrupt chip is registered and therefore irq_of_parse_and_map() fails. In theory the driver works as module. In reality most of the irq functions are not exported to modules and it is possible that _this_ module is unloaded while the provided irqs are still in use. Signed-off-by: Hans J. Koch <hjk@linutronix.de> [torbenh@linutronix.de: make it work after the irq namespace cleanup, add some device tree entries.] Signed-off-by: Torben Hohn <torbenh@linutronix.de> [bigeasy@linutronix.de: convert to generic irq & gpio chip] Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> [grant.likely@secretlab.ca: depend on x86 to avoid irq_domain breakage] Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
This commit is contained in:
Sebastian Andrzej Siewior
Grant Likely
parent
608589b15f
commit
b43ab901d6
48
Documentation/devicetree/bindings/gpio/sodaville.txt
Normal file
48
Documentation/devicetree/bindings/gpio/sodaville.txt
Normal file
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@ -0,0 +1,48 @@
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GPIO controller on CE4100 / Sodaville SoCs
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==========================================
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The bindings for CE4100's GPIO controller match the generic description
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which is covered by the gpio.txt file in this folder.
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The only additional property is the intel,muxctl property which holds the
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value which is written into the MUXCNTL register.
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There is no compatible property for now because the driver is probed via
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PCI id (vendor 0x8086 device 0x2e67).
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The interrupt specifier consists of two cells encoded as follows:
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- <1st cell>: The interrupt-number that identifies the interrupt source.
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- <2nd cell>: The level-sense information, encoded as follows:
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4 - active high level-sensitive
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8 - active low level-sensitive
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Example of the GPIO device and one user:
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pcigpio: gpio@b,1 {
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/* two cells for GPIO and interrupt */
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#gpio-cells = <2>;
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#interrupt-cells = <2>;
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compatible = "pci8086,2e67.2",
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"pci8086,2e67",
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"pciclassff0000",
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"pciclassff00";
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reg = <0x15900 0x0 0x0 0x0 0x0>;
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/* Interrupt line of the gpio device */
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interrupts = <15 1>;
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/* It is an interrupt and GPIO controller itself */
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interrupt-controller;
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gpio-controller;
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intel,muxctl = <0>;
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};
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testuser@20 {
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compatible = "example,testuser";
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/* User the 11th GPIO line as an active high triggered
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* level interrupt
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*/
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interrupts = <11 8>;
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interrupt-parent = <&pcigpio>;
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/* Use this GPIO also with the gpio functions */
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gpios = <&pcigpio 11 0>;
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};
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@ -208,16 +208,19 @@
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interrupts = <14 1>;
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};
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gpio@b,1 {
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pcigpio: gpio@b,1 {
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#gpio-cells = <2>;
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#interrupt-cells = <2>;
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compatible = "pci8086,2e67.2",
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"pci8086,2e67",
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"pciclassff0000",
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"pciclassff00";
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#gpio-cells = <2>;
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reg = <0x15900 0x0 0x0 0x0 0x0>;
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interrupts = <15 1>;
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interrupt-controller;
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gpio-controller;
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intel,muxctl = <0>;
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};
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i2c-controller@b,2 {
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@ -417,6 +417,14 @@ config GPIO_ML_IOH
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Hub) which is for IVI(In-Vehicle Infotainment) use.
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This driver can access the IOH's GPIO device.
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config GPIO_SODAVILLE
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bool "Intel Sodaville GPIO support"
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depends on X86 && PCI && OF
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select GPIO_GENERIC
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select GENERIC_IRQ_CHIP
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help
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Say Y here to support Intel Sodaville GPIO.
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config GPIO_TIMBERDALE
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bool "Support for timberdale GPIO IP"
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depends on MFD_TIMBERDALE && HAS_IOMEM
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@ -46,6 +46,7 @@ obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o
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obj-$(CONFIG_PLAT_SAMSUNG) += gpio-samsung.o
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obj-$(CONFIG_ARCH_SA1100) += gpio-sa1100.o
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obj-$(CONFIG_GPIO_SCH) += gpio-sch.o
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obj-$(CONFIG_GPIO_SODAVILLE) += gpio-sodaville.o
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obj-$(CONFIG_GPIO_STMPE) += gpio-stmpe.o
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obj-$(CONFIG_GPIO_SX150X) += gpio-sx150x.o
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obj-$(CONFIG_GPIO_TC3589X) += gpio-tc3589x.o
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302
drivers/gpio/gpio-sodaville.c
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302
drivers/gpio/gpio-sodaville.c
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@ -0,0 +1,302 @@
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/*
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* GPIO interface for Intel Sodaville SoCs.
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*
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* Copyright (c) 2010, 2011 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License 2 as published
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* by the Free Software Foundation.
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*
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*/
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#include <linux/errno.h>
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#include <linux/gpio.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/of_irq.h>
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#include <linux/basic_mmio_gpio.h>
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#define DRV_NAME "sdv_gpio"
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#define SDV_NUM_PUB_GPIOS 12
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#define PCI_DEVICE_ID_SDV_GPIO 0x2e67
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#define GPIO_BAR 0
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#define GPOUTR 0x00
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#define GPOER 0x04
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#define GPINR 0x08
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#define GPSTR 0x0c
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#define GPIT1R0 0x10
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#define GPIO_INT 0x14
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#define GPIT1R1 0x18
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#define GPMUXCTL 0x1c
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struct sdv_gpio_chip_data {
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int irq_base;
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void __iomem *gpio_pub_base;
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struct irq_domain id;
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struct irq_chip_generic *gc;
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struct bgpio_chip bgpio;
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};
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static int sdv_gpio_pub_set_type(struct irq_data *d, unsigned int type)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct sdv_gpio_chip_data *sd = gc->private;
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void __iomem *type_reg;
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u32 irq_offs = d->irq - sd->irq_base;
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u32 reg;
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if (irq_offs < 8)
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type_reg = sd->gpio_pub_base + GPIT1R0;
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else
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type_reg = sd->gpio_pub_base + GPIT1R1;
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reg = readl(type_reg);
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switch (type) {
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case IRQ_TYPE_LEVEL_HIGH:
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reg &= ~BIT(4 * (irq_offs % 8));
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break;
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case IRQ_TYPE_LEVEL_LOW:
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reg |= BIT(4 * (irq_offs % 8));
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break;
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default:
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return -EINVAL;
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}
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writel(reg, type_reg);
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return 0;
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}
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static irqreturn_t sdv_gpio_pub_irq_handler(int irq, void *data)
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{
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struct sdv_gpio_chip_data *sd = data;
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u32 irq_stat = readl(sd->gpio_pub_base + GPSTR);
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irq_stat &= readl(sd->gpio_pub_base + GPIO_INT);
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if (!irq_stat)
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return IRQ_NONE;
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while (irq_stat) {
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u32 irq_bit = __fls(irq_stat);
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irq_stat &= ~BIT(irq_bit);
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generic_handle_irq(sd->irq_base + irq_bit);
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}
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return IRQ_HANDLED;
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}
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static int sdv_xlate(struct irq_domain *h, struct device_node *node,
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const u32 *intspec, u32 intsize, irq_hw_number_t *out_hwirq,
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u32 *out_type)
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{
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u32 line, type;
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if (node != h->of_node)
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return -EINVAL;
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if (intsize < 2)
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return -EINVAL;
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line = *intspec;
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*out_hwirq = line;
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intspec++;
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type = *intspec;
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switch (type) {
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case IRQ_TYPE_LEVEL_LOW:
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case IRQ_TYPE_LEVEL_HIGH:
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*out_type = type;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static struct irq_domain_ops irq_domain_sdv_ops = {
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.dt_translate = sdv_xlate,
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};
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static __devinit int sdv_register_irqsupport(struct sdv_gpio_chip_data *sd,
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struct pci_dev *pdev)
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{
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struct irq_chip_type *ct;
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int ret;
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sd->irq_base = irq_alloc_descs(-1, 0, SDV_NUM_PUB_GPIOS, -1);
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if (sd->irq_base < 0)
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return sd->irq_base;
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/* mask + ACK all interrupt sources */
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writel(0, sd->gpio_pub_base + GPIO_INT);
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writel((1 << 11) - 1, sd->gpio_pub_base + GPSTR);
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ret = request_irq(pdev->irq, sdv_gpio_pub_irq_handler, IRQF_SHARED,
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"sdv_gpio", sd);
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if (ret)
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goto out_free_desc;
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sd->id.irq_base = sd->irq_base;
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sd->id.of_node = of_node_get(pdev->dev.of_node);
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sd->id.ops = &irq_domain_sdv_ops;
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/*
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* This gpio irq controller latches level irqs. Testing shows that if
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* we unmask & ACK the IRQ before the source of the interrupt is gone
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* then the interrupt is active again.
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*/
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sd->gc = irq_alloc_generic_chip("sdv-gpio", 1, sd->irq_base,
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sd->gpio_pub_base, handle_fasteoi_irq);
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if (!sd->gc) {
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ret = -ENOMEM;
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goto out_free_irq;
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}
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sd->gc->private = sd;
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ct = sd->gc->chip_types;
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ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
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ct->regs.eoi = GPSTR;
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ct->regs.mask = GPIO_INT;
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ct->chip.irq_mask = irq_gc_mask_clr_bit;
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ct->chip.irq_unmask = irq_gc_mask_set_bit;
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ct->chip.irq_eoi = irq_gc_eoi;
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ct->chip.irq_set_type = sdv_gpio_pub_set_type;
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irq_setup_generic_chip(sd->gc, IRQ_MSK(SDV_NUM_PUB_GPIOS),
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IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST,
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IRQ_LEVEL | IRQ_NOPROBE);
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irq_domain_add(&sd->id);
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return 0;
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out_free_irq:
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free_irq(pdev->irq, sd);
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out_free_desc:
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irq_free_descs(sd->irq_base, SDV_NUM_PUB_GPIOS);
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return ret;
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}
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static int __devinit sdv_gpio_probe(struct pci_dev *pdev,
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const struct pci_device_id *pci_id)
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{
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struct sdv_gpio_chip_data *sd;
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unsigned long addr;
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const void *prop;
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int len;
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int ret;
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u32 mux_val;
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sd = kzalloc(sizeof(struct sdv_gpio_chip_data), GFP_KERNEL);
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if (!sd)
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return -ENOMEM;
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ret = pci_enable_device(pdev);
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if (ret) {
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dev_err(&pdev->dev, "can't enable device.\n");
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goto done;
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}
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ret = pci_request_region(pdev, GPIO_BAR, DRV_NAME);
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if (ret) {
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dev_err(&pdev->dev, "can't alloc PCI BAR #%d\n", GPIO_BAR);
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goto disable_pci;
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}
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addr = pci_resource_start(pdev, GPIO_BAR);
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if (!addr)
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goto release_reg;
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sd->gpio_pub_base = ioremap(addr, pci_resource_len(pdev, GPIO_BAR));
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prop = of_get_property(pdev->dev.of_node, "intel,muxctl", &len);
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if (prop && len == 4) {
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mux_val = of_read_number(prop, 1);
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writel(mux_val, sd->gpio_pub_base + GPMUXCTL);
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}
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ret = bgpio_init(&sd->bgpio, &pdev->dev, 4,
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sd->gpio_pub_base + GPINR, sd->gpio_pub_base + GPOUTR,
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NULL, sd->gpio_pub_base + GPOER, NULL, false);
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if (ret)
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goto unmap;
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sd->bgpio.gc.ngpio = SDV_NUM_PUB_GPIOS;
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ret = gpiochip_add(&sd->bgpio.gc);
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if (ret < 0) {
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dev_err(&pdev->dev, "gpiochip_add() failed.\n");
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goto unmap;
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}
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ret = sdv_register_irqsupport(sd, pdev);
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if (ret)
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goto unmap;
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pci_set_drvdata(pdev, sd);
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dev_info(&pdev->dev, "Sodaville GPIO driver registered.\n");
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return 0;
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unmap:
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iounmap(sd->gpio_pub_base);
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release_reg:
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pci_release_region(pdev, GPIO_BAR);
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disable_pci:
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pci_disable_device(pdev);
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done:
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kfree(sd);
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return ret;
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}
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static void sdv_gpio_remove(struct pci_dev *pdev)
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{
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struct sdv_gpio_chip_data *sd = pci_get_drvdata(pdev);
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irq_domain_del(&sd->id);
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free_irq(pdev->irq, sd);
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irq_free_descs(sd->irq_base, SDV_NUM_PUB_GPIOS);
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if (gpiochip_remove(&sd->bgpio.gc))
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dev_err(&pdev->dev, "gpiochip_remove() failed.\n");
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pci_release_region(pdev, GPIO_BAR);
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iounmap(sd->gpio_pub_base);
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pci_disable_device(pdev);
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kfree(sd);
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}
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static struct pci_device_id sdv_gpio_pci_ids[] __devinitdata = {
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_SDV_GPIO) },
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{ 0, },
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};
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static struct pci_driver sdv_gpio_driver = {
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.name = DRV_NAME,
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.id_table = sdv_gpio_pci_ids,
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.probe = sdv_gpio_probe,
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.remove = sdv_gpio_remove,
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};
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static int __init sdv_gpio_init(void)
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{
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return pci_register_driver(&sdv_gpio_driver);
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}
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module_init(sdv_gpio_init);
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static void __exit sdv_gpio_exit(void)
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{
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pci_unregister_driver(&sdv_gpio_driver);
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}
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module_exit(sdv_gpio_exit);
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MODULE_AUTHOR("Hans J. Koch <hjk@linutronix.de>");
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MODULE_DESCRIPTION("GPIO interface for Intel Sodaville SoCs");
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MODULE_LICENSE("GPL v2");
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