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ARM: SoC platform changes for 3.17

Browse Source 
This is the bulk of new SoC enablement and other platform changes for 3.17:
 
 * Samsung S5PV210 has been converted to DT and multiplatform
 * Clock drivers and bindings for some of the lower-end i.MX 1/2 platforms
 * Kirkwood, one of the popular Marvell platforms, is folded into the
   mvebu platform code, removing mach-kirkwood.
 * Hwmod data for TI AM43xx and DRA7 platforms.
 * More additions of Renesas shmobile platform support
 * Removal of plat-samsung contents that can be removed with S5PV210 being
   multiplatform/DT-enabled and the other two old platforms being removed.
 
 New platforms (most with only basic support right now):
 
 * Hisilicon X5HD2 settop box chipset is introduced
 * Mediatek MT6589 (mobile chipset) is introduced
 * Broadcom BCM7xxx settop box chipset is introduced
 
 + as usual a lot other pieces all over the platform code.
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Merge tag 'soc-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC platform changes from Olof Johansson:
 "This is the bulk of new SoC enablement and other platform changes for
  3.17:

   - Samsung S5PV210 has been converted to DT and multiplatform
   - Clock drivers and bindings for some of the lower-end i.MX 1/2
     platforms
   - Kirkwood, one of the popular Marvell platforms, is folded into the
     mvebu platform code, removing mach-kirkwood
   - Hwmod data for TI AM43xx and DRA7 platforms
   - More additions of Renesas shmobile platform support
   - Removal of plat-samsung contents that can be removed with S5PV210
     being multiplatform/DT-enabled and the other two old platforms
     being removed

  New platforms (most with only basic support right now):

   - Hisilicon X5HD2 settop box chipset is introduced
   - Mediatek MT6589 (mobile chipset) is introduced
   - Broadcom BCM7xxx settop box chipset is introduced

  + as usual a lot other pieces all over the platform code"

* tag 'soc-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (240 commits)
  ARM: hisi: remove smp from machine descriptor
  power: reset: move hisilicon reboot code
  ARM: dts: Add hix5hd2-dkb dts file.
  ARM: debug: Rename Hi3716 to HIX5HD2
  ARM: hisi: enable hix5hd2 SoC
  ARM: hisi: add ARCH_HISI
  MAINTAINERS: add entry for Broadcom ARM STB architecture
  ARM: brcmstb: select GISB arbiter and interrupt drivers
  ARM: brcmstb: add infrastructure for ARM-based Broadcom STB SoCs
  ARM: configs: enable SMP in bcm_defconfig
  ARM: add SMP support for Broadcom mobile SoCs
  Documentation: arm: misc updates to Marvell EBU SoC status
  Documentation: arm: add URLs to public datasheets for the Marvell Armada XP SoC
  ARM: mvebu: fix build without platforms selected
  ARM: mvebu: add cpuidle support for Armada 38x
  ARM: mvebu: add cpuidle support for Armada 370
  cpuidle: mvebu: add Armada 38x support
  cpuidle: mvebu: add Armada 370 support
  cpuidle: mvebu: rename the driver from armada-370-xp to mvebu-v7
  ARM: mvebu: export the SCU address
  ...
This commit is contained in:
Linus Torvalds 2014-08-08 11:14:29 -07:00
commit b3345d7c57
407 changed files with 11492 additions and 19495 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
Documentation/arm/Marvell/README
View File

@ -53,8 +53,8 @@ Kirkwood family
Functional Spec: http://www.marvell.com/embedded-processors/kirkwood/assets/FS_88F6180_9x_6281_OpenSource.pdf
Homepage: http://www.marvell.com/embedded-processors/kirkwood/
Core: Feroceon ARMv5 compatible
Linux kernel mach directory: arch/arm/mach-kirkwood
Linux kernel plat directory: arch/arm/plat-orion
Linux kernel mach directory: arch/arm/mach-mvebu
Linux kernel plat directory: none
Discovery family
----------------
@ -83,7 +83,9 @@ EBU Armada family
88F6710
88F6707
88F6W11
Product Brief: http://www.marvell.com/embedded-processors/armada-300/assets/Marvell_ARMADA_370_SoC.pdf
Product Brief: http://www.marvell.com/embedded-processors/armada-300/assets/Marvell_ARMADA_370_SoC.pdf
Hardware Spec: http://www.marvell.com/embedded-processors/armada-300/assets/ARMADA370-datasheet.pdf
Functional Spec: http://www.marvell.com/embedded-processors/armada-300/assets/ARMADA370-FunctionalSpec-datasheet.pdf
Armada 375 Flavors:
88F6720
@ -100,8 +102,7 @@ EBU Armada family
MV78460
NOTE: not to be confused with the non-SMP 78xx0 SoCs
Product Brief: http://www.marvell.com/embedded-processors/armada-xp/assets/Marvell-ArmadaXP-SoC-product%20brief.pdf
No public datasheet available.
Functional Spec: http://www.marvell.com/embedded-processors/armada-xp/assets/ARMADA-XP-Functional-SpecDatasheet.pdf
Core: Sheeva ARMv7 compatible
@ -135,7 +136,9 @@ Dove family (application processor)
Functional Spec : http://www.marvell.com/application-processors/armada-500/assets/Armada-510-Functional-Spec.pdf
Homepage: http://www.marvell.com/application-processors/armada-500/
Core: ARMv7 compatible
Directory: arch/arm/mach-dove
Directory: arch/arm/mach-mvebu (DT enabled platforms)
arch/arm/mach-dove (non-DT enabled platforms)
PXA 2xx/3xx/93x/95x family
--------------------------
@ -253,10 +256,10 @@ Berlin family (Digital Entertainment)
Long-term plans
---------------
* Unify the mach-dove/, mach-mv78xx0/, mach-orion5x/ and
mach-kirkwood/ into the mach-mvebu/ to support all SoCs from the
Marvell EBU (Engineering Business Unit) in a single mach-<foo>
directory. The plat-orion/ would therefore disappear.
* Unify the mach-dove/, mach-mv78xx0/, mach-orion5x/ into the
mach-mvebu/ to support all SoCs from the Marvell EBU (Engineering
Business Unit) in a single mach-<foo> directory. The plat-orion/
would therefore disappear.
* Unify the mach-mmp/ and mach-pxa/ into the same mach-pxa
directory. The plat-pxa/ would therefore disappear.

6
Documentation/devicetree/bindings/arm/arm-boards
View File

@ -86,3 +86,9 @@ Interrupt controllers:
compatible = "arm,versatile-sic";
interrupt-controller;
#interrupt-cells = <1>;
Required nodes:
- core-module: the root node to the Versatile platforms must have
a core-module with regs and the compatible strings
"arm,core-module-versatile", "syscon"

11
Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
View File

@ -31,6 +31,17 @@ Example:
reboot-offset = <0x4>;
};
-----------------------------------------------------------------------
Hisilicon CPU controller
Required properties:
- compatible : "hisilicon,cpuctrl"
- reg : Register address and size
The clock registers and power registers of secondary cores are defined
in CPU controller, especially in HIX5HD2 SoC.
-----------------------------------------------------------------------
PCTRL: Peripheral misc control register
Required Properties:

8
Documentation/devicetree/bindings/arm/mediatek.txt Normal file
View File

@ -0,0 +1,8 @@
Mediatek MT6589 Platforms Device Tree Bindings
Boards with a SoC of the Mediatek MT6589 shall have the following property:
Required root node property:
compatible: must contain "mediatek,mt6589"

4
Documentation/devicetree/bindings/clock/arm-integrator.txt
View File

@ -1,4 +1,4 @@
Clock bindings for ARM Integrator Core Module clocks
Clock bindings for ARM Integrator and Versatile Core Module clocks
Auxilary Oscillator Clock
@ -12,7 +12,7 @@ parent node.
Required properties:
- compatible: must be "arm,integrator-cm-auxosc"
- compatible: must be "arm,integrator-cm-auxosc" or "arm,versatile-cm-auxosc"
- #clock-cells: must be <0>
Optional properties:

53
Documentation/devicetree/bindings/clock/clk-s5pv210-audss.txt Normal file
View File

@ -0,0 +1,53 @@
* Samsung Audio Subsystem Clock Controller
The Samsung Audio Subsystem clock controller generates and supplies clocks
to Audio Subsystem block available in the S5PV210 and compatible SoCs.
Required Properties:
- compatible: should be "samsung,s5pv210-audss-clock".
- reg: physical base address and length of the controller's register set.
- #clock-cells: should be 1.
- clocks:
- hclk: AHB bus clock of the Audio Subsystem.
- xxti: Optional fixed rate PLL reference clock, parent of mout_audss. If
not specified (i.e. xusbxti is used for PLL reference), it is fixed to
a clock named "xxti".
- fout_epll: Input PLL to the AudioSS block, parent of mout_audss.
- iiscdclk0: Optional external i2s clock, parent of mout_i2s. If not
specified, it is fixed to a clock named "iiscdclk0".
- sclk_audio0: Audio bus clock, parent of mout_i2s.
- clock-names: Aliases for the above clocks. They should be "hclk",
"xxti", "fout_epll", "iiscdclk0", and "sclk_audio0" respectively.
All available clocks are defined as preprocessor macros in
dt-bindings/clock/s5pv210-audss-clk.h header and can be used in device
tree sources.
Example: Clock controller node.
clk_audss: clock-controller@c0900000 {
compatible = "samsung,s5pv210-audss-clock";
reg = <0xc0900000 0x1000>;
#clock-cells = <1>;
clock-names = "hclk", "xxti",
"fout_epll", "sclk_audio0";
clocks = <&clocks DOUT_HCLKP>, <&xxti>,
<&clocks FOUT_EPLL>, <&clocks SCLK_AUDIO0>;
};
Example: I2S controller node that consumes the clock generated by the clock
controller. Refer to the standard clock bindings for information
about 'clocks' and 'clock-names' property.
i2s0: i2s@03830000 {
/* ... */
clock-names = "iis", "i2s_opclk0",
"i2s_opclk1";
clocks = <&clk_audss CLK_I2S>, <&clk_audss CLK_I2S>,
<&clk_audss CLK_DOUT_AUD_BUS>;
/* ... */
};

26
Documentation/devicetree/bindings/clock/imx1-clock.txt Normal file
View File

@ -0,0 +1,26 @@
* Clock bindings for Freescale i.MX1 CPUs
Required properties:
- compatible: Should be "fsl,imx1-ccm".
- reg: Address and length of the register set.
- #clock-cells: Should be <1>.
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx1-clock.h
for the full list of i.MX1 clock IDs.
Examples:
clks: ccm@0021b000 {
#clock-cells = <1>;
compatible = "fsl,imx1-ccm";
reg = <0x0021b000 0x1000>;
};
pwm: pwm@00208000 {
#pwm-cells = <2>;
compatible = "fsl,imx1-pwm";
reg = <0x00208000 0x1000>;
interrupts = <34>;
clocks = <&clks IMX1_CLK_DUMMY>, <&clks IMX1_CLK_PER1>;
clock-names = "ipg", "per";
};

28
Documentation/devicetree/bindings/clock/imx21-clock.txt Normal file
View File

@ -0,0 +1,28 @@
* Clock bindings for Freescale i.MX21
Required properties:
- compatible : Should be "fsl,imx21-ccm".
- reg : Address and length of the register set.
- interrupts : Should contain CCM interrupt.
- #clock-cells: Should be <1>.
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx21-clock.h
for the full list of i.MX21 clock IDs.
Examples:
clks: ccm@10027000{
compatible = "fsl,imx21-ccm";
reg = <0x10027000 0x800>;
#clock-cells = <1>;
};
uart1: serial@1000a000 {
compatible = "fsl,imx21-uart";
reg = <0x1000a000 0x1000>;
interrupts = <20>;
clocks = <&clks IMX21_CLK_UART1_IPG_GATE>,
<&clks IMX21_CLK_PER1>;
clock-names = "ipg", "per";
status = "disabled";
};

127
Documentation/devicetree/bindings/clock/imx27-clock.txt
View File

@ -7,117 +7,22 @@ Required properties:
- #clock-cells: Should be <1>
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. The following is a full list of i.MX27
clocks and IDs.
Clock ID
-----------------------
dummy 0
ckih 1
ckil 2
mpll 3
spll 4
mpll_main2 5
ahb 6
ipg 7
nfc_div 8
per1_div 9
per2_div 10
per3_div 11
per4_div 12
vpu_sel 13
vpu_div 14
usb_div 15
cpu_sel 16
clko_sel 17
cpu_div 18
clko_div 19
ssi1_sel 20
ssi2_sel 21
ssi1_div 22
ssi2_div 23
clko_en 24
ssi2_ipg_gate 25
ssi1_ipg_gate 26
slcdc_ipg_gate 27
sdhc3_ipg_gate 28
sdhc2_ipg_gate 29
sdhc1_ipg_gate 30
scc_ipg_gate 31
sahara_ipg_gate 32
rtc_ipg_gate 33
pwm_ipg_gate 34
owire_ipg_gate 35
lcdc_ipg_gate 36
kpp_ipg_gate 37
iim_ipg_gate 38
i2c2_ipg_gate 39
i2c1_ipg_gate 40
gpt6_ipg_gate 41
gpt5_ipg_gate 42
gpt4_ipg_gate 43
gpt3_ipg_gate 44
gpt2_ipg_gate 45
gpt1_ipg_gate 46
gpio_ipg_gate 47
fec_ipg_gate 48
emma_ipg_gate 49
dma_ipg_gate 50
cspi3_ipg_gate 51
cspi2_ipg_gate 52
cspi1_ipg_gate 53
nfc_baud_gate 54
ssi2_baud_gate 55
ssi1_baud_gate 56
vpu_baud_gate 57
per4_gate 58
per3_gate 59
per2_gate 60
per1_gate 61
usb_ahb_gate 62
slcdc_ahb_gate 63
sahara_ahb_gate 64
lcdc_ahb_gate 65
vpu_ahb_gate 66
fec_ahb_gate 67
emma_ahb_gate 68
emi_ahb_gate 69
dma_ahb_gate 70
csi_ahb_gate 71
brom_ahb_gate 72
ata_ahb_gate 73
wdog_ipg_gate 74
usb_ipg_gate 75
uart6_ipg_gate 76
uart5_ipg_gate 77
uart4_ipg_gate 78
uart3_ipg_gate 79
uart2_ipg_gate 80
uart1_ipg_gate 81
ckih_div1p5 82
fpm 83
mpll_osc_sel 84
mpll_sel 85
spll_gate 86
mshc_div 87
rtic_ipg_gate 88
mshc_ipg_gate 89
rtic_ahb_gate 90
mshc_baud_gate 91
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx27-clock.h
for the full list of i.MX27 clock IDs.
Examples:
clks: ccm@10027000{
compatible = "fsl,imx27-ccm";
reg = <0x10027000 0x1000>;
#clock-cells = <1>;
};
clks: ccm@10027000{
compatible = "fsl,imx27-ccm";
reg = <0x10027000 0x1000>;
#clock-cells = <1>;
};
uart1: serial@1000a000 {
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
reg = <0x1000a000 0x1000>;
interrupts = <20>;
clocks = <&clks 81>, <&clks 61>;
clock-names = "ipg", "per";
status = "disabled";
};
uart1: serial@1000a000 {
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
reg = <0x1000a000 0x1000>;
interrupts = <20>;
clocks = <&clks IMX27_CLK_UART1_IPG_GATE>,
<&clks IMX27_CLK_PER1_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};

220
Documentation/devicetree/bindings/clock/imx6q-clock.txt
View File

@ -7,223 +7,13 @@ Required properties:
- #clock-cells: Should be <1>
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. The following is a full list of i.MX6Q
clocks and IDs.
Clock ID
---------------------------
dummy 0
ckil 1
ckih 2
osc 3
pll2_pfd0_352m 4
pll2_pfd1_594m 5
pll2_pfd2_396m 6
pll3_pfd0_720m 7
pll3_pfd1_540m 8
pll3_pfd2_508m 9
pll3_pfd3_454m 10
pll2_198m 11
pll3_120m 12
pll3_80m 13
pll3_60m 14
twd 15
step 16
pll1_sw 17
periph_pre 18
periph2_pre 19
periph_clk2_sel 20
periph2_clk2_sel 21
axi_sel 22
esai_sel 23
asrc_sel 24
spdif_sel 25
gpu2d_axi 26
gpu3d_axi 27
gpu2d_core_sel 28
gpu3d_core_sel 29
gpu3d_shader_sel 30
ipu1_sel 31
ipu2_sel 32
ldb_di0_sel 33
ldb_di1_sel 34
ipu1_di0_pre_sel 35
ipu1_di1_pre_sel 36
ipu2_di0_pre_sel 37
ipu2_di1_pre_sel 38
ipu1_di0_sel 39
ipu1_di1_sel 40
ipu2_di0_sel 41
ipu2_di1_sel 42
hsi_tx_sel 43
pcie_axi_sel 44
ssi1_sel 45
ssi2_sel 46
ssi3_sel 47
usdhc1_sel 48
usdhc2_sel 49
usdhc3_sel 50
usdhc4_sel 51
enfc_sel 52
emi_sel 53
emi_slow_sel 54
vdo_axi_sel 55
vpu_axi_sel 56
cko1_sel 57
periph 58
periph2 59
periph_clk2 60
periph2_clk2 61
ipg 62
ipg_per 63
esai_pred 64
esai_podf 65
asrc_pred 66
asrc_podf 67
spdif_pred 68
spdif_podf 69
can_root 70
ecspi_root 71
gpu2d_core_podf 72
gpu3d_core_podf 73
gpu3d_shader 74
ipu1_podf 75
ipu2_podf 76
ldb_di0_podf 77
ldb_di1_podf 78
ipu1_di0_pre 79
ipu1_di1_pre 80
ipu2_di0_pre 81
ipu2_di1_pre 82
hsi_tx_podf 83
ssi1_pred 84
ssi1_podf 85
ssi2_pred 86
ssi2_podf 87
ssi3_pred 88
ssi3_podf 89
uart_serial_podf 90
usdhc1_podf 91
usdhc2_podf 92
usdhc3_podf 93
usdhc4_podf 94
enfc_pred 95
enfc_podf 96
emi_podf 97
emi_slow_podf 98
vpu_axi_podf 99
cko1_podf 100
axi 101
mmdc_ch0_axi_podf 102
mmdc_ch1_axi_podf 103
arm 104
ahb 105
apbh_dma 106
asrc 107
can1_ipg 108
can1_serial 109
can2_ipg 110
can2_serial 111
ecspi1 112
ecspi2 113
ecspi3 114
ecspi4 115
ecspi5 116
enet 117
esai 118
gpt_ipg 119
gpt_ipg_per 120
gpu2d_core 121
gpu3d_core 122
hdmi_iahb 123
hdmi_isfr 124
i2c1 125
i2c2 126
i2c3 127
iim 128
enfc 129
ipu1 130
ipu1_di0 131
ipu1_di1 132
ipu2 133
ipu2_di0 134
ldb_di0 135
ldb_di1 136
ipu2_di1 137
hsi_tx 138
mlb 139
mmdc_ch0_axi 140
mmdc_ch1_axi 141
ocram 142
openvg_axi 143
pcie_axi 144
pwm1 145
pwm2 146
pwm3 147
pwm4 148
per1_bch 149
gpmi_bch_apb 150
gpmi_bch 151
gpmi_io 152
gpmi_apb 153
sata 154
sdma 155
spba 156
ssi1 157
ssi2 158
ssi3 159
uart_ipg 160
uart_serial 161
usboh3 162
usdhc1 163
usdhc2 164
usdhc3 165
usdhc4 166
vdo_axi 167
vpu_axi 168
cko1 169
pll1_sys 170
pll2_bus 171
pll3_usb_otg 172
pll4_audio 173
pll5_video 174
pll8_mlb 175
pll7_usb_host 176
pll6_enet 177
ssi1_ipg 178
ssi2_ipg 179
ssi3_ipg 180
rom 181
usbphy1 182
usbphy2 183
ldb_di0_div_3_5 184
ldb_di1_div_3_5 185
sata_ref 186
sata_ref_100m 187
pcie_ref 188
pcie_ref_125m 189
enet_ref 190
usbphy1_gate 191
usbphy2_gate 192
pll4_post_div 193
pll5_post_div 194
pll5_video_div 195
eim_slow 196
spdif 197
cko2_sel 198
cko2_podf 199
cko2 200
cko 201
vdoa 202
pll4_audio_div 203
lvds1_sel 204
lvds2_sel 205
lvds1_gate 206
lvds2_gate 207
esai_ahb 208
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6qdl-clock.h
for the full list of i.MX6 Quad and DualLite clock IDs.
Examples:
#include <dt-bindings/clock/imx6qdl-clock.h>
clks: ccm@020c4000 {
compatible = "fsl,imx6q-ccm";
reg = <0x020c4000 0x4000>;
@ -235,7 +25,7 @@ uart1: serial@02020000 {
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x02020000 0x4000>;
interrupts = <0 26 0x04>;
clocks = <&clks 160>, <&clks 161>;
clocks = <&clks IMX6QDL_CLK_UART_IPG>, <&clks IMX6QDL_CLK_UART_SERIAL>;
clock-names = "ipg", "per";
status = "disabled";
};

5
Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
View File

@ -3,14 +3,15 @@ Device Tree Clock bindings for cpu clock of Marvell EBU platforms
Required properties:
- compatible : shall be one of the following:
"marvell,armada-xp-cpu-clock" - cpu clocks for Armada XP
- reg : Address and length of the clock complex register set
- reg : Address and length of the clock complex register set, followed
by address and length of the PMU DFS registers
- #clock-cells : should be set to 1.
- clocks : shall be the input parent clock phandle for the clock.
cpuclk: clock-complex@d0018700 {
#clock-cells = <1>;
compatible = "marvell,armada-xp-cpu-clock";
reg = <0xd0018700 0xA0>;
reg = <0xd0018700 0xA0>, <0x1c054 0x10>;
clocks = <&coreclk 1>;
}

78
Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.txt Normal file
View File

@ -0,0 +1,78 @@
* Samsung S5P6442/S5PC110/S5PV210 Clock Controller
Samsung S5P6442, S5PC110 and S5PV210 SoCs contain integrated clock
controller, which generates and supplies clock to various controllers
within the SoC.
Required Properties:
- compatible: should be one of following:
- "samsung,s5pv210-clock" : for clock controller of Samsung
S5PC110/S5PV210 SoCs,
- "samsung,s5p6442-clock" : for clock controller of Samsung
S5P6442 SoC.
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
All available clocks are defined as preprocessor macros in
dt-bindings/clock/s5pv210.h header and can be used in device tree sources.
External clocks:
There are several clocks that are generated outside the SoC. It is expected
that they are defined using standard clock bindings with following
clock-output-names:
- "xxti": external crystal oscillator connected to XXTI and XXTO pins of
the SoC,
- "xusbxti": external crystal oscillator connected to XUSBXTI and XUSBXTO
pins of the SoC,
A subset of above clocks available on given board shall be specified in
board device tree, including the system base clock, as selected by XOM[0]
pin of the SoC. Refer to generic fixed rate clock bindings
documentation[1] for more information how to specify these clocks.
[1] Documentation/devicetree/bindings/clock/fixed-clock.txt
Example: Clock controller node:
clock: clock-controller@7e00f000 {
compatible = "samsung,s5pv210-clock";
reg = <0x7e00f000 0x1000>;
#clock-cells = <1>;
};
Example: Required external clocks:
xxti: clock-xxti {
compatible = "fixed-clock";
clock-output-names = "xxti";
clock-frequency = <24000000>;
#clock-cells = <0>;
};
xusbxti: clock-xusbxti {
compatible = "fixed-clock";
clock-output-names = "xusbxti";
clock-frequency = <24000000>;
#clock-cells = <0>;
};
Example: UART controller node that consumes the clock generated by the clock
controller (refer to the standard clock bindings for information about
"clocks" and "clock-names" properties):
uart0: serial@e2900000 {
compatible = "samsung,s5pv210-uart";
reg = <0xe2900000 0x400>;
interrupt-parent = <&vic1>;
interrupts = <10>;
clock-names = "uart", "clk_uart_baud0",
"clk_uart_baud1";
clocks = <&clocks UART0>, <&clocks UART0>,
<&clocks SCLK_UART0>;
status = "disabled";
};

1
Documentation/devicetree/bindings/phy/samsung-phy.txt
View File

@ -30,6 +30,7 @@ Required properties:
- "samsung,exynos4210-usb2-phy"
- "samsung,exynos4x12-usb2-phy"
- "samsung,exynos5250-usb2-phy"
- "samsung,s5pv210-usb2-phy"
- reg : a list of registers used by phy driver
- first and obligatory is the location of phy modules registers
- samsung,sysreg-phandle - handle to syscon used to control the system registers

16
MAINTAINERS
View File

@ -985,6 +985,14 @@ F: arch/arm/mach-pxa/hx4700.c
F: arch/arm/mach-pxa/include/mach/hx4700.h
F: sound/soc/pxa/hx4700.c
ARM/HISILICON SOC SUPPORT
M: Wei Xu <xuwei5@hisilicon.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
W: http://www.hisilicon.com
S: Supported
T: git git://github.com/hisilicon/linux-hisi.git
F: arch/arm/mach-hisi/
ARM/HP JORNADA 7XX MACHINE SUPPORT
M: Kristoffer Ericson <kristoffer.ericson@gmail.com>
W: www.jlime.com
@ -2004,6 +2012,14 @@ F: arch/arm/mach-bcm/bcm_5301x.c
F: arch/arm/boot/dts/bcm5301x.dtsi
F: arch/arm/boot/dts/bcm470*
BROADCOM BCM7XXX ARM ARCHITECTURE
M: Marc Carino <marc.ceeeee@gmail.com>
M: Brian Norris <computersforpeace@gmail.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: arch/arm/mach-bcm/*brcmstb*
F: arch/arm/boot/dts/bcm7*.dts*
BROADCOM TG3 GIGABIT ETHERNET DRIVER
M: Prashant Sreedharan <prashant@broadcom.com>
M: Michael Chan <mchan@broadcom.com>

40
arch/arm/Kconfig
View File

@ -531,21 +531,6 @@ config ARCH_DOVE
help
Support for the Marvell Dove SoC 88AP510
config ARCH_KIRKWOOD
bool "Marvell Kirkwood"
select ARCH_REQUIRE_GPIOLIB
select CPU_FEROCEON
select GENERIC_CLOCKEVENTS
select MVEBU_MBUS
select PCI
select PCI_QUIRKS
select PINCTRL
select PINCTRL_KIRKWOOD
select PLAT_ORION_LEGACY
help
Support for the following Marvell Kirkwood series SoCs:
88F6180, 88F6192 and 88F6281.
config ARCH_MV78XX0
bool "Marvell MV78xx0"
select ARCH_REQUIRE_GPIOLIB
@ -762,24 +747,6 @@ config ARCH_S3C64XX
help
Samsung S3C64XX series based systems
config ARCH_S5PV210
bool "Samsung S5PV210/S5PC110"
select ARCH_HAS_HOLES_MEMORYMODEL
select ARCH_SPARSEMEM_ENABLE
select ATAGS
select CLKDEV_LOOKUP
select CLKSRC_SAMSUNG_PWM
select CPU_V7
select GENERIC_CLOCKEVENTS
select GPIO_SAMSUNG
select HAVE_S3C2410_I2C if I2C
select HAVE_S3C2410_WATCHDOG if WATCHDOG
select HAVE_S3C_RTC if RTC_CLASS
select NEED_MACH_MEMORY_H
select SAMSUNG_ATAGS
help
Samsung S5PV210/S5PC110 series based systems
config ARCH_DAVINCI
bool "TI DaVinci"
select ARCH_HAS_HOLES_MEMORYMODEL
@ -918,8 +885,6 @@ source "arch/arm/mach-ixp4xx/Kconfig"
source "arch/arm/mach-keystone/Kconfig"
source "arch/arm/mach-kirkwood/Kconfig"
source "arch/arm/mach-ks8695/Kconfig"
source "arch/arm/mach-msm/Kconfig"
@ -930,6 +895,8 @@ source "arch/arm/mach-mv78xx0/Kconfig"
source "arch/arm/mach-imx/Kconfig"
source "arch/arm/mach-mediatek/Kconfig"
source "arch/arm/mach-mxs/Kconfig"
source "arch/arm/mach-netx/Kconfig"
@ -1517,7 +1484,8 @@ config ARM_PSCI
config ARCH_NR_GPIO
int
default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX
default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
default 416 if ARCH_SUNXI
default 392 if ARCH_U8500
default 352 if ARCH_VT8500

39
arch/arm/Kconfig.debug
View File

@ -223,6 +223,14 @@ choice
Say Y here if you want kernel low-level debugging support
on HI3716 UART.
config DEBUG_HIX5HD2_UART
bool "Hisilicon Hix5hd2 Debug UART"
depends on ARCH_HIX5HD2
select DEBUG_UART_PL01X
help
Say Y here if you want kernel low-level debugging support
on Hix5hd2 UART.
config DEBUG_HIGHBANK_UART
bool "Kernel low-level debugging messages via Highbank UART"
depends on ARCH_HIGHBANK
@ -617,6 +625,7 @@ choice
depends on PLAT_SAMSUNG
select DEBUG_EXYNOS_UART if ARCH_EXYNOS
select DEBUG_S3C24XX_UART if ARCH_S3C24XX
select DEBUG_S5PV210_UART if ARCH_S5PV210
bool "Use Samsung S3C UART 0 for low-level debug"
help
Say Y here if you want the debug print routines to direct
@ -627,6 +636,7 @@ choice
depends on PLAT_SAMSUNG
select DEBUG_EXYNOS_UART if ARCH_EXYNOS
select DEBUG_S3C24XX_UART if ARCH_S3C24XX
select DEBUG_S5PV210_UART if ARCH_S5PV210
bool "Use Samsung S3C UART 1 for low-level debug"
help
Say Y here if you want the debug print routines to direct
@ -637,6 +647,7 @@ choice
depends on PLAT_SAMSUNG
select DEBUG_EXYNOS_UART if ARCH_EXYNOS
select DEBUG_S3C24XX_UART if ARCH_S3C24XX
select DEBUG_S5PV210_UART if ARCH_S5PV210
bool "Use Samsung S3C UART 2 for low-level debug"
help
Say Y here if you want the debug print routines to direct
@ -644,8 +655,9 @@ choice
by the boot-loader before use.
config DEBUG_S3C_UART3
depends on PLAT_SAMSUNG && ARCH_EXYNOS
select DEBUG_EXYNOS_UART
depends on PLAT_SAMSUNG && (ARCH_EXYNOS || ARCH_S5PV210)
select DEBUG_EXYNOS_UART if ARCH_EXYNOS
select DEBUG_S5PV210_UART if ARCH_S5PV210
bool "Use Samsung S3C UART 3 for low-level debug"
help
Say Y here if you want the debug print routines to direct
@ -703,6 +715,14 @@ choice
Say Y here if you want kernel low-level debugging support
on Allwinner A1X based platforms on the UART1.
config DEBUG_SUNXI_R_UART
bool "Kernel low-level debugging messages via sunXi R_UART"
depends on MACH_SUN6I || MACH_SUN8I
select DEBUG_UART_8250
help
Say Y here if you want kernel low-level debugging support
on Allwinner A31/A23 based platforms on the R_UART.
config TEGRA_DEBUG_UART_AUTO_ODMDATA
bool "Kernel low-level debugging messages via Tegra UART via ODMDATA"
depends on ARCH_TEGRA
@ -937,6 +957,9 @@ config DEBUG_S3C2410_UART
config DEBUG_S3C24XX_UART
bool
config DEBUG_S5PV210_UART
bool
config DEBUG_OMAP2PLUS_UART
bool
depends on ARCH_OMAP2PLUS
@ -998,6 +1021,7 @@ config DEBUG_LL_INCLUDE
default "debug/msm.S" if DEBUG_MSM_UART || DEBUG_QCOM_UARTDM
default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART
default "debug/s3c24xx.S" if DEBUG_S3C24XX_UART
default "debug/s5pv210.S" if DEBUG_S5PV210_UART
default "debug/sirf.S" if DEBUG_SIRFPRIMA2_UART1 || DEBUG_SIRFMARCO_UART1
default "debug/sti.S" if DEBUG_STI_UART
default "debug/tegra.S" if DEBUG_TEGRA_UART
@ -1022,7 +1046,7 @@ config DEBUG_UART_8250
def_bool ARCH_DOVE || ARCH_EBSA110 || \
(FOOTBRIDGE && !DEBUG_DC21285_PORT) || \
ARCH_GEMINI || ARCH_IOP13XX || ARCH_IOP32X || \
ARCH_IOP33X || ARCH_IXP4XX || ARCH_KIRKWOOD || \
ARCH_IOP33X || ARCH_IXP4XX || \
ARCH_LPC32XX || ARCH_MV78XX0 || ARCH_ORION5X || ARCH_RPC
config DEBUG_UART_PHYS
@ -1032,6 +1056,7 @@ config DEBUG_UART_PHYS
default 0x01c28400 if DEBUG_SUNXI_UART1
default 0x01d0c000 if DEBUG_DAVINCI_DA8XX_UART1
default 0x01d0d000 if DEBUG_DAVINCI_DA8XX_UART2
default 0x01f02800 if DEBUG_SUNXI_R_UART
default 0x02530c00 if DEBUG_KEYSTONE_UART0
default 0x02531000 if DEBUG_KEYSTONE_UART1
default 0x03010fe0 if ARCH_RPC
@ -1078,10 +1103,10 @@ config DEBUG_UART_PHYS
default 0xe0000000 if ARCH_SPEAR13XX
default 0xf0000be0 if ARCH_EBSA110
default 0xf1012000 if DEBUG_MVEBU_UART_ALTERNATE
default 0xf1012000 if ARCH_DOVE || ARCH_KIRKWOOD || ARCH_MV78XX0 || \
default 0xf1012000 if ARCH_DOVE || ARCH_MV78XX0 || \
ARCH_ORION5X
default 0xf7fc9000 if DEBUG_BERLIN_UART
default 0xf8b00000 if DEBUG_HI3716_UART
default 0xf8b00000 if DEBUG_HIX5HD2_UART
default 0xf991e000 if DEBUG_QCOM_UARTDM
default 0xfcb00000 if DEBUG_HI3620_UART
default 0xfe800000 if ARCH_IOP32X
@ -1107,6 +1132,7 @@ config DEBUG_UART_VIRT
default 0xf1600000 if ARCH_INTEGRATOR
default 0xf1c28000 if DEBUG_SUNXI_UART0
default 0xf1c28400 if DEBUG_SUNXI_UART1
default 0xf1f02800 if DEBUG_SUNXI_R_UART
default 0xf2100000 if DEBUG_PXA_UART1
default 0xf4090000 if ARCH_LPC32XX
default 0xf4200000 if ARCH_GEMINI
@ -1133,7 +1159,7 @@ config DEBUG_UART_VIRT
default 0xfe230000 if DEBUG_PICOXCELL_UART
default 0xfe300000 if DEBUG_BCM_KONA_UART
default 0xfe800000 if ARCH_IOP32X
default 0xfeb00000 if DEBUG_HI3620_UART || DEBUG_HI3716_UART
default 0xfeb00000 if DEBUG_HI3620_UART || DEBUG_HIX5HD2_UART
default 0xfeb24000 if DEBUG_RK3X_UART0
default 0xfeb26000 if DEBUG_RK3X_UART1
default 0xfeb30c00 if DEBUG_KEYSTONE_UART0
@ -1143,7 +1169,6 @@ config DEBUG_UART_VIRT
default 0xfec20000 if DEBUG_DAVINCI_DMx_UART0
default 0xfed0c000 if DEBUG_DAVINCI_DA8XX_UART1
default 0xfed0d000 if DEBUG_DAVINCI_DA8XX_UART2
default 0xfed12000 if ARCH_KIRKWOOD
default 0xfed60000 if DEBUG_RK29_UART0
default 0xfed64000 if DEBUG_RK29_UART1 || DEBUG_RK3X_UART2
default 0xfed68000 if DEBUG_RK29_UART2 || DEBUG_RK3X_UART3

8
arch/arm/Makefile
View File

@ -159,14 +159,13 @@ machine-$(CONFIG_ARCH_EP93XX) += ep93xx
machine-$(CONFIG_ARCH_EXYNOS) += exynos
machine-$(CONFIG_ARCH_GEMINI) += gemini
machine-$(CONFIG_ARCH_HIGHBANK) += highbank
machine-$(CONFIG_ARCH_HI3xxx) += hisi
machine-$(CONFIG_ARCH_HISI) += hisi
machine-$(CONFIG_ARCH_INTEGRATOR) += integrator
machine-$(CONFIG_ARCH_IOP13XX) += iop13xx
machine-$(CONFIG_ARCH_IOP32X) += iop32x
machine-$(CONFIG_ARCH_IOP33X) += iop33x
machine-$(CONFIG_ARCH_IXP4XX) += ixp4xx
machine-$(CONFIG_ARCH_KEYSTONE) += keystone
machine-$(CONFIG_ARCH_KIRKWOOD) += kirkwood
machine-$(CONFIG_ARCH_KS8695) += ks8695
machine-$(CONFIG_ARCH_LPC32XX) += lpc32xx
machine-$(CONFIG_ARCH_MMP) += mmp
@ -175,6 +174,7 @@ machine-$(CONFIG_ARCH_MSM) += msm
machine-$(CONFIG_ARCH_MV78XX0) += mv78xx0
machine-$(CONFIG_ARCH_MVEBU) += mvebu
machine-$(CONFIG_ARCH_MXC) += imx
machine-$(CONFIG_ARCH_MEDIATEK) += mediatek
machine-$(CONFIG_ARCH_MXS) += mxs
machine-$(CONFIG_ARCH_NETX) += netx
machine-$(CONFIG_ARCH_NOMADIK) += nomadik
@ -213,11 +213,11 @@ machine-$(CONFIG_PLAT_SPEAR) += spear
plat-$(CONFIG_ARCH_EXYNOS) += samsung
plat-$(CONFIG_ARCH_OMAP) += omap
plat-$(CONFIG_ARCH_S3C64XX) += samsung
plat-$(CONFIG_ARCH_S5PV210) += samsung
plat-$(CONFIG_PLAT_IOP) += iop
plat-$(CONFIG_PLAT_ORION) += orion
plat-$(CONFIG_PLAT_PXA) += pxa
plat-$(CONFIG_PLAT_S3C24XX) += samsung
plat-$(CONFIG_PLAT_S5P) += samsung
plat-$(CONFIG_PLAT_VERSATILE) += versatile
ifeq ($(CONFIG_ARCH_EBSA110),y)
@ -241,7 +241,7 @@ MACHINE :=
endif
machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
platdirs := $(patsubst %,arch/arm/plat-%/,$(plat-y))
platdirs := $(patsubst %,arch/arm/plat-%/,$(sort $(plat-y)))
ifneq ($(CONFIG_ARCH_MULTIPLATFORM),y)
ifeq ($(KBUILD_SRC),)

15
arch/arm/boot/dts/Makefile
View File

@ -83,6 +83,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos5440-ssdk5440.dtb \
exynos5800-peach-pi.dtb
dtb-$(CONFIG_ARCH_HI3xxx) += hi3620-hi4511.dtb
dtb-$(CONFIG_ARCH_HIX5HD2) += hisi-x5hd2-dkb.dtb
dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \
ecx-2000.dtb
dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \
@ -90,8 +91,7 @@ dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \
dtb-$(CONFIG_ARCH_KEYSTONE) += k2hk-evm.dtb \
k2l-evm.dtb \
k2e-evm.dtb
kirkwood := \
kirkwood-b3.dtb \
dtb-$(CONFIG_MACH_KIRKWOOD) += kirkwood-b3.dtb \
kirkwood-cloudbox.dtb \
kirkwood-db-88f6281.dtb \
kirkwood-db-88f6282.dtb \
@ -150,8 +150,6 @@ kirkwood := \
kirkwood-ts219-6282.dtb \
kirkwood-ts419-6281.dtb \
kirkwood-ts419-6282.dtb
dtb-$(CONFIG_ARCH_KIRKWOOD) += $(kirkwood)
dtb-$(CONFIG_MACH_KIRKWOOD) += $(kirkwood)
dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb
dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb
@ -321,13 +319,17 @@ dtb-$(CONFIG_ARCH_QCOM) += \
dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb
dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb \
s3c6410-smdk6410.dtb
dtb-$(CONFIG_ARCH_S5PV210) += s5pv210-aquila.dtb \
s5pv210-goni.dtb \
s5pv210-smdkc110.dtb \
s5pv210-smdkv210.dtb \
s5pv210-torbreck.dtb
dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += r7s72100-genmai.dtb \
r8a7740-armadillo800eva.dtb \
r8a7778-bockw.dtb \
r8a7778-bockw-reference.dtb \
r8a7740-armadillo800eva-reference.dtb \
r8a7779-marzen.dtb \
r8a7779-marzen-reference.dtb \
r8a7791-koelsch.dtb \
r8a7790-lager.dtb \
sh73a0-kzm9g.dtb \
@ -339,7 +341,8 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb \
r7s72100-genmai.dtb \
r8a7791-henninger.dtb \
r8a7791-koelsch.dtb \
r8a7790-lager.dtb
r8a7790-lager.dtb \
r8a7779-marzen.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \
socfpga_cyclone5_socdk.dtb \
socfpga_cyclone5_sockit.dtb \

9
arch/arm/boot/dts/am33xx.dtsi
View File

@ -347,6 +347,15 @@
status = "disabled";
};
mailbox: mailbox@480C8000 {
compatible = "ti,omap4-mailbox";
reg = <0x480C8000 0x200>;
interrupts = <77>;
ti,hwmods = "mailbox";
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <8>;
};
timer1: timer@44e31000 {
compatible = "ti,am335x-timer-1ms";
reg = <0x44e31000 0x400>;

3
arch/arm/boot/dts/am4372.dtsi
View File

@ -168,9 +168,6 @@
ti,hwmods = "mailbox";
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <8>;
ti,mbox-names = "wkup_m3";
ti,mbox-data = <0 0 0 0>;
status = "disabled";
};
timer1: timer@44e31000 {

117
arch/arm/boot/dts/dra7.dtsi
View File

@ -338,6 +338,123 @@
status = "disabled";
};
mailbox1: mailbox@4a0f4000 {
compatible = "ti,omap4-mailbox";
reg = <0x4a0f4000 0x200>;
ti,hwmods = "mailbox1";
ti,mbox-num-users = <3>;
ti,mbox-num-fifos = <8>;
status = "disabled";
};
mailbox2: mailbox@4883a000 {
compatible = "ti,omap4-mailbox";
reg = <0x4883a000 0x200>;
ti,hwmods = "mailbox2";
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <12>;
status = "disabled";
};
mailbox3: mailbox@4883c000 {
compatible = "ti,omap4-mailbox";
reg = <0x4883c000 0x200>;
ti,hwmods = "mailbox3";
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <12>;
status = "disabled";
};
mailbox4: mailbox@4883e000 {
compatible = "ti,omap4-mailbox";
reg = <0x4883e000 0x200>;
ti,hwmods = "mailbox4";
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <12>;
status = "disabled";
};
mailbox5: mailbox@48840000 {
compatible = "ti,omap4-mailbox";
reg = <0x48840000 0x200>;
ti,hwmods = "mailbox5";
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <12>;
status = "disabled";
};
mailbox6: mailbox@48842000 {
compatible = "ti,omap4-mailbox";
reg = <0x48842000 0x200>;
ti,hwmods = "mailbox6";
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <12>;
status = "disabled";
};
mailbox7: mailbox@48844000 {
compatible = "ti,omap4-mailbox";
reg = <0x48844000 0x200>;
ti,hwmods = "mailbox7";
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <12>;
status = "disabled";
};
mailbox8: mailbox@48846000 {
compatible = "ti,omap4-mailbox";
reg = <0x48846000 0x200>;
ti,hwmods = "mailbox8";
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <12>;
status = "disabled";
};
mailbox9: mailbox@4885e000 {
compatible = "ti,omap4-mailbox";
reg = <0x4885e000 0x200>;
ti,hwmods = "mailbox9";
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <12>;
status = "disabled";
};
mailbox10: mailbox@48860000 {
compatible = "ti,omap4-mailbox";
reg = <0x48860000 0x200>;
ti,hwmods = "mailbox10";
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <12>;
status = "disabled";
};
mailbox11: mailbox@48862000 {
compatible = "ti,omap4-mailbox";
reg = <0x48862000 0x200>;
ti,hwmods = "mailbox11";
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <12>;
status = "disabled";
};
mailbox12: mailbox@48864000 {
compatible = "ti,omap4-mailbox";
reg = <0x48864000 0x200>;
ti,hwmods = "mailbox12";
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <12>;
status = "disabled";
};
mailbox13: mailbox@48802000 {
compatible = "ti,omap4-mailbox";
reg = <0x48802000 0x200>;
ti,hwmods = "mailbox13";
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <12>;
status = "disabled";
};
timer1: timer@4ae18000 {
compatible = "ti,omap5430-timer";
reg = <0x4ae18000 0x80>;

1
arch/arm/boot/dts/hi3620.dtsi
View File

@ -33,6 +33,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "hisilicon,hi3620-smp";
cpu@0 {
device_type = "cpu";

53
arch/arm/boot/dts/hisi-x5hd2-dkb.dts Normal file
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@ -0,0 +1,53 @@
/*
* Copyright (c) 2013-2014 Linaro Ltd.
* Copyright (c) 2013-2014 Hisilicon Limited.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* publishhed by the Free Software Foundation.
*/
/dts-v1/;
#include "hisi-x5hd2.dtsi"
/ {
model = "Hisilicon HIX5HD2 Development Board";
compatible = "hisilicon,hix5hd2";
chosen {
bootargs = "console=ttyAMA0,115200 earlyprintk";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "hisilicon,hix5hd2-smp";
cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0>;
next-level-cache = <&l2>;
};
cpu@1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <1>;
next-level-cache = <&l2>;
};
};
memory {
device_type = "memory";
reg = <0x00000000 0x80000000>;
};
};
&timer0 {
status = "okay";
};
&uart0 {
status = "okay";
};

170
arch/arm/boot/dts/hisi-x5hd2.dtsi Normal file
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@ -0,0 +1,170 @@
/*
* Copyright (c) 2013-2014 Linaro Ltd.
* Copyright (c) 2013-2014 Hisilicon Limited.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* publishhed by the Free Software Foundation.
*/
#include "skeleton.dtsi"
#include <dt-bindings/clock/hix5hd2-clock.h>
/ {
aliases {
serial0 = &uart0;
};
gic: interrupt-controller@f8a01000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
/* gic dist base, gic cpu base */
reg = <0xf8a01000 0x1000>, <0xf8a00100 0x100>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&gic>;
ranges = <0 0xf8000000 0x8000000>;
amba {
#address-cells = <1>;
#size-cells = <1>;
compatible = "arm,amba-bus";
ranges;
timer0: timer@00002000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x00002000 0x1000>;
/* timer00 & timer01 */
interrupts = <0 24 4>;
clocks = <&clock HIX5HD2_FIXED_24M>;
status = "disabled";
};
timer1: timer@00a29000 {
/*
* Only used in NORMAL state, not available ins
* SLOW or DOZE state.
* The rate is fixed in 24MHz.
*/
compatible = "arm,sp804", "arm,primecell";
reg = <0x00a29000 0x1000>;
/* timer10 & timer11 */
interrupts = <0 25 4>;
clocks = <&clock HIX5HD2_FIXED_24M>;
status = "disabled";
};
timer2: timer@00a2a000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x00a2a000 0x1000>;
/* timer20 & timer21 */
interrupts = <0 26 4>;
clocks = <&clock HIX5HD2_FIXED_24M>;
status = "disabled";
};
timer3: timer@00a2b000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x00a2b000 0x1000>;
/* timer30 & timer31 */
interrupts = <0 27 4>;
clocks = <&clock HIX5HD2_FIXED_24M>;
status = "disabled";
};
timer4: timer@00a81000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x00a81000 0x1000>;
/* timer30 & timer31 */
interrupts = <0 28 4>;
clocks = <&clock HIX5HD2_FIXED_24M>;
status = "disabled";
};
uart0: uart@00b00000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x00b00000 0x1000>;
interrupts = <0 49 4>;
clocks = <&clock HIX5HD2_FIXED_83M>;
clock-names = "apb_pclk";
status = "disabled";
};
uart1: uart@00006000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x00006000 0x1000>;
interrupts = <0 50 4>;
clocks = <&clock HIX5HD2_FIXED_83M>;
clock-names = "apb_pclk";
status = "disabled";
};
uart2: uart@00b02000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x00b02000 0x1000>;
interrupts = <0 51 4>;
clocks = <&clock HIX5HD2_FIXED_83M>;
clock-names = "apb_pclk";
status = "disabled";
};
uart3: uart@00b03000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x00b03000 0x1000>;
interrupts = <0 52 4>;
clocks = <&clock HIX5HD2_FIXED_83M>;
clock-names = "apb_pclk";
status = "disabled";
};
uart4: uart@00b04000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xb04000 0x1000>;
interrupts = <0 53 4>;
clocks = <&clock HIX5HD2_FIXED_83M>;
clock-names = "apb_pclk";
status = "disabled";
};
};
local_timer@00a00600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x00a00600 0x20>;
interrupts = <1 13 0xf01>;
};
l2: l2-cache {
compatible = "arm,pl310-cache";
reg = <0x00a10000 0x100000>;
interrupts = <0 15 4>;
cache-unified;
cache-level = <2>;
};
sysctrl: system-controller@00000000 {
compatible = "hisilicon,sysctrl";
reg = <0x00000000 0x1000>;
reboot-offset = <0x4>;
};
cpuctrl@00a22000 {
compatible = "hisilicon,cpuctrl";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x00a22000 0x2000>;
ranges = <0 0x00a22000 0x2000>;
clock: clock@0 {
compatible = "hisilicon,hix5hd2-clock";
reg = <0 0x2000>;
#clock-cells = <1>;
};
};
};
};

25
arch/arm/boot/dts/mt6589-aquaris5.dts Normal file
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@ -0,0 +1,25 @@
/*
* Copyright (c) 2014 MundoReader S.L.
* Author: Matthias Brugger <matthias.bgg@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/dts-v1/;
#include "mt6589.dtsi"
/ {
model = "bq Aquaris5";
memory {
reg = <0x80000000 0x40000000>;
};
};

94
arch/arm/boot/dts/mt6589.dtsi Normal file
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@ -0,0 +1,94 @@
/*
* Copyright (c) 2014 MundoReader S.L.
* Author: Matthias Brugger <matthias.bgg@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "skeleton.dtsi"
/ {
compatible = "mediatek,mt6589";
interrupt-parent = <&gic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x0>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x1>;
};
cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x2>;
};
cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x3>;
};
};
clocks {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
system_clk: dummy13m {
compatible = "fixed-clock";
clock-frequency = <13000000>;
#clock-cells = <0>;
};
rtc_clk: dummy32k {
compatible = "fixed-clock";
clock-frequency = <32000>;
#clock-cells = <0>;
};
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
timer: timer@10008000 {
compatible = "mediatek,mt6577-timer";
reg = <0x10008000 0x80>;
interrupts = <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>;
clocks = <&system_clk>, <&rtc_clk>;
clock-names = "system-clk", "rtc-clk";
};
gic: interrupt-controller@10212000 {
compatible = "arm,cortex-a15-gic";
interrupt-controller;
#interrupt-cells = <3>;
reg = <0x10211000 0x1000>,
<0x10212000 0x1000>,
<0x10214000 0x2000>,
<0x10216000 0x2000>;
};
};
};

2
arch/arm/boot/dts/omap2420.dtsi
View File

@ -157,6 +157,8 @@
interrupts = <26>, <34>;
interrupt-names = "dsp", "iva";
ti,hwmods = "mailbox";
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <6>;
};
timer1: timer@48028000 {

2
arch/arm/boot/dts/omap2430.dtsi
View File

@ -247,6 +247,8 @@
reg = <0x48094000 0x200>;
interrupts = <26>;
ti,hwmods = "mailbox";
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <6>;
};
timer1: timer@49018000 {

2
arch/arm/boot/dts/omap3.dtsi
View File

@ -332,6 +332,8 @@
ti,hwmods = "mailbox";
reg = <0x48094000 0x200>;
interrupts = <26>;
ti,mbox-num-users = <2>;
ti,mbox-num-fifos = <2>;
};
mcspi1: spi@48098000 {

9
arch/arm/boot/dts/omap4.dtsi
View File

@ -649,6 +649,15 @@
};
};
mailbox: mailbox@4a0f4000 {
compatible = "ti,omap4-mailbox";
reg = <0x4a0f4000 0x200>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mailbox";
ti,mbox-num-users = <3>;
ti,mbox-num-fifos = <8>;
};
timer1: timer@4a318000 {
compatible = "ti,omap3430-timer";
reg = <0x4a318000 0x80>;

2
arch/arm/boot/dts/omap5.dtsi
View File

@ -640,6 +640,8 @@
reg = <0x4a0f4000 0x200>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mailbox";
ti,mbox-num-users = <3>;
ti,mbox-num-fifos = <8>;
};
timer1: timer@4ae18000 {

121
arch/arm/boot/dts/r8a7779-marzen-reference.dts
View File

@ -1,121 +0,0 @@
/*
* Reference Device Tree Source for the Marzen board
*
* Copyright (C) 2013 Renesas Solutions Corp.
* Copyright (C) 2013 Simon Horman
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
/dts-v1/;
#include "r8a7779.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "marzen";
compatible = "renesas,marzen-reference", "renesas,r8a7779";
chosen {
bootargs = "console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel root=/dev/nfs ip=on rw";
};
memory {
device_type = "memory";
reg = <0x60000000 0x40000000>;
};
fixedregulator3v3: fixedregulator@0 {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
lan0@18000000 {
compatible = "smsc,lan9220", "smsc,lan9115";
reg = <0x18000000 0x100>;
pinctrl-0 = <&lan0_pins>;
pinctrl-names = "default";
phy-mode = "mii";
interrupt-parent = <&irqpin0>;
interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
smsc,irq-push-pull;
reg-io-width = <4>;
vddvario-supply = <&fixedregulator3v3>;
vdd33a-supply = <&fixedregulator3v3>;
};
leds {
compatible = "gpio-leds";
led2 {
gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
};
led3 {
gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
};
led4 {
gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;
};
};
};
&irqpin0 {
status = "okay";
};
&pfc {
pinctrl-0 = <&scif2_pins &scif4_pins>;
pinctrl-names = "default";
lan0_pins: lan0 {
intc {
renesas,groups = "intc_irq1_b";
renesas,function = "intc";
};
lbsc {
renesas,groups = "lbsc_ex_cs0";
renesas,function = "lbsc";
};
};
scif2_pins: serial2 {
renesas,groups = "scif2_data_c";
renesas,function = "scif2";
};
scif4_pins: serial4 {
renesas,groups = "scif4_data";
renesas,function = "scif4";
};
sdhi0_pins: sd0 {
renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
renesas,function = "sdhi0";
};
hspi0_pins: hspi0 {
renesas,groups = "hspi0";
renesas,function = "hspi0";
};
};
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-names = "default";
vmmc-supply = <&fixedregulator3v3>;
bus-width = <4>;
status = "okay";
};
&hspi0 {
pinctrl-0 = <&hspi0_pins>;
pinctrl-names = "default";
status = "okay";
};

116
arch/arm/boot/dts/r8a7779-marzen.dts
View File

@ -11,17 +11,131 @@
/dts-v1/;
#include "r8a7779.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "marzen";
compatible = "renesas,marzen", "renesas,r8a7779";
aliases {
serial2 = &scif2;
serial4 = &scif4;
};
chosen {
bootargs = "console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel root=/dev/nfs ip=on";
bootargs = "console=ttySC2,115200 ignore_loglevel root=/dev/nfs ip=on";
};
memory {
device_type = "memory";
reg = <0x60000000 0x40000000>;
};
fixedregulator3v3: fixedregulator@0 {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
lan0@18000000 {
compatible = "smsc,lan9220", "smsc,lan9115";
reg = <0x18000000 0x100>;
pinctrl-0 = <&lan0_pins>;
pinctrl-names = "default";
phy-mode = "mii";
interrupt-parent = <&irqpin0>;
interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
smsc,irq-push-pull;
reg-io-width = <4>;
vddvario-supply = <&fixedregulator3v3>;
vdd33a-supply = <&fixedregulator3v3>;
};
leds {
compatible = "gpio-leds";
led2 {
gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
};
led3 {
gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
};
led4 {
gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;
};
};
};
&irqpin0 {
status = "okay";
};
&extal_clk {
clock-frequency = <31250000>;
};
&pfc {
lan0_pins: lan0 {
intc {
renesas,groups = "intc_irq1_b";
renesas,function = "intc";
};
lbsc {
renesas,groups = "lbsc_ex_cs0";
renesas,function = "lbsc";
};
};
scif2_pins: serial2 {
renesas,groups = "scif2_data_c";
renesas,function = "scif2";
};
scif4_pins: serial4 {
renesas,groups = "scif4_data";
renesas,function = "scif4";
};
sdhi0_pins: sd0 {
renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
renesas,function = "sdhi0";
};
hspi0_pins: hspi0 {
renesas,groups = "hspi0";
renesas,function = "hspi0";
};
};
&scif2 {
pinctrl-0 = <&scif2_pins>;
pinctrl-names = "default";
status = "okay";
};
&scif4 {
pinctrl-0 = <&scif4_pins>;
pinctrl-names = "default";
status = "okay";
};
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-names = "default";
vmmc-supply = <&fixedregulator3v3>;
bus-width = <4>;
status = "okay";
};
&hspi0 {
pinctrl-0 = <&hspi0_pins>;
pinctrl-names = "default";
status = "okay";
};

220
arch/arm/boot/dts/r8a7779.dtsi
View File

@ -11,6 +11,7 @@
/include/ "skeleton.dtsi"
#include <dt-bindings/clock/r8a7779-clock.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
@ -25,21 +26,25 @@
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
clock-frequency = <1000000000>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
clock-frequency = <1000000000>;
};
cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <2>;
clock-frequency = <1000000000>;
};
cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <3>;
clock-frequency = <1000000000>;
};
};
@ -157,6 +162,7 @@
compatible = "renesas,i2c-r8a7779";
reg = <0xffc70000 0x1000>;
interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
status = "disabled";
};
@ -166,6 +172,7 @@
compatible = "renesas,i2c-r8a7779";
reg = <0xffc71000 0x1000>;
interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
status = "disabled";
};
@ -175,6 +182,7 @@
compatible = "renesas,i2c-r8a7779";
reg = <0xffc72000 0x1000>;
interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
status = "disabled";
};
@ -184,6 +192,67 @@
compatible = "renesas,i2c-r8a7779";
reg = <0xffc73000 0x1000>;
interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
status = "disabled";
};
scif0: serial@ffe40000 {
compatible = "renesas,scif-r8a7779", "renesas,scif";
reg = <0xffe40000 0x100>;
interrupt-parent = <&gic>;
interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg_clocks R8A7779_CLK_P>;
clock-names = "sci_ick";
status = "disabled";
};
scif1: serial@ffe41000 {
compatible = "renesas,scif-r8a7779", "renesas,scif";
reg = <0xffe41000 0x100>;
interrupt-parent = <&gic>;
interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg_clocks R8A7779_CLK_P>;
clock-names = "sci_ick";
status = "disabled";
};
scif2: serial@ffe42000 {
compatible = "renesas,scif-r8a7779", "renesas,scif";
reg = <0xffe42000 0x100>;
interrupt-parent = <&gic>;
interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg_clocks R8A7779_CLK_P>;
clock-names = "sci_ick";
status = "disabled";
};
scif3: serial@ffe43000 {
compatible = "renesas,scif-r8a7779", "renesas,scif";
reg = <0xffe43000 0x100>;
interrupt-parent = <&gic>;
interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg_clocks R8A7779_CLK_P>;
clock-names = "sci_ick";
status = "disabled";
};
scif4: serial@ffe44000 {
compatible = "renesas,scif-r8a7779", "renesas,scif";
reg = <0xffe44000 0x100>;
interrupt-parent = <&gic>;
interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg_clocks R8A7779_CLK_P>;
clock-names = "sci_ick";
status = "disabled";
};
scif5: serial@ffe45000 {
compatible = "renesas,scif-r8a7779", "renesas,scif";
reg = <0xffe45000 0x100>;
interrupt-parent = <&gic>;
interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg_clocks R8A7779_CLK_P>;
clock-names = "sci_ick";
status = "disabled";
};
@ -201,12 +270,14 @@
compatible = "renesas,rcar-sata";
reg = <0xfc600000 0x2000>;
interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7779_CLK_SATA>;
};
sdhi0: sd@ffe4c000 {
compatible = "renesas,sdhi-r8a7779";
reg = <0xffe4c000 0x100>;
interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
cap-sd-highspeed;
cap-sdio-irq;
status = "disabled";
@ -216,6 +287,7 @@
compatible = "renesas,sdhi-r8a7779";
reg = <0xffe4d000 0x100>;
interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
cap-sd-highspeed;
cap-sdio-irq;
status = "disabled";
@ -225,6 +297,7 @@
compatible = "renesas,sdhi-r8a7779";
reg = <0xffe4e000 0x100>;
interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
cap-sd-highspeed;
cap-sdio-irq;
status = "disabled";
@ -234,6 +307,7 @@
compatible = "renesas,sdhi-r8a7779";
reg = <0xffe4f000 0x100>;
interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
cap-sd-highspeed;
cap-sdio-irq;
status = "disabled";
@ -245,6 +319,7 @@
interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
status = "disabled";
};
@ -254,6 +329,7 @@
interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
status = "disabled";
};
@ -263,6 +339,150 @@
interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
status = "disabled";
};
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
/* External root clock */
extal_clk: extal_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overriden by the board. */
clock-frequency = <0>;
clock-output-names = "extal";
};
/* Special CPG clocks */
cpg_clocks: clocks@ffc80000 {
compatible = "renesas,r8a7779-cpg-clocks";
reg = <0xffc80000 0x30>;
clocks = <&extal_clk>;
#clock-cells = <1>;
clock-output-names = "plla", "z", "zs", "s",
"s1", "p", "b", "out";
};
/* Fixed factor clocks */
i_clk: i_clk {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
#clock-cells = <0>;
clock-div = <2>;
clock-mult = <1>;
clock-output-names = "i";
};
s3_clk: s3_clk {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
#clock-cells = <0>;
clock-div = <8>;
clock-mult = <1>;
clock-output-names = "s3";
};
s4_clk: s4_clk {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
#clock-cells = <0>;
clock-div = <16>;
clock-mult = <1>;
clock-output-names = "s4";
};
g_clk: g_clk {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
#clock-cells = <0>;
clock-div = <24>;
clock-mult = <1>;
clock-output-names = "g";
};
/* Gate clocks */
mstp0_clks: clocks@ffc80030 {
compatible = "renesas,r8a7779-mstp-clocks",
"renesas,cpg-mstp-clocks";
reg = <0xffc80030 4>;
clocks = <&cpg_clocks R8A7779_CLK_S>,
<&cpg_clocks R8A7779_CLK_P>,
<&cpg_clocks R8A7779_CLK_P>,
<&cpg_clocks R8A7779_CLK_P>,
<&cpg_clocks R8A7779_CLK_S>,
<&cpg_clocks R8A7779_CLK_S>,
<&cpg_clocks R8A7779_CLK_S1>,
<&cpg_clocks R8A7779_CLK_S1>,
<&cpg_clocks R8A7779_CLK_S1>,
<&cpg_clocks R8A7779_CLK_S1>,
<&cpg_clocks R8A7779_CLK_S1>,
<&cpg_clocks R8A7779_CLK_S1>,
<&cpg_clocks R8A7779_CLK_P>,
<&cpg_clocks R8A7779_CLK_P>,
<&cpg_clocks R8A7779_CLK_P>,
<&cpg_clocks R8A7779_CLK_P>;
#clock-cells = <1>;
renesas,clock-indices = <
R8A7779_CLK_HSPI R8A7779_CLK_TMU2
R8A7779_CLK_TMU1 R8A7779_CLK_TMU0
R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0
R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2
R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0
R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
>;
clock-output-names =
"hspi", "tmu2", "tmu1", "tmu0", "hscif1",
"hscif0", "scif5", "scif4", "scif3", "scif2",
"scif1", "scif0", "i2c3", "i2c2", "i2c1",
"i2c0";
};
mstp1_clks: clocks@ffc80034 {
compatible = "renesas,r8a7779-mstp-clocks",
"renesas,cpg-mstp-clocks";
reg = <0xffc80034 4>, <0xffc80044 4>;
clocks = <&cpg_clocks R8A7779_CLK_P>,
<&cpg_clocks R8A7779_CLK_P>,
<&cpg_clocks R8A7779_CLK_S>,
<&cpg_clocks R8A7779_CLK_S>,
<&cpg_clocks R8A7779_CLK_S>,
<&cpg_clocks R8A7779_CLK_S>,
<&cpg_clocks R8A7779_CLK_P>,
<&cpg_clocks R8A7779_CLK_P>,
<&cpg_clocks R8A7779_CLK_P>,
<&cpg_clocks R8A7779_CLK_S>;
#clock-cells = <1>;
renesas,clock-indices = <
R8A7779_CLK_USB01 R8A7779_CLK_USB2
R8A7779_CLK_DU R8A7779_CLK_VIN2
R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
R8A7779_CLK_ETHER R8A7779_CLK_SATA
R8A7779_CLK_PCIE R8A7779_CLK_VIN3
>;
clock-output-names =
"usb01", "usb2",
"du", "vin2",
"vin1", "vin0",
"ether", "sata",
"pcie", "vin3";
};
mstp3_clks: clocks@ffc8003c {
compatible = "renesas,r8a7779-mstp-clocks",
"renesas,cpg-mstp-clocks";
reg = <0xffc8003c 4>;
clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
<&s4_clk>, <&s4_clk>;
#clock-cells = <1>;
renesas,clock-indices = <
R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
>;
clock-output-names =
"sdhi3", "sdhi2", "sdhi1", "sdhi0",
"mmc1", "mmc0";
};
};
};

392
arch/arm/boot/dts/s5pv210-aquila.dts Normal file
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@ -0,0 +1,392 @@
/*
* Samsung's S5PV210 SoC device tree source
*
* Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
*
* Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
* Tomasz Figa <t.figa@samsung.com>
*
* Board device tree source for Samsung Aquila board.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "s5pv210.dtsi"
/ {
model = "Samsung Aquila based on S5PC110";
compatible = "samsung,aquila", "samsung,s5pv210";
aliases {
i2c3 = &i2c_pmic;
};
chosen {
bootargs = "console=ttySAC2,115200n8 root=/dev/mmcblk1p5 rw rootwait ignore_loglevel earlyprintk";
};
memory {
device_type = "memory";
reg = <0x30000000 0x05000000
0x40000000 0x18000000>;
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
vtf_reg: fixed-regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "V_TF_2.8V";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
gpios = <&mp05 4 0>;
enable-active-high;
};
pda_reg: fixed-regulator@1 {
compatible = "regulator-fixed";
regulator-name = "VCC_1.8V_PDA";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
reg = <1>;
};
bat_reg: fixed-regulator@2 {
compatible = "regulator-fixed";
regulator-name = "V_BAT";
regulator-min-microvolt = <3700000>;
regulator-max-microvolt = <3700000>;
reg = <2>;
};
};
i2c_pmic: i2c-pmic {
compatible = "i2c-gpio";
gpios = <&gpj4 0 0>, /* sda */
<&gpj4 3 0>; /* scl */
i2c-gpio,delay-us = <2>; /* ~100 kHz */
#address-cells = <1>;
#size-cells = <0>;
pmic@66 {
compatible = "national,lp3974";
reg = <0x66>;
max8998,pmic-buck1-default-dvs-idx = <0>;
max8998,pmic-buck1-dvs-gpios = <&gph0 3 0>,
<&gph0 4 0>;
max8998,pmic-buck1-dvs-voltage = <1200000>, <1200000>,
<1200000>, <1200000>;
max8998,pmic-buck2-default-dvs-idx = <0>;
max8998,pmic-buck2-dvs-gpio = <&gph0 5 0>;
max8998,pmic-buck2-dvs-voltage = <1200000>, <1200000>;
regulators {
ldo2_reg: LDO2 {
regulator-name = "VALIVE_1.1V";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
};
ldo3_reg: LDO3 {
regulator-name = "VUSB+MIPI_1.1V";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
};
ldo4_reg: LDO4 {
regulator-name = "VADC_3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
ldo5_reg: LDO5 {
regulator-name = "VTF_2.8V";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
};
ldo6_reg: LDO6 {
regulator-name = "VCC_3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
ldo7_reg: LDO7 {
regulator-name = "VCC_3.0V";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
regulator-boot-on;
};
ldo8_reg: LDO8 {
regulator-name = "VUSB+VDAC_3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
ldo9_reg: LDO9 {
regulator-name = "VCC+VCAM_2.8V";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
};
ldo10_reg: LDO10 {
regulator-name = "VPLL_1.1V";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
regulator-boot-on;
};
ldo11_reg: LDO11 {
regulator-name = "CAM_IO_2.8V";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
};
ldo12_reg: LDO12 {
regulator-name = "CAM_ISP_1.2V";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
ldo13_reg: LDO13 {
regulator-name = "CAM_A_2.8V";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
};
ldo14_reg: LDO14 {
regulator-name = "CAM_CIF_1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ldo15_reg: LDO15 {
regulator-name = "CAM_AF_3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
ldo16_reg: LDO16 {
regulator-name = "VMIPI_1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ldo17_reg: LDO17 {
regulator-name = "CAM_8M_1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
buck1_reg: BUCK1 {
regulator-name = "VARM_1.2V";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
buck2_reg: BUCK2 {
regulator-name = "VINT_1.2V";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
buck3_reg: BUCK3 {
regulator-name = "VCC_1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
buck4_reg: BUCK4 {
regulator-name = "CAM_CORE_1.2V";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
vichg_reg: ENVICHG {
regulator-name = "VICHG";
};
safeout1_reg: ESAFEOUT1 {
regulator-name = "SAFEOUT1";
regulator-always-on;
};
safeout2_reg: ESAFEOUT2 {
regulator-name = "SAFEOUT2";
regulator-boot-on;
};
};
};
};
gpio-keys {
compatible = "gpio-keys";
power-key {
gpios = <&gph2 6 1>;
linux,code = <KEY_POWER>;
label = "power";
debounce-interval = <1>;
gpio-key,wakeup;
};
};
};
&xusbxti {
clock-frequency = <24000000>;
};
&keypad {
linux,input-no-autorepeat;
linux,input-wakeup;
samsung,keypad-num-rows = <3>;
samsung,keypad-num-columns = <3>;
pinctrl-names = "default";
pinctrl-0 = <&keypad_row0>, <&keypad_row1>, <&keypad_row2>,
<&keypad_col0>, <&keypad_col1>, <&keypad_col2>;
status = "okay";
key_1 {
keypad,row = <0>;
keypad,column = <1>;
linux,code = <KEY_CONNECT>;
};
key_2 {
keypad,row = <0>;
keypad,column = <2>;
linux,code = <KEY_BACK>;
};
key_3 {
keypad,row = <1>;
keypad,column = <1>;
linux,code = <KEY_CAMERA_FOCUS>;
};
key_4 {
keypad,row = <1>;
keypad,column = <2>;
linux,code = <KEY_VOLUMEUP>;
};
key_5 {
keypad,row = <2>;
keypad,column = <1>;
linux,code = <KEY_CAMERA>;
};
key_6 {
keypad,row = <2>;
keypad,column = <2>;
linux,code = <KEY_VOLUMEDOWN>;
};
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&uart2 {
status = "okay";
};
&uart3 {
status = "okay";
};
&sdhci0 {
bus-width = <4>;
non-removable;
status = "okay";
vmmc-supply = <&ldo5_reg>;
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4>;
pinctrl-names = "default";
};
&sdhci2 {
bus-width = <4>;
cd-gpios = <&gph3 4 1>;
vmmc-supply = <&vtf_reg>;
cd-inverted;
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &t_flash_detect>;
pinctrl-names = "default";
status = "okay";
};
&onenand {
status = "okay";
};
&hsotg {
vusb_a-supply = <&ldo3_reg>;
vusb_d-supply = <&ldo8_reg>;
status = "okay";
};
&usbphy {
status = "okay";
};
&fimd {
pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>;
pinctrl-names = "default";
status = "okay";
display-timings {
native-mode = <&timing0>;
timing0: timing {
clock-frequency = <0>;
hactive = <800>;
vactive = <480>;
hfront-porch = <16>;
hback-porch = <16>;
hsync-len = <2>;
vback-porch = <3>;
vfront-porch = <28>;
vsync-len = <1>;
};
};
};
&pinctrl0 {
t_flash_detect: t-flash-detect {
samsung,pins = "gph3-4";
samsung,pin-function = <0>;
samsung,pin-pud = <0>;
};
};

449
arch/arm/boot/dts/s5pv210-goni.dts Normal file
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@ -0,0 +1,449 @@
/*
* Samsung's S5PV210 SoC device tree source
*
* Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
*
* Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
* Tomasz Figa <t.figa@samsung.com>
*
* Board device tree source for Samsung Goni board.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "s5pv210.dtsi"
/ {
model = "Samsung Goni based on S5PC110";
compatible = "samsung,goni", "samsung,s5pv210";
aliases {
i2c3 = &i2c_pmic;
};
chosen {
bootargs = "console=ttySAC0,115200n8 root=/dev/mmcblk0p5 rw rootwait ignore_loglevel earlyprintk";
};
memory {
device_type = "memory";
reg = <0x30000000 0x05000000
0x40000000 0x10000000
0x50000000 0x08000000>;
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
vtf_reg: fixed-regulator@0 {
compatible = "regulator-fixed";
regulator-name = "V_TF_2.8V";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
reg = <0>;
gpios = <&mp05 4 0>;
enable-active-high;
};
pda_reg: fixed-regulator@1 {
compatible = "regulator-fixed";
regulator-name = "VCC_1.8V_PDA";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
reg = <1>;
};
bat_reg: fixed-regulator@2 {
compatible = "regulator-fixed";
regulator-name = "V_BAT";
regulator-min-microvolt = <3700000>;
regulator-max-microvolt = <3700000>;
reg = <2>;
};
tsp_reg: fixed-regulator@3 {
compatible = "regulator-fixed";
regulator-name = "TSP_VDD";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
reg = <3>;
gpios = <&gpj1 3 0>;
enable-active-high;
};
};
i2c_pmic: i2c-pmic {
compatible = "i2c-gpio";
gpios = <&gpj4 0 0>, /* sda */
<&gpj4 3 0>; /* scl */
i2c-gpio,delay-us = <2>; /* ~100 kHz */
#address-cells = <1>;
#size-cells = <0>;
pmic@66 {
compatible = "national,lp3974";
reg = <0x66>;
max8998,pmic-buck1-default-dvs-idx = <0>;
max8998,pmic-buck1-dvs-gpios = <&gph0 3 0>,
<&gph0 4 0>;
max8998,pmic-buck1-dvs-voltage = <1200000>, <1200000>,
<1200000>, <1200000>;
max8998,pmic-buck2-default-dvs-idx = <0>;
max8998,pmic-buck2-dvs-gpio = <&gph0 5 0>;
max8998,pmic-buck2-dvs-voltage = <1200000>, <1200000>;
regulators {
ldo2_reg: LDO2 {
regulator-name = "VALIVE_1.1V";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
};
ldo3_reg: LDO3 {
regulator-name = "VUSB+MIPI_1.1V";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
};
ldo4_reg: LDO4 {
regulator-name = "VADC_3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
ldo5_reg: LDO5 {
regulator-name = "VTF_2.8V";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
ldo6_reg: LDO6 {
regulator-name = "VCC_3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
ldo7_reg: LDO7 {
regulator-name = "VLCD_1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ldo8_reg: LDO8 {
regulator-name = "VUSB+VDAC_3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
ldo9_reg: LDO9 {
regulator-name = "VCC+VCAM_2.8V";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
ldo10_reg: LDO10 {
regulator-name = "VPLL_1.1V";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-boot-on;
};
ldo11_reg: LDO11 {
regulator-name = "CAM_IO_2.8V";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
ldo12_reg: LDO12 {
regulator-name = "CAM_ISP_1.2V";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
ldo13_reg: LDO13 {
regulator-name = "CAM_A_2.8V";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
ldo14_reg: LDO14 {
regulator-name = "CAM_CIF_1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
ldo15_reg: LDO15 {
regulator-name = "CAM_AF_3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
ldo16_reg: LDO16 {
regulator-name = "VMIPI_1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
ldo17_reg: LDO17 {
regulator-name = "CAM_8M_1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
buck1_reg: BUCK1 {
regulator-name = "VARM_1.2V";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
buck2_reg: BUCK2 {
regulator-name = "VINT_1.2V";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
buck3_reg: BUCK3 {
regulator-name = "VCC_1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
buck4_reg: BUCK4 {
regulator-name = "CAM_CORE_1.2V";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
};
};
};
gpio-keys {
compatible = "gpio-keys";
power-key {
gpios = <&gph2 6 1>;
linux,code = <KEY_POWER>;
label = "power";
debounce-interval = <1>;
gpio-key,wakeup;
};
};
};
&xusbxti {
clock-frequency = <24000000>;
};
&keypad {
linux,input-no-autorepeat;
linux,input-wakeup;
samsung,keypad-num-rows = <3>;
samsung,keypad-num-columns = <3>;
pinctrl-names = "default";
pinctrl-0 = <&keypad_row0>, <&keypad_row1>, <&keypad_row2>,
<&keypad_col0>, <&keypad_col1>, <&keypad_col2>;
status = "okay";
key_1 {
keypad,row = <0>;
keypad,column = <1>;
linux,code = <KEY_CONNECT>;
};
key_2 {
keypad,row = <0>;
keypad,column = <2>;
linux,code = <KEY_BACK>;
};
key_3 {
keypad,row = <1>;
keypad,column = <1>;
linux,code = <KEY_CAMERA_FOCUS>;
};
key_4 {
keypad,row = <1>;
keypad,column = <2>;
linux,code = <KEY_VOLUMEUP>;
};
key_5 {
keypad,row = <2>;
keypad,column = <1>;
linux,code = <KEY_CAMERA>;
};
key_6 {
keypad,row = <2>;
keypad,column = <2>;
linux,code = <KEY_VOLUMEDOWN>;
};
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&uart2 {
status = "okay";
};
&uart3 {
status = "okay";
};
&sdhci0 {
bus-width = <4>;
non-removable;
vmmc-supply = <&ldo5_reg>;
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus1 &sd0_bus4>;
pinctrl-names = "default";
status = "okay";
};
&sdhci2 {
bus-width = <4>;
cd-gpios = <&gph3 4 1>;
vmmc-supply = <&vtf_reg>;
cd-inverted;
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>;
pinctrl-names = "default";
status = "okay";
};
&hsotg {
vusb_a-supply = <&ldo3_reg>;
vusb_d-supply = <&ldo8_reg>;
status = "okay";
};
&usbphy {
status = "okay";
};
&i2c2 {
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <400000>;
samsung,i2c-slave-addr = <0x10>;
status = "okay";
tsp@4a {
compatible = "atmel,maxtouch";
reg = <0x4a>;
interrupt-parent = <&gpj0>;
interrupts = <5 2>;
atmel,x-line = <17>;
atmel,y-line = <11>;
atmel,x-size = <800>;
atmel,y-size = <480>;
atmel,burst-length = <0x21>;
atmel,threshold = <0x28>;
atmel,orientation = <1>;
vdd-supply = <&tsp_reg>;
};
};
&i2c0 {
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <100000>;
samsung,i2c-slave-addr = <0x10>;
status = "okay";
noon010pc30: sensor@30 {
compatible = "siliconfile,noon010pc30";
reg = <0x30>;
vddio-supply = <&ldo11_reg>;
vdda-supply = <&ldo13_reg>;
vdd_core-supply = <&ldo14_reg>;
clock-frequency = <16000000>;
clocks = <&clock_cam 0>;
clock-names = "mclk";
nreset-gpios = <&gpb 2 0>;
nstby-gpios = <&gpb 0 0>;
port {
noon010pc30_ep: endpoint {
remote-endpoint = <&fimc0_ep>;
bus-width = <8>;
hsync-active = <0>;
vsync-active = <1>;
pclk-sample = <1>;
};
};
};
};
&camera {
pinctrl-0 = <&cam_port_a_io &cam_port_a_clk_active>;
pinctrl-1 = <&cam_port_a_io &cam_port_a_clk_idle>;
pinctrl-names = "default", "idle";
parallel-ports {
#address-cells = <1>;
#size-cells = <0>;
/* camera A input */
port@1 {
reg = <1>;
fimc0_ep: endpoint {
remote-endpoint = <&noon010pc30_ep>;
bus-width = <8>;
hsync-active = <1>;
vsync-active = <1>;
pclk-sample = <0>;
};
};
};
};
&fimd {
pinctrl-0 = <&lcd_clk &lcd_data24>;
pinctrl-names = "default";
status = "okay";
display-timings {
native-mode = <&timing0>;
timing0: timing {
/* 480x800@55Hz */
clock-frequency = <23439570>;
hactive = <480>;
hfront-porch = <16>;
hback-porch = <16>;
hsync-len = <2>;
vactive = <800>;
vback-porch = <2>;
vfront-porch = <28>;
vsync-len = <1>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
};
&onenand {
status = "okay";
};

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arch/arm/boot/dts/s5pv210-pinctrl.dtsi Normal file
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/*
* Samsung's S5PV210 SoC device tree source
*
* Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
*
* Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
* Tomasz Figa <t.figa@samsung.com>
*
* Samsung's S5PV210 SoC device nodes are listed in this file. S5PV210
* based board files can include this file and provide values for board specfic
* bindings.
*
* Note: This file does not include device nodes for all the controllers in
* S5PV210 SoC. As device tree coverage for S5PV210 increases, additional
* nodes can be added to this file.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
&pinctrl0 {
gpa0: gpa0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpa1: gpa1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpb: gpb {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpc0: gpc0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpc1: gpc1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpd0: gpd0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpd1: gpd1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpe0: gpe0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpe1: gpe1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpf0: gpf0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpf1: gpf1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpf2: gpf2 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpf3: gpf3 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpg0: gpg0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpg1: gpg1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpg2: gpg2 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpg3: gpg3 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpj0: gpj0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpj1: gpj1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpj2: gpj2 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpj3: gpj3 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpj4: gpj4 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpgi: gpgi {
gpio-controller;
#gpio-cells = <2>;
};
mp01: mp01 {
gpio-controller;
#gpio-cells = <2>;
};
mp02: mp02 {
gpio-controller;
#gpio-cells = <2>;
};
mp03: mp03 {
gpio-controller;
#gpio-cells = <2>;
};
mp04: mp04 {
gpio-controller;
#gpio-cells = <2>;
};
mp05: mp05 {
gpio-controller;
#gpio-cells = <2>;
};
mp06: mp06 {
gpio-controller;
#gpio-cells = <2>;
};
mp07: mp07 {
gpio-controller;
#gpio-cells = <2>;
};
gph0: gph0 {
gpio-controller;
interrupt-controller;
interrupt-parent = <&vic0>;
interrupts = <0>, <1>, <2>, <3>,
<4>, <5>, <6>, <7>;
#gpio-cells = <2>;
#interrupt-cells = <2>;
};
gph1: gph1 {
gpio-controller;
interrupt-controller;
interrupt-parent = <&vic0>;
interrupts = <8>, <9>, <10>, <11>,
<12>, <13>, <14>, <15>;
#gpio-cells = <2>;
#interrupt-cells = <2>;
};
gph2: gph2 {
gpio-controller;
#gpio-cells = <2>;
#interrupt-cells = <2>;
};
gph3: gph3 {
gpio-controller;
#gpio-cells = <2>;
#interrupt-cells = <2>;
};
uart0_data: uart0-data {
samsung,pins = "gpa0-0", "gpa0-1";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
uart0_fctl: uart0-fctl {
samsung,pins = "gpa0-2", "gpa0-3";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
uart1_data: uart1-data {
samsung,pins = "gpa0-4", "gpa0-5";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
uart1_fctl: uart1-fctl {
samsung,pins = "gpa0-6", "gpa0-7";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
uart2_data: uart2-data {
samsung,pins = "gpa1-0", "gpa1-1";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
uart2_fctl: uart2-fctl {
samsung,pins = "gpa1-2", "gpa1-3";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
uart3_data: uart3-data {
samsung,pins = "gpa1-2", "gpa1-3";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
uart_audio: uart-audio {
samsung,pins = "gpa1-2", "gpa1-3";
samsung,pin-function = <4>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
spi0_bus: spi0-bus {
samsung,pins = "gpb-0", "gpb-2", "gpb-3";
samsung,pin-function = <2>;
samsung,pin-pud = <2>;
samsung,pin-drv = <0>;
};
spi1_bus: spi1-bus {
samsung,pins = "gpb-4", "gpb-6", "gpb-7";
samsung,pin-function = <2>;
samsung,pin-pud = <2>;
samsung,pin-drv = <0>;
};
i2s0_bus: i2s0-bus {
samsung,pins = "gpi-0", "gpi-1", "gpi-2", "gpi-3",
"gpi-4", "gpi-5", "gpi-6";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
i2s1_bus: i2s1-bus {
samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
"gpc0-4";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
i2s2_bus: i2s2-bus {
samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
"gpc1-4";
samsung,pin-function = <4>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
pcm1_bus: pcm1-bus {
samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
"gpc0-4";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
ac97_bus: ac97-bus {
samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
"gpc0-4";
samsung,pin-function = <4>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
i2s2_bus: i2s2-bus {
samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
"gpc1-4";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
pcm2_bus: pcm2-bus {
samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
"gpc1-4";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
spdif_bus: spdif-bus {
samsung,pins = "gpc1-0", "gpc1-1";
samsung,pin-function = <4>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
spi2_bus: spi2-bus {
samsung,pins = "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4";
samsung,pin-function = <5>;
samsung,pin-pud = <2>;
samsung,pin-drv = <0>;
};
i2c0_bus: i2c0-bus {
samsung,pins = "gpd1-0", "gpd1-1";
samsung,pin-function = <2>;
samsung,pin-pud = <2>;
samsung,pin-drv = <0>;
};
i2c1_bus: i2c1-bus {
samsung,pins = "gpd1-2", "gpd1-3";
samsung,pin-function = <2>;
samsung,pin-pud = <2>;
samsung,pin-drv = <0>;
};
i2c2_bus: i2c2-bus {
samsung,pins = "gpd1-4", "gpd1-5";
samsung,pin-function = <2>;
samsung,pin-pud = <2>;
samsung,pin-drv = <0>;
};
pwm0_out: pwm0-out {
samsung,pins = "gpd0-0";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
pwm1_out: pwm1-out {
samsung,pins = "gpd0-1";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
pwm2_out: pwm2-out {
samsung,pins = "gpd0-2";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
pwm3_out: pwm3-out {
samsung,pins = "gpd0-3";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
keypad_row0: keypad-row-0 {
samsung,pins = "gph3-0";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
keypad_row1: keypad-row-1 {
samsung,pins = "gph3-1";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
keypad_row2: keypad-row-2 {
samsung,pins = "gph3-2";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
keypad_row3: keypad-row-3 {
samsung,pins = "gph3-3";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
keypad_row4: keypad-row-4 {
samsung,pins = "gph3-4";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
keypad_row5: keypad-row-5 {
samsung,pins = "gph3-5";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
keypad_row6: keypad-row-6 {
samsung,pins = "gph3-6";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
keypad_row7: keypad-row-7 {
samsung,pins = "gph3-7";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
keypad_col0: keypad-col-0 {
samsung,pins = "gph2-0";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
keypad_col1: keypad-col-1 {
samsung,pins = "gph2-1";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
keypad_col2: keypad-col-2 {
samsung,pins = "gph2-2";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
keypad_col3: keypad-col-3 {
samsung,pins = "gph2-3";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
keypad_col4: keypad-col-4 {
samsung,pins = "gph2-4";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
keypad_col5: keypad-col-5 {
samsung,pins = "gph2-5";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
keypad_col6: keypad-col-6 {
samsung,pins = "gph2-6";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
keypad_col7: keypad-col-7 {
samsung,pins = "gph2-7";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
sd0_clk: sd0-clk {
samsung,pins = "gpg0-0";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <3>;
};
sd0_cmd: sd0-cmd {
samsung,pins = "gpg0-1";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <3>;
};
sd0_cd: sd0-cd {
samsung,pins = "gpg0-2";
samsung,pin-function = <2>;
samsung,pin-pud = <2>;
samsung,pin-drv = <3>;
};
sd0_bus1: sd0-bus-width1 {
samsung,pins = "gpg0-3";
samsung,pin-function = <2>;
samsung,pin-pud = <2>;
samsung,pin-drv = <3>;
};
sd0_bus4: sd0-bus-width4 {
samsung,pins = "gpg0-3", "gpg0-4", "gpg0-5", "gpg0-6";
samsung,pin-function = <2>;
samsung,pin-pud = <2>;
samsung,pin-drv = <3>;
};
sd0_bus8: sd0-bus-width8 {
samsung,pins = "gpg1-3", "gpg1-4", "gpg1-5", "gpg1-6";
samsung,pin-function = <3>;
samsung,pin-pud = <2>;
samsung,pin-drv = <3>;
};
sd1_clk: sd1-clk {
samsung,pins = "gpg1-0";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <3>;
};
sd1_cmd: sd1-cmd {
samsung,pins = "gpg1-1";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <3>;
};
sd1_cd: sd1-cd {
samsung,pins = "gpg1-2";
samsung,pin-function = <2>;
samsung,pin-pud = <2>;
samsung,pin-drv = <3>;
};
sd1_bus1: sd1-bus-width1 {
samsung,pins = "gpg1-3";
samsung,pin-function = <2>;
samsung,pin-pud = <2>;
samsung,pin-drv = <3>;
};
sd1_bus4: sd1-bus-width4 {
samsung,pins = "gpg1-3", "gpg1-4", "gpg1-5", "gpg1-6";
samsung,pin-function = <2>;
samsung,pin-pud = <2>;
samsung,pin-drv = <3>;
};
sd2_clk: sd2-clk {
samsung,pins = "gpg2-0";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <3>;
};
sd2_cmd: sd2-cmd {
samsung,pins = "gpg2-1";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <3>;
};
sd2_cd: sd2-cd {
samsung,pins = "gpg2-2";
samsung,pin-function = <2>;
samsung,pin-pud = <2>;
samsung,pin-drv = <3>;
};
sd2_bus1: sd2-bus-width1 {
samsung,pins = "gpg2-3";
samsung,pin-function = <2>;
samsung,pin-pud = <2>;
samsung,pin-drv = <3>;
};
sd2_bus4: sd2-bus-width4 {
samsung,pins = "gpg2-3", "gpg2-4", "gpg2-5", "gpg2-6";
samsung,pin-function = <2>;
samsung,pin-pud = <2>;
samsung,pin-drv = <3>;
};
sd2_bus8: sd2-bus-width8 {
samsung,pins = "gpg3-3", "gpg3-4", "gpg3-5", "gpg3-6";
samsung,pin-function = <3>;
samsung,pin-pud = <2>;
samsung,pin-drv = <3>;
};
sd3_clk: sd3-clk {
samsung,pins = "gpg3-0";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <3>;
};
sd3_cmd: sd3-cmd {
samsung,pins = "gpg3-1";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <3>;
};
sd3_cd: sd3-cd {
samsung,pins = "gpg3-2";
samsung,pin-function = <2>;
samsung,pin-pud = <2>;
samsung,pin-drv = <3>;
};
sd3_bus1: sd3-bus-width1 {
samsung,pins = "gpg3-3";
samsung,pin-function = <2>;
samsung,pin-pud = <2>;
samsung,pin-drv = <3>;
};
sd3_bus4: sd3-bus-width4 {
samsung,pins = "gpg3-3", "gpg3-4", "gpg3-5", "gpg3-6";
samsung,pin-function = <2>;
samsung,pin-pud = <2>;
samsung,pin-drv = <3>;
};
eint0: ext-int0 {
samsung,pins = "gph0-0";
samsung,pin-function = <0xf>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
eint8: ext-int8 {
samsung,pins = "gph1-0";
samsung,pin-function = <0xf>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
eint15: ext-int15 {
samsung,pins = "gph1-7";
samsung,pin-function = <0xf>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
eint16: ext-int16 {
samsung,pins = "gph2-0";
samsung,pin-function = <0xf>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
eint31: ext-int31 {
samsung,pins = "gph3-7";
samsung,pin-function = <0xf>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
cam_port_a_io: cam-port-a-io {
samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3",
"gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7",
"gpe1-0", "gpe1-1", "gpe1-2", "gpe1-4";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
cam_port_a_clk_active: cam-port-a-clk-active {
samsung,pins = "gpe1-3";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <3>;
};
cam_port_a_clk_idle: cam-port-a-clk-idle {
samsung,pins = "gpe1-3";
samsung,pin-function = <0>;
samsung,pin-pud = <1>;
samsung,pin-drv = <0>;
};
cam_port_b_io: cam-port-b-io {
samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3",
"gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7",
"gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
cam_port_b_clk_active: cam-port-b-clk-active {
samsung,pins = "gpj1-3";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samsung,pin-drv = <3>;
};
cam_port_b_clk_idle: cam-port-b-clk-idle {
samsung,pins = "gpj1-3";
samsung,pin-function = <0>;
samsung,pin-pud = <1>;
samsung,pin-drv = <0>;
};
lcd_ctrl: lcd-ctrl {
samsung,pins = "gpd0-0", "gpd0-1";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
lcd_sync: lcd-sync {
samsung,pins = "gpf0-0", "gpf0-1";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
lcd_clk: lcd-clk {
samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
lcd_data24: lcd-data-width24 {
samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7",
"gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3",
"gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7",
"gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3",
"gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7",
"gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
};

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/*
* Samsung's S5PV210 SoC device tree source
*
* Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
*
* Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
* Tomasz Figa <t.figa@samsung.com>
*
* Board device tree source for YIC System SMDC110 board.
*
* NOTE: This file is completely based on original board file for mach-smdkc110
* available in Linux 3.15 and intends to provide equivalent level of hardware
* support. Due to lack of hardware, _no_ testing has been performed.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "s5pv210.dtsi"
/ {
model = "YIC System SMDKC110 based on S5PC110";
compatible = "yic,smdkc110", "samsung,s5pv210";
chosen {
bootargs = "console=ttySAC0,115200n8 root=/dev/mmcblk0p1 rw rootwait ignore_loglevel earlyprintk";
};
memory {
device_type = "memory";
reg = <0x20000000 0x20000000>;
};
};
&xusbxti {
clock-frequency = <24000000>;
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&uart2 {
status = "okay";
};
&uart3 {
status = "okay";
};
&rtc {
status = "okay";
};
&i2c0 {
status = "okay";
audio-codec@1b {
compatible = "wlf,wm8580";
reg = <0x1b>;
};
eeprom@50 {
compatible = "atmel,24c08";
reg = <0x50>;
};
};
&i2s0 {
status = "okay";
};

238
arch/arm/boot/dts/s5pv210-smdkv210.dts Normal file
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/*
* Samsung's S5PV210 SoC device tree source
*
* Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
*
* Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
* Tomasz Figa <t.figa@samsung.com>
*
* Board device tree source for YIC System SMDV210 board.
*
* NOTE: This file is completely based on original board file for mach-smdkv210
* available in Linux 3.15 and intends to provide equivalent level of hardware
* support. Due to lack of hardware, _no_ testing has been performed.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "s5pv210.dtsi"
/ {
model = "YIC System SMDKV210 based on S5PV210";
compatible = "yic,smdkv210", "samsung,s5pv210";
chosen {
bootargs = "console=ttySAC0,115200n8 root=/dev/mmcblk0p1 rw rootwait ignore_loglevel earlyprintk";
};
memory {
device_type = "memory";
reg = <0x20000000 0x40000000>;
};
ethernet@18000000 {
compatible = "davicom,dm9000";
reg = <0xA8000000 0x2 0xA8000002 0x2>;
interrupt-parent = <&gph1>;
interrupts = <1 4>;
local-mac-address = [00 00 de ad be ef];
davicom,no-eeprom;
};
backlight {
compatible = "pwm-backlight";
pwms = <&pwm 3 5000000 0>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
pinctrl-names = "default";
pinctrl-0 = <&pwm3_out>;
};
};
&xusbxti {
clock-frequency = <24000000>;
};
&keypad {
linux,input-no-autorepeat;
linux,input-wakeup;
samsung,keypad-num-rows = <8>;
samsung,keypad-num-columns = <8>;
pinctrl-names = "default";
pinctrl-0 = <&keypad_row0>, <&keypad_row1>, <&keypad_row2>,
<&keypad_row3>, <&keypad_row4>, <&keypad_row5>,
<&keypad_row6>, <&keypad_row7>,
<&keypad_col0>, <&keypad_col1>, <&keypad_col2>,
<&keypad_col3>, <&keypad_col4>, <&keypad_col5>,
<&keypad_col6>, <&keypad_col7>;
status = "okay";
key_1 {
keypad,row = <0>;
keypad,column = <3>;
linux,code = <KEY_1>;
};
key_2 {
keypad,row = <0>;
keypad,column = <4>;
linux,code = <KEY_2>;
};
key_3 {
keypad,row = <0>;
keypad,column = <5>;
linux,code = <KEY_3>;
};
key_4 {
keypad,row = <0>;
keypad,column = <6>;
linux,code = <KEY_4>;
};
key_5 {
keypad,row = <0
>;
keypad,column = <7>;
linux,code = <KEY_5>;
};
key_6 {
keypad,row = <1>;
keypad,column = <3>;
linux,code = <KEY_A>;
};
key_7 {
keypad,row = <1>;
keypad,column = <4>;
linux,code = <KEY_B>;
};
key_8 {
keypad,row = <1>;
keypad,column = <5>;
linux,code = <KEY_C>;
};
key_9 {
keypad,row = <1>;
keypad,column = <6>;
linux,code = <KEY_D>;
};
key_10 {
keypad,row = <1>;
keypad,column = <7>;
linux,code = <KEY_E>;
};
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&uart2 {
status = "okay";
};
&uart3 {
status = "okay";
};
&rtc {
status = "okay";
};
&sdhci0 {
bus-width = <4>;
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus1 &sd0_bus4>;
pinctrl-names = "default";
status = "okay";
};
&sdhci1 {
bus-width = <4>;
pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus1 &sd1_bus4>;
pinctrl-names = "default";
status = "okay";
};
&sdhci2 {
bus-width = <4>;
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
pinctrl-names = "default";
status = "okay";
};
&sdhci3 {
bus-width = <4>;
pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_cd &sd3_bus1 &sd3_bus4>;
pinctrl-names = "default";
status = "okay";
};
&hsotg {
status = "okay";
};
&usbphy {
status = "okay";
};
&fimd {
pinctrl-0 = <&lcd_clk &lcd_data24>;
pinctrl-names = "default";
status = "okay";
display-timings {
native-mode = <&timing0>;
timing0: timing@0 {
/* 800x480@60Hz */
clock-frequency = <24373920>;
hactive = <800>;
vactive = <480>;
hfront-porch = <8>;
hback-porch = <13>;
hsync-len = <3>;
vback-porch = <7>;
vfront-porch = <5>;
vsync-len = <1>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <1>;
};
};
};
&pwm {
samsung,pwm-outputs = <3>;
};
&i2c0 {
status = "okay";
audio-codec@1b {
compatible = "wlf,wm8580";
reg = <0x1b>;
};
eeprom@50 {
compatible = "atmel,24c08";
reg = <0x50>;
};
};
&i2s0 {
status = "okay";
};

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arch/arm/boot/dts/s5pv210-torbreck.dts Normal file
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/*
* Samsung's S5PV210 SoC device tree source
*
* Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
*
* Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
* Tomasz Figa <t.figa@samsung.com>
*
* Board device tree source for Torbreck board.
*
* NOTE: This file is completely based on original board file for mach-torbreck
* available in Linux 3.15 and intends to provide equivalent level of hardware
* support. Due to lack of hardware, _no_ testing has been performed.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "s5pv210.dtsi"
/ {
model = "aESOP Torbreck based on S5PV210";
compatible = "aesop,torbreck", "samsung,s5pv210";
chosen {
bootargs = "console=ttySAC0,115200n8 root=/dev/mmcblk0p1 rw rootwait ignore_loglevel earlyprintk";
};
memory {
device_type = "memory";
reg = <0x20000000 0x20000000>;
};
};
&xusbxti {
clock-frequency = <24000000>;
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&uart2 {
status = "okay";
};
&uart3 {
status = "okay";
};
&rtc {
status = "okay";
};
&sdhci0 {
bus-width = <4>;
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus1 &sd0_bus4>;
pinctrl-names = "default";
status = "okay";
};
&sdhci1 {
bus-width = <4>;
pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus1 &sd1_bus4>;
pinctrl-names = "default";
status = "okay";
};
&sdhci2 {
bus-width = <4>;
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus1 &sd2_bus4>;
pinctrl-names = "default";
status = "okay";
};
&sdhci3 {
bus-width = <4>;
pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_cd &sd3_bus1 &sd3_bus4>;
pinctrl-names = "default";
status = "okay";
};
&i2s0 {
status = "okay";
};

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/*
* Samsung's S5PV210 SoC device tree source
*
* Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
*
* Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
* Tomasz Figa <t.figa@samsung.com>
*
* Samsung's S5PV210 SoC device nodes are listed in this file. S5PV210
* based board files can include this file and provide values for board specfic
* bindings.
*
* Note: This file does not include device nodes for all the controllers in
* S5PV210 SoC. As device tree coverage for S5PV210 increases, additional
* nodes can be added to this file.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "skeleton.dtsi"
#include <dt-bindings/clock/s5pv210.h>
#include <dt-bindings/clock/s5pv210-audss.h>
/ {
aliases {
csis0 = &csis0;
fimc0 = &fimc0;
fimc1 = &fimc1;
fimc2 = &fimc2;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2s0 = &i2s0;
i2s1 = &i2s1;
i2s2 = &i2s2;
pinctrl0 = &pinctrl0;
spi0 = &spi0;
spi1 = &spi1;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a8";
reg = <0>;
};
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
external-clocks {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
xxti: oscillator@0 {
compatible = "fixed-clock";
reg = <0>;
clock-frequency = <0>;
clock-output-names = "xxti";
#clock-cells = <0>;
};
xusbxti: oscillator@1 {
compatible = "fixed-clock";
reg = <1>;
clock-frequency = <0>;
clock-output-names = "xusbxti";
#clock-cells = <0>;
};
};
onenand: onenand@b0000000 {
compatible = "samsung,s5pv210-onenand";
reg = <0xb0600000 0x2000>,
<0xb0000000 0x20000>,
<0xb0040000 0x20000>;
interrupt-parent = <&vic1>;
interrupts = <31>;
clocks = <&clocks CLK_NANDXL>, <&clocks DOUT_FLASH>;
clock-names = "bus", "onenand";
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
};
chipid@e0000000 {
compatible = "samsung,s5pv210-chipid";
reg = <0xe0000000 0x1000>;
};
clocks: clock-controller@e0100000 {
compatible = "samsung,s5pv210-clock", "simple-bus";
reg = <0xe0100000 0x10000>;
clock-names = "xxti", "xusbxti";
clocks = <&xxti>, <&xusbxti>;
#clock-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
pmu_syscon: syscon@e0108000 {
compatible = "samsung-s5pv210-pmu", "syscon";
reg = <0xe0108000 0x8000>;
};
};
pinctrl0: pinctrl@e0200000 {
compatible = "samsung,s5pv210-pinctrl";
reg = <0xe0200000 0x1000>;
interrupt-parent = <&vic0>;
interrupts = <30>;
wakeup-interrupt-controller {
compatible = "samsung,exynos4210-wakeup-eint";
interrupts = <16>;
interrupt-parent = <&vic0>;
};
};
amba {
#address-cells = <1>;
#size-cells = <1>;
compatible = "arm,amba-bus";
ranges;
pdma0: dma@e0900000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0xe0900000 0x1000>;
interrupt-parent = <&vic0>;
interrupts = <19>;
clocks = <&clocks CLK_PDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
};
pdma1: dma@e0a00000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0xe0a00000 0x1000>;
interrupt-parent = <&vic0>;
interrupts = <20>;
clocks = <&clocks CLK_PDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
};
};
spi0: spi@e1300000 {
compatible = "samsung,s5pv210-spi";
reg = <0xe1300000 0x1000>;
interrupt-parent = <&vic1>;
interrupts = <15>;
dmas = <&pdma0 7>, <&pdma0 6>;
dma-names = "tx", "rx";
clocks = <&clocks SCLK_SPI0>, <&clocks CLK_SPI0>;
clock-names = "spi", "spi_busclk0";
pinctrl-names = "default";
pinctrl-0 = <&spi0_bus>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi1: spi@e1400000 {
compatible = "samsung,s5pv210-spi";
reg = <0xe1400000 0x1000>;
interrupt-parent = <&vic1>;
interrupts = <16>;
dmas = <&pdma1 7>, <&pdma1 6>;
dma-names = "tx", "rx";
clocks = <&clocks SCLK_SPI1>, <&clocks CLK_SPI1>;
clock-names = "spi", "spi_busclk0";
pinctrl-names = "default";
pinctrl-0 = <&spi1_bus>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
keypad: keypad@e1600000 {
compatible = "samsung,s5pv210-keypad";
reg = <0xe1600000 0x1000>;
interrupt-parent = <&vic2>;
interrupts = <25>;
clocks = <&clocks CLK_KEYIF>;
clock-names = "keypad";
status = "disabled";
};
i2c0: i2c@e1800000 {
compatible = "samsung,s3c2440-i2c";
reg = <0xe1800000 0x1000>;
interrupt-parent = <&vic1>;
interrupts = <14>;
clocks = <&clocks CLK_I2C0>;
clock-names = "i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c0_bus>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@e1a00000 {
compatible = "samsung,s3c2440-i2c";
reg = <0xe1a00000 0x1000>;
interrupt-parent = <&vic1>;
interrupts = <19>;
clocks = <&clocks CLK_I2C2>;
clock-names = "i2c";
pinctrl-0 = <&i2c2_bus>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
audio-subsystem {
compatible = "samsung,s5pv210-audss", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
clk_audss: clock-controller@eee10000 {
compatible = "samsung,s5pv210-audss-clock";
reg = <0xeee10000 0x1000>;
clock-names = "hclk", "xxti",
"fout_epll",
"sclk_audio0";
clocks = <&clocks DOUT_HCLKP>, <&xxti>,
<&clocks FOUT_EPLL>,
<&clocks SCLK_AUDIO0>;
#clock-cells = <1>;
};
i2s0: i2s@eee30000 {
compatible = "samsung,s5pv210-i2s";
reg = <0xeee30000 0x1000>;
interrupt-parent = <&vic2>;
interrupts = <16>;
dma-names = "rx", "tx", "tx-sec";
dmas = <&pdma1 9>, <&pdma1 10>, <&pdma1 11>;
clock-names = "iis",
"i2s_opclk0",
"i2s_opclk1";
clocks = <&clk_audss CLK_I2S>,
<&clk_audss CLK_I2S>,
<&clk_audss CLK_DOUT_AUD_BUS>;
samsung,idma-addr = <0xc0010000>;
pinctrl-names = "default";
pinctrl-0 = <&i2s0_bus>;
#sound-dai-cells = <0>;
status = "disabled";
};
};
i2s1: i2s@e2100000 {
compatible = "samsung,s3c6410-i2s";
reg = <0xe2100000 0x1000>;
interrupt-parent = <&vic2>;
interrupts = <17>;
dma-names = "rx", "tx";
dmas = <&pdma1 12>, <&pdma1 13>;
clock-names = "iis", "i2s_opclk0";
clocks = <&clocks CLK_I2S1>, <&clocks SCLK_AUDIO1>;
pinctrl-names = "default";
pinctrl-0 = <&i2s1_bus>;
#sound-dai-cells = <0>;
status = "disabled";
};
i2s2: i2s@e2a00000 {
compatible = "samsung,s3c6410-i2s";
reg = <0xe2a00000 0x1000>;
interrupt-parent = <&vic2>;
interrupts = <18>;
dma-names = "rx", "tx";
dmas = <&pdma1 14>, <&pdma1 15>;
clock-names = "iis", "i2s_opclk0";
clocks = <&clocks CLK_I2S2>, <&clocks SCLK_AUDIO2>;
pinctrl-names = "default";
pinctrl-0 = <&i2s2_bus>;
#sound-dai-cells = <0>;
status = "disabled";
};
pwm: pwm@e2500000 {
compatible = "samsung,s5pc100-pwm";
reg = <0xe2500000 0x1000>;
interrupt-parent = <&vic0>;
interrupts = <21>, <22>, <23>, <24>, <25>;
clock-names = "timers";
clocks = <&clocks CLK_PWM>;
#pwm-cells = <3>;
};
watchdog: watchdog@e2700000 {
compatible = "samsung,s3c2410-wdt";
reg = <0xe2700000 0x1000>;
interrupt-parent = <&vic0>;
interrupts = <26>;
clock-names = "watchdog";
clocks = <&clocks CLK_WDT>;
};
rtc: rtc@e2800000 {
compatible = "samsung,s3c6410-rtc";
reg = <0xe2800000 0x100>;
interrupt-parent = <&vic0>;
interrupts = <28>, <29>;
clocks = <&clocks CLK_RTC>;
clock-names = "rtc";
status = "disabled";
};
uart0: serial@e2900000 {
compatible = "samsung,s5pv210-uart";
reg = <0xe2900000 0x400>;
interrupt-parent = <&vic1>;
interrupts = <10>;
clock-names = "uart", "clk_uart_baud0",
"clk_uart_baud1";
clocks = <&clocks CLK_UART0>, <&clocks CLK_UART0>,
<&clocks SCLK_UART0>;
status = "disabled";
};
uart1: serial@e2900400 {
compatible = "samsung,s5pv210-uart";
reg = <0xe2900400 0x400>;
interrupt-parent = <&vic1>;
interrupts = <11>;
clock-names = "uart", "clk_uart_baud0",
"clk_uart_baud1";
clocks = <&clocks CLK_UART1>, <&clocks CLK_UART1>,
<&clocks SCLK_UART1>;
status = "disabled";
};
uart2: serial@e2900800 {
compatible = "samsung,s5pv210-uart";
reg = <0xe2900800 0x400>;
interrupt-parent = <&vic1>;
interrupts = <12>;
clock-names = "uart", "clk_uart_baud0",
"clk_uart_baud1";
clocks = <&clocks CLK_UART2>, <&clocks CLK_UART2>,
<&clocks SCLK_UART2>;
status = "disabled";
};
uart3: serial@e2900c00 {
compatible = "samsung,s5pv210-uart";
reg = <0xe2900c00 0x400>;
interrupt-parent = <&vic1>;
interrupts = <13>;
clock-names = "uart", "clk_uart_baud0",
"clk_uart_baud1";
clocks = <&clocks CLK_UART3>, <&clocks CLK_UART3>,
<&clocks SCLK_UART3>;
status = "disabled";
};
sdhci0: sdhci@eb000000 {
compatible = "samsung,s3c6410-sdhci";
reg = <0xeb000000 0x100000>;
interrupt-parent = <&vic1>;
interrupts = <26>;
clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2";
clocks = <&clocks CLK_HSMMC0>, <&clocks CLK_HSMMC0>,
<&clocks SCLK_MMC0>;
status = "disabled";
};
sdhci1: sdhci@eb100000 {
compatible = "samsung,s3c6410-sdhci";
reg = <0xeb100000 0x100000>;
interrupt-parent = <&vic1>;
interrupts = <27>;
clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2";
clocks = <&clocks CLK_HSMMC1>, <&clocks CLK_HSMMC1>,
<&clocks SCLK_MMC1>;
status = "disabled";
};
sdhci2: sdhci@eb200000 {
compatible = "samsung,s3c6410-sdhci";
reg = <0xeb200000 0x100000>;
interrupt-parent = <&vic1>;
interrupts = <28>;
clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2";
clocks = <&clocks CLK_HSMMC2>, <&clocks CLK_HSMMC2>,
<&clocks SCLK_MMC2>;
status = "disabled";
};
sdhci3: sdhci@eb300000 {
compatible = "samsung,s3c6410-sdhci";
reg = <0xeb300000 0x100000>;
interrupt-parent = <&vic3>;
interrupts = <2>;
clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.3";
clocks = <&clocks CLK_HSMMC3>, <&clocks CLK_HSMMC3>,
<&clocks SCLK_MMC3>;
status = "disabled";
};
hsotg: hsotg@ec000000 {
compatible = "samsung,s3c6400-hsotg";
reg = <0xec000000 0x20000>;
interrupt-parent = <&vic1>;
interrupts = <24>;
clocks = <&clocks CLK_USB_OTG>;
clock-names = "otg";
phy-names = "usb2-phy";
phys = <&usbphy 0>;
status = "disabled";
};
usbphy: usbphy@ec100000 {
compatible = "samsung,s5pv210-usb2-phy";
reg = <0xec100000 0x100>;
samsung,pmureg-phandle = <&pmu_syscon>;
clocks = <&clocks CLK_USB_OTG>, <&xusbxti>;
clock-names = "phy", "ref";
#phy-cells = <1>;
status = "disabled";
};
ehci: ehci@ec200000 {
compatible = "samsung,exynos4210-ehci";
reg = <0xec200000 0x100>;
interrupts = <23>;
interrupt-parent = <&vic1>;
clocks = <&clocks CLK_USB_HOST>;
clock-names = "usbhost";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
port@0 {
reg = <0>;
phys = <&usbphy 1>;
};
};
ohci: ohci@ec300000 {
compatible = "samsung,exynos4210-ohci";
reg = <0xec300000 0x100>;
interrupts = <23>;
clocks = <&clocks CLK_USB_HOST>;
clock-names = "usbhost";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
port@0 {
reg = <0>;
phys = <&usbphy 1>;
};
};
mfc: codec@f1700000 {
compatible = "samsung,mfc-v5";
reg = <0xf1700000 0x10000>;
interrupt-parent = <&vic2>;
interrupts = <14>;
clocks = <&clocks DOUT_MFC>, <&clocks CLK_MFC>;
clock-names = "sclk_mfc", "mfc";
};
vic0: interrupt-controller@f2000000 {
compatible = "arm,pl192-vic";
interrupt-controller;
reg = <0xf2000000 0x1000>;
#interrupt-cells = <1>;
};
vic1: interrupt-controller@f2100000 {
compatible = "arm,pl192-vic";
interrupt-controller;
reg = <0xf2100000 0x1000>;
#interrupt-cells = <1>;
};
vic2: interrupt-controller@f2200000 {
compatible = "arm,pl192-vic";
interrupt-controller;
reg = <0xf2200000 0x1000>;
#interrupt-cells = <1>;
};
vic3: interrupt-controller@f2300000 {
compatible = "arm,pl192-vic";
interrupt-controller;
reg = <0xf2300000 0x1000>;
#interrupt-cells = <1>;
};
fimd: fimd@f8000000 {
compatible = "samsung,exynos4210-fimd";
interrupt-parent = <&vic2>;
reg = <0xf8000000 0x20000>;
interrupt-names = "fifo", "vsync", "lcd_sys";
interrupts = <0>, <1>, <2>;
clocks = <&clocks SCLK_FIMD>, <&clocks CLK_FIMD>;
clock-names = "sclk_fimd", "fimd";
status = "disabled";
};
g2d: g2d@fa000000 {
compatible = "samsung,s5pv210-g2d";
reg = <0xfa000000 0x1000>;
interrupt-parent = <&vic2>;
interrupts = <9>;
clocks = <&clocks DOUT_G2D>, <&clocks CLK_G2D>;
clock-names = "sclk_fimg2d", "fimg2d";
};
mdma1: mdma@fa200000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0xfa200000 0x1000>;
interrupt-parent = <&vic0>;
interrupts = <18>;
clocks = <&clocks CLK_MDMA>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <1>;
};
i2c1: i2c@fab00000 {
compatible = "samsung,s3c2440-i2c";
reg = <0xfab00000 0x1000>;
interrupt-parent = <&vic2>;
interrupts = <13>;
clocks = <&clocks CLK_I2C1>;
clock-names = "i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c1_bus>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
camera: camera {
compatible = "samsung,fimc", "simple-bus";
pinctrl-names = "default";
pinctrl-0 = <>;
clocks = <&clocks SCLK_CAM0>, <&clocks SCLK_CAM1>;
clock-names = "sclk_cam0", "sclk_cam1";
#address-cells = <1>;
#size-cells = <1>;
ranges;
clock_cam: clock-controller {
#clock-cells = <1>;
};
csis0: csis@fa600000 {
compatible = "samsung,s5pv210-csis";
reg = <0xfa600000 0x4000>;
interrupt-parent = <&vic2>;
interrupts = <29>;
clocks = <&clocks CLK_CSIS>,
<&clocks SCLK_CSIS>;
clock-names = "clk_csis",
"sclk_csis";
bus-width = <4>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
fimc0: fimc@fb200000 {
compatible = "samsung,s5pv210-fimc";
reg = <0xfb200000 0x1000>;
interrupts = <5>;
interrupt-parent = <&vic2>;
clocks = <&clocks CLK_FIMC0>,
<&clocks SCLK_FIMC0>;
clock-names = "fimc",
"sclk_fimc";
samsung,pix-limits = <4224 8192 1920 4224>;
samsung,mainscaler-ext;
samsung,cam-if;
};
fimc1: fimc@fb300000 {
compatible = "samsung,s5pv210-fimc";
reg = <0xfb300000 0x1000>;
interrupt-parent = <&vic2>;
interrupts = <6>;
clocks = <&clocks CLK_FIMC1>,
<&clocks SCLK_FIMC1>;
clock-names = "fimc",
"sclk_fimc";
samsung,pix-limits = <4224 8192 1920 4224>;
samsung,mainscaler-ext;
samsung,cam-if;
};
fimc2: fimc@fb400000 {
compatible = "samsung,s5pv210-fimc";
reg = <0xfb400000 0x1000>;
interrupt-parent = <&vic2>;
interrupts = <7>;
clocks = <&clocks CLK_FIMC2>,
<&clocks SCLK_FIMC2>;
clock-names = "fimc",
"sclk_fimc";
samsung,pix-limits = <4224 8192 1920 4224>;
samsung,mainscaler-ext;
samsung,lcd-wb;
};
};
};
};
#include "s5pv210-pinctrl.dtsi"

81
arch/arm/boot/dts/versatile-ab.dts
View File

@ -19,6 +19,41 @@
reg = <0x0 0x08000000>;
};
xtal24mhz: xtal24mhz@24M {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
};
core-module@10000000 {
compatible = "arm,core-module-versatile", "syscon";
reg = <0x10000000 0x200>;
/* OSC1 on AB, OSC4 on PB */
osc1: cm_aux_osc@24M {
#clock-cells = <0>;
compatible = "arm,versatile-cm-auxosc";
clocks = <&xtal24mhz>;
};
/* The timer clock is the 24 MHz oscillator divided to 1MHz */
timclk: timclk@1M {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <24>;
clock-mult = <1>;
clocks = <&xtal24mhz>;
};
pclk: pclk@24M {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <1>;
clock-mult = <1>;
clocks = <&xtal24mhz>;
};
};
flash@34000000 {
compatible = "arm,versatile-flash";
reg = <0x34000000 0x4000000>;
@ -59,6 +94,8 @@
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x10140000 0x1000>;
clear-mask = <0xffffffff>;
valid-mask = <0xffffffff>;
};
sic: intc@10003000 {
@ -68,69 +105,93 @@
reg = <0x10003000 0x1000>;
interrupt-parent = <&vic>;
interrupts = <31>; /* Cascaded to vic */
clear-mask = <0xffffffff>;
valid-mask = <0xffc203f8>;
};
dma@10130000 {
compatible = "arm,pl081", "arm,primecell";
reg = <0x10130000 0x1000>;
interrupts = <17>;
clocks = <&pclk>;
clock-names = "apb_pclk";
};
uart0: uart@101f1000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x101f1000 0x1000>;
interrupts = <12>;
clocks = <&xtal24mhz>, <&pclk>;
clock-names = "uartclk", "apb_pclk";
};
uart1: uart@101f2000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x101f2000 0x1000>;
interrupts = <13>;
clocks = <&xtal24mhz>, <&pclk>;
clock-names = "uartclk", "apb_pclk";
};
uart2: uart@101f3000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x101f3000 0x1000>;
interrupts = <14>;
clocks = <&xtal24mhz>, <&pclk>;
clock-names = "uartclk", "apb_pclk";
};
smc@10100000 {
compatible = "arm,primecell";
reg = <0x10100000 0x1000>;
clocks = <&pclk>;
clock-names = "apb_pclk";
};
mpmc@10110000 {
compatible = "arm,primecell";
reg = <0x10110000 0x1000>;
clocks = <&pclk>;
clock-names = "apb_pclk";
};
display@10120000 {
compatible = "arm,pl110", "arm,primecell";
reg = <0x10120000 0x1000>;
interrupts = <16>;
clocks = <&osc1>, <&pclk>;
clock-names = "clcd", "apb_pclk";
};
sctl@101e0000 {
compatible = "arm,primecell";
reg = <0x101e0000 0x1000>;
clocks = <&pclk>;
clock-names = "apb_pclk";
};
watchdog@101e1000 {
compatible = "arm,primecell";
reg = <0x101e1000 0x1000>;
interrupts = <0>;
clocks = <&pclk>;
clock-names = "apb_pclk";
};
timer@101e2000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x101e2000 0x1000>;
interrupts = <4>;
clocks = <&timclk>, <&timclk>, <&pclk>;
clock-names = "timer0", "timer1", "apb_pclk";
};
timer@101e3000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x101e3000 0x1000>;
interrupts = <5>;
clocks = <&timclk>, <&timclk>, <&pclk>;
clock-names = "timer0", "timer1", "apb_pclk";
};
gpio0: gpio@101e4000 {
@ -141,6 +202,8 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pclk>;
clock-names = "apb_pclk";
};
gpio1: gpio@101e5000 {
@ -151,24 +214,32 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pclk>;
clock-names = "apb_pclk";
};
rtc@101e8000 {
compatible = "arm,pl030", "arm,primecell";
reg = <0x101e8000 0x1000>;
interrupts = <10>;
clocks = <&pclk>;
clock-names = "apb_pclk";
};
sci@101f0000 {
compatible = "arm,primecell";
reg = <0x101f0000 0x1000>;
interrupts = <15>;
clocks = <&pclk>;
clock-names = "apb_pclk";
};
ssp@101f4000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x101f4000 0x1000>;
interrupts = <11>;
clocks = <&xtal24mhz>, <&pclk>;
clock-names = "SSPCLK", "apb_pclk";
};
fpga {
@ -181,23 +252,31 @@
compatible = "arm,primecell";
reg = <0x4000 0x1000>;
interrupts = <24>;
clocks = <&pclk>;
clock-names = "apb_pclk";
};
mmc@5000 {
compatible = "arm,primecell";
compatible = "arm,pl180", "arm,primecell";
reg = < 0x5000 0x1000>;
interrupts-extended = <&vic 22 &sic 2>;
clocks = <&xtal24mhz>, <&pclk>;
clock-names = "mclk", "apb_pclk";
};
kmi@6000 {
compatible = "arm,pl050", "arm,primecell";
reg = <0x6000 0x1000>;
interrupt-parent = <&sic>;
interrupts = <3>;
clocks = <&xtal24mhz>, <&pclk>;
clock-names = "KMIREFCLK", "apb_pclk";
};
kmi@7000 {
compatible = "arm,pl050", "arm,primecell";
reg = <0x7000 0x1000>;
interrupt-parent = <&sic>;
interrupts = <4>;
clocks = <&xtal24mhz>, <&pclk>;
clock-names = "KMIREFCLK", "apb_pclk";
};
};
};

12
arch/arm/boot/dts/versatile-pb.dts
View File

@ -13,6 +13,8 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pclk>;
clock-names = "apb_pclk";
};
gpio3: gpio@101e7000 {
@ -23,6 +25,8 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pclk>;
clock-names = "apb_pclk";
};
fpga {
@ -31,17 +35,23 @@
reg = <0x9000 0x1000>;
interrupt-parent = <&sic>;
interrupts = <6>;
clocks = <&xtal24mhz>, <&pclk>;
clock-names = "uartclk", "apb_pclk";
};
sci@a000 {
compatible = "arm,primecell";
reg = <0xa000 0x1000>;
interrupt-parent = <&sic>;
interrupts = <5>;
clocks = <&xtal24mhz>;
clock-names = "apb_pclk";
};
mmc@b000 {
compatible = "arm,primecell";
compatible = "arm,pl180", "arm,primecell";
reg = <0xb000 0x1000>;
interrupts-extended = <&vic 23 &sic 2>;
clocks = <&xtal24mhz>, <&pclk>;
clock-names = "mclk", "apb_pclk";
};
};
};

4
arch/arm/common/timer-sp.c
View File

@ -233,13 +233,13 @@ static void __init sp804_of_init(struct device_node *np)
if (IS_ERR(clk1))
clk1 = NULL;
/* Get the 2nd clock if the timer has 2 timer clocks */
/* Get the 2nd clock if the timer has 3 timer clocks */
if (of_count_phandle_with_args(np, "clocks", "#clock-cells") == 3) {
clk2 = of_clk_get(np, 1);
if (IS_ERR(clk2)) {
pr_err("sp804: %s clock not found: %d\n", np->name,
(int)PTR_ERR(clk2));
goto err;
clk2 = NULL;
}
} else
clk2 = clk1;

1
arch/arm/configs/bcm_defconfig
View File

@ -27,6 +27,7 @@ CONFIG_PARTITION_ADVANCED=y
CONFIG_ARCH_BCM=y
CONFIG_ARCH_BCM_MOBILE=y
CONFIG_ARM_THUMBEE=y
CONFIG_SMP=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
# CONFIG_COMPACTION is not set

5
arch/arm/configs/imx_v4_v5_defconfig
View File

@ -1,6 +1,7 @@
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_FHANDLE=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_LOG_BUF_SHIFT=14
@ -35,10 +36,8 @@ CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2=y
CONFIG_MACH_EUKREA_CPUIMX27_USEUART4=y
CONFIG_MACH_MX27_3DS=y
CONFIG_MACH_IMX27_VISSTRIM_M10=y
CONFIG_MACH_IMX27LITE=y
CONFIG_MACH_PCA100=y
CONFIG_MACH_MXT_TD60=y
CONFIG_MACH_IMX27IPCAM=y
CONFIG_MACH_IMX27_DT=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
@ -159,6 +158,8 @@ CONFIG_USB_CHIPIDEA=y
CONFIG_USB_CHIPIDEA_UDC=y
CONFIG_USB_CHIPIDEA_HOST=y
CONFIG_NOP_USB_XCEIV=y
CONFIG_USB_GADGET=y
CONFIG_USB_ETH=m
CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y

9
arch/arm/configs/imx_v6_v7_defconfig
View File

@ -1,5 +1,6 @@
CONFIG_KERNEL_LZO=y
CONFIG_SYSVIPC=y
CONFIG_FHANDLE=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_LOG_BUF_SHIFT=18
@ -31,11 +32,12 @@ CONFIG_MACH_IMX35_DT=y
CONFIG_MACH_PCM043=y
CONFIG_MACH_MX35_3DS=y
CONFIG_MACH_VPR200=y
CONFIG_MACH_IMX51_DT=y
CONFIG_SOC_IMX51=y
CONFIG_SOC_IMX50=y
CONFIG_SOC_IMX53=y
CONFIG_SOC_IMX6Q=y
CONFIG_SOC_IMX6SL=y
CONFIG_SOC_IMX6SX=y
CONFIG_SOC_VF610=y
CONFIG_PCI=y
CONFIG_PCI_IMX6=y
@ -67,6 +69,8 @@ CONFIG_IP_PNP_DHCP=y
# CONFIG_INET_LRO is not set
CONFIG_IPV6=y
CONFIG_NETFILTER=y
CONFIG_CAN=y
CONFIG_CAN_FLEXCAN=y
CONFIG_CFG80211=y
CONFIG_MAC80211=y
CONFIG_RFKILL=y
@ -160,6 +164,7 @@ CONFIG_SPI=y
CONFIG_SPI_IMX=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_MC9S08DZ60=y
CONFIG_GPIO_STMPE=y
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
CONFIG_IMX2_WDT=y
@ -242,6 +247,7 @@ CONFIG_RTC_DRV_SNVS=y
CONFIG_DMADEVICES=y
CONFIG_IMX_SDMA=y
CONFIG_MXS_DMA=y
CONFIG_FSL_EDMA=y
CONFIG_STAGING=y
CONFIG_DRM_IMX=y
CONFIG_DRM_IMX_FB_HELPER=y
@ -288,6 +294,7 @@ CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_ISO8859_15=m
CONFIG_NLS_UTF8=y
CONFIG_PRINTK_TIME=y
CONFIG_DEBUG_FS=y
CONFIG_MAGIC_SYSRQ=y
# CONFIG_SCHED_DEBUG is not set

3
arch/arm/configs/multi_v7_defconfig
View File

@ -19,6 +19,7 @@ CONFIG_MACH_DOVE=y
CONFIG_ARCH_BCM=y
CONFIG_ARCH_BCM_MOBILE=y
CONFIG_ARCH_BCM_5301X=y
CONFIG_ARCH_BRCMSTB=y
CONFIG_ARCH_BERLIN=y
CONFIG_MACH_BERLIN_BG2=y
CONFIG_MACH_BERLIN_BG2CD=y
@ -27,7 +28,7 @@ CONFIG_ARCH_HIGHBANK=y
CONFIG_ARCH_HI3xxx=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_ARCH_MXC=y
CONFIG_MACH_IMX51_DT=y
CONFIG_SOC_IMX51=y
CONFIG_SOC_IMX53=y
CONFIG_SOC_IMX6Q=y
CONFIG_SOC_IMX6SL=y

1
arch/arm/configs/mxs_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_SYSVIPC=y
CONFIG_FHANDLE=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_TASKSTATS=y

23
arch/arm/mach-s5pv210/include/mach/debug-macro.S → arch/arm/include/debug/s5pv210.S
View File

@ -1,9 +1,6 @@
/* linux/arch/arm/mach-s5pv210/include/mach/debug-macro.S
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* Based on arch/arm/mach-s3c6400/include/mach/debug-macro.S
/*
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@ -12,8 +9,9 @@
/* pull in the relevant register and map files. */
#include <linux/serial_s3c.h>
#include <mach/map.h>
#define S3C_ADDR_BASE 0xF6000000
#define S3C_VA_UART S3C_ADDR_BASE + 0x01000000
#define S5PV210_PA_UART 0xe2900000
/* note, for the boot process to work we have to keep the UART
* virtual address aligned to an 1MiB boundary for the L1
@ -22,8 +20,8 @@
*/
.macro addruart, rp, rv, tmp
ldr \rp, = S3C_PA_UART
ldr \rv, = S3C_VA_UART
ldr \rp, =S5PV210_PA_UART
ldr \rv, =S3C_VA_UART
#if CONFIG_DEBUG_S3C_UART != 0
add \rp, \rp, #(0x400 * CONFIG_DEBUG_S3C_UART)
add \rv, \rv, #(0x400 * CONFIG_DEBUG_S3C_UART)
@ -33,9 +31,4 @@
#define fifo_full fifo_full_s5pv210
#define fifo_level fifo_level_s5pv210
/* include the reset of the code which will do the work, we're only
* compiling for a single cpu processor type so the default of s3c2440
* will be fine with us.
*/
#include <debug/samsung.S>

26
arch/arm/lib/delay.c
View File

@ -19,6 +19,7 @@
* Author: Will Deacon <will.deacon@arm.com>
*/
#include <linux/clocksource.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/kernel.h>
@ -36,6 +37,7 @@ struct arm_delay_ops arm_delay_ops = {
static const struct delay_timer *delay_timer;
static bool delay_calibrated;
static u64 delay_res;
int read_current_timer(unsigned long *timer_val)
{
@ -47,6 +49,11 @@ int read_current_timer(unsigned long *timer_val)
}
EXPORT_SYMBOL_GPL(read_current_timer);
static inline u64 cyc_to_ns(u64 cyc, u32 mult, u32 shift)
{
return (cyc * mult) >> shift;
}
static void __timer_delay(unsigned long cycles)
{
cycles_t start = get_cycles();
@ -69,18 +76,24 @@ static void __timer_udelay(unsigned long usecs)
void __init register_current_timer_delay(const struct delay_timer *timer)
{
if (!delay_calibrated) {
pr_info("Switching to timer-based delay loop\n");
u32 new_mult, new_shift;
u64 res;
clocks_calc_mult_shift(&new_mult, &new_shift, timer->freq,
NSEC_PER_SEC, 3600);
res = cyc_to_ns(1ULL, new_mult, new_shift);
if (!delay_calibrated && (!delay_res || (res < delay_res))) {
pr_info("Switching to timer-based delay loop, resolution %lluns\n", res);
delay_timer = timer;
lpj_fine = timer->freq / HZ;
delay_res = res;
/* cpufreq may scale loops_per_jiffy, so keep a private copy */
arm_delay_ops.ticks_per_jiffy = lpj_fine;
arm_delay_ops.delay = __timer_delay;
arm_delay_ops.const_udelay = __timer_const_udelay;
arm_delay_ops.udelay = __timer_udelay;
delay_calibrated = true;
} else {
pr_info("Ignoring duplicate/late registration of read_current_timer delay\n");
}
@ -91,3 +104,8 @@ unsigned long calibrate_delay_is_known(void)
delay_calibrated = true;
return lpj_fine;
}
void calibration_delay_done(void)
{
delay_calibrated = true;
}

34
arch/arm/mach-bcm/Kconfig
View File

@ -9,7 +9,6 @@ config ARCH_BCM_MOBILE
bool "Broadcom Mobile SoC Support" if ARCH_MULTI_V7
select ARCH_REQUIRE_GPIOLIB
select ARM_ERRATA_754322
select ARM_ERRATA_764369 if SMP
select ARM_ERRATA_775420
select ARM_GIC
select GPIO_BCM_KONA
@ -26,16 +25,18 @@ menu "Broadcom Mobile SoC Selection"
config ARCH_BCM_281XX
bool "Broadcom BCM281XX SoC family"
default y
select HAVE_SMP
help
Enable support for the the BCM281XX family, which includes
Enable support for the BCM281XX family, which includes
BCM11130, BCM11140, BCM11351, BCM28145 and BCM28155
variants.
config ARCH_BCM_21664
bool "Broadcom BCM21664 SoC family"
default y
select HAVE_SMP
help
Enable support for the the BCM21664 family, which includes
Enable support for the BCM21664 family, which includes
BCM21663 and BCM21664 variants.
config ARCH_BCM_MOBILE_L2_CACHE
@ -49,6 +50,17 @@ config ARCH_BCM_MOBILE_SMC
bool
depends on ARCH_BCM_281XX || ARCH_BCM_21664
config ARCH_BCM_MOBILE_SMP
bool "Broadcom mobile SoC SMP support"
depends on (ARCH_BCM_281XX || ARCH_BCM_21664) && SMP
default y
select HAVE_ARM_SCU
select ARM_ERRATA_764369
help
SMP support for the BCM281XX and BCM21664 SoC families.
Provided as an option so SMP support for SoCs of this type
can be disabled for an SMP-enabled kernel.
endmenu
endif
@ -87,4 +99,20 @@ config ARCH_BCM_5301X
different SoC or with the older BCM47XX and BCM53XX based
network SoC using a MIPS CPU, they are supported by arch/mips/bcm47xx
config ARCH_BRCMSTB
bool "Broadcom BCM7XXX based boards" if ARCH_MULTI_V7
depends on MMU
select ARM_GIC
select MIGHT_HAVE_PCI
select HAVE_SMP
select HAVE_ARM_ARCH_TIMER
select BRCMSTB_GISB_ARB
select BRCMSTB_L2_IRQ
help
Say Y if you intend to run the kernel on a Broadcom ARM-based STB
chipset.
This enables support for Broadcom ARM-based set-top box chipsets,
including the 7445 family of chips.
endif

8
arch/arm/mach-bcm/Makefile
View File

@ -16,6 +16,9 @@ obj-$(CONFIG_ARCH_BCM_281XX) += board_bcm281xx.o
# BCM21664
obj-$(CONFIG_ARCH_BCM_21664) += board_bcm21664.o
# BCM281XX and BCM21664 SMP support
obj-$(CONFIG_ARCH_BCM_MOBILE_SMP) += kona_smp.o
# BCM281XX and BCM21664 L2 cache control
obj-$(CONFIG_ARCH_BCM_MOBILE_L2_CACHE) += kona_l2_cache.o
@ -30,3 +33,8 @@ obj-$(CONFIG_ARCH_BCM2835) += board_bcm2835.o
# BCM5301X
obj-$(CONFIG_ARCH_BCM_5301X) += bcm_5301x.o
ifeq ($(CONFIG_ARCH_BRCMSTB),y)
obj-y += brcmstb.o
obj-$(CONFIG_SMP) += headsmp-brcmstb.o platsmp-brcmstb.o
endif

28
arch/arm/mach-bcm/brcmstb.c Normal file
View File

@ -0,0 +1,28 @@
/*
* Copyright (C) 2013-2014 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/init.h>
#include <linux/of_platform.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
static const char *brcmstb_match[] __initconst = {
"brcm,bcm7445",
"brcm,brcmstb",
NULL
};
DT_MACHINE_START(BRCMSTB, "Broadcom STB (Flattened Device Tree)")
.dt_compat = brcmstb_match,
MACHINE_END

19
arch/arm/mach-bcm/brcmstb.h Normal file
View File

@ -0,0 +1,19 @@
/*
* Copyright (C) 2013-2014 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __BRCMSTB_H__
#define __BRCMSTB_H__
void brcmstb_secondary_startup(void);
#endif /* __BRCMSTB_H__ */

33
arch/arm/mach-bcm/headsmp-brcmstb.S Normal file
View File

@ -0,0 +1,33 @@
/*
* SMP boot code for secondary CPUs
* Based on arch/arm/mach-tegra/headsmp.S
*
* Copyright (C) 2010 NVIDIA, Inc.
* Copyright (C) 2013-2014 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <asm/assembler.h>
#include <linux/linkage.h>
#include <linux/init.h>
.section ".text.head", "ax"
ENTRY(brcmstb_secondary_startup)
/*
* Ensure CPU is in a sane state by disabling all IRQs and switching
* into SVC mode.
*/
setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r0
bl v7_invalidate_l1
b secondary_startup
ENDPROC(brcmstb_secondary_startup)

202
arch/arm/mach-bcm/kona_smp.c Normal file
View File

@ -0,0 +1,202 @@
/*
* Copyright (C) 2014 Broadcom Corporation
* Copyright 2014 Linaro Limited
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/sched.h>
#include <asm/smp.h>
#include <asm/smp_plat.h>
#include <asm/smp_scu.h>
/* Size of mapped Cortex A9 SCU address space */
#define CORTEX_A9_SCU_SIZE 0x58
#define SECONDARY_TIMEOUT_NS NSEC_PER_MSEC /* 1 msec (in nanoseconds) */
#define BOOT_ADDR_CPUID_MASK 0x3
/* Name of device node property defining secondary boot register location */
#define OF_SECONDARY_BOOT "secondary-boot-reg"
/* I/O address of register used to coordinate secondary core startup */
static u32 secondary_boot;
/*
* Enable the Cortex A9 Snoop Control Unit
*
* By the time this is called we already know there are multiple
* cores present. We assume we're running on a Cortex A9 processor,
* so any trouble getting the base address register or getting the
* SCU base is a problem.
*
* Return 0 if successful or an error code otherwise.
*/
static int __init scu_a9_enable(void)
{
unsigned long config_base;
void __iomem *scu_base;
if (!scu_a9_has_base()) {
pr_err("no configuration base address register!\n");
return -ENXIO;
}
/* Config base address register value is zero for uniprocessor */
config_base = scu_a9_get_base();
if (!config_base) {
pr_err("hardware reports only one core\n");
return -ENOENT;
}
scu_base = ioremap((phys_addr_t)config_base, CORTEX_A9_SCU_SIZE);
if (!scu_base) {
pr_err("failed to remap config base (%lu/%u) for SCU\n",
config_base, CORTEX_A9_SCU_SIZE);
return -ENOMEM;
}
scu_enable(scu_base);
iounmap(scu_base); /* That's the last we'll need of this */
return 0;
}
static void __init bcm_smp_prepare_cpus(unsigned int max_cpus)
{
static cpumask_t only_cpu_0 = { CPU_BITS_CPU0 };
struct device_node *node;
int ret;
BUG_ON(secondary_boot); /* We're called only once */
/*
* This function is only called via smp_ops->smp_prepare_cpu().
* That only happens if a "/cpus" device tree node exists
* and has an "enable-method" property that selects the SMP
* operations defined herein.
*/
node = of_find_node_by_path("/cpus");
BUG_ON(!node);
/*
* Our secondary enable method requires a "secondary-boot-reg"
* property to specify a register address used to request the
* ROM code boot a secondary code. If we have any trouble
* getting this we fall back to uniprocessor mode.
*/
if (of_property_read_u32(node, OF_SECONDARY_BOOT, &secondary_boot)) {
pr_err("%s: missing/invalid " OF_SECONDARY_BOOT " property\n",
node->name);
ret = -ENOENT; /* Arrange to disable SMP */
goto out;
}
/*
* Enable the SCU on Cortex A9 based SoCs. If -ENOENT is
* returned, the SoC reported a uniprocessor configuration.
* We bail on any other error.
*/
ret = scu_a9_enable();
out:
of_node_put(node);
if (ret) {
/* Update the CPU present map to reflect uniprocessor mode */
BUG_ON(ret != -ENOENT);
pr_warn("disabling SMP\n");
init_cpu_present(&only_cpu_0);
}
}
/*
* The ROM code has the secondary cores looping, waiting for an event.
* When an event occurs each core examines the bottom two bits of the
* secondary boot register. When a core finds those bits contain its
* own core id, it performs initialization, including computing its boot
* address by clearing the boot register value's bottom two bits. The
* core signals that it is beginning its execution by writing its boot
* address back to the secondary boot register, and finally jumps to
* that address.
*
* So to start a core executing we need to:
* - Encode the (hardware) CPU id with the bottom bits of the secondary
* start address.
* - Write that value into the secondary boot register.
* - Generate an event to wake up the secondary CPU(s).
* - Wait for the secondary boot register to be re-written, which
* indicates the secondary core has started.
*/
static int bcm_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
void __iomem *boot_reg;
phys_addr_t boot_func;
u64 start_clock;
u32 cpu_id;
u32 boot_val;
bool timeout = false;
cpu_id = cpu_logical_map(cpu);
if (cpu_id & ~BOOT_ADDR_CPUID_MASK) {
pr_err("bad cpu id (%u > %u)\n", cpu_id, BOOT_ADDR_CPUID_MASK);
return -EINVAL;
}
if (!secondary_boot) {
pr_err("required secondary boot register not specified\n");
return -EINVAL;
}
boot_reg = ioremap_nocache((phys_addr_t)secondary_boot, sizeof(u32));
if (!boot_reg) {
pr_err("unable to map boot register for cpu %u\n", cpu_id);
return -ENOSYS;
}
/*
* Secondary cores will start in secondary_startup(),
* defined in "arch/arm/kernel/head.S"
*/
boot_func = virt_to_phys(secondary_startup);
BUG_ON(boot_func & BOOT_ADDR_CPUID_MASK);
BUG_ON(boot_func > (phys_addr_t)U32_MAX);
/* The core to start is encoded in the low bits */
boot_val = (u32)boot_func | cpu_id;
writel_relaxed(boot_val, boot_reg);
sev();
/* The low bits will be cleared once the core has started */
start_clock = local_clock();
while (!timeout && readl_relaxed(boot_reg) == boot_val)
timeout = local_clock() - start_clock > SECONDARY_TIMEOUT_NS;
iounmap(boot_reg);
if (!timeout)
return 0;
pr_err("timeout waiting for cpu %u to start\n", cpu_id);
return -ENOSYS;
}
static struct smp_operations bcm_smp_ops __initdata = {
.smp_prepare_cpus = bcm_smp_prepare_cpus,
.smp_boot_secondary = bcm_boot_secondary,
};
CPU_METHOD_OF_DECLARE(bcm_smp_bcm281xx, "brcm,bcm11351-cpu-method",
&bcm_smp_ops);

363
arch/arm/mach-bcm/platsmp-brcmstb.c Normal file
View File

@ -0,0 +1,363 @@
/*
* Broadcom STB CPU SMP and hotplug support for ARM
*
* Copyright (C) 2013-2014 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/printk.h>
#include <linux/regmap.h>
#include <linux/smp.h>
#include <linux/mfd/syscon.h>
#include <linux/spinlock.h>
#include <asm/cacheflush.h>
#include <asm/cp15.h>
#include <asm/mach-types.h>
#include <asm/smp_plat.h>
#include "brcmstb.h"
enum {
ZONE_MAN_CLKEN_MASK = BIT(0),
ZONE_MAN_RESET_CNTL_MASK = BIT(1),
ZONE_MAN_MEM_PWR_MASK = BIT(4),
ZONE_RESERVED_1_MASK = BIT(5),
ZONE_MAN_ISO_CNTL_MASK = BIT(6),
ZONE_MANUAL_CONTROL_MASK = BIT(7),
ZONE_PWR_DN_REQ_MASK = BIT(9),
ZONE_PWR_UP_REQ_MASK = BIT(10),
ZONE_BLK_RST_ASSERT_MASK = BIT(12),
ZONE_PWR_OFF_STATE_MASK = BIT(25),
ZONE_PWR_ON_STATE_MASK = BIT(26),
ZONE_DPG_PWR_STATE_MASK = BIT(28),
ZONE_MEM_PWR_STATE_MASK = BIT(29),
ZONE_RESET_STATE_MASK = BIT(31),
CPU0_PWR_ZONE_CTRL_REG = 1,
CPU_RESET_CONFIG_REG = 2,
};
static void __iomem *cpubiuctrl_block;
static void __iomem *hif_cont_block;
static u32 cpu0_pwr_zone_ctrl_reg;
static u32 cpu_rst_cfg_reg;
static u32 hif_cont_reg;
#ifdef CONFIG_HOTPLUG_CPU
static DEFINE_PER_CPU_ALIGNED(int, per_cpu_sw_state);
static int per_cpu_sw_state_rd(u32 cpu)
{
sync_cache_r(SHIFT_PERCPU_PTR(&per_cpu_sw_state, per_cpu_offset(cpu)));
return per_cpu(per_cpu_sw_state, cpu);
}
static void per_cpu_sw_state_wr(u32 cpu, int val)
{
per_cpu(per_cpu_sw_state, cpu) = val;
dmb();
sync_cache_w(SHIFT_PERCPU_PTR(&per_cpu_sw_state, per_cpu_offset(cpu)));
dsb_sev();
}
#else
static inline void per_cpu_sw_state_wr(u32 cpu, int val) { }
#endif
static void __iomem *pwr_ctrl_get_base(u32 cpu)
{
void __iomem *base = cpubiuctrl_block + cpu0_pwr_zone_ctrl_reg;
base += (cpu_logical_map(cpu) * 4);
return base;
}
static u32 pwr_ctrl_rd(u32 cpu)
{
void __iomem *base = pwr_ctrl_get_base(cpu);
return readl_relaxed(base);
}
static void pwr_ctrl_wr(u32 cpu, u32 val)
{
void __iomem *base = pwr_ctrl_get_base(cpu);
writel(val, base);
}
static void cpu_rst_cfg_set(u32 cpu, int set)
{
u32 val;
val = readl_relaxed(cpubiuctrl_block + cpu_rst_cfg_reg);
if (set)
val |= BIT(cpu_logical_map(cpu));
else
val &= ~BIT(cpu_logical_map(cpu));
writel_relaxed(val, cpubiuctrl_block + cpu_rst_cfg_reg);
}
static void cpu_set_boot_addr(u32 cpu, unsigned long boot_addr)
{
const int reg_ofs = cpu_logical_map(cpu) * 8;
writel_relaxed(0, hif_cont_block + hif_cont_reg + reg_ofs);
writel_relaxed(boot_addr, hif_cont_block + hif_cont_reg + 4 + reg_ofs);
}
static void brcmstb_cpu_boot(u32 cpu)
{
pr_info("SMP: Booting CPU%d...\n", cpu);
/*
* set the reset vector to point to the secondary_startup
* routine
*/
cpu_set_boot_addr(cpu, virt_to_phys(brcmstb_secondary_startup));
/* unhalt the cpu */
cpu_rst_cfg_set(cpu, 0);
}
static void brcmstb_cpu_power_on(u32 cpu)
{
/*
* The secondary cores power was cut, so we must go through
* power-on initialization.
*/
u32 tmp;
pr_info("SMP: Powering up CPU%d...\n", cpu);
/* Request zone power up */
pwr_ctrl_wr(cpu, ZONE_PWR_UP_REQ_MASK);
/* Wait for the power up FSM to complete */
do {
tmp = pwr_ctrl_rd(cpu);
} while (!(tmp & ZONE_PWR_ON_STATE_MASK));
per_cpu_sw_state_wr(cpu, 1);
}
static int brcmstb_cpu_get_power_state(u32 cpu)
{
int tmp = pwr_ctrl_rd(cpu);
return (tmp & ZONE_RESET_STATE_MASK) ? 0 : 1;
}
#ifdef CONFIG_HOTPLUG_CPU
static void brcmstb_cpu_die(u32 cpu)
{
v7_exit_coherency_flush(all);
/* Prevent all interrupts from reaching this CPU. */
arch_local_irq_disable();
/*
* Final full barrier to ensure everything before this instruction has
* quiesced.
*/
isb();
dsb();
per_cpu_sw_state_wr(cpu, 0);
/* Sit and wait to die */
wfi();
/* We should never get here... */
panic("Spurious interrupt on CPU %d received!\n", cpu);
}
static int brcmstb_cpu_kill(u32 cpu)
{
u32 tmp;
pr_info("SMP: Powering down CPU%d...\n", cpu);
while (per_cpu_sw_state_rd(cpu))
;
/* Program zone reset */
pwr_ctrl_wr(cpu, ZONE_RESET_STATE_MASK | ZONE_BLK_RST_ASSERT_MASK |
ZONE_PWR_DN_REQ_MASK);
/* Verify zone reset */
tmp = pwr_ctrl_rd(cpu);
if (!(tmp & ZONE_RESET_STATE_MASK))
pr_err("%s: Zone reset bit for CPU %d not asserted!\n",
__func__, cpu);
/* Wait for power down */
do {
tmp = pwr_ctrl_rd(cpu);
} while (!(tmp & ZONE_PWR_OFF_STATE_MASK));
/* Settle-time from Broadcom-internal DVT reference code */
udelay(7);
/* Assert reset on the CPU */
cpu_rst_cfg_set(cpu, 1);
return 1;
}
#endif /* CONFIG_HOTPLUG_CPU */
static int __init setup_hifcpubiuctrl_regs(struct device_node *np)
{
int rc = 0;
char *name;
struct device_node *syscon_np = NULL;
name = "syscon-cpu";
syscon_np = of_parse_phandle(np, name, 0);
if (!syscon_np) {
pr_err("can't find phandle %s\n", name);
rc = -EINVAL;
goto cleanup;
}
cpubiuctrl_block = of_iomap(syscon_np, 0);
if (!cpubiuctrl_block) {
pr_err("iomap failed for cpubiuctrl_block\n");
rc = -EINVAL;
goto cleanup;
}
rc = of_property_read_u32_index(np, name, CPU0_PWR_ZONE_CTRL_REG,
&cpu0_pwr_zone_ctrl_reg);
if (rc) {
pr_err("failed to read 1st entry from %s property (%d)\n", name,
rc);
rc = -EINVAL;
goto cleanup;
}
rc = of_property_read_u32_index(np, name, CPU_RESET_CONFIG_REG,
&cpu_rst_cfg_reg);
if (rc) {
pr_err("failed to read 2nd entry from %s property (%d)\n", name,
rc);
rc = -EINVAL;
goto cleanup;
}
cleanup:
if (syscon_np)
of_node_put(syscon_np);
return rc;
}
static int __init setup_hifcont_regs(struct device_node *np)
{
int rc = 0;
char *name;
struct device_node *syscon_np = NULL;
name = "syscon-cont";
syscon_np = of_parse_phandle(np, name, 0);
if (!syscon_np) {
pr_err("can't find phandle %s\n", name);
rc = -EINVAL;
goto cleanup;
}
hif_cont_block = of_iomap(syscon_np, 0);
if (!hif_cont_block) {
pr_err("iomap failed for hif_cont_block\n");
rc = -EINVAL;
goto cleanup;
}
/* offset is at top of hif_cont_block */
hif_cont_reg = 0;
cleanup:
if (syscon_np)
of_node_put(syscon_np);
return rc;
}
static void __init brcmstb_cpu_ctrl_setup(unsigned int max_cpus)
{
int rc;
struct device_node *np;
char *name;
name = "brcm,brcmstb-smpboot";
np = of_find_compatible_node(NULL, NULL, name);
if (!np) {
pr_err("can't find compatible node %s\n", name);
return;
}
rc = setup_hifcpubiuctrl_regs(np);
if (rc)
return;
rc = setup_hifcont_regs(np);
if (rc)
return;
}
static DEFINE_SPINLOCK(boot_lock);
static void brcmstb_secondary_init(unsigned int cpu)
{
/*
* Synchronise with the boot thread.
*/
spin_lock(&boot_lock);
spin_unlock(&boot_lock);
}
static int brcmstb_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
/*
* set synchronisation state between this boot processor
* and the secondary one
*/
spin_lock(&boot_lock);
/* Bring up power to the core if necessary */
if (brcmstb_cpu_get_power_state(cpu) == 0)
brcmstb_cpu_power_on(cpu);
brcmstb_cpu_boot(cpu);
/*
* now the secondary core is starting up let it run its
* calibrations, then wait for it to finish
*/
spin_unlock(&boot_lock);
return 0;
}
static struct smp_operations brcmstb_smp_ops __initdata = {
.smp_prepare_cpus = brcmstb_cpu_ctrl_setup,
.smp_secondary_init = brcmstb_secondary_init,
.smp_boot_secondary = brcmstb_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU
.cpu_kill = brcmstb_cpu_kill,
.cpu_die = brcmstb_cpu_die,
#endif
};
CPU_METHOD_OF_DECLARE(brcmstb_smp, "brcm,brahma-b15", &brcmstb_smp_ops);

3
arch/arm/mach-berlin/Kconfig
View File

@ -13,7 +13,9 @@ config MACH_BERLIN_BG2
bool "Marvell Armada 1500 (BG2)"
select CACHE_L2X0
select CPU_PJ4B
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
select HAVE_SMP
select PINCTRL_BERLIN_BG2
config MACH_BERLIN_BG2CD
@ -25,6 +27,7 @@ config MACH_BERLIN_BG2CD
config MACH_BERLIN_BG2Q
bool "Marvell Armada 1500 Pro (BG2-Q)"
select CACHE_L2X0
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
select PINCTRL_BERLIN_BG2Q

3
arch/arm/mach-berlin/Makefile
View File

@ -1 +1,2 @@
obj-y += berlin.o
obj-y += berlin.o
obj-$(CONFIG_SMP) += headsmp.o platsmp.o

30
arch/arm/mach-berlin/headsmp.S Normal file
View File

@ -0,0 +1,30 @@
/*
* Copyright (C) 2014 Marvell Technology Group Ltd.
*
* Antoine Ténart <antoine.tenart@free-electrons.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/assembler.h>
ENTRY(berlin_secondary_startup)
ARM_BE8(setend be)
bl v7_invalidate_l1
b secondary_startup
ENDPROC(berlin_secondary_startup)
/*
* If the following instruction is set in the reset exception vector, CPUs
* will fetch the value of the software reset address vector when being
* reset.
*/
.global boot_inst
boot_inst:
ldr pc, [pc, #140]
.align

99
arch/arm/mach-berlin/platsmp.c Normal file
View File

@ -0,0 +1,99 @@
/*
* Copyright (C) 2014 Marvell Technology Group Ltd.
*
* Antoine Ténart <antoine.tenart@free-electrons.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <asm/cacheflush.h>
#include <asm/smp_plat.h>
#include <asm/smp_scu.h>
#define CPU_RESET 0x00
#define RESET_VECT 0x00
#define SW_RESET_ADDR 0x94
extern void berlin_secondary_startup(void);
extern u32 boot_inst;
static void __iomem *cpu_ctrl;
static inline void berlin_perform_reset_cpu(unsigned int cpu)
{
u32 val;
val = readl(cpu_ctrl + CPU_RESET);
val |= BIT(cpu_logical_map(cpu));
writel(val, cpu_ctrl + CPU_RESET);
}
static int berlin_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
if (!cpu_ctrl)
return -EFAULT;
/*
* Reset the CPU, making it to execute the instruction in the reset
* exception vector.
*/
berlin_perform_reset_cpu(cpu);
return 0;
}
static void __init berlin_smp_prepare_cpus(unsigned int max_cpus)
{
struct device_node *np;
void __iomem *scu_base;
void __iomem *vectors_base;
np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
scu_base = of_iomap(np, 0);
of_node_put(np);
if (!scu_base)
return;
np = of_find_compatible_node(NULL, NULL, "marvell,berlin-cpu-ctrl");
cpu_ctrl = of_iomap(np, 0);
of_node_put(np);
if (!cpu_ctrl)
goto unmap_scu;
vectors_base = ioremap(CONFIG_VECTORS_BASE, SZ_32K);
if (!vectors_base)
goto unmap_scu;
scu_enable(scu_base);
flush_cache_all();
/*
* Write the first instruction the CPU will execute after being reset
* in the reset exception vector.
*/
writel(boot_inst, vectors_base + RESET_VECT);
/*
* Write the secondary startup address into the SW reset address
* vector. This is used by boot_inst.
*/
writel(virt_to_phys(berlin_secondary_startup), vectors_base + SW_RESET_ADDR);
iounmap(vectors_base);
unmap_scu:
iounmap(scu_base);
}
static struct smp_operations berlin_smp_ops __initdata = {
.smp_prepare_cpus = berlin_smp_prepare_cpus,
.smp_boot_secondary = berlin_boot_secondary,
};
CPU_METHOD_OF_DECLARE(berlin_smp, "marvell,berlin-smp", &berlin_smp_ops);

14
arch/arm/mach-exynos/common.h
View File

@ -134,7 +134,7 @@ extern void exynos_cpu_die(unsigned int cpu);
/* PMU(Power Management Unit) support */
#define PMU_TABLE_END NULL
#define PMU_TABLE_END (-1U)
enum sys_powerdown {
SYS_AFTR,
@ -144,7 +144,7 @@ enum sys_powerdown {
};
struct exynos_pmu_conf {
void __iomem *reg;
unsigned int offset;
unsigned int val[NUM_SYS_POWERDOWN];
};
@ -160,4 +160,14 @@ extern void exynos_enter_aftr(void);
extern void s5p_init_cpu(void __iomem *cpuid_addr);
extern unsigned int samsung_rev(void);
static inline void pmu_raw_writel(u32 val, u32 offset)
{
__raw_writel(val, pmu_base_addr + offset);
}
static inline u32 pmu_raw_readl(u32 offset)
{
return __raw_readl(pmu_base_addr + offset);
}
#endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */

30
arch/arm/mach-exynos/exynos.c
View File

@ -60,11 +60,6 @@ static struct map_desc exynos4_iodesc[] __initdata = {
.pfn = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_PMU,
.pfn = __phys_to_pfn(EXYNOS4_PA_PMU),
.length = SZ_64K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_COMBINER_BASE,
.pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER),
@ -139,11 +134,6 @@ static struct map_desc exynos5_iodesc[] __initdata = {
.pfn = __phys_to_pfn(EXYNOS5_PA_CMU),
.length = 144 * SZ_1K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_PMU,
.pfn = __phys_to_pfn(EXYNOS5_PA_PMU),
.length = SZ_64K,
.type = MT_DEVICE,
},
};
@ -151,7 +141,7 @@ static void exynos_restart(enum reboot_mode mode, const char *cmd)
{
struct device_node *np;
u32 val = 0x1;
void __iomem *addr = EXYNOS_SWRESET;
void __iomem *addr = pmu_base_addr + EXYNOS_SWRESET;
if (of_machine_is_compatible("samsung,exynos5440")) {
u32 status;
@ -175,17 +165,6 @@ static struct platform_device exynos_cpuidle = {
.id = -1,
};
void __init exynos_cpuidle_init(void)
{
if (soc_is_exynos4210() || soc_is_exynos5250())
platform_device_register(&exynos_cpuidle);
}
void __init exynos_cpufreq_init(void)
{
platform_device_register_simple("exynos-cpufreq", -1, NULL, 0);
}
void __iomem *sysram_base_addr;
void __iomem *sysram_ns_base_addr;
@ -335,8 +314,11 @@ static void __init exynos_dt_machine_init(void)
if (!IS_ENABLED(CONFIG_SMP))
exynos_sysram_init();
exynos_cpuidle_init();
exynos_cpufreq_init();
if (of_machine_is_compatible("samsung,exynos4210") ||
of_machine_is_compatible("samsung,exynos5250"))
platform_device_register(&exynos_cpuidle);
platform_device_register_simple("exynos-cpufreq", -1, NULL, 0);
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}

3
arch/arm/mach-exynos/include/mach/map.h
View File

@ -27,9 +27,6 @@
#define EXYNOS4_PA_SYSCON 0x10010000
#define EXYNOS5_PA_SYSCON 0x10050100
#define EXYNOS4_PA_PMU 0x10020000
#define EXYNOS5_PA_PMU 0x10040000
#define EXYNOS4_PA_CMU 0x10030000
#define EXYNOS5_PA_CMU 0x10010000

106
arch/arm/mach-exynos/mcpm-exynos.c
View File

@ -26,6 +26,10 @@
#define EXYNOS5420_CPUS_PER_CLUSTER 4
#define EXYNOS5420_NR_CLUSTERS 2
#define EXYNOS5420_ENABLE_AUTOMATIC_CORE_DOWN BIT(9)
#define EXYNOS5420_USE_ARM_CORE_DOWN_STATE BIT(29)
#define EXYNOS5420_USE_L2_COMMON_UP_STATE BIT(30)
/*
* The common v7_exit_coherency_flush API could not be used because of the
* Erratum 799270 workaround. This macro is the same as the common one (in
@ -51,7 +55,7 @@
"dsb\n\t" \
"ldmfd sp!, {fp, ip}" \
: \
: "Ir" (S5P_INFORM0) \
: "Ir" (pmu_base_addr + S5P_INFORM0) \
: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
"r9", "r10", "lr", "memory")
@ -73,36 +77,9 @@ cpu_use_count[EXYNOS5420_CPUS_PER_CLUSTER][EXYNOS5420_NR_CLUSTERS];
#define exynos_cluster_unused(cluster) !exynos_cluster_usecnt(cluster)
static int exynos_cluster_power_control(unsigned int cluster, int enable)
{
unsigned int tries = 100;
unsigned int val;
if (enable) {
exynos_cluster_power_up(cluster);
val = S5P_CORE_LOCAL_PWR_EN;
} else {
exynos_cluster_power_down(cluster);
val = 0;
}
/* Wait until cluster power control is applied */
while (tries--) {
if (exynos_cluster_power_state(cluster) == val)
return 0;
cpu_relax();
}
pr_debug("timed out waiting for cluster %u to power %s\n", cluster,
enable ? "on" : "off");
return -ETIMEDOUT;
}
static int exynos_power_up(unsigned int cpu, unsigned int cluster)
{
unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
int err = 0;
pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
if (cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
@ -126,12 +103,9 @@ static int exynos_power_up(unsigned int cpu, unsigned int cluster)
* cores.
*/
if (was_cluster_down)
err = exynos_cluster_power_control(cluster, 1);
exynos_cluster_power_up(cluster);
if (!err)
exynos_cpu_power_up(cpunr);
else
exynos_cluster_power_control(cluster, 0);
exynos_cpu_power_up(cpunr);
} else if (cpu_use_count[cpu][cluster] != 2) {
/*
* The only possible values are:
@ -147,7 +121,7 @@ static int exynos_power_up(unsigned int cpu, unsigned int cluster)
arch_spin_unlock(&exynos_mcpm_lock);
local_irq_enable();
return err;
return 0;
}
/*
@ -178,9 +152,10 @@ static void exynos_power_down(void)
if (cpu_use_count[cpu][cluster] == 0) {
exynos_cpu_power_down(cpunr);
if (exynos_cluster_unused(cluster))
/* TODO: Turn off the cluster here to save power. */
if (exynos_cluster_unused(cluster)) {
exynos_cluster_power_down(cluster);
last_man = true;
}
} else if (cpu_use_count[cpu][cluster] == 1) {
/*
* A power_up request went ahead of us.
@ -257,10 +232,46 @@ static int exynos_wait_for_powerdown(unsigned int cpu, unsigned int cluster)
return -ETIMEDOUT; /* timeout */
}
static void exynos_powered_up(void)
{
unsigned int mpidr, cpu, cluster;
mpidr = read_cpuid_mpidr();
cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
arch_spin_lock(&exynos_mcpm_lock);
if (cpu_use_count[cpu][cluster] == 0)
cpu_use_count[cpu][cluster] = 1;
arch_spin_unlock(&exynos_mcpm_lock);
}
static void exynos_suspend(u64 residency)
{
unsigned int mpidr, cpunr;
exynos_power_down();
/*
* Execution reaches here only if cpu did not power down.
* Hence roll back the changes done in exynos_power_down function.
*
* CAUTION: "This function requires the stack data to be visible through
* power down and can only be executed on processors like A15 and A7
* that hit the cache with the C bit clear in the SCTLR register."
*/
mpidr = read_cpuid_mpidr();
cpunr = exynos_pmu_cpunr(mpidr);
exynos_cpu_power_up(cpunr);
}
static const struct mcpm_platform_ops exynos_power_ops = {
.power_up = exynos_power_up,
.power_down = exynos_power_down,
.wait_for_powerdown = exynos_wait_for_powerdown,
.suspend = exynos_suspend,
.powered_up = exynos_powered_up,
};
static void __init exynos_mcpm_usage_count_init(void)
@ -312,6 +323,7 @@ static int __init exynos_mcpm_init(void)
{
struct device_node *node;
void __iomem *ns_sram_base_addr;
unsigned int value, i;
int ret;
node = of_find_matching_node(NULL, exynos_dt_mcpm_match);
@ -338,7 +350,7 @@ static int __init exynos_mcpm_init(void)
* To increase the stability of KFC reset we need to program
* the PMU SPARE3 register
*/
__raw_writel(EXYNOS5420_SWRESET_KFC_SEL, S5P_PMU_SPARE3);
pmu_raw_writel(EXYNOS5420_SWRESET_KFC_SEL, S5P_PMU_SPARE3);
exynos_mcpm_usage_count_init();
@ -356,6 +368,26 @@ static int __init exynos_mcpm_init(void)
pr_info("Exynos MCPM support installed\n");
/*
* On Exynos5420/5800 for the A15 and A7 clusters:
*
* EXYNOS5420_ENABLE_AUTOMATIC_CORE_DOWN ensures that all the cores
* in a cluster are turned off before turning off the cluster L2.
*
* EXYNOS5420_USE_ARM_CORE_DOWN_STATE ensures that a cores is powered
* off before waking it up.
*
* EXYNOS5420_USE_L2_COMMON_UP_STATE ensures that cluster L2 will be
* turned on before the first man is powered up.
*/
for (i = 0; i < EXYNOS5420_NR_CLUSTERS; i++) {
value = pmu_raw_readl(EXYNOS_COMMON_OPTION(i));
value |= EXYNOS5420_ENABLE_AUTOMATIC_CORE_DOWN |
EXYNOS5420_USE_ARM_CORE_DOWN_STATE |
EXYNOS5420_USE_L2_COMMON_UP_STATE;
pmu_raw_writel(value, EXYNOS_COMMON_OPTION(i));
}
/*
* U-Boot SPL is hardcoded to jump to the start of ns_sram_base_addr
* as part of secondary_cpu_start(). Let's redirect it to the

22
arch/arm/mach-exynos/platsmp.c
View File

@ -26,6 +26,8 @@
#include <asm/smp_scu.h>
#include <asm/firmware.h>
#include <mach/map.h>
#include "common.h"
#include "regs-pmu.h"
@ -41,7 +43,7 @@ extern void exynos4_secondary_startup(void);
*/
void exynos_cpu_power_down(int cpu)
{
__raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
pmu_raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
}
/**
@ -52,8 +54,8 @@ void exynos_cpu_power_down(int cpu)
*/
void exynos_cpu_power_up(int cpu)
{
__raw_writel(S5P_CORE_LOCAL_PWR_EN,
EXYNOS_ARM_CORE_CONFIGURATION(cpu));
pmu_raw_writel(S5P_CORE_LOCAL_PWR_EN,
EXYNOS_ARM_CORE_CONFIGURATION(cpu));
}
/**
@ -63,7 +65,7 @@ void exynos_cpu_power_up(int cpu)
*/
int exynos_cpu_power_state(int cpu)
{
return (__raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) &
return (pmu_raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) &
S5P_CORE_LOCAL_PWR_EN);
}
@ -73,7 +75,7 @@ int exynos_cpu_power_state(int cpu)
*/
void exynos_cluster_power_down(int cluster)
{
__raw_writel(0, EXYNOS_COMMON_CONFIGURATION(cluster));
pmu_raw_writel(0, EXYNOS_COMMON_CONFIGURATION(cluster));
}
/**
@ -82,8 +84,8 @@ void exynos_cluster_power_down(int cluster)
*/
void exynos_cluster_power_up(int cluster)
{
__raw_writel(S5P_CORE_LOCAL_PWR_EN,
EXYNOS_COMMON_CONFIGURATION(cluster));
pmu_raw_writel(S5P_CORE_LOCAL_PWR_EN,
EXYNOS_COMMON_CONFIGURATION(cluster));
}
/**
@ -93,14 +95,14 @@ void exynos_cluster_power_up(int cluster)
*/
int exynos_cluster_power_state(int cluster)
{
return (__raw_readl(EXYNOS_COMMON_STATUS(cluster)) &
S5P_CORE_LOCAL_PWR_EN);
return (pmu_raw_readl(EXYNOS_COMMON_STATUS(cluster)) &
S5P_CORE_LOCAL_PWR_EN);
}
static inline void __iomem *cpu_boot_reg_base(void)
{
if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
return S5P_INFORM5;
return pmu_base_addr + S5P_INFORM5;
return sysram_base_addr;
}

61
arch/arm/mach-exynos/pm.c
View File

@ -28,7 +28,6 @@
#include <asm/suspend.h>
#include <plat/pm-common.h>
#include <plat/pll.h>
#include <plat/regs-srom.h>
#include <mach/map.h>
@ -102,11 +101,15 @@ static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
}
#define EXYNOS_BOOT_VECTOR_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \
S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
(sysram_base_addr + 0x24) : S5P_INFORM0))
pmu_base_addr + S5P_INFORM7 : \
(samsung_rev() == EXYNOS4210_REV_1_0 ? \
(sysram_base_addr + 0x24) : \
pmu_base_addr + S5P_INFORM0))
#define EXYNOS_BOOT_VECTOR_FLAG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
(sysram_base_addr + 0x20) : S5P_INFORM1))
pmu_base_addr + S5P_INFORM6 : \
(samsung_rev() == EXYNOS4210_REV_1_0 ? \
(sysram_base_addr + 0x20) : \
pmu_base_addr + S5P_INFORM1))
#define S5P_CHECK_AFTR 0xFCBA0D10
#define S5P_CHECK_SLEEP 0x00000BAD
@ -114,7 +117,7 @@ static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
static void exynos_set_wakeupmask(long mask)
{
__raw_writel(mask, S5P_WAKEUP_MASK);
pmu_raw_writel(mask, S5P_WAKEUP_MASK);
}
static void exynos_cpu_set_boot_vector(long flags)
@ -191,27 +194,27 @@ static void exynos_pm_prepare(void)
unsigned int tmp;
/* Set wake-up mask registers */
__raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
__raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
pmu_raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
if (soc_is_exynos5250()) {
s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save));
/* Disable USE_RETENTION of JPEG_MEM_OPTION */
tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION);
tmp = pmu_raw_readl(EXYNOS5_JPEG_MEM_OPTION);
tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
__raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
pmu_raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
}
/* Set value of power down register for sleep mode */
exynos_sys_powerdown_conf(SYS_SLEEP);
__raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
pmu_raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
/* ensure at least INFORM0 has the resume address */
__raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
}
static void exynos_pm_central_suspend(void)
@ -219,9 +222,9 @@ static void exynos_pm_central_suspend(void)
unsigned long tmp;
/* Setting Central Sequence Register for power down mode */
tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
}
static int exynos_pm_suspend(void)
@ -233,7 +236,7 @@ static int exynos_pm_suspend(void)
/* Setting SEQ_OPTION register */
tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
__raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
exynos_cpu_save_register();
@ -251,12 +254,12 @@ static int exynos_pm_central_resume(void)
* S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
* in this situation.
*/
tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
tmp |= S5P_CENTRAL_LOWPWR_CFG;
__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
/* clear the wakeup state register */
__raw_writel(0x0, S5P_WAKEUP_STAT);
pmu_raw_writel(0x0, S5P_WAKEUP_STAT);
/* No need to perform below restore code */
return -1;
}
@ -274,13 +277,13 @@ static void exynos_pm_resume(void)
/* For release retention */
__raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
__raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
__raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
__raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
__raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
__raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
__raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
pmu_raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
pmu_raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
pmu_raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
pmu_raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
pmu_raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
pmu_raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
pmu_raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
if (soc_is_exynos5250())
s3c_pm_do_restore(exynos5_sys_save,
@ -294,7 +297,7 @@ static void exynos_pm_resume(void)
early_wakeup:
/* Clear SLEEP mode set in INFORM1 */
__raw_writel(0x0, S5P_INFORM1);
pmu_raw_writel(0x0, S5P_INFORM1);
return;
}
@ -338,7 +341,7 @@ static int exynos_suspend_enter(suspend_state_t state)
s3c_pm_restore_uarts();
S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
__raw_readl(S5P_WAKEUP_STAT));
pmu_raw_readl(S5P_WAKEUP_STAT));
s3c_pm_check_restore();
@ -408,9 +411,9 @@ void __init exynos_pm_init(void)
gic_arch_extn.irq_set_wake = exynos_irq_set_wake;
/* All wakeup disable */
tmp = __raw_readl(S5P_WAKEUP_MASK);
tmp = pmu_raw_readl(S5P_WAKEUP_MASK);
tmp |= ((0xFF << 8) | (0x1F << 1));
__raw_writel(tmp, S5P_WAKEUP_MASK);
pmu_raw_writel(tmp, S5P_WAKEUP_MASK);
register_syscore_ops(&exynos_pm_syscore_ops);
suspend_set_ops(&exynos_suspend_ops);

40
arch/arm/mach-exynos/pmu.c
View File

@ -18,7 +18,7 @@
static const struct exynos_pmu_conf *exynos_pmu_config;
static const struct exynos_pmu_conf exynos4210_pmu_config[] = {
/* { .reg = address, .val = { AFTR, LPA, SLEEP } */
/* { .offset = offset, .val = { AFTR, LPA, SLEEP } */
{ S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } },
{ S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } },
{ S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } },
@ -212,7 +212,7 @@ static const struct exynos_pmu_conf exynos4412_pmu_config[] = {
};
static const struct exynos_pmu_conf exynos5250_pmu_config[] = {
/* { .reg = address, .val = { AFTR, LPA, SLEEP } */
/* { .offset = offset, .val = { AFTR, LPA, SLEEP } */
{ EXYNOS5_ARM_CORE0_SYS_PWR_REG, { 0x0, 0x0, 0x2} },
{ EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
{ EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
@ -315,7 +315,7 @@ static const struct exynos_pmu_conf exynos5250_pmu_config[] = {
{ PMU_TABLE_END,},
};
static void __iomem * const exynos5_list_both_cnt_feed[] = {
static unsigned int const exynos5_list_both_cnt_feed[] = {
EXYNOS5_ARM_CORE0_OPTION,
EXYNOS5_ARM_CORE1_OPTION,
EXYNOS5_ARM_COMMON_OPTION,
@ -329,7 +329,7 @@ static void __iomem * const exynos5_list_both_cnt_feed[] = {
EXYNOS5_TOP_PWR_SYSMEM_OPTION,
};
static void __iomem * const exynos5_list_diable_wfi_wfe[] = {
static unsigned int const exynos5_list_diable_wfi_wfe[] = {
EXYNOS5_ARM_CORE1_OPTION,
EXYNOS5_FSYS_ARM_OPTION,
EXYNOS5_ISP_ARM_OPTION,
@ -344,27 +344,27 @@ static void exynos5_init_pmu(void)
* Enable both SC_FEEDBACK and SC_COUNTER
*/
for (i = 0 ; i < ARRAY_SIZE(exynos5_list_both_cnt_feed) ; i++) {
tmp = __raw_readl(exynos5_list_both_cnt_feed[i]);
tmp = pmu_raw_readl(exynos5_list_both_cnt_feed[i]);
tmp |= (EXYNOS5_USE_SC_FEEDBACK |
EXYNOS5_USE_SC_COUNTER);
__raw_writel(tmp, exynos5_list_both_cnt_feed[i]);
pmu_raw_writel(tmp, exynos5_list_both_cnt_feed[i]);
}
/*
* SKIP_DEACTIVATE_ACEACP_IN_PWDN_BITFIELD Enable
*/
tmp = __raw_readl(EXYNOS5_ARM_COMMON_OPTION);
tmp = pmu_raw_readl(EXYNOS5_ARM_COMMON_OPTION);
tmp |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN;
__raw_writel(tmp, EXYNOS5_ARM_COMMON_OPTION);
pmu_raw_writel(tmp, EXYNOS5_ARM_COMMON_OPTION);
/*
* Disable WFI/WFE on XXX_OPTION
*/
for (i = 0 ; i < ARRAY_SIZE(exynos5_list_diable_wfi_wfe) ; i++) {
tmp = __raw_readl(exynos5_list_diable_wfi_wfe[i]);
tmp = pmu_raw_readl(exynos5_list_diable_wfi_wfe[i]);
tmp &= ~(EXYNOS5_OPTION_USE_STANDBYWFE |
EXYNOS5_OPTION_USE_STANDBYWFI);
__raw_writel(tmp, exynos5_list_diable_wfi_wfe[i]);
pmu_raw_writel(tmp, exynos5_list_diable_wfi_wfe[i]);
}
}
@ -375,14 +375,14 @@ void exynos_sys_powerdown_conf(enum sys_powerdown mode)
if (soc_is_exynos5250())
exynos5_init_pmu();
for (i = 0; (exynos_pmu_config[i].reg != PMU_TABLE_END) ; i++)
__raw_writel(exynos_pmu_config[i].val[mode],
exynos_pmu_config[i].reg);
for (i = 0; (exynos_pmu_config[i].offset != PMU_TABLE_END) ; i++)
pmu_raw_writel(exynos_pmu_config[i].val[mode],
exynos_pmu_config[i].offset);
if (soc_is_exynos4412()) {
for (i = 0; exynos4412_pmu_config[i].reg != PMU_TABLE_END ; i++)
__raw_writel(exynos4412_pmu_config[i].val[mode],
exynos4412_pmu_config[i].reg);
for (i = 0; exynos4412_pmu_config[i].offset != PMU_TABLE_END ; i++)
pmu_raw_writel(exynos4412_pmu_config[i].val[mode],
exynos4412_pmu_config[i].offset);
}
}
@ -403,13 +403,13 @@ static int __init exynos_pmu_init(void)
* When SYS_WDTRESET is set, watchdog timer reset request
* is ignored by power management unit.
*/
value = __raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE);
value = pmu_raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE);
value &= ~EXYNOS5_SYS_WDTRESET;
__raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE);
pmu_raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE);
value = __raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST);
value = pmu_raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST);
value &= ~EXYNOS5_SYS_WDTRESET;
__raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST);
pmu_raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST);
exynos_pmu_config = exynos5250_pmu_config;
pr_info("EXYNOS5250 PMU Initialize\n");

521
arch/arm/mach-exynos/regs-pmu.h
View File

@ -12,300 +12,298 @@
#ifndef __ASM_ARCH_REGS_PMU_H
#define __ASM_ARCH_REGS_PMU_H __FILE__
#include <mach/map.h>
#define S5P_PMUREG(x) (S5P_VA_PMU + (x))
#define S5P_CENTRAL_SEQ_CONFIGURATION S5P_PMUREG(0x0200)
#define S5P_CENTRAL_SEQ_CONFIGURATION 0x0200
#define S5P_CENTRAL_LOWPWR_CFG (1 << 16)
#define S5P_CENTRAL_SEQ_OPTION S5P_PMUREG(0x0208)
#define S5P_CENTRAL_SEQ_OPTION 0x0208
#define S5P_USE_STANDBY_WFI0 (1 << 16)
#define S5P_USE_STANDBY_WFE0 (1 << 24)
#define EXYNOS_SWRESET S5P_PMUREG(0x0400)
#define EXYNOS5440_SWRESET S5P_PMUREG(0x00C4)
#define EXYNOS_SWRESET 0x0400
#define EXYNOS5440_SWRESET 0x00C4
#define S5P_WAKEUP_STAT S5P_PMUREG(0x0600)
#define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604)
#define S5P_WAKEUP_MASK S5P_PMUREG(0x0608)
#define S5P_WAKEUP_STAT 0x0600
#define S5P_EINT_WAKEUP_MASK 0x0604
#define S5P_WAKEUP_MASK 0x0608
#define S5P_INFORM0 S5P_PMUREG(0x0800)
#define S5P_INFORM1 S5P_PMUREG(0x0804)
#define S5P_INFORM5 S5P_PMUREG(0x0814)
#define S5P_INFORM6 S5P_PMUREG(0x0818)
#define S5P_INFORM7 S5P_PMUREG(0x081C)
#define S5P_PMU_SPARE3 S5P_PMUREG(0x090C)
#define S5P_INFORM0 0x0800
#define S5P_INFORM1 0x0804
#define S5P_INFORM5 0x0814
#define S5P_INFORM6 0x0818
#define S5P_INFORM7 0x081C
#define S5P_PMU_SPARE3 0x090C
#define S5P_ARM_CORE0_LOWPWR S5P_PMUREG(0x1000)
#define S5P_DIS_IRQ_CORE0 S5P_PMUREG(0x1004)
#define S5P_DIS_IRQ_CENTRAL0 S5P_PMUREG(0x1008)
#define S5P_ARM_CORE1_LOWPWR S5P_PMUREG(0x1010)
#define S5P_DIS_IRQ_CORE1 S5P_PMUREG(0x1014)
#define S5P_DIS_IRQ_CENTRAL1 S5P_PMUREG(0x1018)
#define S5P_ARM_COMMON_LOWPWR S5P_PMUREG(0x1080)
#define S5P_L2_0_LOWPWR S5P_PMUREG(0x10C0)
#define S5P_L2_1_LOWPWR S5P_PMUREG(0x10C4)
#define S5P_CMU_ACLKSTOP_LOWPWR S5P_PMUREG(0x1100)
#define S5P_CMU_SCLKSTOP_LOWPWR S5P_PMUREG(0x1104)
#define S5P_CMU_RESET_LOWPWR S5P_PMUREG(0x110C)
#define S5P_APLL_SYSCLK_LOWPWR S5P_PMUREG(0x1120)
#define S5P_MPLL_SYSCLK_LOWPWR S5P_PMUREG(0x1124)
#define S5P_VPLL_SYSCLK_LOWPWR S5P_PMUREG(0x1128)
#define S5P_EPLL_SYSCLK_LOWPWR S5P_PMUREG(0x112C)
#define S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR S5P_PMUREG(0x1138)
#define S5P_CMU_RESET_GPSALIVE_LOWPWR S5P_PMUREG(0x113C)
#define S5P_CMU_CLKSTOP_CAM_LOWPWR S5P_PMUREG(0x1140)
#define S5P_CMU_CLKSTOP_TV_LOWPWR S5P_PMUREG(0x1144)
#define S5P_CMU_CLKSTOP_MFC_LOWPWR S5P_PMUREG(0x1148)
#define S5P_CMU_CLKSTOP_G3D_LOWPWR S5P_PMUREG(0x114C)
#define S5P_CMU_CLKSTOP_LCD0_LOWPWR S5P_PMUREG(0x1150)
#define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR S5P_PMUREG(0x1158)
#define S5P_CMU_CLKSTOP_GPS_LOWPWR S5P_PMUREG(0x115C)
#define S5P_CMU_RESET_CAM_LOWPWR S5P_PMUREG(0x1160)
#define S5P_CMU_RESET_TV_LOWPWR S5P_PMUREG(0x1164)
#define S5P_CMU_RESET_MFC_LOWPWR S5P_PMUREG(0x1168)
#define S5P_CMU_RESET_G3D_LOWPWR S5P_PMUREG(0x116C)
#define S5P_CMU_RESET_LCD0_LOWPWR S5P_PMUREG(0x1170)
#define S5P_CMU_RESET_MAUDIO_LOWPWR S5P_PMUREG(0x1178)
#define S5P_CMU_RESET_GPS_LOWPWR S5P_PMUREG(0x117C)
#define S5P_TOP_BUS_LOWPWR S5P_PMUREG(0x1180)
#define S5P_TOP_RETENTION_LOWPWR S5P_PMUREG(0x1184)
#define S5P_TOP_PWR_LOWPWR S5P_PMUREG(0x1188)
#define S5P_LOGIC_RESET_LOWPWR S5P_PMUREG(0x11A0)
#define S5P_ONENAND_MEM_LOWPWR S5P_PMUREG(0x11C0)
#define S5P_G2D_ACP_MEM_LOWPWR S5P_PMUREG(0x11C8)
#define S5P_USBOTG_MEM_LOWPWR S5P_PMUREG(0x11CC)
#define S5P_HSMMC_MEM_LOWPWR S5P_PMUREG(0x11D0)
#define S5P_CSSYS_MEM_LOWPWR S5P_PMUREG(0x11D4)
#define S5P_SECSS_MEM_LOWPWR S5P_PMUREG(0x11D8)
#define S5P_PAD_RETENTION_DRAM_LOWPWR S5P_PMUREG(0x1200)
#define S5P_PAD_RETENTION_MAUDIO_LOWPWR S5P_PMUREG(0x1204)
#define S5P_PAD_RETENTION_GPIO_LOWPWR S5P_PMUREG(0x1220)
#define S5P_PAD_RETENTION_UART_LOWPWR S5P_PMUREG(0x1224)
#define S5P_PAD_RETENTION_MMCA_LOWPWR S5P_PMUREG(0x1228)
#define S5P_PAD_RETENTION_MMCB_LOWPWR S5P_PMUREG(0x122C)
#define S5P_PAD_RETENTION_EBIA_LOWPWR S5P_PMUREG(0x1230)
#define S5P_PAD_RETENTION_EBIB_LOWPWR S5P_PMUREG(0x1234)
#define S5P_PAD_RETENTION_ISOLATION_LOWPWR S5P_PMUREG(0x1240)
#define S5P_PAD_RETENTION_ALV_SEL_LOWPWR S5P_PMUREG(0x1260)
#define S5P_XUSBXTI_LOWPWR S5P_PMUREG(0x1280)
#define S5P_XXTI_LOWPWR S5P_PMUREG(0x1284)
#define S5P_EXT_REGULATOR_LOWPWR S5P_PMUREG(0x12C0)
#define S5P_GPIO_MODE_LOWPWR S5P_PMUREG(0x1300)
#define S5P_GPIO_MODE_MAUDIO_LOWPWR S5P_PMUREG(0x1340)
#define S5P_CAM_LOWPWR S5P_PMUREG(0x1380)
#define S5P_TV_LOWPWR S5P_PMUREG(0x1384)
#define S5P_MFC_LOWPWR S5P_PMUREG(0x1388)
#define S5P_G3D_LOWPWR S5P_PMUREG(0x138C)
#define S5P_LCD0_LOWPWR S5P_PMUREG(0x1390)
#define S5P_MAUDIO_LOWPWR S5P_PMUREG(0x1398)
#define S5P_GPS_LOWPWR S5P_PMUREG(0x139C)
#define S5P_GPS_ALIVE_LOWPWR S5P_PMUREG(0x13A0)
#define S5P_ARM_CORE0_LOWPWR 0x1000
#define S5P_DIS_IRQ_CORE0 0x1004
#define S5P_DIS_IRQ_CENTRAL0 0x1008
#define S5P_ARM_CORE1_LOWPWR 0x1010
#define S5P_DIS_IRQ_CORE1 0x1014
#define S5P_DIS_IRQ_CENTRAL1 0x1018
#define S5P_ARM_COMMON_LOWPWR 0x1080
#define S5P_L2_0_LOWPWR 0x10C0
#define S5P_L2_1_LOWPWR 0x10C4
#define S5P_CMU_ACLKSTOP_LOWPWR 0x1100
#define S5P_CMU_SCLKSTOP_LOWPWR 0x1104
#define S5P_CMU_RESET_LOWPWR 0x110C
#define S5P_APLL_SYSCLK_LOWPWR 0x1120
#define S5P_MPLL_SYSCLK_LOWPWR 0x1124
#define S5P_VPLL_SYSCLK_LOWPWR 0x1128
#define S5P_EPLL_SYSCLK_LOWPWR 0x112C
#define S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR 0x1138
#define S5P_CMU_RESET_GPSALIVE_LOWPWR 0x113C
#define S5P_CMU_CLKSTOP_CAM_LOWPWR 0x1140
#define S5P_CMU_CLKSTOP_TV_LOWPWR 0x1144
#define S5P_CMU_CLKSTOP_MFC_LOWPWR 0x1148
#define S5P_CMU_CLKSTOP_G3D_LOWPWR 0x114C
#define S5P_CMU_CLKSTOP_LCD0_LOWPWR 0x1150
#define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR 0x1158
#define S5P_CMU_CLKSTOP_GPS_LOWPWR 0x115C
#define S5P_CMU_RESET_CAM_LOWPWR 0x1160
#define S5P_CMU_RESET_TV_LOWPWR 0x1164
#define S5P_CMU_RESET_MFC_LOWPWR 0x1168
#define S5P_CMU_RESET_G3D_LOWPWR 0x116C
#define S5P_CMU_RESET_LCD0_LOWPWR 0x1170
#define S5P_CMU_RESET_MAUDIO_LOWPWR 0x1178
#define S5P_CMU_RESET_GPS_LOWPWR 0x117C
#define S5P_TOP_BUS_LOWPWR 0x1180
#define S5P_TOP_RETENTION_LOWPWR 0x1184
#define S5P_TOP_PWR_LOWPWR 0x1188
#define S5P_LOGIC_RESET_LOWPWR 0x11A0
#define S5P_ONENAND_MEM_LOWPWR 0x11C0
#define S5P_G2D_ACP_MEM_LOWPWR 0x11C8
#define S5P_USBOTG_MEM_LOWPWR 0x11CC
#define S5P_HSMMC_MEM_LOWPWR 0x11D0
#define S5P_CSSYS_MEM_LOWPWR 0x11D4
#define S5P_SECSS_MEM_LOWPWR 0x11D8
#define S5P_PAD_RETENTION_DRAM_LOWPWR 0x1200
#define S5P_PAD_RETENTION_MAUDIO_LOWPWR 0x1204
#define S5P_PAD_RETENTION_GPIO_LOWPWR 0x1220
#define S5P_PAD_RETENTION_UART_LOWPWR 0x1224
#define S5P_PAD_RETENTION_MMCA_LOWPWR 0x1228
#define S5P_PAD_RETENTION_MMCB_LOWPWR 0x122C
#define S5P_PAD_RETENTION_EBIA_LOWPWR 0x1230
#define S5P_PAD_RETENTION_EBIB_LOWPWR 0x1234
#define S5P_PAD_RETENTION_ISOLATION_LOWPWR 0x1240
#define S5P_PAD_RETENTION_ALV_SEL_LOWPWR 0x1260
#define S5P_XUSBXTI_LOWPWR 0x1280
#define S5P_XXTI_LOWPWR 0x1284
#define S5P_EXT_REGULATOR_LOWPWR 0x12C0
#define S5P_GPIO_MODE_LOWPWR 0x1300
#define S5P_GPIO_MODE_MAUDIO_LOWPWR 0x1340
#define S5P_CAM_LOWPWR 0x1380
#define S5P_TV_LOWPWR 0x1384
#define S5P_MFC_LOWPWR 0x1388
#define S5P_G3D_LOWPWR 0x138C
#define S5P_LCD0_LOWPWR 0x1390
#define S5P_MAUDIO_LOWPWR 0x1398
#define S5P_GPS_LOWPWR 0x139C
#define S5P_GPS_ALIVE_LOWPWR 0x13A0
#define EXYNOS_ARM_CORE0_CONFIGURATION S5P_PMUREG(0x2000)
#define EXYNOS_ARM_CORE0_CONFIGURATION 0x2000
#define EXYNOS_ARM_CORE_CONFIGURATION(_nr) \
(EXYNOS_ARM_CORE0_CONFIGURATION + (0x80 * (_nr)))
#define EXYNOS_ARM_CORE_STATUS(_nr) \
(EXYNOS_ARM_CORE_CONFIGURATION(_nr) + 0x4)
#define EXYNOS_ARM_COMMON_CONFIGURATION S5P_PMUREG(0x2500)
#define EXYNOS_ARM_COMMON_CONFIGURATION 0x2500
#define EXYNOS_COMMON_CONFIGURATION(_nr) \
(EXYNOS_ARM_COMMON_CONFIGURATION + (0x80 * (_nr)))
#define EXYNOS_COMMON_STATUS(_nr) \
(EXYNOS_COMMON_CONFIGURATION(_nr) + 0x4)
#define EXYNOS_COMMON_OPTION(_nr) \
(EXYNOS_COMMON_CONFIGURATION(_nr) + 0x8)
#define S5P_PAD_RET_MAUDIO_OPTION S5P_PMUREG(0x3028)
#define S5P_PAD_RET_GPIO_OPTION S5P_PMUREG(0x3108)
#define S5P_PAD_RET_UART_OPTION S5P_PMUREG(0x3128)
#define S5P_PAD_RET_MMCA_OPTION S5P_PMUREG(0x3148)
#define S5P_PAD_RET_MMCB_OPTION S5P_PMUREG(0x3168)
#define S5P_PAD_RET_EBIA_OPTION S5P_PMUREG(0x3188)
#define S5P_PAD_RET_EBIB_OPTION S5P_PMUREG(0x31A8)
#define S5P_PAD_RET_MAUDIO_OPTION 0x3028
#define S5P_PAD_RET_GPIO_OPTION 0x3108
#define S5P_PAD_RET_UART_OPTION 0x3128
#define S5P_PAD_RET_MMCA_OPTION 0x3148
#define S5P_PAD_RET_MMCB_OPTION 0x3168
#define S5P_PAD_RET_EBIA_OPTION 0x3188
#define S5P_PAD_RET_EBIB_OPTION 0x31A8
#define S5P_CORE_LOCAL_PWR_EN 0x3
/* Only for EXYNOS4210 */
#define S5P_CMU_CLKSTOP_LCD1_LOWPWR S5P_PMUREG(0x1154)
#define S5P_CMU_RESET_LCD1_LOWPWR S5P_PMUREG(0x1174)
#define S5P_MODIMIF_MEM_LOWPWR S5P_PMUREG(0x11C4)
#define S5P_PCIE_MEM_LOWPWR S5P_PMUREG(0x11E0)
#define S5P_SATA_MEM_LOWPWR S5P_PMUREG(0x11E4)
#define S5P_LCD1_LOWPWR S5P_PMUREG(0x1394)
#define S5P_CMU_CLKSTOP_LCD1_LOWPWR 0x1154
#define S5P_CMU_RESET_LCD1_LOWPWR 0x1174
#define S5P_MODIMIF_MEM_LOWPWR 0x11C4
#define S5P_PCIE_MEM_LOWPWR 0x11E0
#define S5P_SATA_MEM_LOWPWR 0x11E4
#define S5P_LCD1_LOWPWR 0x1394
/* Only for EXYNOS4x12 */
#define S5P_ISP_ARM_LOWPWR S5P_PMUREG(0x1050)
#define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR S5P_PMUREG(0x1054)
#define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR S5P_PMUREG(0x1058)
#define S5P_CMU_ACLKSTOP_COREBLK_LOWPWR S5P_PMUREG(0x1110)
#define S5P_CMU_SCLKSTOP_COREBLK_LOWPWR S5P_PMUREG(0x1114)
#define S5P_CMU_RESET_COREBLK_LOWPWR S5P_PMUREG(0x111C)
#define S5P_MPLLUSER_SYSCLK_LOWPWR S5P_PMUREG(0x1130)
#define S5P_CMU_CLKSTOP_ISP_LOWPWR S5P_PMUREG(0x1154)
#define S5P_CMU_RESET_ISP_LOWPWR S5P_PMUREG(0x1174)
#define S5P_TOP_BUS_COREBLK_LOWPWR S5P_PMUREG(0x1190)
#define S5P_TOP_RETENTION_COREBLK_LOWPWR S5P_PMUREG(0x1194)
#define S5P_TOP_PWR_COREBLK_LOWPWR S5P_PMUREG(0x1198)
#define S5P_OSCCLK_GATE_LOWPWR S5P_PMUREG(0x11A4)
#define S5P_LOGIC_RESET_COREBLK_LOWPWR S5P_PMUREG(0x11B0)
#define S5P_OSCCLK_GATE_COREBLK_LOWPWR S5P_PMUREG(0x11B4)
#define S5P_HSI_MEM_LOWPWR S5P_PMUREG(0x11C4)
#define S5P_ROTATOR_MEM_LOWPWR S5P_PMUREG(0x11DC)
#define S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR S5P_PMUREG(0x123C)
#define S5P_PAD_ISOLATION_COREBLK_LOWPWR S5P_PMUREG(0x1250)
#define S5P_GPIO_MODE_COREBLK_LOWPWR S5P_PMUREG(0x1320)
#define S5P_TOP_ASB_RESET_LOWPWR S5P_PMUREG(0x1344)
#define S5P_TOP_ASB_ISOLATION_LOWPWR S5P_PMUREG(0x1348)
#define S5P_ISP_LOWPWR S5P_PMUREG(0x1394)
#define S5P_DRAM_FREQ_DOWN_LOWPWR S5P_PMUREG(0x13B0)
#define S5P_DDRPHY_DLLOFF_LOWPWR S5P_PMUREG(0x13B4)
#define S5P_CMU_SYSCLK_ISP_LOWPWR S5P_PMUREG(0x13B8)
#define S5P_CMU_SYSCLK_GPS_LOWPWR S5P_PMUREG(0x13BC)
#define S5P_LPDDR_PHY_DLL_LOCK_LOWPWR S5P_PMUREG(0x13C0)
#define S5P_ISP_ARM_LOWPWR 0x1050
#define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR 0x1054
#define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR 0x1058
#define S5P_CMU_ACLKSTOP_COREBLK_LOWPWR 0x1110
#define S5P_CMU_SCLKSTOP_COREBLK_LOWPWR 0x1114
#define S5P_CMU_RESET_COREBLK_LOWPWR 0x111C
#define S5P_MPLLUSER_SYSCLK_LOWPWR 0x1130
#define S5P_CMU_CLKSTOP_ISP_LOWPWR 0x1154
#define S5P_CMU_RESET_ISP_LOWPWR 0x1174
#define S5P_TOP_BUS_COREBLK_LOWPWR 0x1190
#define S5P_TOP_RETENTION_COREBLK_LOWPWR 0x1194
#define S5P_TOP_PWR_COREBLK_LOWPWR 0x1198
#define S5P_OSCCLK_GATE_LOWPWR 0x11A4
#define S5P_LOGIC_RESET_COREBLK_LOWPWR 0x11B0
#define S5P_OSCCLK_GATE_COREBLK_LOWPWR 0x11B4
#define S5P_HSI_MEM_LOWPWR 0x11C4
#define S5P_ROTATOR_MEM_LOWPWR 0x11DC
#define S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR 0x123C
#define S5P_PAD_ISOLATION_COREBLK_LOWPWR 0x1250
#define S5P_GPIO_MODE_COREBLK_LOWPWR 0x1320
#define S5P_TOP_ASB_RESET_LOWPWR 0x1344
#define S5P_TOP_ASB_ISOLATION_LOWPWR 0x1348
#define S5P_ISP_LOWPWR 0x1394
#define S5P_DRAM_FREQ_DOWN_LOWPWR 0x13B0
#define S5P_DDRPHY_DLLOFF_LOWPWR 0x13B4
#define S5P_CMU_SYSCLK_ISP_LOWPWR 0x13B8
#define S5P_CMU_SYSCLK_GPS_LOWPWR 0x13BC
#define S5P_LPDDR_PHY_DLL_LOCK_LOWPWR 0x13C0
#define S5P_ARM_L2_0_OPTION S5P_PMUREG(0x2608)
#define S5P_ARM_L2_1_OPTION S5P_PMUREG(0x2628)
#define S5P_ONENAND_MEM_OPTION S5P_PMUREG(0x2E08)
#define S5P_HSI_MEM_OPTION S5P_PMUREG(0x2E28)
#define S5P_G2D_ACP_MEM_OPTION S5P_PMUREG(0x2E48)
#define S5P_USBOTG_MEM_OPTION S5P_PMUREG(0x2E68)
#define S5P_HSMMC_MEM_OPTION S5P_PMUREG(0x2E88)
#define S5P_CSSYS_MEM_OPTION S5P_PMUREG(0x2EA8)
#define S5P_SECSS_MEM_OPTION S5P_PMUREG(0x2EC8)
#define S5P_ROTATOR_MEM_OPTION S5P_PMUREG(0x2F48)
#define S5P_ARM_L2_0_OPTION 0x2608
#define S5P_ARM_L2_1_OPTION 0x2628
#define S5P_ONENAND_MEM_OPTION 0x2E08
#define S5P_HSI_MEM_OPTION 0x2E28
#define S5P_G2D_ACP_MEM_OPTION 0x2E48
#define S5P_USBOTG_MEM_OPTION 0x2E68
#define S5P_HSMMC_MEM_OPTION 0x2E88
#define S5P_CSSYS_MEM_OPTION 0x2EA8
#define S5P_SECSS_MEM_OPTION 0x2EC8
#define S5P_ROTATOR_MEM_OPTION 0x2F48
/* Only for EXYNOS4412 */
#define S5P_ARM_CORE2_LOWPWR S5P_PMUREG(0x1020)
#define S5P_DIS_IRQ_CORE2 S5P_PMUREG(0x1024)
#define S5P_DIS_IRQ_CENTRAL2 S5P_PMUREG(0x1028)
#define S5P_ARM_CORE3_LOWPWR S5P_PMUREG(0x1030)
#define S5P_DIS_IRQ_CORE3 S5P_PMUREG(0x1034)
#define S5P_DIS_IRQ_CENTRAL3 S5P_PMUREG(0x1038)
#define S5P_ARM_CORE2_LOWPWR 0x1020
#define S5P_DIS_IRQ_CORE2 0x1024
#define S5P_DIS_IRQ_CENTRAL2 0x1028
#define S5P_ARM_CORE3_LOWPWR 0x1030
#define S5P_DIS_IRQ_CORE3 0x1034
#define S5P_DIS_IRQ_CENTRAL3 0x1038
/* For EXYNOS5 */
#define EXYNOS5_AUTO_WDTRESET_DISABLE S5P_PMUREG(0x0408)
#define EXYNOS5_MASK_WDTRESET_REQUEST S5P_PMUREG(0x040C)
#define EXYNOS5_AUTO_WDTRESET_DISABLE 0x0408
#define EXYNOS5_MASK_WDTRESET_REQUEST 0x040C
#define EXYNOS5_SYS_WDTRESET (1 << 20)
#define EXYNOS5_ARM_CORE0_SYS_PWR_REG S5P_PMUREG(0x1000)
#define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1004)
#define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1008)
#define EXYNOS5_ARM_CORE1_SYS_PWR_REG S5P_PMUREG(0x1010)
#define EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1014)
#define EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1018)
#define EXYNOS5_FSYS_ARM_SYS_PWR_REG S5P_PMUREG(0x1040)
#define EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1048)
#define EXYNOS5_ISP_ARM_SYS_PWR_REG S5P_PMUREG(0x1050)
#define EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1054)
#define EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1058)
#define EXYNOS5_ARM_COMMON_SYS_PWR_REG S5P_PMUREG(0x1080)
#define EXYNOS5_ARM_L2_SYS_PWR_REG S5P_PMUREG(0x10C0)
#define EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG S5P_PMUREG(0x1100)
#define EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG S5P_PMUREG(0x1104)
#define EXYNOS5_CMU_RESET_SYS_PWR_REG S5P_PMUREG(0x110C)
#define EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1120)
#define EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1124)
#define EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x112C)
#define EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG S5P_PMUREG(0x1130)
#define EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG S5P_PMUREG(0x1134)
#define EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG S5P_PMUREG(0x1138)
#define EXYNOS5_APLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1140)
#define EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1144)
#define EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1148)
#define EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x114C)
#define EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1150)
#define EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1154)
#define EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1164)
#define EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1170)
#define EXYNOS5_TOP_BUS_SYS_PWR_REG S5P_PMUREG(0x1180)
#define EXYNOS5_TOP_RETENTION_SYS_PWR_REG S5P_PMUREG(0x1184)
#define EXYNOS5_TOP_PWR_SYS_PWR_REG S5P_PMUREG(0x1188)
#define EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1190)
#define EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1194)
#define EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1198)
#define EXYNOS5_LOGIC_RESET_SYS_PWR_REG S5P_PMUREG(0x11A0)
#define EXYNOS5_OSCCLK_GATE_SYS_PWR_REG S5P_PMUREG(0x11A4)
#define EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x11B0)
#define EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x11B4)
#define EXYNOS5_USBOTG_MEM_SYS_PWR_REG S5P_PMUREG(0x11C0)
#define EXYNOS5_G2D_MEM_SYS_PWR_REG S5P_PMUREG(0x11C8)
#define EXYNOS5_USBDRD_MEM_SYS_PWR_REG S5P_PMUREG(0x11CC)
#define EXYNOS5_SDMMC_MEM_SYS_PWR_REG S5P_PMUREG(0x11D0)
#define EXYNOS5_CSSYS_MEM_SYS_PWR_REG S5P_PMUREG(0x11D4)
#define EXYNOS5_SECSS_MEM_SYS_PWR_REG S5P_PMUREG(0x11D8)
#define EXYNOS5_ROTATOR_MEM_SYS_PWR_REG S5P_PMUREG(0x11DC)
#define EXYNOS5_INTRAM_MEM_SYS_PWR_REG S5P_PMUREG(0x11E0)
#define EXYNOS5_INTROM_MEM_SYS_PWR_REG S5P_PMUREG(0x11E4)
#define EXYNOS5_JPEG_MEM_SYS_PWR_REG S5P_PMUREG(0x11E8)
#define EXYNOS5_HSI_MEM_SYS_PWR_REG S5P_PMUREG(0x11EC)
#define EXYNOS5_MCUIOP_MEM_SYS_PWR_REG S5P_PMUREG(0x11F4)
#define EXYNOS5_SATA_MEM_SYS_PWR_REG S5P_PMUREG(0x11FC)
#define EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG S5P_PMUREG(0x1200)
#define EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG S5P_PMUREG(0x1204)
#define EXYNOS5_PAD_RETENTION_EFNAND_SYS_PWR_REG S5P_PMUREG(0x1208)
#define EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG S5P_PMUREG(0x1220)
#define EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG S5P_PMUREG(0x1224)
#define EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG S5P_PMUREG(0x1228)
#define EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG S5P_PMUREG(0x122C)
#define EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG S5P_PMUREG(0x1230)
#define EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG S5P_PMUREG(0x1234)
#define EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG S5P_PMUREG(0x1238)
#define EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x123C)
#define EXYNOS5_PAD_ISOLATION_SYS_PWR_REG S5P_PMUREG(0x1240)
#define EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1250)
#define EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG S5P_PMUREG(0x1260)
#define EXYNOS5_XUSBXTI_SYS_PWR_REG S5P_PMUREG(0x1280)
#define EXYNOS5_XXTI_SYS_PWR_REG S5P_PMUREG(0x1284)
#define EXYNOS5_EXT_REGULATOR_SYS_PWR_REG S5P_PMUREG(0x12C0)
#define EXYNOS5_GPIO_MODE_SYS_PWR_REG S5P_PMUREG(0x1300)
#define EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1320)
#define EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG S5P_PMUREG(0x1340)
#define EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG S5P_PMUREG(0x1344)
#define EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG S5P_PMUREG(0x1348)
#define EXYNOS5_GSCL_SYS_PWR_REG S5P_PMUREG(0x1400)
#define EXYNOS5_ISP_SYS_PWR_REG S5P_PMUREG(0x1404)
#define EXYNOS5_MFC_SYS_PWR_REG S5P_PMUREG(0x1408)
#define EXYNOS5_G3D_SYS_PWR_REG S5P_PMUREG(0x140C)
#define EXYNOS5_DISP1_SYS_PWR_REG S5P_PMUREG(0x1414)
#define EXYNOS5_MAU_SYS_PWR_REG S5P_PMUREG(0x1418)
#define EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG S5P_PMUREG(0x1480)
#define EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG S5P_PMUREG(0x1484)
#define EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG S5P_PMUREG(0x1488)
#define EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG S5P_PMUREG(0x148C)
#define EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG S5P_PMUREG(0x1494)
#define EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG S5P_PMUREG(0x1498)
#define EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG S5P_PMUREG(0x14C0)
#define EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG S5P_PMUREG(0x14C4)
#define EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG S5P_PMUREG(0x14C8)
#define EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG S5P_PMUREG(0x14CC)
#define EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG S5P_PMUREG(0x14D4)
#define EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG S5P_PMUREG(0x14D8)
#define EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG S5P_PMUREG(0x1580)
#define EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG S5P_PMUREG(0x1584)
#define EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG S5P_PMUREG(0x1588)
#define EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG S5P_PMUREG(0x158C)
#define EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG S5P_PMUREG(0x1594)
#define EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG S5P_PMUREG(0x1598)
#define EXYNOS5_ARM_CORE0_SYS_PWR_REG 0x1000
#define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG 0x1004
#define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG 0x1008
#define EXYNOS5_ARM_CORE1_SYS_PWR_REG 0x1010
#define EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG 0x1014
#define EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG 0x1018
#define EXYNOS5_FSYS_ARM_SYS_PWR_REG 0x1040
#define EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG 0x1048
#define EXYNOS5_ISP_ARM_SYS_PWR_REG 0x1050
#define EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG 0x1054
#define EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG 0x1058
#define EXYNOS5_ARM_COMMON_SYS_PWR_REG 0x1080
#define EXYNOS5_ARM_L2_SYS_PWR_REG 0x10C0
#define EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG 0x1100
#define EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG 0x1104
#define EXYNOS5_CMU_RESET_SYS_PWR_REG 0x110C
#define EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG 0x1120
#define EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG 0x1124
#define EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG 0x112C
#define EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG 0x1130
#define EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG 0x1134
#define EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG 0x1138
#define EXYNOS5_APLL_SYSCLK_SYS_PWR_REG 0x1140
#define EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG 0x1144
#define EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG 0x1148
#define EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG 0x114C
#define EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG 0x1150
#define EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG 0x1154
#define EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG 0x1164
#define EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG 0x1170
#define EXYNOS5_TOP_BUS_SYS_PWR_REG 0x1180
#define EXYNOS5_TOP_RETENTION_SYS_PWR_REG 0x1184
#define EXYNOS5_TOP_PWR_SYS_PWR_REG 0x1188
#define EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG 0x1190
#define EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG 0x1194
#define EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG 0x1198
#define EXYNOS5_LOGIC_RESET_SYS_PWR_REG 0x11A0
#define EXYNOS5_OSCCLK_GATE_SYS_PWR_REG 0x11A4
#define EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG 0x11B0
#define EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG 0x11B4
#define EXYNOS5_USBOTG_MEM_SYS_PWR_REG 0x11C0
#define EXYNOS5_G2D_MEM_SYS_PWR_REG 0x11C8
#define EXYNOS5_USBDRD_MEM_SYS_PWR_REG 0x11CC
#define EXYNOS5_SDMMC_MEM_SYS_PWR_REG 0x11D0
#define EXYNOS5_CSSYS_MEM_SYS_PWR_REG 0x11D4
#define EXYNOS5_SECSS_MEM_SYS_PWR_REG 0x11D8
#define EXYNOS5_ROTATOR_MEM_SYS_PWR_REG 0x11DC
#define EXYNOS5_INTRAM_MEM_SYS_PWR_REG 0x11E0
#define EXYNOS5_INTROM_MEM_SYS_PWR_REG 0x11E4
#define EXYNOS5_JPEG_MEM_SYS_PWR_REG 0x11E8
#define EXYNOS5_HSI_MEM_SYS_PWR_REG 0x11EC
#define EXYNOS5_MCUIOP_MEM_SYS_PWR_REG 0x11F4
#define EXYNOS5_SATA_MEM_SYS_PWR_REG 0x11FC
#define EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG 0x1200
#define EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG 0x1204
#define EXYNOS5_PAD_RETENTION_EFNAND_SYS_PWR_REG 0x1208
#define EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG 0x1220
#define EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG 0x1224
#define EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG 0x1228
#define EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG 0x122C
#define EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG 0x1230
#define EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG 0x1234
#define EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG 0x1238
#define EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG 0x123C
#define EXYNOS5_PAD_ISOLATION_SYS_PWR_REG 0x1240
#define EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG 0x1250
#define EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG 0x1260
#define EXYNOS5_XUSBXTI_SYS_PWR_REG 0x1280
#define EXYNOS5_XXTI_SYS_PWR_REG 0x1284
#define EXYNOS5_EXT_REGULATOR_SYS_PWR_REG 0x12C0
#define EXYNOS5_GPIO_MODE_SYS_PWR_REG 0x1300
#define EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG 0x1320
#define EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG 0x1340
#define EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG 0x1344
#define EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG 0x1348
#define EXYNOS5_GSCL_SYS_PWR_REG 0x1400
#define EXYNOS5_ISP_SYS_PWR_REG 0x1404
#define EXYNOS5_MFC_SYS_PWR_REG 0x1408
#define EXYNOS5_G3D_SYS_PWR_REG 0x140C
#define EXYNOS5_DISP1_SYS_PWR_REG 0x1414
#define EXYNOS5_MAU_SYS_PWR_REG 0x1418
#define EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG 0x1480
#define EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG 0x1484
#define EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG 0x1488
#define EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG 0x148C
#define EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG 0x1494
#define EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG 0x1498
#define EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG 0x14C0
#define EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG 0x14C4
#define EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG 0x14C8
#define EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG 0x14CC
#define EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG 0x14D4
#define EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG 0x14D8
#define EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG 0x1580
#define EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG 0x1584
#define EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG 0x1588
#define EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG 0x158C
#define EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG 0x1594
#define EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG 0x1598
#define EXYNOS5_ARM_CORE0_OPTION S5P_PMUREG(0x2008)
#define EXYNOS5_ARM_CORE1_OPTION S5P_PMUREG(0x2088)
#define EXYNOS5_FSYS_ARM_OPTION S5P_PMUREG(0x2208)
#define EXYNOS5_ISP_ARM_OPTION S5P_PMUREG(0x2288)
#define EXYNOS5_ARM_COMMON_OPTION S5P_PMUREG(0x2408)
#define EXYNOS5_ARM_L2_OPTION S5P_PMUREG(0x2608)
#define EXYNOS5_TOP_PWR_OPTION S5P_PMUREG(0x2C48)
#define EXYNOS5_TOP_PWR_SYSMEM_OPTION S5P_PMUREG(0x2CC8)
#define EXYNOS5_JPEG_MEM_OPTION S5P_PMUREG(0x2F48)
#define EXYNOS5_GSCL_OPTION S5P_PMUREG(0x4008)
#define EXYNOS5_ISP_OPTION S5P_PMUREG(0x4028)
#define EXYNOS5_MFC_OPTION S5P_PMUREG(0x4048)
#define EXYNOS5_G3D_OPTION S5P_PMUREG(0x4068)
#define EXYNOS5_DISP1_OPTION S5P_PMUREG(0x40A8)
#define EXYNOS5_MAU_OPTION S5P_PMUREG(0x40C8)
#define EXYNOS5_ARM_CORE0_OPTION 0x2008
#define EXYNOS5_ARM_CORE1_OPTION 0x2088
#define EXYNOS5_FSYS_ARM_OPTION 0x2208
#define EXYNOS5_ISP_ARM_OPTION 0x2288
#define EXYNOS5_ARM_COMMON_OPTION 0x2408
#define EXYNOS5_ARM_L2_OPTION 0x2608
#define EXYNOS5_TOP_PWR_OPTION 0x2C48
#define EXYNOS5_TOP_PWR_SYSMEM_OPTION 0x2CC8
#define EXYNOS5_JPEG_MEM_OPTION 0x2F48
#define EXYNOS5_GSCL_OPTION 0x4008
#define EXYNOS5_ISP_OPTION 0x4028
#define EXYNOS5_MFC_OPTION 0x4048
#define EXYNOS5_G3D_OPTION 0x4068
#define EXYNOS5_DISP1_OPTION 0x40A8
#define EXYNOS5_MAU_OPTION 0x40C8
#define EXYNOS5_USE_SC_FEEDBACK (1 << 1)
#define EXYNOS5_USE_SC_COUNTER (1 << 0)
@ -319,4 +317,13 @@
#define EXYNOS5420_SWRESET_KFC_SEL 0x3
#include <asm/cputype.h>
#define MAX_CPUS_IN_CLUSTER 4
static inline unsigned int exynos_pmu_cpunr(unsigned int mpidr)
{
return ((MPIDR_AFFINITY_LEVEL(mpidr, 1) * MAX_CPUS_IN_CLUSTER)
+ MPIDR_AFFINITY_LEVEL(mpidr, 0));
}
#endif /* __ASM_ARCH_REGS_PMU_H */

30
arch/arm/mach-hisi/Kconfig
View File

@ -1,12 +1,36 @@
config ARCH_HI3xxx
bool "Hisilicon Hi36xx/Hi37xx family" if ARCH_MULTI_V7
config ARCH_HISI
bool "Hisilicon SoC Support"
depends on ARCH_MULTIPLATFORM
select ARM_AMBA
select ARM_GIC
select ARM_TIMER_SP804
select POWER_RESET
select POWER_RESET_HISI
select POWER_SUPPLY
if ARCH_HISI
menu "Hisilicon platform type"
config ARCH_HI3xxx
bool "Hisilicon Hi36xx family" if ARCH_MULTI_V7
select CACHE_L2X0
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
select PINCTRL
select PINCTRL_SINGLE
help
Support for Hisilicon Hi36xx/Hi37xx processor family
Support for Hisilicon Hi36xx SoC family
config ARCH_HIX5HD2
bool "Hisilicon X5HD2 family" if ARCH_MULTI_V7
select CACHE_L2X0
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
select PINCTRL
select PINCTRL_SINGLE
help
Support for Hisilicon HIX5HD2 SoC family
endmenu
endif

2
arch/arm/mach-hisi/Makefile
View File

@ -3,4 +3,4 @@
#
obj-y += hisilicon.o
obj-$(CONFIG_SMP) += platsmp.o hotplug.o
obj-$(CONFIG_SMP) += platsmp.o hotplug.o headsmp.o

5
arch/arm/mach-hisi/core.h
View File

@ -12,4 +12,9 @@ extern void hi3xxx_cpu_die(unsigned int cpu);
extern int hi3xxx_cpu_kill(unsigned int cpu);
extern void hi3xxx_set_cpu(int cpu, bool enable);
extern void hix5hd2_secondary_startup(void);
extern struct smp_operations hix5hd2_smp_ops;
extern void hix5hd2_set_cpu(int cpu, bool enable);
extern void hix5hd2_cpu_die(unsigned int cpu);
#endif

16
arch/arm/mach-hisi/headsmp.S Normal file
View File

@ -0,0 +1,16 @@
/*
* Copyright (c) 2014 Hisilicon Limited.
* Copyright (c) 2014 Linaro Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/linkage.h>
#include <linux/init.h>
__CPUINIT
ENTRY(hix5hd2_secondary_startup)
bl v7_invalidate_l1
b secondary_startup

43
arch/arm/mach-hisi/hisilicon.c
View File

@ -14,16 +14,10 @@
#include <linux/clk-provider.h>
#include <linux/clocksource.h>
#include <linux/irqchip.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <asm/proc-fns.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include "core.h"
#define HI3620_SYSCTRL_PHYS_BASE 0xfc802000
#define HI3620_SYSCTRL_VIRT_BASE 0xfe802000
@ -51,32 +45,6 @@ static void __init hi3620_map_io(void)
iotable_init(hi3620_io_desc, ARRAY_SIZE(hi3620_io_desc));
}
static void hi3xxx_restart(enum reboot_mode mode, const char *cmd)
{
struct device_node *np;
void __iomem *base;
int offset;
np = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl");
if (!np) {
pr_err("failed to find hisilicon,sysctrl node\n");
return;
}
base = of_iomap(np, 0);
if (!base) {
pr_err("failed to map address in hisilicon,sysctrl node\n");
return;
}
if (of_property_read_u32(np, "reboot-offset", &offset) < 0) {
pr_err("failed to find reboot-offset property\n");
return;
}
writel_relaxed(0xdeadbeef, base + offset);
while (1)
cpu_do_idle();
}
static const char *hi3xxx_compat[] __initconst = {
"hisilicon,hi3620-hi4511",
NULL,
@ -85,6 +53,13 @@ static const char *hi3xxx_compat[] __initconst = {
DT_MACHINE_START(HI3620, "Hisilicon Hi3620 (Flattened Device Tree)")
.map_io = hi3620_map_io,
.dt_compat = hi3xxx_compat,
.smp = smp_ops(hi3xxx_smp_ops),
.restart = hi3xxx_restart,
MACHINE_END
static const char *hix5hd2_compat[] __initconst = {
"hisilicon,hix5hd2",
NULL,
};
DT_MACHINE_START(HIX5HD2_DT, "Hisilicon HIX5HD2 (Flattened Device Tree)")
.dt_compat = hix5hd2_compat,
MACHINE_END

58
arch/arm/mach-hisi/hotplug.c
View File

@ -57,6 +57,14 @@
#define CPU0_NEON_SRST_REQ_EN (1 << 4)
#define CPU0_SRST_REQ_EN (1 << 0)
#define HIX5HD2_PERI_CRG20 0x50
#define CRG20_CPU1_RESET (1 << 17)
#define HIX5HD2_PERI_PMC0 0x1000
#define PMC0_CPU1_WAIT_MTCOMS_ACK (1 << 8)
#define PMC0_CPU1_PMC_ENABLE (1 << 7)
#define PMC0_CPU1_POWERDOWN (1 << 3)
enum {
HI3620_CTRL,
ERROR_CTRL,
@ -157,6 +165,50 @@ void hi3xxx_set_cpu(int cpu, bool enable)
set_cpu_hi3620(cpu, enable);
}
static bool hix5hd2_hotplug_init(void)
{
struct device_node *np;
np = of_find_compatible_node(NULL, NULL, "hisilicon,cpuctrl");
if (np) {
ctrl_base = of_iomap(np, 0);
return true;
}
return false;
}
void hix5hd2_set_cpu(int cpu, bool enable)
{
u32 val = 0;
if (!ctrl_base)
if (!hix5hd2_hotplug_init())
BUG();
if (enable) {
/* power on cpu1 */
val = readl_relaxed(ctrl_base + HIX5HD2_PERI_PMC0);
val &= ~(PMC0_CPU1_WAIT_MTCOMS_ACK | PMC0_CPU1_POWERDOWN);
val |= PMC0_CPU1_PMC_ENABLE;
writel_relaxed(val, ctrl_base + HIX5HD2_PERI_PMC0);
/* unreset */
val = readl_relaxed(ctrl_base + HIX5HD2_PERI_CRG20);
val &= ~CRG20_CPU1_RESET;
writel_relaxed(val, ctrl_base + HIX5HD2_PERI_CRG20);
} else {
/* power down cpu1 */
val = readl_relaxed(ctrl_base + HIX5HD2_PERI_PMC0);
val |= PMC0_CPU1_PMC_ENABLE | PMC0_CPU1_POWERDOWN;
val &= ~PMC0_CPU1_WAIT_MTCOMS_ACK;
writel_relaxed(val, ctrl_base + HIX5HD2_PERI_PMC0);
/* reset */
val = readl_relaxed(ctrl_base + HIX5HD2_PERI_CRG20);
val |= CRG20_CPU1_RESET;
writel_relaxed(val, ctrl_base + HIX5HD2_PERI_CRG20);
}
}
static inline void cpu_enter_lowpower(void)
{
unsigned int v;
@ -199,4 +251,10 @@ int hi3xxx_cpu_kill(unsigned int cpu)
hi3xxx_set_cpu(cpu, false);
return 1;
}
void hix5hd2_cpu_die(unsigned int cpu)
{
flush_cache_all();
hix5hd2_set_cpu(cpu, false);
}
#endif

53
arch/arm/mach-hisi/platsmp.c
View File

@ -17,6 +17,8 @@
#include "core.h"
#define HIX5HD2_BOOT_ADDRESS 0xffff0000
static void __iomem *ctrl_base;
void hi3xxx_set_cpu_jump(int cpu, void *jump_addr)
@ -35,11 +37,9 @@ int hi3xxx_get_cpu_jump(int cpu)
return readl_relaxed(ctrl_base + ((cpu - 1) << 2));
}
static void __init hi3xxx_smp_prepare_cpus(unsigned int max_cpus)
static void __init hisi_enable_scu_a9(void)
{
struct device_node *np = NULL;
unsigned long base = 0;
u32 offset = 0;
void __iomem *scu_base = NULL;
if (scu_a9_has_base()) {
@ -52,6 +52,14 @@ static void __init hi3xxx_smp_prepare_cpus(unsigned int max_cpus)
scu_enable(scu_base);
iounmap(scu_base);
}
}
static void __init hi3xxx_smp_prepare_cpus(unsigned int max_cpus)
{
struct device_node *np = NULL;
u32 offset = 0;
hisi_enable_scu_a9();
if (!ctrl_base) {
np = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl");
if (!np) {
@ -87,3 +95,42 @@ struct smp_operations hi3xxx_smp_ops __initdata = {
.cpu_kill = hi3xxx_cpu_kill,
#endif
};
static void __init hix5hd2_smp_prepare_cpus(unsigned int max_cpus)
{
hisi_enable_scu_a9();
}
void hix5hd2_set_scu_boot_addr(phys_addr_t start_addr, phys_addr_t jump_addr)
{
void __iomem *virt;
virt = ioremap(start_addr, PAGE_SIZE);
writel_relaxed(0xe51ff004, virt); /* ldr pc, [rc, #-4] */
writel_relaxed(jump_addr, virt + 4); /* pc jump phy address */
iounmap(virt);
}
static int hix5hd2_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
phys_addr_t jumpaddr;
jumpaddr = virt_to_phys(hix5hd2_secondary_startup);
hix5hd2_set_scu_boot_addr(HIX5HD2_BOOT_ADDRESS, jumpaddr);
hix5hd2_set_cpu(cpu, true);
arch_send_wakeup_ipi_mask(cpumask_of(cpu));
return 0;
}
struct smp_operations hix5hd2_smp_ops __initdata = {
.smp_prepare_cpus = hix5hd2_smp_prepare_cpus,
.smp_boot_secondary = hix5hd2_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU
.cpu_die = hix5hd2_cpu_die,
#endif
};
CPU_METHOD_OF_DECLARE(hi3xxx_smp, "hisilicon,hi3620-smp", &hi3xxx_smp_ops);
CPU_METHOD_OF_DECLARE(hix5hd2_smp, "hisilicon,hix5hd2-smp", &hix5hd2_smp_ops);

59
arch/arm/mach-imx/Kconfig
View File

@ -64,18 +64,8 @@ config IMX_HAVE_IOMUX_V1
config ARCH_MXC_IOMUX_V3
bool
config ARCH_MX1
bool
config ARCH_MX25
bool
config MACH_MX27
bool
config SOC_IMX1
bool
select ARCH_MX1
select CPU_ARM920T
select IMX_HAVE_IOMUX_V1
select MXC_AVIC
@ -88,7 +78,6 @@ config SOC_IMX21
config SOC_IMX25
bool
select ARCH_MX25
select ARCH_MXC_IOMUX_V3
select CPU_ARM926T
select MXC_AVIC
@ -99,7 +88,6 @@ config SOC_IMX27
select ARCH_HAS_OPP
select CPU_ARM926T
select IMX_HAVE_IOMUX_V1
select MACH_MX27
select MXC_AVIC
select PINCTRL_IMX27
@ -118,18 +106,6 @@ config SOC_IMX35
select PINCTRL_IMX35
select SMP_ON_UP if SMP
config SOC_IMX5
bool
select ARCH_HAS_OPP
select ARCH_MXC_IOMUX_V3
select MXC_TZIC
config SOC_IMX51
bool
select HAVE_IMX_SRC
select PINCTRL_IMX51
select SOC_IMX5
if ARCH_MULTI_V4T
comment "MX1 platforms:"
@ -365,15 +341,6 @@ config MACH_IMX27_VISSTRIM_M10
This includes specific configurations for the board and its
peripherals.
config MACH_IMX27LITE
bool "LogicPD MX27 LITEKIT platform"
select IMX_HAVE_PLATFORM_IMX_SSI
select IMX_HAVE_PLATFORM_IMX_UART
select SOC_IMX27
help
Include support for MX27 LITEKIT platform. This includes specific
configurations for the board and its peripherals.
config MACH_PCA100
bool "Phytec phyCARD-s (pca100)"
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
@ -405,15 +372,6 @@ config MACH_MXT_TD60
Include support for i-MXT (aka td60) platform. This
includes specific configurations for the module and its peripherals.
config MACH_IMX27IPCAM
bool "IMX27 IPCAM platform"
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_UART
select SOC_IMX27
help
Include support for IMX27 IPCAM platform. This includes specific
configurations for the board and its peripherals.
config MACH_IMX27_DT
bool "Support i.MX27 platforms from device tree"
select SOC_IMX27
@ -699,24 +657,29 @@ if ARCH_MULTI_V7
comment "Device tree only"
config SOC_IMX5
bool
select ARCH_HAS_OPP
select HAVE_IMX_SRC
select MXC_TZIC
config SOC_IMX50
bool "i.MX50 support"
select HAVE_IMX_SRC
select PINCTRL_IMX50
select SOC_IMX5
help
This enables support for Freescale i.MX50 processor.
config MACH_IMX51_DT
config SOC_IMX51
bool "i.MX51 support"
select SOC_IMX51
select PINCTRL_IMX51
select SOC_IMX5
help
This enables support for Freescale i.MX51 processor
config SOC_IMX53
bool "i.MX53 support"
select HAVE_IMX_SRC
select PINCTRL_IMX53
select SOC_IMX5
@ -733,8 +696,6 @@ config SOC_IMX6
select HAVE_IMX_MMDC
select HAVE_IMX_SRC
select MFD_SYSCON
select PL310_ERRATA_588369 if CACHE_L2X0
select PL310_ERRATA_727915 if CACHE_L2X0
select PL310_ERRATA_769419 if CACHE_L2X0
config SOC_IMX6Q
@ -770,8 +731,6 @@ config SOC_VF610
select ARM_GIC
select PINCTRL_VF610
select VF_PIT_TIMER
select PL310_ERRATA_588369 if CACHE_L2X0
select PL310_ERRATA_727915 if CACHE_L2X0
select PL310_ERRATA_769419 if CACHE_L2X0
help

11
arch/arm/mach-imx/Makefile
View File

@ -12,7 +12,7 @@ obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clk-imx31.o iomux-imx31.o ehci-
obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clk-imx35.o ehci-imx35.o pm-imx3.o
imx5-pm-$(CONFIG_PM) += pm-imx5.o
obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o $(imx5-pm-y)
obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o clk-imx51-imx53.o $(imx5-pm-y)
obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \
clk-pfd.o clk-busy.o clk.o \
@ -31,6 +31,8 @@ ifeq ($(CONFIG_CPU_IDLE),y)
obj-$(CONFIG_SOC_IMX5) += cpuidle-imx5.o
obj-$(CONFIG_SOC_IMX6Q) += cpuidle-imx6q.o
obj-$(CONFIG_SOC_IMX6SL) += cpuidle-imx6sl.o
# i.MX6SX reuses i.MX6Q cpuidle driver
obj-$(CONFIG_SOC_IMX6SX) += cpuidle-imx6q.o
endif
ifdef CONFIG_SND_IMX_SOC
@ -38,9 +40,6 @@ obj-y += ssi-fiq.o
obj-y += ssi-fiq-ksym.o
endif
# Support for CMOS sensor interface
obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o
# i.MX1 based machines
obj-$(CONFIG_ARCH_MX1ADS) += mach-mx1ads.o
obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o
@ -60,13 +59,11 @@ obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o
obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o
obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o
obj-$(CONFIG_MACH_MX27_3DS) += mach-mx27_3ds.o
obj-$(CONFIG_MACH_IMX27LITE) += mach-imx27lite.o
obj-$(CONFIG_MACH_IMX27_VISSTRIM_M10) += mach-imx27_visstrim_m10.o
obj-$(CONFIG_MACH_CPUIMX27) += mach-cpuimx27.o
obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o
obj-$(CONFIG_MACH_PCA100) += mach-pca100.o
obj-$(CONFIG_MACH_MXT_TD60) += mach-mxt_td60.o
obj-$(CONFIG_MACH_IMX27IPCAM) += mach-imx27ipcam.o
obj-$(CONFIG_MACH_IMX27_DT) += imx27-dt.o
# i.MX31 based machines
@ -109,8 +106,8 @@ obj-$(CONFIG_SOC_IMX6) += suspend-imx6.o
endif
obj-$(CONFIG_SOC_IMX6) += pm-imx6.o
obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o
obj-$(CONFIG_SOC_IMX50) += mach-imx50.o
obj-$(CONFIG_SOC_IMX51) += mach-imx51.o
obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
obj-$(CONFIG_SOC_VF610) += clk-vf610.o mach-vf610.o

151
arch/arm/mach-imx/clk-imx1.c
View File

@ -15,100 +15,103 @@
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/clkdev.h>
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <dt-bindings/clock/imx1-clock.h>
#include "clk.h"
#include "common.h"
#include "hardware.h"
/* CCM register addresses */
#define IO_ADDR_CCM(off) (MX1_IO_ADDRESS(MX1_CCM_BASE_ADDR + (off)))
#define CCM_CSCR IO_ADDR_CCM(0x0)
#define CCM_MPCTL0 IO_ADDR_CCM(0x4)
#define CCM_SPCTL0 IO_ADDR_CCM(0xc)
#define CCM_PCDR IO_ADDR_CCM(0x20)
/* SCM register addresses */
#define IO_ADDR_SCM(off) (MX1_IO_ADDRESS(MX1_SCM_BASE_ADDR + (off)))
#define SCM_GCCR IO_ADDR_SCM(0xc)
static const char *prem_sel_clks[] = { "clk32_premult", "clk16m", };
static const char *clko_sel_clks[] = { "per1", "hclk", "clk48m", "clk16m",
"prem", "fclk", };
enum imx1_clks {
dummy, clk32, clk16m_ext, clk16m, clk32_premult, prem, mpll, mpll_gate,
spll, spll_gate, mcu, fclk, hclk, clk48m, per1, per2, per3, clko,
uart3_gate, ssi2_gate, brom_gate, dma_gate, csi_gate, mma_gate,
usbd_gate, clk_max
};
static struct clk *clk[IMX1_CLK_MAX];
static struct clk_onecell_data clk_data;
static struct clk *clk[clk_max];
static void __iomem *ccm __initdata;
#define CCM_CSCR (ccm + 0x0000)
#define CCM_MPCTL0 (ccm + 0x0004)
#define CCM_SPCTL0 (ccm + 0x000c)
#define CCM_PCDR (ccm + 0x0020)
#define SCM_GCCR (ccm + 0x0810)
static void __init _mx1_clocks_init(unsigned long fref)
{
clk[IMX1_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
clk[IMX1_CLK_CLK32] = imx_obtain_fixed_clock("clk32", fref);
clk[IMX1_CLK_CLK16M_EXT] = imx_clk_fixed("clk16m_ext", 16000000);
clk[IMX1_CLK_CLK16M] = imx_clk_gate("clk16m", "clk16m_ext", CCM_CSCR, 17);
clk[IMX1_CLK_CLK32_PREMULT] = imx_clk_fixed_factor("clk32_premult", "clk32", 512, 1);
clk[IMX1_CLK_PREM] = imx_clk_mux("prem", CCM_CSCR, 16, 1, prem_sel_clks, ARRAY_SIZE(prem_sel_clks));
clk[IMX1_CLK_MPLL] = imx_clk_pllv1("mpll", "clk32_premult", CCM_MPCTL0);
clk[IMX1_CLK_MPLL_GATE] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0);
clk[IMX1_CLK_SPLL] = imx_clk_pllv1("spll", "prem", CCM_SPCTL0);
clk[IMX1_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1);
clk[IMX1_CLK_MCU] = imx_clk_divider("mcu", "clk32_premult", CCM_CSCR, 15, 1);
clk[IMX1_CLK_FCLK] = imx_clk_divider("fclk", "mpll_gate", CCM_CSCR, 15, 1);
clk[IMX1_CLK_HCLK] = imx_clk_divider("hclk", "spll_gate", CCM_CSCR, 10, 4);
clk[IMX1_CLK_CLK48M] = imx_clk_divider("clk48m", "spll_gate", CCM_CSCR, 26, 3);
clk[IMX1_CLK_PER1] = imx_clk_divider("per1", "spll_gate", CCM_PCDR, 0, 4);
clk[IMX1_CLK_PER2] = imx_clk_divider("per2", "spll_gate", CCM_PCDR, 4, 4);
clk[IMX1_CLK_PER3] = imx_clk_divider("per3", "spll_gate", CCM_PCDR, 16, 7);
clk[IMX1_CLK_CLKO] = imx_clk_mux("clko", CCM_CSCR, 29, 3, clko_sel_clks, ARRAY_SIZE(clko_sel_clks));
clk[IMX1_CLK_UART3_GATE] = imx_clk_gate("uart3_gate", "hclk", SCM_GCCR, 6);
clk[IMX1_CLK_SSI2_GATE] = imx_clk_gate("ssi2_gate", "hclk", SCM_GCCR, 5);
clk[IMX1_CLK_BROM_GATE] = imx_clk_gate("brom_gate", "hclk", SCM_GCCR, 4);
clk[IMX1_CLK_DMA_GATE] = imx_clk_gate("dma_gate", "hclk", SCM_GCCR, 3);
clk[IMX1_CLK_CSI_GATE] = imx_clk_gate("csi_gate", "hclk", SCM_GCCR, 2);
clk[IMX1_CLK_MMA_GATE] = imx_clk_gate("mma_gate", "hclk", SCM_GCCR, 1);
clk[IMX1_CLK_USBD_GATE] = imx_clk_gate("usbd_gate", "clk48m", SCM_GCCR, 0);
imx_check_clocks(clk, ARRAY_SIZE(clk));
}
int __init mx1_clocks_init(unsigned long fref)
{
int i;
ccm = MX1_IO_ADDRESS(MX1_CCM_BASE_ADDR);
clk[dummy] = imx_clk_fixed("dummy", 0);
clk[clk32] = imx_clk_fixed("clk32", fref);
clk[clk16m_ext] = imx_clk_fixed("clk16m_ext", 16000000);
clk[clk16m] = imx_clk_gate("clk16m", "clk16m_ext", CCM_CSCR, 17);
clk[clk32_premult] = imx_clk_fixed_factor("clk32_premult", "clk32", 512, 1);
clk[prem] = imx_clk_mux("prem", CCM_CSCR, 16, 1, prem_sel_clks,
ARRAY_SIZE(prem_sel_clks));
clk[mpll] = imx_clk_pllv1("mpll", "clk32_premult", CCM_MPCTL0);
clk[mpll_gate] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0);
clk[spll] = imx_clk_pllv1("spll", "prem", CCM_SPCTL0);
clk[spll_gate] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1);
clk[mcu] = imx_clk_divider("mcu", "clk32_premult", CCM_CSCR, 15, 1);
clk[fclk] = imx_clk_divider("fclk", "mpll_gate", CCM_CSCR, 15, 1);
clk[hclk] = imx_clk_divider("hclk", "spll_gate", CCM_CSCR, 10, 4);
clk[clk48m] = imx_clk_divider("clk48m", "spll_gate", CCM_CSCR, 26, 3);
clk[per1] = imx_clk_divider("per1", "spll_gate", CCM_PCDR, 0, 4);
clk[per2] = imx_clk_divider("per2", "spll_gate", CCM_PCDR, 4, 4);
clk[per3] = imx_clk_divider("per3", "spll_gate", CCM_PCDR, 16, 7);
clk[clko] = imx_clk_mux("clko", CCM_CSCR, 29, 3, clko_sel_clks,
ARRAY_SIZE(clko_sel_clks));
clk[uart3_gate] = imx_clk_gate("uart3_gate", "hclk", SCM_GCCR, 6);
clk[ssi2_gate] = imx_clk_gate("ssi2_gate", "hclk", SCM_GCCR, 5);
clk[brom_gate] = imx_clk_gate("brom_gate", "hclk", SCM_GCCR, 4);
clk[dma_gate] = imx_clk_gate("dma_gate", "hclk", SCM_GCCR, 3);
clk[csi_gate] = imx_clk_gate("csi_gate", "hclk", SCM_GCCR, 2);
clk[mma_gate] = imx_clk_gate("mma_gate", "hclk", SCM_GCCR, 1);
clk[usbd_gate] = imx_clk_gate("usbd_gate", "clk48m", SCM_GCCR, 0);
_mx1_clocks_init(fref);
for (i = 0; i < ARRAY_SIZE(clk); i++)
if (IS_ERR(clk[i]))
pr_err("imx1 clk %d: register failed with %ld\n",
i, PTR_ERR(clk[i]));
clk_register_clkdev(clk[dma_gate], "ahb", "imx1-dma");
clk_register_clkdev(clk[hclk], "ipg", "imx1-dma");
clk_register_clkdev(clk[per1], "per", "imx-gpt.0");
clk_register_clkdev(clk[hclk], "ipg", "imx-gpt.0");
clk_register_clkdev(clk[per1], "per", "imx1-uart.0");
clk_register_clkdev(clk[hclk], "ipg", "imx1-uart.0");
clk_register_clkdev(clk[per1], "per", "imx1-uart.1");
clk_register_clkdev(clk[hclk], "ipg", "imx1-uart.1");
clk_register_clkdev(clk[per1], "per", "imx1-uart.2");
clk_register_clkdev(clk[uart3_gate], "ipg", "imx1-uart.2");
clk_register_clkdev(clk[hclk], NULL, "imx1-i2c.0");
clk_register_clkdev(clk[per2], "per", "imx1-cspi.0");
clk_register_clkdev(clk[dummy], "ipg", "imx1-cspi.0");
clk_register_clkdev(clk[per2], "per", "imx1-cspi.1");
clk_register_clkdev(clk[dummy], "ipg", "imx1-cspi.1");
clk_register_clkdev(clk[per2], "per", "imx1-fb.0");
clk_register_clkdev(clk[dummy], "ipg", "imx1-fb.0");
clk_register_clkdev(clk[dummy], "ahb", "imx1-fb.0");
clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx-gpt.0");
clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx-gpt.0");
clk_register_clkdev(clk[IMX1_CLK_DMA_GATE], "ahb", "imx1-dma");
clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx1-dma");
clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx1-uart.0");
clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx1-uart.0");
clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx1-uart.1");
clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx1-uart.1");
clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx1-uart.2");
clk_register_clkdev(clk[IMX1_CLK_UART3_GATE], "ipg", "imx1-uart.2");
clk_register_clkdev(clk[IMX1_CLK_HCLK], NULL, "imx1-i2c.0");
clk_register_clkdev(clk[IMX1_CLK_PER2], "per", "imx1-cspi.0");
clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ipg", "imx1-cspi.0");
clk_register_clkdev(clk[IMX1_CLK_PER2], "per", "imx1-cspi.1");
clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ipg", "imx1-cspi.1");
clk_register_clkdev(clk[IMX1_CLK_PER2], "per", "imx1-fb.0");
clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ipg", "imx1-fb.0");
clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ahb", "imx1-fb.0");
mxc_timer_init(MX1_IO_ADDRESS(MX1_TIM1_BASE_ADDR), MX1_TIM1_INT);
return 0;
}
static void __init mx1_clocks_init_dt(struct device_node *np)
{
ccm = of_iomap(np, 0);
BUG_ON(!ccm);
_mx1_clocks_init(32768);
clk_data.clks = clk;
clk_data.clk_num = ARRAY_SIZE(clk);
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
}
CLK_OF_DECLARE(imx1_ccm, "fsl,imx1-ccm", mx1_clocks_init_dt);

289
arch/arm/mach-imx/clk-imx21.c
View File

@ -7,178 +7,165 @@
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/err.h>
#include <linux/clkdev.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <dt-bindings/clock/imx21-clock.h>
#include "clk.h"
#include "common.h"
#include "hardware.h"
#define IO_ADDR_CCM(off) (MX21_IO_ADDRESS(MX21_CCM_BASE_ADDR + (off)))
static void __iomem *ccm __initdata;
/* Register offsets */
#define CCM_CSCR IO_ADDR_CCM(0x0)
#define CCM_MPCTL0 IO_ADDR_CCM(0x4)
#define CCM_MPCTL1 IO_ADDR_CCM(0x8)
#define CCM_SPCTL0 IO_ADDR_CCM(0xc)
#define CCM_SPCTL1 IO_ADDR_CCM(0x10)
#define CCM_OSC26MCTL IO_ADDR_CCM(0x14)
#define CCM_PCDR0 IO_ADDR_CCM(0x18)
#define CCM_PCDR1 IO_ADDR_CCM(0x1c)
#define CCM_PCCR0 IO_ADDR_CCM(0x20)
#define CCM_PCCR1 IO_ADDR_CCM(0x24)
#define CCM_CCSR IO_ADDR_CCM(0x28)
#define CCM_PMCTL IO_ADDR_CCM(0x2c)
#define CCM_PMCOUNT IO_ADDR_CCM(0x30)
#define CCM_WKGDCTL IO_ADDR_CCM(0x34)
#define CCM_CSCR (ccm + 0x00)
#define CCM_MPCTL0 (ccm + 0x04)
#define CCM_SPCTL0 (ccm + 0x0c)
#define CCM_PCDR0 (ccm + 0x18)
#define CCM_PCDR1 (ccm + 0x1c)
#define CCM_PCCR0 (ccm + 0x20)
#define CCM_PCCR1 (ccm + 0x24)
static const char *mpll_sel_clks[] = { "fpm", "ckih", };
static const char *spll_sel_clks[] = { "fpm", "ckih", };
static const char *mpll_osc_sel_clks[] = { "ckih_gate", "ckih_div1p5", };
static const char *mpll_sel_clks[] = { "fpm_gate", "mpll_osc_sel", };
static const char *spll_sel_clks[] = { "fpm_gate", "mpll_osc_sel", };
static const char *ssi_sel_clks[] = { "spll_gate", "mpll_gate", };
enum imx21_clks {
ckil, ckih, fpm, mpll_sel, spll_sel, mpll, spll, fclk, hclk, ipg, per1,
per2, per3, per4, uart1_ipg_gate, uart2_ipg_gate, uart3_ipg_gate,
uart4_ipg_gate, gpt1_ipg_gate, gpt2_ipg_gate, gpt3_ipg_gate,
pwm_ipg_gate, sdhc1_ipg_gate, sdhc2_ipg_gate, lcdc_ipg_gate,
lcdc_hclk_gate, cspi3_ipg_gate, cspi2_ipg_gate, cspi1_ipg_gate,
per4_gate, csi_hclk_gate, usb_div, usb_gate, usb_hclk_gate, ssi1_gate,
ssi2_gate, nfc_div, nfc_gate, dma_gate, dma_hclk_gate, brom_gate,
emma_gate, emma_hclk_gate, slcdc_gate, slcdc_hclk_gate, wdog_gate,
gpio_gate, i2c_gate, kpp_gate, owire_gate, rtc_gate, clk_max
};
static struct clk *clk[IMX21_CLK_MAX];
static struct clk_onecell_data clk_data;
static struct clk *clk[clk_max];
static void __init _mx21_clocks_init(unsigned long lref, unsigned long href)
{
BUG_ON(!ccm);
clk[IMX21_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
clk[IMX21_CLK_CKIL] = imx_obtain_fixed_clock("ckil", lref);
clk[IMX21_CLK_CKIH] = imx_obtain_fixed_clock("ckih", href);
clk[IMX21_CLK_FPM] = imx_clk_fixed_factor("fpm", "ckil", 512, 1);
clk[IMX21_CLK_CKIH_DIV1P5] = imx_clk_fixed_factor("ckih_div1p5", "ckih_gate", 2, 3);
clk[IMX21_CLK_MPLL_GATE] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0);
clk[IMX21_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1);
clk[IMX21_CLK_FPM_GATE] = imx_clk_gate("fpm_gate", "fpm", CCM_CSCR, 2);
clk[IMX21_CLK_CKIH_GATE] = imx_clk_gate_dis("ckih_gate", "ckih", CCM_CSCR, 3);
clk[IMX21_CLK_MPLL_OSC_SEL] = imx_clk_mux("mpll_osc_sel", CCM_CSCR, 4, 1, mpll_osc_sel_clks, ARRAY_SIZE(mpll_osc_sel_clks));
clk[IMX21_CLK_IPG] = imx_clk_divider("ipg", "hclk", CCM_CSCR, 9, 1);
clk[IMX21_CLK_HCLK] = imx_clk_divider("hclk", "fclk", CCM_CSCR, 10, 4);
clk[IMX21_CLK_MPLL_SEL] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks, ARRAY_SIZE(mpll_sel_clks));
clk[IMX21_CLK_SPLL_SEL] = imx_clk_mux("spll_sel", CCM_CSCR, 17, 1, spll_sel_clks, ARRAY_SIZE(spll_sel_clks));
clk[IMX21_CLK_SSI1_SEL] = imx_clk_mux("ssi1_sel", CCM_CSCR, 19, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
clk[IMX21_CLK_SSI2_SEL] = imx_clk_mux("ssi2_sel", CCM_CSCR, 20, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
clk[IMX21_CLK_USB_DIV] = imx_clk_divider("usb_div", "spll_gate", CCM_CSCR, 26, 3);
clk[IMX21_CLK_FCLK] = imx_clk_divider("fclk", "mpll_gate", CCM_CSCR, 29, 3);
clk[IMX21_CLK_MPLL] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0);
clk[IMX21_CLK_SPLL] = imx_clk_pllv1("spll", "spll_sel", CCM_SPCTL0);
clk[IMX21_CLK_NFC_DIV] = imx_clk_divider("nfc_div", "fclk", CCM_PCDR0, 12, 4);
clk[IMX21_CLK_SSI1_DIV] = imx_clk_divider("ssi1_div", "ssi1_sel", CCM_PCDR0, 16, 6);
clk[IMX21_CLK_SSI2_DIV] = imx_clk_divider("ssi2_div", "ssi2_sel", CCM_PCDR0, 26, 6);
clk[IMX21_CLK_PER1] = imx_clk_divider("per1", "mpll_gate", CCM_PCDR1, 0, 6);
clk[IMX21_CLK_PER2] = imx_clk_divider("per2", "mpll_gate", CCM_PCDR1, 8, 6);
clk[IMX21_CLK_PER3] = imx_clk_divider("per3", "mpll_gate", CCM_PCDR1, 16, 6);
clk[IMX21_CLK_PER4] = imx_clk_divider("per4", "mpll_gate", CCM_PCDR1, 24, 6);
clk[IMX21_CLK_UART1_IPG_GATE] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR0, 0);
clk[IMX21_CLK_UART2_IPG_GATE] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR0, 1);
clk[IMX21_CLK_UART3_IPG_GATE] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR0, 2);
clk[IMX21_CLK_UART4_IPG_GATE] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR0, 3);
clk[IMX21_CLK_CSPI1_IPG_GATE] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 4);
clk[IMX21_CLK_CSPI2_IPG_GATE] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 5);
clk[IMX21_CLK_SSI1_GATE] = imx_clk_gate("ssi1_gate", "ipg", CCM_PCCR0, 6);
clk[IMX21_CLK_SSI2_GATE] = imx_clk_gate("ssi2_gate", "ipg", CCM_PCCR0, 7);
clk[IMX21_CLK_SDHC1_IPG_GATE] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 9);
clk[IMX21_CLK_SDHC2_IPG_GATE] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 10);
clk[IMX21_CLK_GPIO_GATE] = imx_clk_gate("gpio_gate", "ipg", CCM_PCCR0, 11);
clk[IMX21_CLK_I2C_GATE] = imx_clk_gate("i2c_gate", "ipg", CCM_PCCR0, 12);
clk[IMX21_CLK_DMA_GATE] = imx_clk_gate("dma_gate", "ipg", CCM_PCCR0, 13);
clk[IMX21_CLK_USB_GATE] = imx_clk_gate("usb_gate", "usb_div", CCM_PCCR0, 14);
clk[IMX21_CLK_EMMA_GATE] = imx_clk_gate("emma_gate", "ipg", CCM_PCCR0, 15);
clk[IMX21_CLK_SSI2_BAUD_GATE] = imx_clk_gate("ssi2_baud_gate", "ipg", CCM_PCCR0, 16);
clk[IMX21_CLK_SSI1_BAUD_GATE] = imx_clk_gate("ssi1_baud_gate", "ipg", CCM_PCCR0, 17);
clk[IMX21_CLK_LCDC_IPG_GATE] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 18);
clk[IMX21_CLK_NFC_GATE] = imx_clk_gate("nfc_gate", "nfc_div", CCM_PCCR0, 19);
clk[IMX21_CLK_SLCDC_HCLK_GATE] = imx_clk_gate("slcdc_hclk_gate", "hclk", CCM_PCCR0, 21);
clk[IMX21_CLK_PER4_GATE] = imx_clk_gate("per4_gate", "per4", CCM_PCCR0, 22);
clk[IMX21_CLK_BMI_GATE] = imx_clk_gate("bmi_gate", "hclk", CCM_PCCR0, 23);
clk[IMX21_CLK_USB_HCLK_GATE] = imx_clk_gate("usb_hclk_gate", "hclk", CCM_PCCR0, 24);
clk[IMX21_CLK_SLCDC_GATE] = imx_clk_gate("slcdc_gate", "hclk", CCM_PCCR0, 25);
clk[IMX21_CLK_LCDC_HCLK_GATE] = imx_clk_gate("lcdc_hclk_gate", "hclk", CCM_PCCR0, 26);
clk[IMX21_CLK_EMMA_HCLK_GATE] = imx_clk_gate("emma_hclk_gate", "hclk", CCM_PCCR0, 27);
clk[IMX21_CLK_BROM_GATE] = imx_clk_gate("brom_gate", "hclk", CCM_PCCR0, 28);
clk[IMX21_CLK_DMA_HCLK_GATE] = imx_clk_gate("dma_hclk_gate", "hclk", CCM_PCCR0, 30);
clk[IMX21_CLK_CSI_HCLK_GATE] = imx_clk_gate("csi_hclk_gate", "hclk", CCM_PCCR0, 31);
clk[IMX21_CLK_CSPI3_IPG_GATE] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR1, 23);
clk[IMX21_CLK_WDOG_GATE] = imx_clk_gate("wdog_gate", "ipg", CCM_PCCR1, 24);
clk[IMX21_CLK_GPT1_IPG_GATE] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR1, 25);
clk[IMX21_CLK_GPT2_IPG_GATE] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR1, 26);
clk[IMX21_CLK_GPT3_IPG_GATE] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR1, 27);
clk[IMX21_CLK_PWM_IPG_GATE] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR1, 28);
clk[IMX21_CLK_RTC_GATE] = imx_clk_gate("rtc_gate", "ipg", CCM_PCCR1, 29);
clk[IMX21_CLK_KPP_GATE] = imx_clk_gate("kpp_gate", "ipg", CCM_PCCR1, 30);
clk[IMX21_CLK_OWIRE_GATE] = imx_clk_gate("owire_gate", "ipg", CCM_PCCR1, 31);
imx_check_clocks(clk, ARRAY_SIZE(clk));
}
/*
* must be called very early to get information about the
* available clock rate when the timer framework starts
*/
int __init mx21_clocks_init(unsigned long lref, unsigned long href)
{
int i;
ccm = ioremap(MX21_CCM_BASE_ADDR, SZ_2K);
clk[ckil] = imx_clk_fixed("ckil", lref);
clk[ckih] = imx_clk_fixed("ckih", href);
clk[fpm] = imx_clk_fixed_factor("fpm", "ckil", 512, 1);
clk[mpll_sel] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks,
ARRAY_SIZE(mpll_sel_clks));
clk[spll_sel] = imx_clk_mux("spll_sel", CCM_CSCR, 17, 1, spll_sel_clks,
ARRAY_SIZE(spll_sel_clks));
clk[mpll] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0);
clk[spll] = imx_clk_pllv1("spll", "spll_sel", CCM_SPCTL0);
clk[fclk] = imx_clk_divider("fclk", "mpll", CCM_CSCR, 29, 3);
clk[hclk] = imx_clk_divider("hclk", "fclk", CCM_CSCR, 10, 4);
clk[ipg] = imx_clk_divider("ipg", "hclk", CCM_CSCR, 9, 1);
clk[per1] = imx_clk_divider("per1", "mpll", CCM_PCDR1, 0, 6);
clk[per2] = imx_clk_divider("per2", "mpll", CCM_PCDR1, 8, 6);
clk[per3] = imx_clk_divider("per3", "mpll", CCM_PCDR1, 16, 6);
clk[per4] = imx_clk_divider("per4", "mpll", CCM_PCDR1, 24, 6);
clk[uart1_ipg_gate] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR0, 0);
clk[uart2_ipg_gate] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR0, 1);
clk[uart3_ipg_gate] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR0, 2);
clk[uart4_ipg_gate] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR0, 3);
clk[gpt1_ipg_gate] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR1, 25);
clk[gpt2_ipg_gate] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR1, 26);
clk[gpt3_ipg_gate] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR1, 27);
clk[pwm_ipg_gate] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR1, 28);
clk[sdhc1_ipg_gate] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 9);
clk[sdhc2_ipg_gate] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 10);
clk[lcdc_ipg_gate] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 18);
clk[lcdc_hclk_gate] = imx_clk_gate("lcdc_hclk_gate", "hclk", CCM_PCCR0, 26);
clk[cspi3_ipg_gate] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR1, 23);
clk[cspi2_ipg_gate] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 5);
clk[cspi1_ipg_gate] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 4);
clk[per4_gate] = imx_clk_gate("per4_gate", "per4", CCM_PCCR0, 22);
clk[csi_hclk_gate] = imx_clk_gate("csi_hclk_gate", "hclk", CCM_PCCR0, 31);
clk[usb_div] = imx_clk_divider("usb_div", "spll", CCM_CSCR, 26, 3);
clk[usb_gate] = imx_clk_gate("usb_gate", "usb_div", CCM_PCCR0, 14);
clk[usb_hclk_gate] = imx_clk_gate("usb_hclk_gate", "hclk", CCM_PCCR0, 24);
clk[ssi1_gate] = imx_clk_gate("ssi1_gate", "ipg", CCM_PCCR0, 6);
clk[ssi2_gate] = imx_clk_gate("ssi2_gate", "ipg", CCM_PCCR0, 7);
clk[nfc_div] = imx_clk_divider("nfc_div", "ipg", CCM_PCDR0, 12, 4);
clk[nfc_gate] = imx_clk_gate("nfc_gate", "nfc_div", CCM_PCCR0, 19);
clk[dma_gate] = imx_clk_gate("dma_gate", "ipg", CCM_PCCR0, 13);
clk[dma_hclk_gate] = imx_clk_gate("dma_hclk_gate", "hclk", CCM_PCCR0, 30);
clk[brom_gate] = imx_clk_gate("brom_gate", "hclk", CCM_PCCR0, 28);
clk[emma_gate] = imx_clk_gate("emma_gate", "ipg", CCM_PCCR0, 15);
clk[emma_hclk_gate] = imx_clk_gate("emma_hclk_gate", "hclk", CCM_PCCR0, 27);
clk[slcdc_gate] = imx_clk_gate("slcdc_gate", "ipg", CCM_PCCR0, 25);
clk[slcdc_hclk_gate] = imx_clk_gate("slcdc_hclk_gate", "hclk", CCM_PCCR0, 21);
clk[wdog_gate] = imx_clk_gate("wdog_gate", "ipg", CCM_PCCR1, 24);
clk[gpio_gate] = imx_clk_gate("gpio_gate", "ipg", CCM_PCCR0, 11);
clk[i2c_gate] = imx_clk_gate("i2c_gate", "ipg", CCM_PCCR0, 12);
clk[kpp_gate] = imx_clk_gate("kpp_gate", "ipg", CCM_PCCR1, 30);
clk[owire_gate] = imx_clk_gate("owire_gate", "ipg", CCM_PCCR1, 31);
clk[rtc_gate] = imx_clk_gate("rtc_gate", "ipg", CCM_PCCR1, 29);
_mx21_clocks_init(lref, href);
for (i = 0; i < ARRAY_SIZE(clk); i++)
if (IS_ERR(clk[i]))
pr_err("i.MX21 clk %d: register failed with %ld\n",
i, PTR_ERR(clk[i]));
clk_register_clkdev(clk[per1], "per1", NULL);
clk_register_clkdev(clk[per2], "per2", NULL);
clk_register_clkdev(clk[per3], "per3", NULL);
clk_register_clkdev(clk[per4], "per4", NULL);
clk_register_clkdev(clk[per1], "per", "imx21-uart.0");
clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0");
clk_register_clkdev(clk[per1], "per", "imx21-uart.1");
clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1");
clk_register_clkdev(clk[per1], "per", "imx21-uart.2");
clk_register_clkdev(clk[uart3_ipg_gate], "ipg", "imx21-uart.2");
clk_register_clkdev(clk[per1], "per", "imx21-uart.3");
clk_register_clkdev(clk[uart4_ipg_gate], "ipg", "imx21-uart.3");
clk_register_clkdev(clk[gpt1_ipg_gate], "ipg", "imx-gpt.0");
clk_register_clkdev(clk[per1], "per", "imx-gpt.0");
clk_register_clkdev(clk[gpt2_ipg_gate], "ipg", "imx-gpt.1");
clk_register_clkdev(clk[per1], "per", "imx-gpt.1");
clk_register_clkdev(clk[gpt3_ipg_gate], "ipg", "imx-gpt.2");
clk_register_clkdev(clk[per1], "per", "imx-gpt.2");
clk_register_clkdev(clk[per2], "per", "imx21-cspi.0");
clk_register_clkdev(clk[cspi1_ipg_gate], "ipg", "imx21-cspi.0");
clk_register_clkdev(clk[per2], "per", "imx21-cspi.1");
clk_register_clkdev(clk[cspi2_ipg_gate], "ipg", "imx21-cspi.1");
clk_register_clkdev(clk[per2], "per", "imx21-cspi.2");
clk_register_clkdev(clk[cspi3_ipg_gate], "ipg", "imx21-cspi.2");
clk_register_clkdev(clk[per3], "per", "imx21-fb.0");
clk_register_clkdev(clk[lcdc_ipg_gate], "ipg", "imx21-fb.0");
clk_register_clkdev(clk[lcdc_hclk_gate], "ahb", "imx21-fb.0");
clk_register_clkdev(clk[usb_gate], "per", "imx21-hcd.0");
clk_register_clkdev(clk[usb_hclk_gate], "ahb", "imx21-hcd.0");
clk_register_clkdev(clk[nfc_gate], NULL, "imx21-nand.0");
clk_register_clkdev(clk[dma_hclk_gate], "ahb", "imx21-dma");
clk_register_clkdev(clk[dma_gate], "ipg", "imx21-dma");
clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");
clk_register_clkdev(clk[i2c_gate], NULL, "imx21-i2c.0");
clk_register_clkdev(clk[kpp_gate], NULL, "mxc-keypad");
clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1.0");
clk_register_clkdev(clk[brom_gate], "brom", NULL);
clk_register_clkdev(clk[emma_gate], "emma", NULL);
clk_register_clkdev(clk[slcdc_gate], "slcdc", NULL);
clk_register_clkdev(clk[gpio_gate], "gpio", NULL);
clk_register_clkdev(clk[rtc_gate], "rtc", NULL);
clk_register_clkdev(clk[csi_hclk_gate], "csi", NULL);
clk_register_clkdev(clk[ssi1_gate], "ssi1", NULL);
clk_register_clkdev(clk[ssi2_gate], "ssi2", NULL);
clk_register_clkdev(clk[sdhc1_ipg_gate], "sdhc1", NULL);
clk_register_clkdev(clk[sdhc2_ipg_gate], "sdhc2", NULL);
clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.0");
clk_register_clkdev(clk[IMX21_CLK_UART1_IPG_GATE], "ipg", "imx21-uart.0");
clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.1");
clk_register_clkdev(clk[IMX21_CLK_UART2_IPG_GATE], "ipg", "imx21-uart.1");
clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.2");
clk_register_clkdev(clk[IMX21_CLK_UART3_IPG_GATE], "ipg", "imx21-uart.2");
clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.3");
clk_register_clkdev(clk[IMX21_CLK_UART4_IPG_GATE], "ipg", "imx21-uart.3");
clk_register_clkdev(clk[IMX21_CLK_GPT1_IPG_GATE], "ipg", "imx-gpt.0");
clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx-gpt.0");
clk_register_clkdev(clk[IMX21_CLK_PER2], "per", "imx21-cspi.0");
clk_register_clkdev(clk[IMX21_CLK_CSPI1_IPG_GATE], "ipg", "imx21-cspi.0");
clk_register_clkdev(clk[IMX21_CLK_PER2], "per", "imx21-cspi.1");
clk_register_clkdev(clk[IMX21_CLK_CSPI2_IPG_GATE], "ipg", "imx21-cspi.1");
clk_register_clkdev(clk[IMX21_CLK_PER2], "per", "imx21-cspi.2");
clk_register_clkdev(clk[IMX21_CLK_CSPI3_IPG_GATE], "ipg", "imx21-cspi.2");
clk_register_clkdev(clk[IMX21_CLK_PER3], "per", "imx21-fb.0");
clk_register_clkdev(clk[IMX21_CLK_LCDC_IPG_GATE], "ipg", "imx21-fb.0");
clk_register_clkdev(clk[IMX21_CLK_LCDC_HCLK_GATE], "ahb", "imx21-fb.0");
clk_register_clkdev(clk[IMX21_CLK_USB_GATE], "per", "imx21-hcd.0");
clk_register_clkdev(clk[IMX21_CLK_USB_HCLK_GATE], "ahb", "imx21-hcd.0");
clk_register_clkdev(clk[IMX21_CLK_NFC_GATE], NULL, "imx21-nand.0");
clk_register_clkdev(clk[IMX21_CLK_DMA_HCLK_GATE], "ahb", "imx21-dma");
clk_register_clkdev(clk[IMX21_CLK_DMA_GATE], "ipg", "imx21-dma");
clk_register_clkdev(clk[IMX21_CLK_WDOG_GATE], NULL, "imx2-wdt.0");
clk_register_clkdev(clk[IMX21_CLK_I2C_GATE], NULL, "imx21-i2c.0");
clk_register_clkdev(clk[IMX21_CLK_OWIRE_GATE], NULL, "mxc_w1.0");
mxc_timer_init(MX21_IO_ADDRESS(MX21_GPT1_BASE_ADDR), MX21_INT_GPT1);
return 0;
}
static void __init mx21_clocks_init_dt(struct device_node *np)
{
ccm = of_iomap(np, 0);
_mx21_clocks_init(32768, 26000000);
clk_data.clks = clk;
clk_data.clk_num = ARRAY_SIZE(clk);
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
}
CLK_OF_DECLARE(imx27_ccm, "fsl,imx21-ccm", mx21_clocks_init_dt);

47
arch/arm/mach-imx/clk-imx25.c
View File

@ -32,8 +32,6 @@
#include "hardware.h"
#include "mx25.h"
#define CRM_BASE MX25_IO_ADDRESS(MX25_CRM_BASE_ADDR)
#define CCM_MPCTL 0x00
#define CCM_UPCTL 0x04
#define CCM_CCTL 0x08
@ -56,7 +54,7 @@
#define CCM_LTR3 0x4c
#define CCM_MCR 0x64
#define ccm(x) (CRM_BASE + (x))
#define ccm(x) (ccm_base + (x))
static struct clk_onecell_data clk_data;
@ -91,9 +89,10 @@ enum mx25_clks {
static struct clk *clk[clk_max];
static int __init __mx25_clocks_init(unsigned long osc_rate)
static int __init __mx25_clocks_init(unsigned long osc_rate,
void __iomem *ccm_base)
{
int i;
BUG_ON(!ccm_base);
clk[dummy] = imx_clk_fixed("dummy", 0);
clk[osc] = imx_clk_fixed("osc", osc_rate);
@ -224,19 +223,13 @@ static int __init __mx25_clocks_init(unsigned long osc_rate)
/* CCM_CGCR2(19): reserved in datasheet, but used as wdt in FSL kernel */
clk[wdt_ipg] = imx_clk_gate("wdt_ipg", "ipg", ccm(CCM_CGCR2), 19);
for (i = 0; i < ARRAY_SIZE(clk); i++)
if (IS_ERR(clk[i]))
pr_err("i.MX25 clk %d: register failed with %ld\n",
i, PTR_ERR(clk[i]));
imx_check_clocks(clk, ARRAY_SIZE(clk));
clk_prepare_enable(clk[emi_ahb]);
/* Clock source for gpt must be derived from AHB */
clk_set_parent(clk[per5_sel], clk[ahb]);
clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
/*
* Let's initially set up CLKO parent as ipg, since this configuration
* is used on some imx25 board designs to clock the audio codec.
@ -248,8 +241,14 @@ static int __init __mx25_clocks_init(unsigned long osc_rate)
int __init mx25_clocks_init(void)
{
__mx25_clocks_init(24000000);
void __iomem *ccm;
ccm = ioremap(MX25_CRM_BASE_ADDR, SZ_16K);
__mx25_clocks_init(24000000, ccm);
clk_register_clkdev(clk[gpt1_ipg], "ipg", "imx-gpt.0");
clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
/* i.mx25 has the i.mx21 type uart */
clk_register_clkdev(clk[uart1_ipg], "ipg", "imx21-uart.0");
clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.0");
@ -314,29 +313,27 @@ int __init mx25_clocks_init(void)
return 0;
}
int __init mx25_clocks_init_dt(void)
static void __init mx25_clocks_init_dt(struct device_node *np)
{
struct device_node *np;
struct device_node *refnp;
unsigned long osc_rate = 24000000;
void __iomem *ccm;
/* retrieve the freqency of fixed clocks from device tree */
for_each_compatible_node(np, NULL, "fixed-clock") {
for_each_compatible_node(refnp, NULL, "fixed-clock") {
u32 rate;
if (of_property_read_u32(np, "clock-frequency", &rate))
if (of_property_read_u32(refnp, "clock-frequency", &rate))
continue;
if (of_device_is_compatible(np, "fsl,imx-osc"))
if (of_device_is_compatible(refnp, "fsl,imx-osc"))
osc_rate = rate;
}
np = of_find_compatible_node(NULL, NULL, "fsl,imx25-ccm");
ccm = of_iomap(np, 0);
__mx25_clocks_init(osc_rate, ccm);
clk_data.clks = clk;
clk_data.clk_num = ARRAY_SIZE(clk);
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
__mx25_clocks_init(osc_rate);
mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx25-gpt"));
return 0;
}
CLK_OF_DECLARE(imx25_ccm, "fsl,imx25-ccm", mx25_clocks_init_dt);

470
arch/arm/mach-imx/clk-imx27.c
View File

@ -1,61 +1,36 @@
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/clk-provider.h>
#include <linux/clkdev.h>
#include <linux/err.h>
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <dt-bindings/clock/imx27-clock.h>
#include "clk.h"
#include "common.h"
#include "hardware.h"
#define IO_ADDR_CCM(off) (MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR + (off)))
static void __iomem *ccm __initdata;
/* Register offsets */
#define CCM_CSCR IO_ADDR_CCM(0x0)
#define CCM_MPCTL0 IO_ADDR_CCM(0x4)
#define CCM_MPCTL1 IO_ADDR_CCM(0x8)
#define CCM_SPCTL0 IO_ADDR_CCM(0xc)
#define CCM_SPCTL1 IO_ADDR_CCM(0x10)
#define CCM_OSC26MCTL IO_ADDR_CCM(0x14)
#define CCM_PCDR0 IO_ADDR_CCM(0x18)
#define CCM_PCDR1 IO_ADDR_CCM(0x1c)
#define CCM_PCCR0 IO_ADDR_CCM(0x20)
#define CCM_PCCR1 IO_ADDR_CCM(0x24)
#define CCM_CCSR IO_ADDR_CCM(0x28)
#define CCM_PMCTL IO_ADDR_CCM(0x2c)
#define CCM_PMCOUNT IO_ADDR_CCM(0x30)
#define CCM_WKGDCTL IO_ADDR_CCM(0x34)
#define CCM_CSCR_UPDATE_DIS (1 << 31)
#define CCM_CSCR_SSI2 (1 << 23)
#define CCM_CSCR_SSI1 (1 << 22)
#define CCM_CSCR_VPU (1 << 21)
#define CCM_CSCR_MSHC (1 << 20)
#define CCM_CSCR_SPLLRES (1 << 19)
#define CCM_CSCR_MPLLRES (1 << 18)
#define CCM_CSCR_SP (1 << 17)
#define CCM_CSCR_MCU (1 << 16)
#define CCM_CSCR_OSC26MDIV (1 << 4)
#define CCM_CSCR_OSC26M (1 << 3)
#define CCM_CSCR_FPM (1 << 2)
#define CCM_CSCR_SPEN (1 << 1)
#define CCM_CSCR_MPEN (1 << 0)
/* i.MX27 TO 2+ */
#define CCM_CSCR_ARM_SRC (1 << 15)
#define CCM_SPCTL1_LF (1 << 15)
#define CCM_SPCTL1_BRMO (1 << 6)
#define CCM_CSCR (ccm + 0x00)
#define CCM_MPCTL0 (ccm + 0x04)
#define CCM_MPCTL1 (ccm + 0x08)
#define CCM_SPCTL0 (ccm + 0x0c)
#define CCM_SPCTL1 (ccm + 0x10)
#define CCM_PCDR0 (ccm + 0x18)
#define CCM_PCDR1 (ccm + 0x1c)
#define CCM_PCCR0 (ccm + 0x20)
#define CCM_PCCR1 (ccm + 0x24)
#define CCM_CCSR (ccm + 0x28)
static const char *vpu_sel_clks[] = { "spll", "mpll_main2", };
static const char *cpu_sel_clks[] = { "mpll_main2", "mpll", };
static const char *mpll_sel_clks[] = { "fpm", "mpll_osc_sel", };
static const char *mpll_osc_sel_clks[] = { "ckih", "ckih_div1p5", };
static const char *mpll_osc_sel_clks[] = { "ckih_gate", "ckih_div1p5", };
static const char *clko_sel_clks[] = {
"ckil", "fpm", "ckih", "ckih",
"ckih", "mpll", "spll", "cpu_div",
"ckil", "fpm", "ckih_gate", "ckih_gate",
"ckih_gate", "mpll", "spll", "cpu_div",
"ahb", "ipg", "per1_div", "per2_div",
"per3_div", "per4_div", "ssi1_div", "ssi2_div",
"nfc_div", "mshc_div", "vpu_div", "60m",
@ -64,239 +39,220 @@ static const char *clko_sel_clks[] = {
static const char *ssi_sel_clks[] = { "spll_gate", "mpll", };
enum mx27_clks {
dummy, ckih, ckil, mpll, spll, mpll_main2, ahb, ipg, nfc_div, per1_div,
per2_div, per3_div, per4_div, vpu_sel, vpu_div, usb_div, cpu_sel,
clko_sel, cpu_div, clko_div, ssi1_sel, ssi2_sel, ssi1_div, ssi2_div,
clko_en, ssi2_ipg_gate, ssi1_ipg_gate, slcdc_ipg_gate, sdhc3_ipg_gate,
sdhc2_ipg_gate, sdhc1_ipg_gate, scc_ipg_gate, sahara_ipg_gate,
rtc_ipg_gate, pwm_ipg_gate, owire_ipg_gate, lcdc_ipg_gate,
kpp_ipg_gate, iim_ipg_gate, i2c2_ipg_gate, i2c1_ipg_gate,
gpt6_ipg_gate, gpt5_ipg_gate, gpt4_ipg_gate, gpt3_ipg_gate,
gpt2_ipg_gate, gpt1_ipg_gate, gpio_ipg_gate, fec_ipg_gate,
emma_ipg_gate, dma_ipg_gate, cspi3_ipg_gate, cspi2_ipg_gate,
cspi1_ipg_gate, nfc_baud_gate, ssi2_baud_gate, ssi1_baud_gate,
vpu_baud_gate, per4_gate, per3_gate, per2_gate, per1_gate,
usb_ahb_gate, slcdc_ahb_gate, sahara_ahb_gate, lcdc_ahb_gate,
vpu_ahb_gate, fec_ahb_gate, emma_ahb_gate, emi_ahb_gate, dma_ahb_gate,
csi_ahb_gate, brom_ahb_gate, ata_ahb_gate, wdog_ipg_gate, usb_ipg_gate,
uart6_ipg_gate, uart5_ipg_gate, uart4_ipg_gate, uart3_ipg_gate,
uart2_ipg_gate, uart1_ipg_gate, ckih_div1p5, fpm, mpll_osc_sel,
mpll_sel, spll_gate, mshc_div, rtic_ipg_gate, mshc_ipg_gate,
rtic_ahb_gate, mshc_baud_gate, clk_max
};
static struct clk *clk[clk_max];
static struct clk *clk[IMX27_CLK_MAX];
static struct clk_onecell_data clk_data;
static void __init _mx27_clocks_init(unsigned long fref)
{
BUG_ON(!ccm);
clk[IMX27_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
clk[IMX27_CLK_CKIH] = imx_clk_fixed("ckih", fref);
clk[IMX27_CLK_CKIL] = imx_clk_fixed("ckil", 32768);
clk[IMX27_CLK_FPM] = imx_clk_fixed_factor("fpm", "ckil", 1024, 1);
clk[IMX27_CLK_CKIH_DIV1P5] = imx_clk_fixed_factor("ckih_div1p5", "ckih_gate", 2, 3);
clk[IMX27_CLK_CKIH_GATE] = imx_clk_gate_dis("ckih_gate", "ckih", CCM_CSCR, 3);
clk[IMX27_CLK_MPLL_OSC_SEL] = imx_clk_mux("mpll_osc_sel", CCM_CSCR, 4, 1, mpll_osc_sel_clks, ARRAY_SIZE(mpll_osc_sel_clks));
clk[IMX27_CLK_MPLL_SEL] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks, ARRAY_SIZE(mpll_sel_clks));
clk[IMX27_CLK_MPLL] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0);
clk[IMX27_CLK_SPLL] = imx_clk_pllv1("spll", "ckih_gate", CCM_SPCTL0);
clk[IMX27_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1);
clk[IMX27_CLK_MPLL_MAIN2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3);
if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
clk[IMX27_CLK_AHB] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 8, 2);
clk[IMX27_CLK_IPG] = imx_clk_fixed_factor("ipg", "ahb", 1, 2);
} else {
clk[IMX27_CLK_AHB] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 9, 4);
clk[IMX27_CLK_IPG] = imx_clk_divider("ipg", "ahb", CCM_CSCR, 8, 1);
}
clk[IMX27_CLK_MSHC_DIV] = imx_clk_divider("mshc_div", "ahb", CCM_PCDR0, 0, 6);
clk[IMX27_CLK_NFC_DIV] = imx_clk_divider("nfc_div", "ahb", CCM_PCDR0, 6, 4);
clk[IMX27_CLK_PER1_DIV] = imx_clk_divider("per1_div", "mpll_main2", CCM_PCDR1, 0, 6);
clk[IMX27_CLK_PER2_DIV] = imx_clk_divider("per2_div", "mpll_main2", CCM_PCDR1, 8, 6);
clk[IMX27_CLK_PER3_DIV] = imx_clk_divider("per3_div", "mpll_main2", CCM_PCDR1, 16, 6);
clk[IMX27_CLK_PER4_DIV] = imx_clk_divider("per4_div", "mpll_main2", CCM_PCDR1, 24, 6);
clk[IMX27_CLK_VPU_SEL] = imx_clk_mux("vpu_sel", CCM_CSCR, 21, 1, vpu_sel_clks, ARRAY_SIZE(vpu_sel_clks));
clk[IMX27_CLK_VPU_DIV] = imx_clk_divider("vpu_div", "vpu_sel", CCM_PCDR0, 10, 6);
clk[IMX27_CLK_USB_DIV] = imx_clk_divider("usb_div", "spll_gate", CCM_CSCR, 28, 3);
clk[IMX27_CLK_CPU_SEL] = imx_clk_mux("cpu_sel", CCM_CSCR, 15, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks));
clk[IMX27_CLK_CLKO_SEL] = imx_clk_mux("clko_sel", CCM_CCSR, 0, 5, clko_sel_clks, ARRAY_SIZE(clko_sel_clks));
if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
clk[IMX27_CLK_CPU_DIV] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 12, 2);
else
clk[IMX27_CLK_CPU_DIV] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 13, 3);
clk[IMX27_CLK_CLKO_DIV] = imx_clk_divider("clko_div", "clko_sel", CCM_PCDR0, 22, 3);
clk[IMX27_CLK_SSI1_SEL] = imx_clk_mux("ssi1_sel", CCM_CSCR, 22, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
clk[IMX27_CLK_SSI2_SEL] = imx_clk_mux("ssi2_sel", CCM_CSCR, 23, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
clk[IMX27_CLK_SSI1_DIV] = imx_clk_divider("ssi1_div", "ssi1_sel", CCM_PCDR0, 16, 6);
clk[IMX27_CLK_SSI2_DIV] = imx_clk_divider("ssi2_div", "ssi2_sel", CCM_PCDR0, 26, 6);
clk[IMX27_CLK_CLKO_EN] = imx_clk_gate("clko_en", "clko_div", CCM_PCCR0, 0);
clk[IMX27_CLK_SSI2_IPG_GATE] = imx_clk_gate("ssi2_ipg_gate", "ipg", CCM_PCCR0, 0);
clk[IMX27_CLK_SSI1_IPG_GATE] = imx_clk_gate("ssi1_ipg_gate", "ipg", CCM_PCCR0, 1);
clk[IMX27_CLK_SLCDC_IPG_GATE] = imx_clk_gate("slcdc_ipg_gate", "ipg", CCM_PCCR0, 2);
clk[IMX27_CLK_SDHC3_IPG_GATE] = imx_clk_gate("sdhc3_ipg_gate", "ipg", CCM_PCCR0, 3);
clk[IMX27_CLK_SDHC2_IPG_GATE] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 4);
clk[IMX27_CLK_SDHC1_IPG_GATE] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 5);
clk[IMX27_CLK_SCC_IPG_GATE] = imx_clk_gate("scc_ipg_gate", "ipg", CCM_PCCR0, 6);
clk[IMX27_CLK_SAHARA_IPG_GATE] = imx_clk_gate("sahara_ipg_gate", "ipg", CCM_PCCR0, 7);
clk[IMX27_CLK_RTIC_IPG_GATE] = imx_clk_gate("rtic_ipg_gate", "ipg", CCM_PCCR0, 8);
clk[IMX27_CLK_RTC_IPG_GATE] = imx_clk_gate("rtc_ipg_gate", "ipg", CCM_PCCR0, 9);
clk[IMX27_CLK_PWM_IPG_GATE] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR0, 11);
clk[IMX27_CLK_OWIRE_IPG_GATE] = imx_clk_gate("owire_ipg_gate", "ipg", CCM_PCCR0, 12);
clk[IMX27_CLK_MSHC_IPG_GATE] = imx_clk_gate("mshc_ipg_gate", "ipg", CCM_PCCR0, 13);
clk[IMX27_CLK_LCDC_IPG_GATE] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 14);
clk[IMX27_CLK_KPP_IPG_GATE] = imx_clk_gate("kpp_ipg_gate", "ipg", CCM_PCCR0, 15);
clk[IMX27_CLK_IIM_IPG_GATE] = imx_clk_gate("iim_ipg_gate", "ipg", CCM_PCCR0, 16);
clk[IMX27_CLK_I2C2_IPG_GATE] = imx_clk_gate("i2c2_ipg_gate", "ipg", CCM_PCCR0, 17);
clk[IMX27_CLK_I2C1_IPG_GATE] = imx_clk_gate("i2c1_ipg_gate", "ipg", CCM_PCCR0, 18);
clk[IMX27_CLK_GPT6_IPG_GATE] = imx_clk_gate("gpt6_ipg_gate", "ipg", CCM_PCCR0, 19);
clk[IMX27_CLK_GPT5_IPG_GATE] = imx_clk_gate("gpt5_ipg_gate", "ipg", CCM_PCCR0, 20);
clk[IMX27_CLK_GPT4_IPG_GATE] = imx_clk_gate("gpt4_ipg_gate", "ipg", CCM_PCCR0, 21);
clk[IMX27_CLK_GPT3_IPG_GATE] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR0, 22);
clk[IMX27_CLK_GPT2_IPG_GATE] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR0, 23);
clk[IMX27_CLK_GPT1_IPG_GATE] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR0, 24);
clk[IMX27_CLK_GPIO_IPG_GATE] = imx_clk_gate("gpio_ipg_gate", "ipg", CCM_PCCR0, 25);
clk[IMX27_CLK_FEC_IPG_GATE] = imx_clk_gate("fec_ipg_gate", "ipg", CCM_PCCR0, 26);
clk[IMX27_CLK_EMMA_IPG_GATE] = imx_clk_gate("emma_ipg_gate", "ipg", CCM_PCCR0, 27);
clk[IMX27_CLK_DMA_IPG_GATE] = imx_clk_gate("dma_ipg_gate", "ipg", CCM_PCCR0, 28);
clk[IMX27_CLK_CSPI3_IPG_GATE] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR0, 29);
clk[IMX27_CLK_CSPI2_IPG_GATE] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 30);
clk[IMX27_CLK_CSPI1_IPG_GATE] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 31);
clk[IMX27_CLK_MSHC_BAUD_GATE] = imx_clk_gate("mshc_baud_gate", "mshc_div", CCM_PCCR1, 2);
clk[IMX27_CLK_NFC_BAUD_GATE] = imx_clk_gate("nfc_baud_gate", "nfc_div", CCM_PCCR1, 3);
clk[IMX27_CLK_SSI2_BAUD_GATE] = imx_clk_gate("ssi2_baud_gate", "ssi2_div", CCM_PCCR1, 4);
clk[IMX27_CLK_SSI1_BAUD_GATE] = imx_clk_gate("ssi1_baud_gate", "ssi1_div", CCM_PCCR1, 5);
clk[IMX27_CLK_VPU_BAUD_GATE] = imx_clk_gate("vpu_baud_gate", "vpu_div", CCM_PCCR1, 6);
clk[IMX27_CLK_PER4_GATE] = imx_clk_gate("per4_gate", "per4_div", CCM_PCCR1, 7);
clk[IMX27_CLK_PER3_GATE] = imx_clk_gate("per3_gate", "per3_div", CCM_PCCR1, 8);
clk[IMX27_CLK_PER2_GATE] = imx_clk_gate("per2_gate", "per2_div", CCM_PCCR1, 9);
clk[IMX27_CLK_PER1_GATE] = imx_clk_gate("per1_gate", "per1_div", CCM_PCCR1, 10);
clk[IMX27_CLK_USB_AHB_GATE] = imx_clk_gate("usb_ahb_gate", "ahb", CCM_PCCR1, 11);
clk[IMX27_CLK_SLCDC_AHB_GATE] = imx_clk_gate("slcdc_ahb_gate", "ahb", CCM_PCCR1, 12);
clk[IMX27_CLK_SAHARA_AHB_GATE] = imx_clk_gate("sahara_ahb_gate", "ahb", CCM_PCCR1, 13);
clk[IMX27_CLK_RTIC_AHB_GATE] = imx_clk_gate("rtic_ahb_gate", "ahb", CCM_PCCR1, 14);
clk[IMX27_CLK_LCDC_AHB_GATE] = imx_clk_gate("lcdc_ahb_gate", "ahb", CCM_PCCR1, 15);
clk[IMX27_CLK_VPU_AHB_GATE] = imx_clk_gate("vpu_ahb_gate", "ahb", CCM_PCCR1, 16);
clk[IMX27_CLK_FEC_AHB_GATE] = imx_clk_gate("fec_ahb_gate", "ahb", CCM_PCCR1, 17);
clk[IMX27_CLK_EMMA_AHB_GATE] = imx_clk_gate("emma_ahb_gate", "ahb", CCM_PCCR1, 18);
clk[IMX27_CLK_EMI_AHB_GATE] = imx_clk_gate("emi_ahb_gate", "ahb", CCM_PCCR1, 19);
clk[IMX27_CLK_DMA_AHB_GATE] = imx_clk_gate("dma_ahb_gate", "ahb", CCM_PCCR1, 20);
clk[IMX27_CLK_CSI_AHB_GATE] = imx_clk_gate("csi_ahb_gate", "ahb", CCM_PCCR1, 21);
clk[IMX27_CLK_BROM_AHB_GATE] = imx_clk_gate("brom_ahb_gate", "ahb", CCM_PCCR1, 22);
clk[IMX27_CLK_ATA_AHB_GATE] = imx_clk_gate("ata_ahb_gate", "ahb", CCM_PCCR1, 23);
clk[IMX27_CLK_WDOG_IPG_GATE] = imx_clk_gate("wdog_ipg_gate", "ipg", CCM_PCCR1, 24);
clk[IMX27_CLK_USB_IPG_GATE] = imx_clk_gate("usb_ipg_gate", "ipg", CCM_PCCR1, 25);
clk[IMX27_CLK_UART6_IPG_GATE] = imx_clk_gate("uart6_ipg_gate", "ipg", CCM_PCCR1, 26);
clk[IMX27_CLK_UART5_IPG_GATE] = imx_clk_gate("uart5_ipg_gate", "ipg", CCM_PCCR1, 27);
clk[IMX27_CLK_UART4_IPG_GATE] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR1, 28);
clk[IMX27_CLK_UART3_IPG_GATE] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR1, 29);
clk[IMX27_CLK_UART2_IPG_GATE] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR1, 30);
clk[IMX27_CLK_UART1_IPG_GATE] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR1, 31);
imx_check_clocks(clk, ARRAY_SIZE(clk));
clk_register_clkdev(clk[IMX27_CLK_CPU_DIV], NULL, "cpu0");
clk_prepare_enable(clk[IMX27_CLK_EMI_AHB_GATE]);
imx_print_silicon_rev("i.MX27", mx27_revision());
}
int __init mx27_clocks_init(unsigned long fref)
{
int i;
struct device_node *np;
ccm = ioremap(MX27_CCM_BASE_ADDR, SZ_4K);
clk[dummy] = imx_clk_fixed("dummy", 0);
clk[ckih] = imx_clk_fixed("ckih", fref);
clk[ckil] = imx_clk_fixed("ckil", 32768);
clk[fpm] = imx_clk_fixed_factor("fpm", "ckil", 1024, 1);
clk[ckih_div1p5] = imx_clk_fixed_factor("ckih_div1p5", "ckih", 2, 3);
_mx27_clocks_init(fref);
clk[mpll_osc_sel] = imx_clk_mux("mpll_osc_sel", CCM_CSCR, 4, 1,
mpll_osc_sel_clks,
ARRAY_SIZE(mpll_osc_sel_clks));
clk[mpll_sel] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks,
ARRAY_SIZE(mpll_sel_clks));
clk[mpll] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0);
clk[spll] = imx_clk_pllv1("spll", "ckih", CCM_SPCTL0);
clk[spll_gate] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1);
clk[mpll_main2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3);
if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
clk[ahb] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 8, 2);
clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2);
} else {
clk[ahb] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 9, 4);
clk[ipg] = imx_clk_divider("ipg", "ahb", CCM_CSCR, 8, 1);
}
clk[mshc_div] = imx_clk_divider("mshc_div", "ahb", CCM_PCDR0, 0, 6);
clk[nfc_div] = imx_clk_divider("nfc_div", "ahb", CCM_PCDR0, 6, 4);
clk[per1_div] = imx_clk_divider("per1_div", "mpll_main2", CCM_PCDR1, 0, 6);
clk[per2_div] = imx_clk_divider("per2_div", "mpll_main2", CCM_PCDR1, 8, 6);
clk[per3_div] = imx_clk_divider("per3_div", "mpll_main2", CCM_PCDR1, 16, 6);
clk[per4_div] = imx_clk_divider("per4_div", "mpll_main2", CCM_PCDR1, 24, 6);
clk[vpu_sel] = imx_clk_mux("vpu_sel", CCM_CSCR, 21, 1, vpu_sel_clks, ARRAY_SIZE(vpu_sel_clks));
clk[vpu_div] = imx_clk_divider("vpu_div", "vpu_sel", CCM_PCDR0, 10, 6);
clk[usb_div] = imx_clk_divider("usb_div", "spll_gate", CCM_CSCR, 28, 3);
clk[cpu_sel] = imx_clk_mux("cpu_sel", CCM_CSCR, 15, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks));
clk[clko_sel] = imx_clk_mux("clko_sel", CCM_CCSR, 0, 5, clko_sel_clks, ARRAY_SIZE(clko_sel_clks));
if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
clk[cpu_div] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 12, 2);
else
clk[cpu_div] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 13, 3);
clk[clko_div] = imx_clk_divider("clko_div", "clko_sel", CCM_PCDR0, 22, 3);
clk[ssi1_sel] = imx_clk_mux("ssi1_sel", CCM_CSCR, 22, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
clk[ssi2_sel] = imx_clk_mux("ssi2_sel", CCM_CSCR, 23, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
clk[ssi1_div] = imx_clk_divider("ssi1_div", "ssi1_sel", CCM_PCDR0, 16, 6);
clk[ssi2_div] = imx_clk_divider("ssi2_div", "ssi2_sel", CCM_PCDR0, 26, 6);
clk[clko_en] = imx_clk_gate("clko_en", "clko_div", CCM_PCCR0, 0);
clk[ssi2_ipg_gate] = imx_clk_gate("ssi2_ipg_gate", "ipg", CCM_PCCR0, 0);
clk[ssi1_ipg_gate] = imx_clk_gate("ssi1_ipg_gate", "ipg", CCM_PCCR0, 1);
clk[slcdc_ipg_gate] = imx_clk_gate("slcdc_ipg_gate", "ipg", CCM_PCCR0, 2);
clk[sdhc3_ipg_gate] = imx_clk_gate("sdhc3_ipg_gate", "ipg", CCM_PCCR0, 3);
clk[sdhc2_ipg_gate] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 4);
clk[sdhc1_ipg_gate] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 5);
clk[scc_ipg_gate] = imx_clk_gate("scc_ipg_gate", "ipg", CCM_PCCR0, 6);
clk[sahara_ipg_gate] = imx_clk_gate("sahara_ipg_gate", "ipg", CCM_PCCR0, 7);
clk[rtic_ipg_gate] = imx_clk_gate("rtic_ipg_gate", "ipg", CCM_PCCR0, 8);
clk[rtc_ipg_gate] = imx_clk_gate("rtc_ipg_gate", "ipg", CCM_PCCR0, 9);
clk[pwm_ipg_gate] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR0, 11);
clk[owire_ipg_gate] = imx_clk_gate("owire_ipg_gate", "ipg", CCM_PCCR0, 12);
clk[mshc_ipg_gate] = imx_clk_gate("mshc_ipg_gate", "ipg", CCM_PCCR0, 13);
clk[lcdc_ipg_gate] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 14);
clk[kpp_ipg_gate] = imx_clk_gate("kpp_ipg_gate", "ipg", CCM_PCCR0, 15);
clk[iim_ipg_gate] = imx_clk_gate("iim_ipg_gate", "ipg", CCM_PCCR0, 16);
clk[i2c2_ipg_gate] = imx_clk_gate("i2c2_ipg_gate", "ipg", CCM_PCCR0, 17);
clk[i2c1_ipg_gate] = imx_clk_gate("i2c1_ipg_gate", "ipg", CCM_PCCR0, 18);
clk[gpt6_ipg_gate] = imx_clk_gate("gpt6_ipg_gate", "ipg", CCM_PCCR0, 19);
clk[gpt5_ipg_gate] = imx_clk_gate("gpt5_ipg_gate", "ipg", CCM_PCCR0, 20);
clk[gpt4_ipg_gate] = imx_clk_gate("gpt4_ipg_gate", "ipg", CCM_PCCR0, 21);
clk[gpt3_ipg_gate] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR0, 22);
clk[gpt2_ipg_gate] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR0, 23);
clk[gpt1_ipg_gate] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR0, 24);
clk[gpio_ipg_gate] = imx_clk_gate("gpio_ipg_gate", "ipg", CCM_PCCR0, 25);
clk[fec_ipg_gate] = imx_clk_gate("fec_ipg_gate", "ipg", CCM_PCCR0, 26);
clk[emma_ipg_gate] = imx_clk_gate("emma_ipg_gate", "ipg", CCM_PCCR0, 27);
clk[dma_ipg_gate] = imx_clk_gate("dma_ipg_gate", "ipg", CCM_PCCR0, 28);
clk[cspi3_ipg_gate] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR0, 29);
clk[cspi2_ipg_gate] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 30);
clk[cspi1_ipg_gate] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 31);
clk[mshc_baud_gate] = imx_clk_gate("mshc_baud_gate", "mshc_div", CCM_PCCR1, 2);
clk[nfc_baud_gate] = imx_clk_gate("nfc_baud_gate", "nfc_div", CCM_PCCR1, 3);
clk[ssi2_baud_gate] = imx_clk_gate("ssi2_baud_gate", "ssi2_div", CCM_PCCR1, 4);
clk[ssi1_baud_gate] = imx_clk_gate("ssi1_baud_gate", "ssi1_div", CCM_PCCR1, 5);
clk[vpu_baud_gate] = imx_clk_gate("vpu_baud_gate", "vpu_div", CCM_PCCR1, 6);
clk[per4_gate] = imx_clk_gate("per4_gate", "per4_div", CCM_PCCR1, 7);
clk[per3_gate] = imx_clk_gate("per3_gate", "per3_div", CCM_PCCR1, 8);
clk[per2_gate] = imx_clk_gate("per2_gate", "per2_div", CCM_PCCR1, 9);
clk[per1_gate] = imx_clk_gate("per1_gate", "per1_div", CCM_PCCR1, 10);
clk[usb_ahb_gate] = imx_clk_gate("usb_ahb_gate", "ahb", CCM_PCCR1, 11);
clk[slcdc_ahb_gate] = imx_clk_gate("slcdc_ahb_gate", "ahb", CCM_PCCR1, 12);
clk[sahara_ahb_gate] = imx_clk_gate("sahara_ahb_gate", "ahb", CCM_PCCR1, 13);
clk[rtic_ahb_gate] = imx_clk_gate("rtic_ahb_gate", "ahb", CCM_PCCR1, 14);
clk[lcdc_ahb_gate] = imx_clk_gate("lcdc_ahb_gate", "ahb", CCM_PCCR1, 15);
clk[vpu_ahb_gate] = imx_clk_gate("vpu_ahb_gate", "ahb", CCM_PCCR1, 16);
clk[fec_ahb_gate] = imx_clk_gate("fec_ahb_gate", "ahb", CCM_PCCR1, 17);
clk[emma_ahb_gate] = imx_clk_gate("emma_ahb_gate", "ahb", CCM_PCCR1, 18);
clk[emi_ahb_gate] = imx_clk_gate("emi_ahb_gate", "ahb", CCM_PCCR1, 19);
clk[dma_ahb_gate] = imx_clk_gate("dma_ahb_gate", "ahb", CCM_PCCR1, 20);
clk[csi_ahb_gate] = imx_clk_gate("csi_ahb_gate", "ahb", CCM_PCCR1, 21);
clk[brom_ahb_gate] = imx_clk_gate("brom_ahb_gate", "ahb", CCM_PCCR1, 22);
clk[ata_ahb_gate] = imx_clk_gate("ata_ahb_gate", "ahb", CCM_PCCR1, 23);
clk[wdog_ipg_gate] = imx_clk_gate("wdog_ipg_gate", "ipg", CCM_PCCR1, 24);
clk[usb_ipg_gate] = imx_clk_gate("usb_ipg_gate", "ipg", CCM_PCCR1, 25);
clk[uart6_ipg_gate] = imx_clk_gate("uart6_ipg_gate", "ipg", CCM_PCCR1, 26);
clk[uart5_ipg_gate] = imx_clk_gate("uart5_ipg_gate", "ipg", CCM_PCCR1, 27);
clk[uart4_ipg_gate] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR1, 28);
clk[uart3_ipg_gate] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR1, 29);
clk[uart2_ipg_gate] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR1, 30);
clk[uart1_ipg_gate] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR1, 31);
for (i = 0; i < ARRAY_SIZE(clk); i++)
if (IS_ERR(clk[i]))
pr_err("i.MX27 clk %d: register failed with %ld\n",
i, PTR_ERR(clk[i]));
np = of_find_compatible_node(NULL, NULL, "fsl,imx27-ccm");
if (np) {
clk_data.clks = clk;
clk_data.clk_num = ARRAY_SIZE(clk);
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
}
clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0");
clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.0");
clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1");
clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.1");
clk_register_clkdev(clk[uart3_ipg_gate], "ipg", "imx21-uart.2");
clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.2");
clk_register_clkdev(clk[uart4_ipg_gate], "ipg", "imx21-uart.3");
clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.3");
clk_register_clkdev(clk[uart5_ipg_gate], "ipg", "imx21-uart.4");
clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.4");
clk_register_clkdev(clk[uart6_ipg_gate], "ipg", "imx21-uart.5");
clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.5");
clk_register_clkdev(clk[gpt1_ipg_gate], "ipg", "imx-gpt.0");
clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.0");
clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.0");
clk_register_clkdev(clk[sdhc1_ipg_gate], "ipg", "imx21-mmc.0");
clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.1");
clk_register_clkdev(clk[sdhc2_ipg_gate], "ipg", "imx21-mmc.1");
clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.2");
clk_register_clkdev(clk[sdhc2_ipg_gate], "ipg", "imx21-mmc.2");
clk_register_clkdev(clk[per2_gate], "per", "imx27-cspi.0");
clk_register_clkdev(clk[cspi1_ipg_gate], "ipg", "imx27-cspi.0");
clk_register_clkdev(clk[per2_gate], "per", "imx27-cspi.1");
clk_register_clkdev(clk[cspi2_ipg_gate], "ipg", "imx27-cspi.1");
clk_register_clkdev(clk[per2_gate], "per", "imx27-cspi.2");
clk_register_clkdev(clk[cspi3_ipg_gate], "ipg", "imx27-cspi.2");
clk_register_clkdev(clk[per3_gate], "per", "imx21-fb.0");
clk_register_clkdev(clk[lcdc_ipg_gate], "ipg", "imx21-fb.0");
clk_register_clkdev(clk[lcdc_ahb_gate], "ahb", "imx21-fb.0");
clk_register_clkdev(clk[csi_ahb_gate], "ahb", "imx27-camera.0");
clk_register_clkdev(clk[per4_gate], "per", "imx27-camera.0");
clk_register_clkdev(clk[usb_div], "per", "imx-udc-mx27");
clk_register_clkdev(clk[usb_ipg_gate], "ipg", "imx-udc-mx27");
clk_register_clkdev(clk[usb_ahb_gate], "ahb", "imx-udc-mx27");
clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0");
clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.0");
clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.0");
clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.1");
clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.1");
clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.1");
clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2");
clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.2");
clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.2");
clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
clk_register_clkdev(clk[nfc_baud_gate], NULL, "imx27-nand.0");
clk_register_clkdev(clk[vpu_baud_gate], "per", "coda-imx27.0");
clk_register_clkdev(clk[vpu_ahb_gate], "ahb", "coda-imx27.0");
clk_register_clkdev(clk[dma_ahb_gate], "ahb", "imx27-dma");
clk_register_clkdev(clk[dma_ipg_gate], "ipg", "imx27-dma");
clk_register_clkdev(clk[fec_ipg_gate], "ipg", "imx27-fec.0");
clk_register_clkdev(clk[fec_ahb_gate], "ahb", "imx27-fec.0");
clk_register_clkdev(clk[wdog_ipg_gate], NULL, "imx2-wdt.0");
clk_register_clkdev(clk[i2c1_ipg_gate], NULL, "imx21-i2c.0");
clk_register_clkdev(clk[i2c2_ipg_gate], NULL, "imx21-i2c.1");
clk_register_clkdev(clk[owire_ipg_gate], NULL, "mxc_w1.0");
clk_register_clkdev(clk[kpp_ipg_gate], NULL, "imx-keypad");
clk_register_clkdev(clk[emma_ahb_gate], "emma-ahb", "imx27-camera.0");
clk_register_clkdev(clk[emma_ipg_gate], "emma-ipg", "imx27-camera.0");
clk_register_clkdev(clk[emma_ahb_gate], "ahb", "m2m-emmaprp.0");
clk_register_clkdev(clk[emma_ipg_gate], "ipg", "m2m-emmaprp.0");
clk_register_clkdev(clk[cpu_div], NULL, "cpu0");
clk_register_clkdev(clk[IMX27_CLK_UART1_IPG_GATE], "ipg", "imx21-uart.0");
clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.0");
clk_register_clkdev(clk[IMX27_CLK_UART2_IPG_GATE], "ipg", "imx21-uart.1");
clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.1");
clk_register_clkdev(clk[IMX27_CLK_UART3_IPG_GATE], "ipg", "imx21-uart.2");
clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.2");
clk_register_clkdev(clk[IMX27_CLK_UART4_IPG_GATE], "ipg", "imx21-uart.3");
clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.3");
clk_register_clkdev(clk[IMX27_CLK_UART5_IPG_GATE], "ipg", "imx21-uart.4");
clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.4");
clk_register_clkdev(clk[IMX27_CLK_UART6_IPG_GATE], "ipg", "imx21-uart.5");
clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.5");
clk_register_clkdev(clk[IMX27_CLK_GPT1_IPG_GATE], "ipg", "imx-gpt.0");
clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx-gpt.0");
clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx21-mmc.0");
clk_register_clkdev(clk[IMX27_CLK_SDHC1_IPG_GATE], "ipg", "imx21-mmc.0");
clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx21-mmc.1");
clk_register_clkdev(clk[IMX27_CLK_SDHC2_IPG_GATE], "ipg", "imx21-mmc.1");
clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx21-mmc.2");
clk_register_clkdev(clk[IMX27_CLK_SDHC2_IPG_GATE], "ipg", "imx21-mmc.2");
clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx27-cspi.0");
clk_register_clkdev(clk[IMX27_CLK_CSPI1_IPG_GATE], "ipg", "imx27-cspi.0");
clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx27-cspi.1");
clk_register_clkdev(clk[IMX27_CLK_CSPI2_IPG_GATE], "ipg", "imx27-cspi.1");
clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx27-cspi.2");
clk_register_clkdev(clk[IMX27_CLK_CSPI3_IPG_GATE], "ipg", "imx27-cspi.2");
clk_register_clkdev(clk[IMX27_CLK_PER3_GATE], "per", "imx21-fb.0");
clk_register_clkdev(clk[IMX27_CLK_LCDC_IPG_GATE], "ipg", "imx21-fb.0");
clk_register_clkdev(clk[IMX27_CLK_LCDC_AHB_GATE], "ahb", "imx21-fb.0");
clk_register_clkdev(clk[IMX27_CLK_CSI_AHB_GATE], "ahb", "imx27-camera.0");
clk_register_clkdev(clk[IMX27_CLK_PER4_GATE], "per", "imx27-camera.0");
clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "imx-udc-mx27");
clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "imx-udc-mx27");
clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "imx-udc-mx27");
clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "mxc-ehci.0");
clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "mxc-ehci.0");
clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "mxc-ehci.0");
clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "mxc-ehci.1");
clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "mxc-ehci.1");
clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "mxc-ehci.1");
clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "mxc-ehci.2");
clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "mxc-ehci.2");
clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "mxc-ehci.2");
clk_register_clkdev(clk[IMX27_CLK_SSI1_IPG_GATE], NULL, "imx-ssi.0");
clk_register_clkdev(clk[IMX27_CLK_SSI2_IPG_GATE], NULL, "imx-ssi.1");
clk_register_clkdev(clk[IMX27_CLK_NFC_BAUD_GATE], NULL, "imx27-nand.0");
clk_register_clkdev(clk[IMX27_CLK_VPU_BAUD_GATE], "per", "coda-imx27.0");
clk_register_clkdev(clk[IMX27_CLK_VPU_AHB_GATE], "ahb", "coda-imx27.0");
clk_register_clkdev(clk[IMX27_CLK_DMA_AHB_GATE], "ahb", "imx27-dma");
clk_register_clkdev(clk[IMX27_CLK_DMA_IPG_GATE], "ipg", "imx27-dma");
clk_register_clkdev(clk[IMX27_CLK_FEC_IPG_GATE], "ipg", "imx27-fec.0");
clk_register_clkdev(clk[IMX27_CLK_FEC_AHB_GATE], "ahb", "imx27-fec.0");
clk_register_clkdev(clk[IMX27_CLK_WDOG_IPG_GATE], NULL, "imx2-wdt.0");
clk_register_clkdev(clk[IMX27_CLK_I2C1_IPG_GATE], NULL, "imx21-i2c.0");
clk_register_clkdev(clk[IMX27_CLK_I2C2_IPG_GATE], NULL, "imx21-i2c.1");
clk_register_clkdev(clk[IMX27_CLK_OWIRE_IPG_GATE], NULL, "mxc_w1.0");
clk_register_clkdev(clk[IMX27_CLK_KPP_IPG_GATE], NULL, "imx-keypad");
clk_register_clkdev(clk[IMX27_CLK_EMMA_AHB_GATE], "emma-ahb", "imx27-camera.0");
clk_register_clkdev(clk[IMX27_CLK_EMMA_IPG_GATE], "emma-ipg", "imx27-camera.0");
clk_register_clkdev(clk[IMX27_CLK_EMMA_AHB_GATE], "ahb", "m2m-emmaprp.0");
clk_register_clkdev(clk[IMX27_CLK_EMMA_IPG_GATE], "ipg", "m2m-emmaprp.0");
mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1);
clk_prepare_enable(clk[emi_ahb_gate]);
imx_print_silicon_rev("i.MX27", mx27_revision());
return 0;
}
int __init mx27_clocks_init_dt(void)
static void __init mx27_clocks_init_dt(struct device_node *np)
{
struct device_node *np;
struct device_node *refnp;
u32 fref = 26000000; /* default */
for_each_compatible_node(np, NULL, "fixed-clock") {
if (!of_device_is_compatible(np, "fsl,imx-osc26m"))
for_each_compatible_node(refnp, NULL, "fixed-clock") {
if (!of_device_is_compatible(refnp, "fsl,imx-osc26m"))
continue;
if (!of_property_read_u32(np, "clock-frequency", &fref))
if (!of_property_read_u32(refnp, "clock-frequency", &fref))
break;
}
return mx27_clocks_init(fref);
ccm = of_iomap(np, 0);
_mx27_clocks_init(fref);
clk_data.clks = clk;
clk_data.clk_num = ARRAY_SIZE(clk);
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
}
CLK_OF_DECLARE(imx27_ccm, "fsl,imx27-ccm", mx27_clocks_init_dt);

6
arch/arm/mach-imx/clk-imx31.c
View File

@ -51,7 +51,6 @@ static struct clk_onecell_data clk_data;
int __init mx31_clocks_init(unsigned long fref)
{
void __iomem *base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR);
int i;
struct device_node *np;
clk[dummy] = imx_clk_fixed("dummy", 0);
@ -114,10 +113,7 @@ int __init mx31_clocks_init(unsigned long fref)
clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MXC_CCM_CGR2, 10);
clk[firi_gate] = imx_clk_gate2("firi_gate", "upll", base+MXC_CCM_CGR2, 12);
for (i = 0; i < ARRAY_SIZE(clk); i++)
if (IS_ERR(clk[i]))
pr_err("imx31 clk %d: register failed with %ld\n",
i, PTR_ERR(clk[i]));
imx_check_clocks(clk, ARRAY_SIZE(clk));
np = of_find_compatible_node(NULL, NULL, "fsl,imx31-ccm");

6
arch/arm/mach-imx/clk-imx35.c
View File

@ -75,7 +75,6 @@ int __init mx35_clocks_init(void)
u32 pdr0, consumer_sel, hsp_sel;
struct arm_ahb_div *aad;
unsigned char *hsp_div;
u32 i;
pdr0 = __raw_readl(base + MXC_CCM_PDR0);
consumer_sel = (pdr0 >> 16) & 0xf;
@ -200,10 +199,7 @@ int __init mx35_clocks_init(void)
clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MX35_CCM_CGR3, 2);
clk[gpu2d_gate] = imx_clk_gate2("gpu2d_gate", "ahb", base + MX35_CCM_CGR3, 4);
for (i = 0; i < ARRAY_SIZE(clk); i++)
if (IS_ERR(clk[i]))
pr_err("i.MX35 clk %d: register failed with %ld\n",
i, PTR_ERR(clk[i]));
imx_check_clocks(clk, ARRAY_SIZE(clk));
clk_register_clkdev(clk[pata_gate], NULL, "pata_imx");
clk_register_clkdev(clk[can1_gate], NULL, "flexcan.0");

256
arch/arm/mach-imx/clk-imx51-imx53.c
View File

@ -18,11 +18,54 @@
#include <linux/of_irq.h>
#include <dt-bindings/clock/imx5-clock.h>
#include "crm-regs-imx5.h"
#include "clk.h"
#include "common.h"
#include "hardware.h"
#define MX51_DPLL1_BASE 0x83f80000
#define MX51_DPLL2_BASE 0x83f84000
#define MX51_DPLL3_BASE 0x83f88000
#define MX53_DPLL1_BASE 0x63f80000
#define MX53_DPLL2_BASE 0x63f84000
#define MX53_DPLL3_BASE 0x63f88000
#define MX53_DPLL4_BASE 0x63f8c000
#define MXC_CCM_CCR (ccm_base + 0x00)
#define MXC_CCM_CCDR (ccm_base + 0x04)
#define MXC_CCM_CSR (ccm_base + 0x08)
#define MXC_CCM_CCSR (ccm_base + 0x0c)
#define MXC_CCM_CACRR (ccm_base + 0x10)
#define MXC_CCM_CBCDR (ccm_base + 0x14)
#define MXC_CCM_CBCMR (ccm_base + 0x18)
#define MXC_CCM_CSCMR1 (ccm_base + 0x1c)
#define MXC_CCM_CSCMR2 (ccm_base + 0x20)
#define MXC_CCM_CSCDR1 (ccm_base + 0x24)
#define MXC_CCM_CS1CDR (ccm_base + 0x28)
#define MXC_CCM_CS2CDR (ccm_base + 0x2c)
#define MXC_CCM_CDCDR (ccm_base + 0x30)
#define MXC_CCM_CHSCDR (ccm_base + 0x34)
#define MXC_CCM_CSCDR2 (ccm_base + 0x38)
#define MXC_CCM_CSCDR3 (ccm_base + 0x3c)
#define MXC_CCM_CSCDR4 (ccm_base + 0x40)
#define MXC_CCM_CWDR (ccm_base + 0x44)
#define MXC_CCM_CDHIPR (ccm_base + 0x48)
#define MXC_CCM_CDCR (ccm_base + 0x4c)
#define MXC_CCM_CTOR (ccm_base + 0x50)
#define MXC_CCM_CLPCR (ccm_base + 0x54)
#define MXC_CCM_CISR (ccm_base + 0x58)
#define MXC_CCM_CIMR (ccm_base + 0x5c)
#define MXC_CCM_CCOSR (ccm_base + 0x60)
#define MXC_CCM_CGPR (ccm_base + 0x64)
#define MXC_CCM_CCGR0 (ccm_base + 0x68)
#define MXC_CCM_CCGR1 (ccm_base + 0x6c)
#define MXC_CCM_CCGR2 (ccm_base + 0x70)
#define MXC_CCM_CCGR3 (ccm_base + 0x74)
#define MXC_CCM_CCGR4 (ccm_base + 0x78)
#define MXC_CCM_CCGR5 (ccm_base + 0x7c)
#define MXC_CCM_CCGR6 (ccm_base + 0x80)
#define MXC_CCM_CCGR7 (ccm_base + 0x84)
/* Low-power Audio Playback Mode clock */
static const char *lp_apm_sel[] = { "osc", };
@ -86,17 +129,15 @@ static const char *mx51_spdif1_com_sel[] = { "spdif1_podf", "ssi2_root_gate", };
static struct clk *clk[IMX5_CLK_END];
static struct clk_onecell_data clk_data;
static void __init mx5_clocks_common_init(unsigned long rate_ckil,
unsigned long rate_osc, unsigned long rate_ckih1,
unsigned long rate_ckih2)
static void __init mx5_clocks_common_init(void __iomem *ccm_base)
{
int i;
imx5_pm_set_ccm_base(ccm_base);
clk[IMX5_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
clk[IMX5_CLK_CKIL] = imx_obtain_fixed_clock("ckil", rate_ckil);
clk[IMX5_CLK_OSC] = imx_obtain_fixed_clock("osc", rate_osc);
clk[IMX5_CLK_CKIH1] = imx_obtain_fixed_clock("ckih1", rate_ckih1);
clk[IMX5_CLK_CKIH2] = imx_obtain_fixed_clock("ckih2", rate_ckih2);
clk[IMX5_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0);
clk[IMX5_CLK_OSC] = imx_obtain_fixed_clock("osc", 0);
clk[IMX5_CLK_CKIH1] = imx_obtain_fixed_clock("ckih1", 0);
clk[IMX5_CLK_CKIH2] = imx_obtain_fixed_clock("ckih2", 0);
clk[IMX5_CLK_PERIPH_APM] = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2,
periph_apm_sel, ARRAY_SIZE(periph_apm_sel));
@ -244,58 +285,8 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
clk[IMX5_CLK_SAHARA_IPG_GATE] = imx_clk_gate2("sahara_ipg_gate", "ipg", MXC_CCM_CCGR4, 14);
clk[IMX5_CLK_SATA_REF] = imx_clk_fixed_factor("sata_ref", "usb_phy1_gate", 1, 1);
for (i = 0; i < ARRAY_SIZE(clk); i++)
if (IS_ERR(clk[i]))
pr_err("i.MX5 clk %d: register failed with %ld\n",
i, PTR_ERR(clk[i]));
clk_register_clkdev(clk[IMX5_CLK_GPT_HF_GATE], "per", "imx-gpt.0");
clk_register_clkdev(clk[IMX5_CLK_GPT_IPG_GATE], "ipg", "imx-gpt.0");
clk_register_clkdev(clk[IMX5_CLK_UART1_PER_GATE], "per", "imx21-uart.0");
clk_register_clkdev(clk[IMX5_CLK_UART1_IPG_GATE], "ipg", "imx21-uart.0");
clk_register_clkdev(clk[IMX5_CLK_UART2_PER_GATE], "per", "imx21-uart.1");
clk_register_clkdev(clk[IMX5_CLK_UART2_IPG_GATE], "ipg", "imx21-uart.1");
clk_register_clkdev(clk[IMX5_CLK_UART3_PER_GATE], "per", "imx21-uart.2");
clk_register_clkdev(clk[IMX5_CLK_UART3_IPG_GATE], "ipg", "imx21-uart.2");
clk_register_clkdev(clk[IMX5_CLK_UART4_PER_GATE], "per", "imx21-uart.3");
clk_register_clkdev(clk[IMX5_CLK_UART4_IPG_GATE], "ipg", "imx21-uart.3");
clk_register_clkdev(clk[IMX5_CLK_UART5_PER_GATE], "per", "imx21-uart.4");
clk_register_clkdev(clk[IMX5_CLK_UART5_IPG_GATE], "ipg", "imx21-uart.4");
clk_register_clkdev(clk[IMX5_CLK_ECSPI1_PER_GATE], "per", "imx51-ecspi.0");
clk_register_clkdev(clk[IMX5_CLK_ECSPI1_IPG_GATE], "ipg", "imx51-ecspi.0");
clk_register_clkdev(clk[IMX5_CLK_ECSPI2_PER_GATE], "per", "imx51-ecspi.1");
clk_register_clkdev(clk[IMX5_CLK_ECSPI2_IPG_GATE], "ipg", "imx51-ecspi.1");
clk_register_clkdev(clk[IMX5_CLK_CSPI_IPG_GATE], NULL, "imx35-cspi.2");
clk_register_clkdev(clk[IMX5_CLK_I2C1_GATE], NULL, "imx21-i2c.0");
clk_register_clkdev(clk[IMX5_CLK_I2C2_GATE], NULL, "imx21-i2c.1");
clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "mxc-ehci.0");
clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "mxc-ehci.0");
clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "mxc-ehci.0");
clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "mxc-ehci.1");
clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "mxc-ehci.1");
clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "mxc-ehci.1");
clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "mxc-ehci.2");
clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "mxc-ehci.2");
clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "mxc-ehci.2");
clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "imx-udc-mx51");
clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "imx-udc-mx51");
clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "imx-udc-mx51");
clk_register_clkdev(clk[IMX5_CLK_NFC_GATE], NULL, "imx51-nand");
clk_register_clkdev(clk[IMX5_CLK_SSI1_IPG_GATE], NULL, "imx-ssi.0");
clk_register_clkdev(clk[IMX5_CLK_SSI2_IPG_GATE], NULL, "imx-ssi.1");
clk_register_clkdev(clk[IMX5_CLK_SSI3_IPG_GATE], NULL, "imx-ssi.2");
clk_register_clkdev(clk[IMX5_CLK_SDMA_GATE], NULL, "imx35-sdma");
clk_register_clkdev(clk[IMX5_CLK_CPU_PODF], NULL, "cpu0");
clk_register_clkdev(clk[IMX5_CLK_IIM_GATE], "iim", NULL);
clk_register_clkdev(clk[IMX5_CLK_DUMMY], NULL, "imx2-wdt.0");
clk_register_clkdev(clk[IMX5_CLK_DUMMY], NULL, "imx2-wdt.1");
clk_register_clkdev(clk[IMX5_CLK_DUMMY], NULL, "imx-keypad");
clk_register_clkdev(clk[IMX5_CLK_IPU_DI1_GATE], "di1", "imx-tve.0");
clk_register_clkdev(clk[IMX5_CLK_GPC_DVFS], "gpc_dvfs", NULL);
clk_register_clkdev(clk[IMX5_CLK_EPIT1_IPG_GATE], "ipg", "imx-epit.0");
clk_register_clkdev(clk[IMX5_CLK_EPIT1_HF_GATE], "per", "imx-epit.0");
clk_register_clkdev(clk[IMX5_CLK_EPIT2_IPG_GATE], "ipg", "imx-epit.1");
clk_register_clkdev(clk[IMX5_CLK_EPIT2_HF_GATE], "per", "imx-epit.1");
/* Set SDHC parents to be PLL2 */
clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]);
@ -322,12 +313,26 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
static void __init mx50_clocks_init(struct device_node *np)
{
void __iomem *ccm_base;
void __iomem *pll_base;
unsigned long r;
int i;
clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE);
pll_base = ioremap(MX53_DPLL1_BASE, SZ_16K);
WARN_ON(!pll_base);
clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", pll_base);
pll_base = ioremap(MX53_DPLL2_BASE, SZ_16K);
WARN_ON(!pll_base);
clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base);
pll_base = ioremap(MX53_DPLL3_BASE, SZ_16K);
WARN_ON(!pll_base);
clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", pll_base);
ccm_base = of_iomap(np, 0);
WARN_ON(!ccm_base);
mx5_clocks_common_init(ccm_base);
clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1,
lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
@ -349,17 +354,12 @@ static void __init mx50_clocks_init(struct device_node *np)
clk[IMX5_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3);
clk[IMX5_CLK_CKO2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
for (i = 0; i < ARRAY_SIZE(clk); i++)
if (IS_ERR(clk[i]))
pr_err("i.MX50 clk %d: register failed with %ld\n",
i, PTR_ERR(clk[i]));
imx_check_clocks(clk, ARRAY_SIZE(clk));
clk_data.clks = clk;
clk_data.clk_num = ARRAY_SIZE(clk);
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
mx5_clocks_common_init(0, 0, 0, 0);
/* set SDHC root clock to 200MHZ*/
clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000);
clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000);
@ -370,21 +370,32 @@ static void __init mx50_clocks_init(struct device_node *np)
r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx50-gpt"));
}
CLK_OF_DECLARE(imx50_ccm, "fsl,imx50-ccm", mx50_clocks_init);
int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
unsigned long rate_ckih1, unsigned long rate_ckih2)
static void __init mx51_clocks_init(struct device_node *np)
{
int i;
void __iomem *ccm_base;
void __iomem *pll_base;
u32 val;
struct device_node *np;
clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", MX51_DPLL1_BASE);
clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", MX51_DPLL2_BASE);
clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", MX51_DPLL3_BASE);
pll_base = ioremap(MX51_DPLL1_BASE, SZ_16K);
WARN_ON(!pll_base);
clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", pll_base);
pll_base = ioremap(MX51_DPLL2_BASE, SZ_16K);
WARN_ON(!pll_base);
clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base);
pll_base = ioremap(MX51_DPLL3_BASE, SZ_16K);
WARN_ON(!pll_base);
clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", pll_base);
ccm_base = of_iomap(np, 0);
WARN_ON(!ccm_base);
mx5_clocks_common_init(ccm_base);
clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1,
lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
clk[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
@ -417,35 +428,12 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
mx51_spdif1_com_sel, ARRAY_SIZE(mx51_spdif1_com_sel));
clk[IMX5_CLK_SPDIF1_GATE] = imx_clk_gate2("spdif1_gate", "spdif1_com_sel", MXC_CCM_CCGR5, 28);
for (i = 0; i < ARRAY_SIZE(clk); i++)
if (IS_ERR(clk[i]))
pr_err("i.MX51 clk %d: register failed with %ld\n",
i, PTR_ERR(clk[i]));
imx_check_clocks(clk, ARRAY_SIZE(clk));
np = of_find_compatible_node(NULL, NULL, "fsl,imx51-ccm");
clk_data.clks = clk;
clk_data.clk_num = ARRAY_SIZE(clk);
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
clk_register_clkdev(clk[IMX5_CLK_HSI2C_GATE], NULL, "imx21-i2c.2");
clk_register_clkdev(clk[IMX5_CLK_MX51_MIPI], "mipi_hsp", NULL);
clk_register_clkdev(clk[IMX5_CLK_FEC_GATE], NULL, "imx27-fec.0");
clk_register_clkdev(clk[IMX5_CLK_USB_PHY_GATE], "phy", "mxc-ehci.0");
clk_register_clkdev(clk[IMX5_CLK_ESDHC1_IPG_GATE], "ipg", "sdhci-esdhc-imx51.0");
clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.0");
clk_register_clkdev(clk[IMX5_CLK_ESDHC1_PER_GATE], "per", "sdhci-esdhc-imx51.0");
clk_register_clkdev(clk[IMX5_CLK_ESDHC2_IPG_GATE], "ipg", "sdhci-esdhc-imx51.1");
clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.1");
clk_register_clkdev(clk[IMX5_CLK_ESDHC2_PER_GATE], "per", "sdhci-esdhc-imx51.1");
clk_register_clkdev(clk[IMX5_CLK_ESDHC3_IPG_GATE], "ipg", "sdhci-esdhc-imx51.2");
clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.2");
clk_register_clkdev(clk[IMX5_CLK_ESDHC3_PER_GATE], "per", "sdhci-esdhc-imx51.2");
clk_register_clkdev(clk[IMX5_CLK_ESDHC4_IPG_GATE], "ipg", "sdhci-esdhc-imx51.3");
clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.3");
clk_register_clkdev(clk[IMX5_CLK_ESDHC4_PER_GATE], "per", "sdhci-esdhc-imx51.3");
/* set the usboh3 parent to pll2_sw */
clk_set_parent(clk[IMX5_CLK_USBOH3_SEL], clk[IMX5_CLK_PLL2_SW]);
@ -453,9 +441,6 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 166250000);
clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 166250000);
/* System timer */
mxc_timer_init(MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), MX51_INT_GPT);
clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]);
imx_print_silicon_rev("i.MX51", mx51_revision());
clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]);
@ -474,25 +459,35 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
val = readl(MXC_CCM_CLPCR);
val |= 1 << 23;
writel(val, MXC_CCM_CLPCR);
return 0;
}
static void __init mx51_clocks_init_dt(struct device_node *np)
{
mx51_clocks_init(0, 0, 0, 0);
}
CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init_dt);
CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init);
static void __init mx53_clocks_init(struct device_node *np)
{
int i;
void __iomem *ccm_base;
void __iomem *pll_base;
unsigned long r;
clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE);
clk[IMX5_CLK_PLL4_SW] = imx_clk_pllv2("pll4_sw", "osc", MX53_DPLL4_BASE);
pll_base = ioremap(MX53_DPLL1_BASE, SZ_16K);
WARN_ON(!pll_base);
clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", pll_base);
pll_base = ioremap(MX53_DPLL2_BASE, SZ_16K);
WARN_ON(!pll_base);
clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base);
pll_base = ioremap(MX53_DPLL3_BASE, SZ_16K);
WARN_ON(!pll_base);
clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", pll_base);
pll_base = ioremap(MX53_DPLL4_BASE, SZ_16K);
WARN_ON(!pll_base);
clk[IMX5_CLK_PLL4_SW] = imx_clk_pllv2("pll4_sw", "osc", pll_base);
ccm_base = of_iomap(np, 0);
WARN_ON(!ccm_base);
mx5_clocks_common_init(ccm_base);
clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1,
lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
@ -543,33 +538,12 @@ static void __init mx53_clocks_init(struct device_node *np)
clk[IMX5_CLK_SPDIF_XTAL_SEL] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
mx53_spdif_xtal_sel, ARRAY_SIZE(mx53_spdif_xtal_sel));
for (i = 0; i < ARRAY_SIZE(clk); i++)
if (IS_ERR(clk[i]))
pr_err("i.MX53 clk %d: register failed with %ld\n",
i, PTR_ERR(clk[i]));
imx_check_clocks(clk, ARRAY_SIZE(clk));
clk_data.clks = clk;
clk_data.clk_num = ARRAY_SIZE(clk);
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
mx5_clocks_common_init(0, 0, 0, 0);
clk_register_clkdev(clk[IMX5_CLK_I2C3_GATE], NULL, "imx21-i2c.2");
clk_register_clkdev(clk[IMX5_CLK_FEC_GATE], NULL, "imx25-fec.0");
clk_register_clkdev(clk[IMX5_CLK_USB_PHY1_GATE], "usb_phy1", "mxc-ehci.0");
clk_register_clkdev(clk[IMX5_CLK_ESDHC1_IPG_GATE], "ipg", "sdhci-esdhc-imx53.0");
clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.0");
clk_register_clkdev(clk[IMX5_CLK_ESDHC1_PER_GATE], "per", "sdhci-esdhc-imx53.0");
clk_register_clkdev(clk[IMX5_CLK_ESDHC2_IPG_GATE], "ipg", "sdhci-esdhc-imx53.1");
clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.1");
clk_register_clkdev(clk[IMX5_CLK_ESDHC2_PER_GATE], "per", "sdhci-esdhc-imx53.1");
clk_register_clkdev(clk[IMX5_CLK_ESDHC3_IPG_GATE], "ipg", "sdhci-esdhc-imx53.2");
clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.2");
clk_register_clkdev(clk[IMX5_CLK_ESDHC3_PER_GATE], "per", "sdhci-esdhc-imx53.2");
clk_register_clkdev(clk[IMX5_CLK_ESDHC4_IPG_GATE], "ipg", "sdhci-esdhc-imx53.3");
clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.3");
clk_register_clkdev(clk[IMX5_CLK_ESDHC4_PER_GATE], "per", "sdhci-esdhc-imx53.3");
/* set SDHC root clock to 200MHZ*/
clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000);
clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000);
@ -583,7 +557,5 @@ static void __init mx53_clocks_init(struct device_node *np)
r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx53-gpt"));
}
CLK_OF_DECLARE(imx53_ccm, "fsl,imx53-ccm", mx53_clocks_init);

524
arch/arm/mach-imx/clk-imx6q.c
View File

@ -19,6 +19,7 @@
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <dt-bindings/clock/imx6qdl-clock.h>
#include "clk.h"
#include "common.h"
@ -73,48 +74,13 @@ static const char *lvds_sels[] = {
"pcie_ref_125m", "sata_ref_100m",
};
enum mx6q_clks {
dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m,
pll3_pfd0_720m, pll3_pfd1_540m, pll3_pfd2_508m, pll3_pfd3_454m,
pll2_198m, pll3_120m, pll3_80m, pll3_60m, twd, step, pll1_sw,
periph_pre, periph2_pre, periph_clk2_sel, periph2_clk2_sel, axi_sel,
esai_sel, asrc_sel, spdif_sel, gpu2d_axi, gpu3d_axi, gpu2d_core_sel,
gpu3d_core_sel, gpu3d_shader_sel, ipu1_sel, ipu2_sel, ldb_di0_sel,
ldb_di1_sel, ipu1_di0_pre_sel, ipu1_di1_pre_sel, ipu2_di0_pre_sel,
ipu2_di1_pre_sel, ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel,
ipu2_di1_sel, hsi_tx_sel, pcie_axi_sel, ssi1_sel, ssi2_sel, ssi3_sel,
usdhc1_sel, usdhc2_sel, usdhc3_sel, usdhc4_sel, enfc_sel, emi_sel,
emi_slow_sel, vdo_axi_sel, vpu_axi_sel, cko1_sel, periph, periph2,
periph_clk2, periph2_clk2, ipg, ipg_per, esai_pred, esai_podf,
asrc_pred, asrc_podf, spdif_pred, spdif_podf, can_root, ecspi_root,
gpu2d_core_podf, gpu3d_core_podf, gpu3d_shader, ipu1_podf, ipu2_podf,
ldb_di0_podf, ldb_di1_podf, ipu1_di0_pre, ipu1_di1_pre, ipu2_di0_pre,
ipu2_di1_pre, hsi_tx_podf, ssi1_pred, ssi1_podf, ssi2_pred, ssi2_podf,
ssi3_pred, ssi3_podf, uart_serial_podf, usdhc1_podf, usdhc2_podf,
usdhc3_podf, usdhc4_podf, enfc_pred, enfc_podf, emi_podf,
emi_slow_podf, vpu_axi_podf, cko1_podf, axi, mmdc_ch0_axi_podf,
mmdc_ch1_axi_podf, arm, ahb, apbh_dma, asrc, can1_ipg, can1_serial,
can2_ipg, can2_serial, ecspi1, ecspi2, ecspi3, ecspi4, ecspi5, enet,
esai, gpt_ipg, gpt_ipg_per, gpu2d_core, gpu3d_core, hdmi_iahb,
hdmi_isfr, i2c1, i2c2, i2c3, iim, enfc, ipu1, ipu1_di0, ipu1_di1, ipu2,
ipu2_di0, ldb_di0, ldb_di1, ipu2_di1, hsi_tx, mlb, mmdc_ch0_axi,
mmdc_ch1_axi, ocram, openvg_axi, pcie_axi, pwm1, pwm2, pwm3, pwm4, per1_bch,
gpmi_bch_apb, gpmi_bch, gpmi_io, gpmi_apb, sata, sdma, spba, ssi1,
ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3,
usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg,
pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg,
ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate,
usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow,
spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, pll4_audio_div,
lvds1_sel, lvds2_sel, lvds1_gate, lvds2_gate, esai_ahb, clk_max
};
static struct clk *clk[clk_max];
static struct clk *clk[IMX6QDL_CLK_END];
static struct clk_onecell_data clk_data;
static enum mx6q_clks const clks_init_on[] __initconst = {
mmdc_ch0_axi, rom, arm,
static unsigned int const clks_init_on[] __initconst = {
IMX6QDL_CLK_MMDC_CH0_AXI,
IMX6QDL_CLK_ROM,
IMX6QDL_CLK_ARM,
};
static struct clk_div_table clk_enet_ref_table[] = {
@ -149,10 +115,10 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
int i;
int ret;
clk[dummy] = imx_clk_fixed("dummy", 0);
clk[ckil] = imx_obtain_fixed_clock("ckil", 0);
clk[ckih] = imx_obtain_fixed_clock("ckih1", 0);
clk[osc] = imx_obtain_fixed_clock("osc", 0);
clk[IMX6QDL_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
clk[IMX6QDL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0);
clk[IMX6QDL_CLK_CKIH] = imx_obtain_fixed_clock("ckih1", 0);
clk[IMX6QDL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0);
np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
base = of_iomap(np, 0);
@ -166,14 +132,14 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
video_div_table[2].div = 1;
};
/* type name parent_name base div_mask */
clk[pll1_sys] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f);
clk[pll2_bus] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1);
clk[pll3_usb_otg] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3);
clk[pll4_audio] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x7f);
clk[pll5_video] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f);
clk[pll6_enet] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3);
clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x3);
/* type name parent_name base div_mask */
clk[IMX6QDL_CLK_PLL1_SYS] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f);
clk[IMX6QDL_CLK_PLL2_BUS] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1);
clk[IMX6QDL_CLK_PLL3_USB_OTG] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3);
clk[IMX6QDL_CLK_PLL4_AUDIO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x7f);
clk[IMX6QDL_CLK_PLL5_VIDEO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f);
clk[IMX6QDL_CLK_PLL6_ENET] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3);
clk[IMX6QDL_CLK_PLL7_USB_HOST] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x3);
/*
* Bit 20 is the reserved and read-only bit, we do this only for:
@ -181,28 +147,28 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
* - Keep refcount when do usbphy clk_enable/disable, in that case,
* the clk framework may need to enable/disable usbphy's parent
*/
clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20);
clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20);
clk[IMX6QDL_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20);
clk[IMX6QDL_CLK_USBPHY2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20);
/*
* usbphy*_gate needs to be on after system boots up, and software
* never needs to control it anymore.
*/
clk[usbphy1_gate] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6);
clk[usbphy2_gate] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6);
clk[IMX6QDL_CLK_USBPHY1_GATE] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6);
clk[IMX6QDL_CLK_USBPHY2_GATE] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6);
clk[sata_ref] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5);
clk[pcie_ref] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4);
clk[IMX6QDL_CLK_SATA_REF] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5);
clk[IMX6QDL_CLK_PCIE_REF] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4);
clk[sata_ref_100m] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20);
clk[pcie_ref_125m] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
clk[IMX6QDL_CLK_SATA_REF_100M] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20);
clk[IMX6QDL_CLK_PCIE_REF_125M] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
clk[enet_ref] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
clk[IMX6QDL_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
base + 0xe0, 0, 2, 0, clk_enet_ref_table,
&imx_ccm_lock);
clk[lvds1_sel] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
clk[lvds2_sel] = imx_clk_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
clk[IMX6QDL_CLK_LVDS1_SEL] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
clk[IMX6QDL_CLK_LVDS2_SEL] = imx_clk_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
/*
* lvds1_gate and lvds2_gate are pseudo-gates. Both can be
@ -210,29 +176,29 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
* the "output_enable" bit as a gate, even though it's really just
* enabling clock output.
*/
clk[lvds1_gate] = imx_clk_gate("lvds1_gate", "lvds1_sel", base + 0x160, 10);
clk[lvds2_gate] = imx_clk_gate("lvds2_gate", "lvds2_sel", base + 0x160, 11);
clk[IMX6QDL_CLK_LVDS1_GATE] = imx_clk_gate("lvds1_gate", "lvds1_sel", base + 0x160, 10);
clk[IMX6QDL_CLK_LVDS2_GATE] = imx_clk_gate("lvds2_gate", "lvds2_sel", base + 0x160, 11);
/* name parent_name reg idx */
clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1);
clk[pll2_pfd2_396m] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2);
clk[pll3_pfd0_720m] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0);
clk[pll3_pfd1_540m] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1);
clk[pll3_pfd2_508m] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2);
clk[pll3_pfd3_454m] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3);
/* name parent_name reg idx */
clk[IMX6QDL_CLK_PLL2_PFD0_352M] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
clk[IMX6QDL_CLK_PLL2_PFD1_594M] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1);
clk[IMX6QDL_CLK_PLL2_PFD2_396M] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2);
clk[IMX6QDL_CLK_PLL3_PFD0_720M] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0);
clk[IMX6QDL_CLK_PLL3_PFD1_540M] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1);
clk[IMX6QDL_CLK_PLL3_PFD2_508M] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2);
clk[IMX6QDL_CLK_PLL3_PFD3_454M] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3);
/* name parent_name mult div */
clk[pll2_198m] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2);
clk[pll3_120m] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4);
clk[pll3_80m] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6);
clk[pll3_60m] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8);
clk[twd] = imx_clk_fixed_factor("twd", "arm", 1, 2);
/* name parent_name mult div */
clk[IMX6QDL_CLK_PLL2_198M] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2);
clk[IMX6QDL_CLK_PLL3_120M] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4);
clk[IMX6QDL_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6);
clk[IMX6QDL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8);
clk[IMX6QDL_CLK_TWD] = imx_clk_fixed_factor("twd", "arm", 1, 2);
clk[pll4_post_div] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
clk[pll4_audio_div] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
clk[pll5_post_div] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
clk[pll5_video_div] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
clk[IMX6QDL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
clk[IMX6QDL_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
clk[IMX6QDL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
clk[IMX6QDL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
np = ccm_node;
base = of_iomap(np, 0);
@ -240,262 +206,254 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
imx6q_pm_set_ccm_base(base);
/* name reg shift width parent_names num_parents */
clk[step] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels));
clk[pll1_sw] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels));
clk[periph_pre] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
clk[periph2_pre] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
clk[periph_clk2_sel] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
clk[periph2_clk2_sel] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
clk[axi_sel] = imx_clk_mux("axi_sel", base + 0x14, 6, 2, axi_sels, ARRAY_SIZE(axi_sels));
clk[esai_sel] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels));
clk[asrc_sel] = imx_clk_mux("asrc_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels));
clk[spdif_sel] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels));
clk[gpu2d_axi] = imx_clk_mux("gpu2d_axi", base + 0x18, 0, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
clk[gpu3d_axi] = imx_clk_mux("gpu3d_axi", base + 0x18, 1, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
clk[gpu2d_core_sel] = imx_clk_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels));
clk[gpu3d_core_sel] = imx_clk_mux("gpu3d_core_sel", base + 0x18, 4, 2, gpu3d_core_sels, ARRAY_SIZE(gpu3d_core_sels));
clk[gpu3d_shader_sel] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels));
clk[ipu1_sel] = imx_clk_mux("ipu1_sel", base + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
clk[ipu2_sel] = imx_clk_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
clk[ldb_di0_sel] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
clk[ldb_di1_sel] = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
clk[ipu1_di0_pre_sel] = imx_clk_mux_flags("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
clk[ipu1_di1_pre_sel] = imx_clk_mux_flags("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
clk[ipu2_di0_pre_sel] = imx_clk_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
clk[ipu2_di1_pre_sel] = imx_clk_mux_flags("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
clk[ipu1_di0_sel] = imx_clk_mux_flags("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels), CLK_SET_RATE_PARENT);
clk[ipu1_di1_sel] = imx_clk_mux_flags("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels), CLK_SET_RATE_PARENT);
clk[ipu2_di0_sel] = imx_clk_mux_flags("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels), CLK_SET_RATE_PARENT);
clk[ipu2_di1_sel] = imx_clk_mux_flags("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels), CLK_SET_RATE_PARENT);
clk[hsi_tx_sel] = imx_clk_mux("hsi_tx_sel", base + 0x30, 28, 1, hsi_tx_sels, ARRAY_SIZE(hsi_tx_sels));
clk[pcie_axi_sel] = imx_clk_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels));
clk[ssi1_sel] = imx_clk_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
clk[ssi2_sel] = imx_clk_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
clk[ssi3_sel] = imx_clk_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
clk[usdhc1_sel] = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
clk[usdhc2_sel] = imx_clk_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
clk[usdhc3_sel] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
clk[usdhc4_sel] = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
clk[enfc_sel] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels));
clk[emi_sel] = imx_clk_fixup_mux("emi_sel", base + 0x1c, 27, 2, emi_sels, ARRAY_SIZE(emi_sels), imx_cscmr1_fixup);
clk[emi_slow_sel] = imx_clk_fixup_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_slow_sels, ARRAY_SIZE(emi_slow_sels), imx_cscmr1_fixup);
clk[vdo_axi_sel] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels));
clk[vpu_axi_sel] = imx_clk_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels));
clk[cko1_sel] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels));
clk[cko2_sel] = imx_clk_mux("cko2_sel", base + 0x60, 16, 5, cko2_sels, ARRAY_SIZE(cko2_sels));
clk[cko] = imx_clk_mux("cko", base + 0x60, 8, 1, cko_sels, ARRAY_SIZE(cko_sels));
/* name reg shift width parent_names num_parents */
clk[IMX6QDL_CLK_STEP] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels));
clk[IMX6QDL_CLK_PLL1_SW] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels));
clk[IMX6QDL_CLK_PERIPH_PRE] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
clk[IMX6QDL_CLK_PERIPH2_PRE] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
clk[IMX6QDL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
clk[IMX6QDL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
clk[IMX6QDL_CLK_AXI_SEL] = imx_clk_mux("axi_sel", base + 0x14, 6, 2, axi_sels, ARRAY_SIZE(axi_sels));
clk[IMX6QDL_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels));
clk[IMX6QDL_CLK_ASRC_SEL] = imx_clk_mux("asrc_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels));
clk[IMX6QDL_CLK_SPDIF_SEL] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels));
clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_mux("gpu2d_axi", base + 0x18, 0, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_mux("gpu3d_axi", base + 0x18, 1, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
clk[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels));
clk[IMX6QDL_CLK_GPU3D_CORE_SEL] = imx_clk_mux("gpu3d_core_sel", base + 0x18, 4, 2, gpu3d_core_sels, ARRAY_SIZE(gpu3d_core_sels));
clk[IMX6QDL_CLK_GPU3D_SHADER_SEL] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels));
clk[IMX6QDL_CLK_IPU1_SEL] = imx_clk_mux("ipu1_sel", base + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
clk[IMX6QDL_CLK_IPU2_SEL] = imx_clk_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
clk[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
clk[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL] = imx_clk_mux_flags("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL] = imx_clk_mux_flags("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL] = imx_clk_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
clk[IMX6QDL_CLK_IPU2_DI1_PRE_SEL] = imx_clk_mux_flags("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
clk[IMX6QDL_CLK_IPU1_DI0_SEL] = imx_clk_mux_flags("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels), CLK_SET_RATE_PARENT);
clk[IMX6QDL_CLK_IPU1_DI1_SEL] = imx_clk_mux_flags("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels), CLK_SET_RATE_PARENT);
clk[IMX6QDL_CLK_IPU2_DI0_SEL] = imx_clk_mux_flags("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels), CLK_SET_RATE_PARENT);
clk[IMX6QDL_CLK_IPU2_DI1_SEL] = imx_clk_mux_flags("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels), CLK_SET_RATE_PARENT);
clk[IMX6QDL_CLK_HSI_TX_SEL] = imx_clk_mux("hsi_tx_sel", base + 0x30, 28, 1, hsi_tx_sels, ARRAY_SIZE(hsi_tx_sels));
clk[IMX6QDL_CLK_PCIE_AXI_SEL] = imx_clk_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels));
clk[IMX6QDL_CLK_SSI1_SEL] = imx_clk_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
clk[IMX6QDL_CLK_SSI2_SEL] = imx_clk_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
clk[IMX6QDL_CLK_SSI3_SEL] = imx_clk_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
clk[IMX6QDL_CLK_USDHC1_SEL] = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
clk[IMX6QDL_CLK_USDHC2_SEL] = imx_clk_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
clk[IMX6QDL_CLK_USDHC3_SEL] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
clk[IMX6QDL_CLK_USDHC4_SEL] = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
clk[IMX6QDL_CLK_ENFC_SEL] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels));
clk[IMX6QDL_CLK_EMI_SEL] = imx_clk_fixup_mux("emi_sel", base + 0x1c, 27, 2, emi_sels, ARRAY_SIZE(emi_sels), imx_cscmr1_fixup);
clk[IMX6QDL_CLK_EMI_SLOW_SEL] = imx_clk_fixup_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_slow_sels, ARRAY_SIZE(emi_slow_sels), imx_cscmr1_fixup);
clk[IMX6QDL_CLK_VDO_AXI_SEL] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels));
clk[IMX6QDL_CLK_VPU_AXI_SEL] = imx_clk_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels));
clk[IMX6QDL_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels));
clk[IMX6QDL_CLK_CKO2_SEL] = imx_clk_mux("cko2_sel", base + 0x60, 16, 5, cko2_sels, ARRAY_SIZE(cko2_sels));
clk[IMX6QDL_CLK_CKO] = imx_clk_mux("cko", base + 0x60, 8, 1, cko_sels, ARRAY_SIZE(cko_sels));
/* name reg shift width busy: reg, shift parent_names num_parents */
clk[periph] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels));
clk[periph2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels));
/* name reg shift width busy: reg, shift parent_names num_parents */
clk[IMX6QDL_CLK_PERIPH] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels));
clk[IMX6QDL_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels));
/* name parent_name reg shift width */
clk[periph_clk2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3);
clk[periph2_clk2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3);
clk[ipg] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2);
clk[ipg_per] = imx_clk_fixup_divider("ipg_per", "ipg", base + 0x1c, 0, 6, imx_cscmr1_fixup);
clk[esai_pred] = imx_clk_divider("esai_pred", "esai_sel", base + 0x28, 9, 3);
clk[esai_podf] = imx_clk_divider("esai_podf", "esai_pred", base + 0x28, 25, 3);
clk[asrc_pred] = imx_clk_divider("asrc_pred", "asrc_sel", base + 0x30, 12, 3);
clk[asrc_podf] = imx_clk_divider("asrc_podf", "asrc_pred", base + 0x30, 9, 3);
clk[spdif_pred] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3);
clk[spdif_podf] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3);
clk[can_root] = imx_clk_divider("can_root", "pll3_60m", base + 0x20, 2, 6);
clk[ecspi_root] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6);
clk[gpu2d_core_podf] = imx_clk_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 23, 3);
clk[gpu3d_core_podf] = imx_clk_divider("gpu3d_core_podf", "gpu3d_core_sel", base + 0x18, 26, 3);
clk[gpu3d_shader] = imx_clk_divider("gpu3d_shader", "gpu3d_shader_sel", base + 0x18, 29, 3);
clk[ipu1_podf] = imx_clk_divider("ipu1_podf", "ipu1_sel", base + 0x3c, 11, 3);
clk[ipu2_podf] = imx_clk_divider("ipu2_podf", "ipu2_sel", base + 0x3c, 16, 3);
clk[ldb_di0_div_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
clk[ldb_di0_podf] = imx_clk_divider_flags("ldb_di0_podf", "ldb_di0_div_3_5", base + 0x20, 10, 1, 0);
clk[ldb_di1_div_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
clk[ldb_di1_podf] = imx_clk_divider_flags("ldb_di1_podf", "ldb_di1_div_3_5", base + 0x20, 11, 1, 0);
clk[ipu1_di0_pre] = imx_clk_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", base + 0x34, 3, 3);
clk[ipu1_di1_pre] = imx_clk_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", base + 0x34, 12, 3);
clk[ipu2_di0_pre] = imx_clk_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", base + 0x38, 3, 3);
clk[ipu2_di1_pre] = imx_clk_divider("ipu2_di1_pre", "ipu2_di1_pre_sel", base + 0x38, 12, 3);
clk[hsi_tx_podf] = imx_clk_divider("hsi_tx_podf", "hsi_tx_sel", base + 0x30, 29, 3);
clk[ssi1_pred] = imx_clk_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3);
clk[ssi1_podf] = imx_clk_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6);
clk[ssi2_pred] = imx_clk_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3);
clk[ssi2_podf] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6);
clk[ssi3_pred] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3);
clk[ssi3_podf] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6);
clk[uart_serial_podf] = imx_clk_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6);
clk[usdhc1_podf] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3);
clk[usdhc2_podf] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3);
clk[usdhc3_podf] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3);
clk[usdhc4_podf] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3);
clk[enfc_pred] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3);
clk[enfc_podf] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6);
clk[emi_podf] = imx_clk_fixup_divider("emi_podf", "emi_sel", base + 0x1c, 20, 3, imx_cscmr1_fixup);
clk[emi_slow_podf] = imx_clk_fixup_divider("emi_slow_podf", "emi_slow_sel", base + 0x1c, 23, 3, imx_cscmr1_fixup);
clk[vpu_axi_podf] = imx_clk_divider("vpu_axi_podf", "vpu_axi_sel", base + 0x24, 25, 3);
clk[cko1_podf] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3);
clk[cko2_podf] = imx_clk_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3);
/* name parent_name reg shift width */
clk[IMX6QDL_CLK_PERIPH_CLK2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3);
clk[IMX6QDL_CLK_PERIPH2_CLK2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3);
clk[IMX6QDL_CLK_IPG] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2);
clk[IMX6QDL_CLK_IPG_PER] = imx_clk_fixup_divider("ipg_per", "ipg", base + 0x1c, 0, 6, imx_cscmr1_fixup);
clk[IMX6QDL_CLK_ESAI_PRED] = imx_clk_divider("esai_pred", "esai_sel", base + 0x28, 9, 3);
clk[IMX6QDL_CLK_ESAI_PODF] = imx_clk_divider("esai_podf", "esai_pred", base + 0x28, 25, 3);
clk[IMX6QDL_CLK_ASRC_PRED] = imx_clk_divider("asrc_pred", "asrc_sel", base + 0x30, 12, 3);
clk[IMX6QDL_CLK_ASRC_PODF] = imx_clk_divider("asrc_podf", "asrc_pred", base + 0x30, 9, 3);
clk[IMX6QDL_CLK_SPDIF_PRED] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3);
clk[IMX6QDL_CLK_SPDIF_PODF] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3);
clk[IMX6QDL_CLK_CAN_ROOT] = imx_clk_divider("can_root", "pll3_60m", base + 0x20, 2, 6);
clk[IMX6QDL_CLK_ECSPI_ROOT] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6);
clk[IMX6QDL_CLK_GPU2D_CORE_PODF] = imx_clk_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 23, 3);
clk[IMX6QDL_CLK_GPU3D_CORE_PODF] = imx_clk_divider("gpu3d_core_podf", "gpu3d_core_sel", base + 0x18, 26, 3);
clk[IMX6QDL_CLK_GPU3D_SHADER] = imx_clk_divider("gpu3d_shader", "gpu3d_shader_sel", base + 0x18, 29, 3);
clk[IMX6QDL_CLK_IPU1_PODF] = imx_clk_divider("ipu1_podf", "ipu1_sel", base + 0x3c, 11, 3);
clk[IMX6QDL_CLK_IPU2_PODF] = imx_clk_divider("ipu2_podf", "ipu2_sel", base + 0x3c, 16, 3);
clk[IMX6QDL_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
clk[IMX6QDL_CLK_LDB_DI0_PODF] = imx_clk_divider_flags("ldb_di0_podf", "ldb_di0_div_3_5", base + 0x20, 10, 1, 0);
clk[IMX6QDL_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
clk[IMX6QDL_CLK_LDB_DI1_PODF] = imx_clk_divider_flags("ldb_di1_podf", "ldb_di1_div_3_5", base + 0x20, 11, 1, 0);
clk[IMX6QDL_CLK_IPU1_DI0_PRE] = imx_clk_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", base + 0x34, 3, 3);
clk[IMX6QDL_CLK_IPU1_DI1_PRE] = imx_clk_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", base + 0x34, 12, 3);
clk[IMX6QDL_CLK_IPU2_DI0_PRE] = imx_clk_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", base + 0x38, 3, 3);
clk[IMX6QDL_CLK_IPU2_DI1_PRE] = imx_clk_divider("ipu2_di1_pre", "ipu2_di1_pre_sel", base + 0x38, 12, 3);
clk[IMX6QDL_CLK_HSI_TX_PODF] = imx_clk_divider("hsi_tx_podf", "hsi_tx_sel", base + 0x30, 29, 3);
clk[IMX6QDL_CLK_SSI1_PRED] = imx_clk_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3);
clk[IMX6QDL_CLK_SSI1_PODF] = imx_clk_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6);
clk[IMX6QDL_CLK_SSI2_PRED] = imx_clk_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3);
clk[IMX6QDL_CLK_SSI2_PODF] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6);
clk[IMX6QDL_CLK_SSI3_PRED] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3);
clk[IMX6QDL_CLK_SSI3_PODF] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6);
clk[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6);
clk[IMX6QDL_CLK_USDHC1_PODF] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3);
clk[IMX6QDL_CLK_USDHC2_PODF] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3);
clk[IMX6QDL_CLK_USDHC3_PODF] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3);
clk[IMX6QDL_CLK_USDHC4_PODF] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3);
clk[IMX6QDL_CLK_ENFC_PRED] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3);
clk[IMX6QDL_CLK_ENFC_PODF] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6);
clk[IMX6QDL_CLK_EMI_PODF] = imx_clk_fixup_divider("emi_podf", "emi_sel", base + 0x1c, 20, 3, imx_cscmr1_fixup);
clk[IMX6QDL_CLK_EMI_SLOW_PODF] = imx_clk_fixup_divider("emi_slow_podf", "emi_slow_sel", base + 0x1c, 23, 3, imx_cscmr1_fixup);
clk[IMX6QDL_CLK_VPU_AXI_PODF] = imx_clk_divider("vpu_axi_podf", "vpu_axi_sel", base + 0x24, 25, 3);
clk[IMX6QDL_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3);
clk[IMX6QDL_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3);
/* name parent_name reg shift width busy: reg, shift */
clk[axi] = imx_clk_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0);
clk[mmdc_ch0_axi_podf] = imx_clk_busy_divider("mmdc_ch0_axi_podf", "periph", base + 0x14, 19, 3, base + 0x48, 4);
clk[mmdc_ch1_axi_podf] = imx_clk_busy_divider("mmdc_ch1_axi_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2);
clk[arm] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16);
clk[ahb] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1);
/* name parent_name reg shift width busy: reg, shift */
clk[IMX6QDL_CLK_AXI] = imx_clk_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0);
clk[IMX6QDL_CLK_MMDC_CH0_AXI_PODF] = imx_clk_busy_divider("mmdc_ch0_axi_podf", "periph", base + 0x14, 19, 3, base + 0x48, 4);
clk[IMX6QDL_CLK_MMDC_CH1_AXI_PODF] = imx_clk_busy_divider("mmdc_ch1_axi_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2);
clk[IMX6QDL_CLK_ARM] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16);
clk[IMX6QDL_CLK_AHB] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1);
/* name parent_name reg shift */
clk[apbh_dma] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4);
clk[asrc] = imx_clk_gate2("asrc", "asrc_podf", base + 0x68, 6);
clk[can1_ipg] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14);
clk[can1_serial] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16);
clk[can2_ipg] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18);
clk[can2_serial] = imx_clk_gate2("can2_serial", "can_root", base + 0x68, 20);
clk[ecspi1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0);
clk[ecspi2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2);
clk[ecspi3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4);
clk[ecspi4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6);
/* name parent_name reg shift */
clk[IMX6QDL_CLK_APBH_DMA] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4);
clk[IMX6QDL_CLK_ASRC] = imx_clk_gate2("asrc", "asrc_podf", base + 0x68, 6);
clk[IMX6QDL_CLK_CAN1_IPG] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14);
clk[IMX6QDL_CLK_CAN1_SERIAL] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16);
clk[IMX6QDL_CLK_CAN2_IPG] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18);
clk[IMX6QDL_CLK_CAN2_SERIAL] = imx_clk_gate2("can2_serial", "can_root", base + 0x68, 20);
clk[IMX6QDL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0);
clk[IMX6QDL_CLK_ECSPI2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2);
clk[IMX6QDL_CLK_ECSPI3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4);
clk[IMX6QDL_CLK_ECSPI4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6);
if (cpu_is_imx6dl())
/* ecspi5 is replaced with i2c4 on imx6dl & imx6s */
clk[ecspi5] = imx_clk_gate2("i2c4", "ipg_per", base + 0x6c, 8);
clk[IMX6DL_CLK_I2C4] = imx_clk_gate2("i2c4", "ipg_per", base + 0x6c, 8);
else
clk[ecspi5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8);
clk[enet] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10);
clk[esai] = imx_clk_gate2_shared("esai", "esai_podf", base + 0x6c, 16, &share_count_esai);
clk[esai_ahb] = imx_clk_gate2_shared("esai_ahb", "ahb", base + 0x6c, 16, &share_count_esai);
clk[gpt_ipg] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20);
clk[gpt_ipg_per] = imx_clk_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22);
clk[IMX6Q_CLK_ECSPI5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8);
clk[IMX6QDL_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10);
clk[IMX6QDL_CLK_ESAI] = imx_clk_gate2_shared("esai", "esai_podf", base + 0x6c, 16, &share_count_esai);
clk[IMX6QDL_CLK_ESAI_AHB] = imx_clk_gate2_shared("esai_ahb", "ahb", base + 0x6c, 16, &share_count_esai);
clk[IMX6QDL_CLK_GPT_IPG] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20);
clk[IMX6QDL_CLK_GPT_IPG_PER] = imx_clk_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22);
if (cpu_is_imx6dl())
/*
* The multiplexer and divider of imx6q clock gpu3d_shader get
* redefined/reused as gpu2d_core_sel and gpu2d_core_podf on imx6dl.
*/
clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu3d_shader", base + 0x6c, 24);
clk[IMX6QDL_CLK_GPU2D_CORE] = imx_clk_gate2("gpu2d_core", "gpu3d_shader", base + 0x6c, 24);
else
clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24);
clk[gpu3d_core] = imx_clk_gate2("gpu3d_core", "gpu3d_core_podf", base + 0x6c, 26);
clk[hdmi_iahb] = imx_clk_gate2("hdmi_iahb", "ahb", base + 0x70, 0);
clk[hdmi_isfr] = imx_clk_gate2("hdmi_isfr", "pll3_pfd1_540m", base + 0x70, 4);
clk[i2c1] = imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6);
clk[i2c2] = imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8);
clk[i2c3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10);
clk[iim] = imx_clk_gate2("iim", "ipg", base + 0x70, 12);
clk[enfc] = imx_clk_gate2("enfc", "enfc_podf", base + 0x70, 14);
clk[vdoa] = imx_clk_gate2("vdoa", "vdo_axi", base + 0x70, 26);
clk[ipu1] = imx_clk_gate2("ipu1", "ipu1_podf", base + 0x74, 0);
clk[ipu1_di0] = imx_clk_gate2("ipu1_di0", "ipu1_di0_sel", base + 0x74, 2);
clk[ipu1_di1] = imx_clk_gate2("ipu1_di1", "ipu1_di1_sel", base + 0x74, 4);
clk[ipu2] = imx_clk_gate2("ipu2", "ipu2_podf", base + 0x74, 6);
clk[ipu2_di0] = imx_clk_gate2("ipu2_di0", "ipu2_di0_sel", base + 0x74, 8);
clk[ldb_di0] = imx_clk_gate2("ldb_di0", "ldb_di0_podf", base + 0x74, 12);
clk[ldb_di1] = imx_clk_gate2("ldb_di1", "ldb_di1_podf", base + 0x74, 14);
clk[ipu2_di1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10);
clk[hsi_tx] = imx_clk_gate2("hsi_tx", "hsi_tx_podf", base + 0x74, 16);
clk[IMX6QDL_CLK_GPU2D_CORE] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24);
clk[IMX6QDL_CLK_GPU3D_CORE] = imx_clk_gate2("gpu3d_core", "gpu3d_core_podf", base + 0x6c, 26);
clk[IMX6QDL_CLK_HDMI_IAHB] = imx_clk_gate2("hdmi_iahb", "ahb", base + 0x70, 0);
clk[IMX6QDL_CLK_HDMI_ISFR] = imx_clk_gate2("hdmi_isfr", "pll3_pfd1_540m", base + 0x70, 4);
clk[IMX6QDL_CLK_I2C1] = imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6);
clk[IMX6QDL_CLK_I2C2] = imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8);
clk[IMX6QDL_CLK_I2C3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10);
clk[IMX6QDL_CLK_IIM] = imx_clk_gate2("iim", "ipg", base + 0x70, 12);
clk[IMX6QDL_CLK_ENFC] = imx_clk_gate2("enfc", "enfc_podf", base + 0x70, 14);
clk[IMX6QDL_CLK_VDOA] = imx_clk_gate2("vdoa", "vdo_axi", base + 0x70, 26);
clk[IMX6QDL_CLK_IPU1] = imx_clk_gate2("ipu1", "ipu1_podf", base + 0x74, 0);
clk[IMX6QDL_CLK_IPU1_DI0] = imx_clk_gate2("ipu1_di0", "ipu1_di0_sel", base + 0x74, 2);
clk[IMX6QDL_CLK_IPU1_DI1] = imx_clk_gate2("ipu1_di1", "ipu1_di1_sel", base + 0x74, 4);
clk[IMX6QDL_CLK_IPU2] = imx_clk_gate2("ipu2", "ipu2_podf", base + 0x74, 6);
clk[IMX6QDL_CLK_IPU2_DI0] = imx_clk_gate2("ipu2_di0", "ipu2_di0_sel", base + 0x74, 8);
clk[IMX6QDL_CLK_LDB_DI0] = imx_clk_gate2("ldb_di0", "ldb_di0_podf", base + 0x74, 12);
clk[IMX6QDL_CLK_LDB_DI1] = imx_clk_gate2("ldb_di1", "ldb_di1_podf", base + 0x74, 14);
clk[IMX6QDL_CLK_IPU2_DI1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10);
clk[IMX6QDL_CLK_HSI_TX] = imx_clk_gate2("hsi_tx", "hsi_tx_podf", base + 0x74, 16);
if (cpu_is_imx6dl())
/*
* The multiplexer and divider of the imx6q clock gpu2d get
* redefined/reused as mlb_sys_sel and mlb_sys_clk_podf on imx6dl.
*/
clk[mlb] = imx_clk_gate2("mlb", "gpu2d_core_podf", base + 0x74, 18);
clk[IMX6QDL_CLK_MLB] = imx_clk_gate2("mlb", "gpu2d_core_podf", base + 0x74, 18);
else
clk[mlb] = imx_clk_gate2("mlb", "axi", base + 0x74, 18);
clk[mmdc_ch0_axi] = imx_clk_gate2("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20);
clk[mmdc_ch1_axi] = imx_clk_gate2("mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22);
clk[ocram] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28);
clk[openvg_axi] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30);
clk[pcie_axi] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0);
clk[per1_bch] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12);
clk[pwm1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16);
clk[pwm2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18);
clk[pwm3] = imx_clk_gate2("pwm3", "ipg_per", base + 0x78, 20);
clk[pwm4] = imx_clk_gate2("pwm4", "ipg_per", base + 0x78, 22);
clk[gpmi_bch_apb] = imx_clk_gate2("gpmi_bch_apb", "usdhc3", base + 0x78, 24);
clk[gpmi_bch] = imx_clk_gate2("gpmi_bch", "usdhc4", base + 0x78, 26);
clk[gpmi_io] = imx_clk_gate2("gpmi_io", "enfc", base + 0x78, 28);
clk[gpmi_apb] = imx_clk_gate2("gpmi_apb", "usdhc3", base + 0x78, 30);
clk[rom] = imx_clk_gate2("rom", "ahb", base + 0x7c, 0);
clk[sata] = imx_clk_gate2("sata", "ipg", base + 0x7c, 4);
clk[sdma] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6);
clk[spba] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
clk[spdif] = imx_clk_gate2("spdif", "spdif_podf", base + 0x7c, 14);
clk[ssi1_ipg] = imx_clk_gate2("ssi1_ipg", "ipg", base + 0x7c, 18);
clk[ssi2_ipg] = imx_clk_gate2("ssi2_ipg", "ipg", base + 0x7c, 20);
clk[ssi3_ipg] = imx_clk_gate2("ssi3_ipg", "ipg", base + 0x7c, 22);
clk[uart_ipg] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24);
clk[uart_serial] = imx_clk_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26);
clk[usboh3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0);
clk[usdhc1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2);
clk[usdhc2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4);
clk[usdhc3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
clk[usdhc4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8);
clk[eim_slow] = imx_clk_gate2("eim_slow", "emi_slow_podf", base + 0x80, 10);
clk[vdo_axi] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12);
clk[vpu_axi] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14);
clk[cko1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7);
clk[cko2] = imx_clk_gate("cko2", "cko2_podf", base + 0x60, 24);
clk[IMX6QDL_CLK_MLB] = imx_clk_gate2("mlb", "axi", base + 0x74, 18);
clk[IMX6QDL_CLK_MMDC_CH0_AXI] = imx_clk_gate2("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20);
clk[IMX6QDL_CLK_MMDC_CH1_AXI] = imx_clk_gate2("mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22);
clk[IMX6QDL_CLK_OCRAM] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28);
clk[IMX6QDL_CLK_OPENVG_AXI] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30);
clk[IMX6QDL_CLK_PCIE_AXI] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0);
clk[IMX6QDL_CLK_PER1_BCH] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12);
clk[IMX6QDL_CLK_PWM1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16);
clk[IMX6QDL_CLK_PWM2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18);
clk[IMX6QDL_CLK_PWM3] = imx_clk_gate2("pwm3", "ipg_per", base + 0x78, 20);
clk[IMX6QDL_CLK_PWM4] = imx_clk_gate2("pwm4", "ipg_per", base + 0x78, 22);
clk[IMX6QDL_CLK_GPMI_BCH_APB] = imx_clk_gate2("gpmi_bch_apb", "usdhc3", base + 0x78, 24);
clk[IMX6QDL_CLK_GPMI_BCH] = imx_clk_gate2("gpmi_bch", "usdhc4", base + 0x78, 26);
clk[IMX6QDL_CLK_GPMI_IO] = imx_clk_gate2("gpmi_io", "enfc", base + 0x78, 28);
clk[IMX6QDL_CLK_GPMI_APB] = imx_clk_gate2("gpmi_apb", "usdhc3", base + 0x78, 30);
clk[IMX6QDL_CLK_ROM] = imx_clk_gate2("rom", "ahb", base + 0x7c, 0);
clk[IMX6QDL_CLK_SATA] = imx_clk_gate2("sata", "ipg", base + 0x7c, 4);
clk[IMX6QDL_CLK_SDMA] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6);
clk[IMX6QDL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
clk[IMX6QDL_CLK_SPDIF] = imx_clk_gate2("spdif", "spdif_podf", base + 0x7c, 14);
clk[IMX6QDL_CLK_SSI1_IPG] = imx_clk_gate2("ssi1_ipg", "ipg", base + 0x7c, 18);
clk[IMX6QDL_CLK_SSI2_IPG] = imx_clk_gate2("ssi2_ipg", "ipg", base + 0x7c, 20);
clk[IMX6QDL_CLK_SSI3_IPG] = imx_clk_gate2("ssi3_ipg", "ipg", base + 0x7c, 22);
clk[IMX6QDL_CLK_UART_IPG] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24);
clk[IMX6QDL_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26);
clk[IMX6QDL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0);
clk[IMX6QDL_CLK_USDHC1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2);
clk[IMX6QDL_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4);
clk[IMX6QDL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
clk[IMX6QDL_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8);
clk[IMX6QDL_CLK_EIM_SLOW] = imx_clk_gate2("eim_slow", "emi_slow_podf", base + 0x80, 10);
clk[IMX6QDL_CLK_VDO_AXI] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12);
clk[IMX6QDL_CLK_VPU_AXI] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14);
clk[IMX6QDL_CLK_CKO1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7);
clk[IMX6QDL_CLK_CKO2] = imx_clk_gate("cko2", "cko2_podf", base + 0x60, 24);
for (i = 0; i < ARRAY_SIZE(clk); i++)
if (IS_ERR(clk[i]))
pr_err("i.MX6q clk %d: register failed with %ld\n",
i, PTR_ERR(clk[i]));
imx_check_clocks(clk, ARRAY_SIZE(clk));
clk_data.clks = clk;
clk_data.clk_num = ARRAY_SIZE(clk);
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0");
clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
clk_register_clkdev(clk[enet_ref], "enet_ref", NULL);
clk_register_clkdev(clk[IMX6QDL_CLK_ENET_REF], "enet_ref", NULL);
if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) ||
cpu_is_imx6dl()) {
clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]);
clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]);
clk_set_parent(clk[IMX6QDL_CLK_LDB_DI0_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
clk_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
}
clk_set_parent(clk[ipu1_di0_pre_sel], clk[pll5_video_div]);
clk_set_parent(clk[ipu1_di1_pre_sel], clk[pll5_video_div]);
clk_set_parent(clk[ipu2_di0_pre_sel], clk[pll5_video_div]);
clk_set_parent(clk[ipu2_di1_pre_sel], clk[pll5_video_div]);
clk_set_parent(clk[ipu1_di0_sel], clk[ipu1_di0_pre]);
clk_set_parent(clk[ipu1_di1_sel], clk[ipu1_di1_pre]);
clk_set_parent(clk[ipu2_di0_sel], clk[ipu2_di0_pre]);
clk_set_parent(clk[ipu2_di1_sel], clk[ipu2_di1_pre]);
clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_SEL], clk[IMX6QDL_CLK_IPU1_DI0_PRE]);
clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_SEL], clk[IMX6QDL_CLK_IPU1_DI1_PRE]);
clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_SEL], clk[IMX6QDL_CLK_IPU2_DI0_PRE]);
clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_SEL], clk[IMX6QDL_CLK_IPU2_DI1_PRE]);
/*
* The gpmi needs 100MHz frequency in the EDO/Sync mode,
* We can not get the 100MHz from the pll2_pfd0_352m.
* So choose pll2_pfd2_396m as enfc_sel's parent.
*/
clk_set_parent(clk[enfc_sel], clk[pll2_pfd2_396m]);
clk_set_parent(clk[IMX6QDL_CLK_ENFC_SEL], clk[IMX6QDL_CLK_PLL2_PFD2_396M]);
for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
clk_prepare_enable(clk[clks_init_on[i]]);
if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
clk_prepare_enable(clk[usbphy1_gate]);
clk_prepare_enable(clk[usbphy2_gate]);
clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY1_GATE]);
clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY2_GATE]);
}
/*
* Let's initially set up CLKO with OSC24M, since this configuration
* is widely used by imx6q board designs to clock audio codec.
*/
ret = clk_set_parent(clk[cko2_sel], clk[osc]);
ret = clk_set_parent(clk[IMX6QDL_CLK_CKO2_SEL], clk[IMX6QDL_CLK_OSC]);
if (!ret)
ret = clk_set_parent(clk[cko], clk[cko2]);
ret = clk_set_parent(clk[IMX6QDL_CLK_CKO], clk[IMX6QDL_CLK_CKO2]);
if (ret)
pr_warn("failed to set up CLKO: %d\n", ret);
/* Audio-related clocks configuration */
clk_set_parent(clk[spdif_sel], clk[pll3_pfd3_454m]);
clk_set_parent(clk[IMX6QDL_CLK_SPDIF_SEL], clk[IMX6QDL_CLK_PLL3_PFD3_454M]);
/* All existing boards with PCIe use LVDS1 */
if (IS_ENABLED(CONFIG_PCI_IMX6))
clk_set_parent(clk[lvds1_sel], clk[sata_ref_100m]);
clk_set_parent(clk[IMX6QDL_CLK_LVDS1_SEL], clk[IMX6QDL_CLK_SATA_REF_100M]);
/* Set initial power mode */
imx6q_set_lpm(WAIT_CLOCKED);
mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt"));
}
CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init);

11
arch/arm/mach-imx/clk-imx6sl.c
View File

@ -348,18 +348,12 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
clks[IMX6SL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
clks[IMX6SL_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8);
for (i = 0; i < ARRAY_SIZE(clks); i++)
if (IS_ERR(clks[i]))
pr_err("i.MX6SL clk %d: register failed with %ld\n",
i, PTR_ERR(clks[i]));
imx_check_clocks(clks, ARRAY_SIZE(clks));
clk_data.clks = clks;
clk_data.clk_num = ARRAY_SIZE(clks);
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
clk_register_clkdev(clks[IMX6SL_CLK_GPT], "ipg", "imx-gpt.0");
clk_register_clkdev(clks[IMX6SL_CLK_GPT_SERIAL], "per", "imx-gpt.0");
/* Ensure the AHB clk is at 132MHz. */
ret = clk_set_rate(clks[IMX6SL_CLK_AHB], 132000000);
if (ret)
@ -383,8 +377,5 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
/* Set initial power mode */
imx6q_set_lpm(WAIT_CLOCKED);
np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-gpt");
mxc_timer_init_dt(np);
}
CLK_OF_DECLARE(imx6sl, "fsl,imx6sl-ccm", imx6sl_clocks_init);

25
arch/arm/mach-imx/clk-imx6sx.c
View File

@ -124,6 +124,9 @@ static struct clk_div_table video_div_table[] = {
static u32 share_count_asrc;
static u32 share_count_audio;
static u32 share_count_esai;
static u32 share_count_ssi1;
static u32 share_count_ssi2;
static u32 share_count_ssi3;
static void __init imx6sx_clocks_init(struct device_node *ccm_node)
{
@ -409,12 +412,12 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
clks[IMX6SX_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
clks[IMX6SX_CLK_AUDIO] = imx_clk_gate2_shared("audio", "audio_podf", base + 0x7c, 14, &share_count_audio);
clks[IMX6SX_CLK_SPDIF] = imx_clk_gate2_shared("spdif", "spdif_podf", base + 0x7c, 14, &share_count_audio);
clks[IMX6SX_CLK_SSI1_IPG] = imx_clk_gate2("ssi1_ipg", "ipg", base + 0x7c, 18);
clks[IMX6SX_CLK_SSI2_IPG] = imx_clk_gate2("ssi2_ipg", "ipg", base + 0x7c, 20);
clks[IMX6SX_CLK_SSI3_IPG] = imx_clk_gate2("ssi3_ipg", "ipg", base + 0x7c, 22);
clks[IMX6SX_CLK_SSI1] = imx_clk_gate2("ssi1", "ssi1_podf", base + 0x7c, 18);
clks[IMX6SX_CLK_SSI2] = imx_clk_gate2("ssi2", "ssi2_podf", base + 0x7c, 20);
clks[IMX6SX_CLK_SSI3] = imx_clk_gate2("ssi3", "ssi3_podf", base + 0x7c, 22);
clks[IMX6SX_CLK_SSI1_IPG] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1);
clks[IMX6SX_CLK_SSI2_IPG] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2);
clks[IMX6SX_CLK_SSI3_IPG] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3);
clks[IMX6SX_CLK_SSI1] = imx_clk_gate2_shared("ssi1", "ssi1_podf", base + 0x7c, 18, &share_count_ssi1);
clks[IMX6SX_CLK_SSI2] = imx_clk_gate2_shared("ssi2", "ssi2_podf", base + 0x7c, 20, &share_count_ssi2);
clks[IMX6SX_CLK_SSI3] = imx_clk_gate2_shared("ssi3", "ssi3_podf", base + 0x7c, 22, &share_count_ssi3);
clks[IMX6SX_CLK_UART_IPG] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24);
clks[IMX6SX_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_podf", base + 0x7c, 26);
clks[IMX6SX_CLK_SAI1_IPG] = imx_clk_gate2("sai1_ipg", "ipg", base + 0x7c, 28);
@ -443,17 +446,12 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
/* mask handshake of mmdc */
writel_relaxed(BM_CCM_CCDR_MMDC_CH0_MASK, base + CCDR);
for (i = 0; i < ARRAY_SIZE(clks); i++)
if (IS_ERR(clks[i]))
pr_err("i.MX6sx clk %d: register failed with %ld\n", i, PTR_ERR(clks[i]));
imx_check_clocks(clks, ARRAY_SIZE(clks));
clk_data.clks = clks;
clk_data.clk_num = ARRAY_SIZE(clks);
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
clk_register_clkdev(clks[IMX6SX_CLK_GPT_BUS], "ipg", "imx-gpt.0");
clk_register_clkdev(clks[IMX6SX_CLK_GPT_SERIAL], "per", "imx-gpt.0");
for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
clk_prepare_enable(clks[clks_init_on[i]]);
@ -517,8 +515,5 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
/* Set initial power mode */
imx6q_set_lpm(WAIT_CLOCKED);
np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-gpt");
mxc_timer_init_dt(np);
}
CLK_OF_DECLARE(imx6sx, "fsl,imx6sx-ccm", imx6sx_clocks_init);

8
arch/arm/mach-imx/clk-vf610.c
View File

@ -295,14 +295,18 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
clk[VF610_CLK_ASRC] = imx_clk_gate2("asrc", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(1));
clk[VF610_CLK_FLEXCAN0] = imx_clk_gate2("flexcan0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(0));
clk[VF610_CLK_FLEXCAN1] = imx_clk_gate2("flexcan1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(4));
clk[VF610_CLK_FLEXCAN0_EN] = imx_clk_gate("flexcan0_en", "ipg_bus", CCM_CSCDR2, 11);
clk[VF610_CLK_FLEXCAN0] = imx_clk_gate2("flexcan0", "flexcan0_en", CCM_CCGR0, CCM_CCGRx_CGn(0));
clk[VF610_CLK_FLEXCAN1_EN] = imx_clk_gate("flexcan1_en", "ipg_bus", CCM_CSCDR2, 12);
clk[VF610_CLK_FLEXCAN1] = imx_clk_gate2("flexcan1", "flexcan1_en", CCM_CCGR9, CCM_CCGRx_CGn(4));
clk[VF610_CLK_DMAMUX0] = imx_clk_gate2("dmamux0", "platform_bus", CCM_CCGR0, CCM_CCGRx_CGn(4));
clk[VF610_CLK_DMAMUX1] = imx_clk_gate2("dmamux1", "platform_bus", CCM_CCGR0, CCM_CCGRx_CGn(5));
clk[VF610_CLK_DMAMUX2] = imx_clk_gate2("dmamux2", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(1));
clk[VF610_CLK_DMAMUX3] = imx_clk_gate2("dmamux3", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(2));
imx_check_clocks(clk, ARRAY_SIZE(clk));
clk_set_parent(clk[VF610_CLK_QSPI0_SEL], clk[VF610_CLK_PLL1_PFD4]);
clk_set_rate(clk[VF610_CLK_QSPI0_X4_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_SEL]) / 2);
clk_set_rate(clk[VF610_CLK_QSPI0_X2_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_X4_DIV]) / 2);

10
arch/arm/mach-imx/clk.c
View File

@ -7,6 +7,16 @@
DEFINE_SPINLOCK(imx_ccm_lock);
void __init imx_check_clocks(struct clk *clks[], unsigned int count)
{
unsigned i;
for (i = 0; i < count; i++)
if (IS_ERR(clks[i]))
pr_err("i.MX clk %u: register failed with %ld\n",
i, PTR_ERR(clks[i]));
}
static struct clk * __init imx_obtain_fixed_clock_from_dt(const char *name)
{
struct of_phandle_args phandle;

9
arch/arm/mach-imx/clk.h
View File

@ -6,6 +6,8 @@
extern spinlock_t imx_ccm_lock;
void imx_check_clocks(struct clk *clks[], unsigned int count);
extern void imx_cscmr1_fixup(u32 *val);
struct clk *imx_clk_pllv1(const char *name, const char *parent,
@ -95,6 +97,13 @@ static inline struct clk *imx_clk_gate(const char *name, const char *parent,
shift, 0, &imx_ccm_lock);
}
static inline struct clk *imx_clk_gate_dis(const char *name, const char *parent,
void __iomem *reg, u8 shift)
{
return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
shift, CLK_GATE_SET_TO_DISABLE, &imx_ccm_lock);
}
static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
u8 shift, u8 width, const char **parents, int num_parents)
{

32
arch/arm/mach-imx/common.h
View File

@ -19,6 +19,7 @@ struct pt_regs;
struct clk;
struct device_node;
enum mxc_cpu_pwr_mode;
struct of_device_id;
void mx1_map_io(void);
void mx21_map_io(void);
@ -26,48 +27,34 @@ void mx25_map_io(void);
void mx27_map_io(void);
void mx31_map_io(void);
void mx35_map_io(void);
void mx51_map_io(void);
void mx53_map_io(void);
void imx1_init_early(void);
void imx21_init_early(void);
void imx25_init_early(void);
void imx27_init_early(void);
void imx31_init_early(void);
void imx35_init_early(void);
void imx51_init_early(void);
void imx53_init_early(void);
void mxc_init_irq(void __iomem *);
void tzic_init_irq(void __iomem *);
void tzic_init_irq(void);
void mx1_init_irq(void);
void mx21_init_irq(void);
void mx25_init_irq(void);
void mx27_init_irq(void);
void mx31_init_irq(void);
void mx35_init_irq(void);
void mx51_init_irq(void);
void mx53_init_irq(void);
void imx1_soc_init(void);
void imx21_soc_init(void);
void imx25_soc_init(void);
void imx27_soc_init(void);
void imx31_soc_init(void);
void imx35_soc_init(void);
void imx51_soc_init(void);
void imx51_init_late(void);
void imx53_init_late(void);
void epit_timer_init(void __iomem *base, int irq);
void mxc_timer_init(void __iomem *, int);
void mxc_timer_init_dt(struct device_node *);
int mx1_clocks_init(unsigned long fref);
int mx21_clocks_init(unsigned long lref, unsigned long fref);
int mx25_clocks_init(void);
int mx27_clocks_init(unsigned long fref);
int mx31_clocks_init(unsigned long fref);
int mx35_clocks_init(void);
int mx51_clocks_init(unsigned long ckil, unsigned long osc,
unsigned long ckih1, unsigned long ckih2);
int mx25_clocks_init_dt(void);
int mx27_clocks_init_dt(void);
int mx31_clocks_init_dt(void);
struct platform_device *mxc_register_gpio(char *name, int id,
resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
@ -75,8 +62,10 @@ void mxc_set_cpu_type(unsigned int type);
void mxc_restart(enum reboot_mode, const char *);
void mxc_arch_reset_init(void __iomem *);
void mxc_arch_reset_init_dt(void);
int mx51_revision(void);
int mx53_revision(void);
void imx_set_aips(void __iomem *);
void imx_aips_allow_unprivileged_access(const char *compat);
int mxc_device_init(void);
void imx_set_soc_revision(unsigned int rev);
unsigned int imx_get_soc_revision(void);
@ -117,7 +106,7 @@ static inline void imx_scu_standby_enable(void) {}
#endif
void imx_src_init(void);
void imx_gpc_init(void);
void imx_gpc_pre_suspend(void);
void imx_gpc_pre_suspend(bool arm_power_off);
void imx_gpc_post_resume(void);
void imx_gpc_mask_all(void);
void imx_gpc_restore_all(void);
@ -127,7 +116,7 @@ void imx_anatop_init(void);
void imx_anatop_pre_suspend(void);
void imx_anatop_post_resume(void);
int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
void imx6q_set_int_mem_clk_lpm(void);
void imx6q_set_int_mem_clk_lpm(bool enable);
void imx6sl_set_wait_clk(bool enter);
void imx_cpu_die(unsigned int cpu);
@ -144,12 +133,17 @@ static inline void imx6_suspend(void __iomem *ocram_vbase) {}
void imx6q_pm_init(void);
void imx6dl_pm_init(void);
void imx6sl_pm_init(void);
void imx6sx_pm_init(void);
void imx6q_pm_set_ccm_base(void __iomem *base);
#ifdef CONFIG_PM
void imx5_pm_init(void);
void imx51_pm_init(void);
void imx53_pm_init(void);
void imx5_pm_set_ccm_base(void __iomem *base);
#else
static inline void imx5_pm_init(void) {}
static inline void imx51_pm_init(void) {}
static inline void imx53_pm_init(void) {}
static inline void imx5_pm_set_ccm_base(void __iomem *base) {}
#endif
#ifdef CONFIG_NEON

25
arch/arm/mach-imx/cpu-imx5.c
View File

@ -16,6 +16,8 @@
#include <linux/init.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include "hardware.h"
#include "common.h"
@ -24,10 +26,26 @@ static int mx5_cpu_rev = -1;
#define IIM_SREV 0x24
static u32 imx5_read_srev_reg(const char *compat)
{
void __iomem *iim_base;
struct device_node *np;
u32 srev;
np = of_find_compatible_node(NULL, NULL, compat);
iim_base = of_iomap(np, 0);
WARN_ON(!iim_base);
srev = readl(iim_base + IIM_SREV) & 0xff;
iounmap(iim_base);
return srev;
}
static int get_mx51_srev(void)
{
void __iomem *iim_base = MX51_IO_ADDRESS(MX51_IIM_BASE_ADDR);
u32 rev = readl(iim_base + IIM_SREV) & 0xff;
u32 rev = imx5_read_srev_reg("fsl,imx51-iim");
switch (rev) {
case 0x0:
@ -77,8 +95,7 @@ int __init mx51_neon_fixup(void)
static int get_mx53_srev(void)
{
void __iomem *iim_base = MX51_IO_ADDRESS(MX53_IIM_BASE_ADDR);
u32 rev = readl(iim_base + IIM_SREV) & 0xff;
u32 rev = imx5_read_srev_reg("fsl,imx53-iim");
switch (rev) {
case 0x0:

13
arch/arm/mach-imx/cpu.c
View File

@ -2,6 +2,7 @@
#include <linux/module.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/slab.h>
#include <linux/sys_soc.h>
@ -60,6 +61,18 @@ void __init imx_set_aips(void __iomem *base)
__raw_writel(reg, base + 0x50);
}
void __init imx_aips_allow_unprivileged_access(
const char *compat)
{
void __iomem *aips_base_addr;
struct device_node *np;
for_each_compatible_node(np, NULL, compat) {
aips_base_addr = of_iomap(np, 0);
imx_set_aips(aips_base_addr);
}
}
struct device * __init imx_soc_device_init(void)
{
struct soc_device_attribute *soc_dev_attr;

6
arch/arm/mach-imx/cpuidle-imx6q.c
View File

@ -13,6 +13,7 @@
#include "common.h"
#include "cpuidle.h"
#include "hardware.h"
static atomic_t master = ATOMIC_INIT(0);
static DEFINE_SPINLOCK(master_lock);
@ -66,10 +67,11 @@ static struct cpuidle_driver imx6q_cpuidle_driver = {
int __init imx6q_cpuidle_init(void)
{
/* Need to enable SCU standby for entering WAIT modes */
imx_scu_standby_enable();
if (!cpu_is_imx6sx())
imx_scu_standby_enable();
/* Set INT_MEM_CLK_LPM bit to get a reliable WAIT mode support */
imx6q_set_int_mem_clk_lpm();
imx6q_set_int_mem_clk_lpm(true);
return cpuidle_register(&imx6q_cpuidle_driver, NULL);
}

600
arch/arm/mach-imx/crm-regs-imx5.h
View File

@ -1,600 +0,0 @@
/*
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__
#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__
#define MX51_CCM_BASE MX51_IO_ADDRESS(MX51_CCM_BASE_ADDR)
#define MX51_DPLL1_BASE MX51_IO_ADDRESS(MX51_PLL1_BASE_ADDR)
#define MX51_DPLL2_BASE MX51_IO_ADDRESS(MX51_PLL2_BASE_ADDR)
#define MX51_DPLL3_BASE MX51_IO_ADDRESS(MX51_PLL3_BASE_ADDR)
#define MX51_CORTEXA8_BASE MX51_IO_ADDRESS(MX51_ARM_BASE_ADDR)
#define MX51_GPC_BASE MX51_IO_ADDRESS(MX51_GPC_BASE_ADDR)
/*MX53*/
#define MX53_CCM_BASE MX53_IO_ADDRESS(MX53_CCM_BASE_ADDR)
#define MX53_DPLL1_BASE MX53_IO_ADDRESS(MX53_PLL1_BASE_ADDR)
#define MX53_DPLL2_BASE MX53_IO_ADDRESS(MX53_PLL2_BASE_ADDR)
#define MX53_DPLL3_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR)
#define MX53_DPLL4_BASE MX53_IO_ADDRESS(MX53_PLL4_BASE_ADDR)
/* PLL Register Offsets */
#define MXC_PLL_DP_CTL 0x00
#define MXC_PLL_DP_CONFIG 0x04
#define MXC_PLL_DP_OP 0x08
#define MXC_PLL_DP_MFD 0x0C
#define MXC_PLL_DP_MFN 0x10
#define MXC_PLL_DP_MFNMINUS 0x14
#define MXC_PLL_DP_MFNPLUS 0x18
#define MXC_PLL_DP_HFS_OP 0x1C
#define MXC_PLL_DP_HFS_MFD 0x20
#define MXC_PLL_DP_HFS_MFN 0x24
#define MXC_PLL_DP_MFN_TOGC 0x28
#define MXC_PLL_DP_DESTAT 0x2c
/* PLL Register Bit definitions */
#define MXC_PLL_DP_CTL_MUL_CTRL 0x2000
#define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000
#define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12
#define MXC_PLL_DP_CTL_ADE 0x800
#define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400
#define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8)
#define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8
#define MXC_PLL_DP_CTL_HFSM 0x80
#define MXC_PLL_DP_CTL_PRE 0x40
#define MXC_PLL_DP_CTL_UPEN 0x20
#define MXC_PLL_DP_CTL_RST 0x10
#define MXC_PLL_DP_CTL_RCP 0x8
#define MXC_PLL_DP_CTL_PLM 0x4
#define MXC_PLL_DP_CTL_BRM0 0x2
#define MXC_PLL_DP_CTL_LRF 0x1
#define MXC_PLL_DP_CONFIG_BIST 0x8
#define MXC_PLL_DP_CONFIG_SJC_CE 0x4
#define MXC_PLL_DP_CONFIG_AREN 0x2
#define MXC_PLL_DP_CONFIG_LDREQ 0x1
#define MXC_PLL_DP_OP_MFI_OFFSET 4
#define MXC_PLL_DP_OP_MFI_MASK (0xF << 4)
#define MXC_PLL_DP_OP_PDF_OFFSET 0
#define MXC_PLL_DP_OP_PDF_MASK 0xF
#define MXC_PLL_DP_MFD_OFFSET 0
#define MXC_PLL_DP_MFD_MASK 0x07FFFFFF
#define MXC_PLL_DP_MFN_OFFSET 0x0
#define MXC_PLL_DP_MFN_MASK 0x07FFFFFF
#define MXC_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17)
#define MXC_PLL_DP_MFN_TOGC_TOG_EN (1 << 16)
#define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0
#define MXC_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF
#define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31)
#define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF
/* Register addresses of CCM*/
#define MXC_CCM_CCR (MX51_CCM_BASE + 0x00)
#define MXC_CCM_CCDR (MX51_CCM_BASE + 0x04)
#define MXC_CCM_CSR (MX51_CCM_BASE + 0x08)
#define MXC_CCM_CCSR (MX51_CCM_BASE + 0x0C)
#define MXC_CCM_CACRR (MX51_CCM_BASE + 0x10)
#define MXC_CCM_CBCDR (MX51_CCM_BASE + 0x14)
#define MXC_CCM_CBCMR (MX51_CCM_BASE + 0x18)
#define MXC_CCM_CSCMR1 (MX51_CCM_BASE + 0x1C)
#define MXC_CCM_CSCMR2 (MX51_CCM_BASE + 0x20)
#define MXC_CCM_CSCDR1 (MX51_CCM_BASE + 0x24)
#define MXC_CCM_CS1CDR (MX51_CCM_BASE + 0x28)
#define MXC_CCM_CS2CDR (MX51_CCM_BASE + 0x2C)
#define MXC_CCM_CDCDR (MX51_CCM_BASE + 0x30)
#define MXC_CCM_CHSCDR (MX51_CCM_BASE + 0x34)
#define MXC_CCM_CSCDR2 (MX51_CCM_BASE + 0x38)
#define MXC_CCM_CSCDR3 (MX51_CCM_BASE + 0x3C)
#define MXC_CCM_CSCDR4 (MX51_CCM_BASE + 0x40)
#define MXC_CCM_CWDR (MX51_CCM_BASE + 0x44)
#define MXC_CCM_CDHIPR (MX51_CCM_BASE + 0x48)
#define MXC_CCM_CDCR (MX51_CCM_BASE + 0x4C)
#define MXC_CCM_CTOR (MX51_CCM_BASE + 0x50)
#define MXC_CCM_CLPCR (MX51_CCM_BASE + 0x54)
#define MXC_CCM_CISR (MX51_CCM_BASE + 0x58)
#define MXC_CCM_CIMR (MX51_CCM_BASE + 0x5C)
#define MXC_CCM_CCOSR (MX51_CCM_BASE + 0x60)
#define MXC_CCM_CGPR (MX51_CCM_BASE + 0x64)
#define MXC_CCM_CCGR0 (MX51_CCM_BASE + 0x68)
#define MXC_CCM_CCGR1 (MX51_CCM_BASE + 0x6C)
#define MXC_CCM_CCGR2 (MX51_CCM_BASE + 0x70)
#define MXC_CCM_CCGR3 (MX51_CCM_BASE + 0x74)
#define MXC_CCM_CCGR4 (MX51_CCM_BASE + 0x78)
#define MXC_CCM_CCGR5 (MX51_CCM_BASE + 0x7C)
#define MXC_CCM_CCGR6 (MX51_CCM_BASE + 0x80)
#define MXC_CCM_CCGR7 (MX51_CCM_BASE + 0x84)
#define MXC_CCM_CMEOR (MX51_CCM_BASE + 0x84)
/* Define the bits in register CCR */
#define MXC_CCM_CCR_COSC_EN (1 << 12)
#define MXC_CCM_CCR_FPM_MULT_MASK (1 << 11)
#define MXC_CCM_CCR_CAMP2_EN (1 << 10)
#define MXC_CCM_CCR_CAMP1_EN (1 << 9)
#define MXC_CCM_CCR_FPM_EN (1 << 8)
#define MXC_CCM_CCR_OSCNT_OFFSET (0)
#define MXC_CCM_CCR_OSCNT_MASK (0xFF)
/* Define the bits in register CCDR */
#define MXC_CCM_CCDR_HSC_HS_MASK (0x1 << 18)
#define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17)
#define MXC_CCM_CCDR_EMI_HS_MASK (0x1 << 16)
/* Define the bits in register CSR */
#define MXC_CCM_CSR_COSR_READY (1 << 5)
#define MXC_CCM_CSR_LVS_VALUE (1 << 4)
#define MXC_CCM_CSR_CAMP2_READY (1 << 3)
#define MXC_CCM_CSR_CAMP1_READY (1 << 2)
#define MXC_CCM_CSR_FPM_READY (1 << 1)
#define MXC_CCM_CSR_REF_EN_B (1 << 0)
/* Define the bits in register CCSR */
#define MXC_CCM_CCSR_LP_APM_SEL (0x1 << 9)
#define MXC_CCM_CCSR_STEP_SEL_OFFSET (7)
#define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7)
#define MXC_CCM_CCSR_STEP_SEL_LP_APM 0
#define MXC_CCM_CCSR_STEP_SEL_PLL1_BYPASS 1 /* Only when JTAG connected? */
#define MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED 2
#define MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED 3
#define MXC_CCM_CCSR_PLL2_PODF_OFFSET (5)
#define MXC_CCM_CCSR_PLL2_PODF_MASK (0x3 << 5)
#define MXC_CCM_CCSR_PLL3_PODF_OFFSET (3)
#define MXC_CCM_CCSR_PLL3_PODF_MASK (0x3 << 3)
#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2) /* 0: pll1_main_clk,
1: step_clk */
#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1)
#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0)
/* Define the bits in register CACRR */
#define MXC_CCM_CACRR_ARM_PODF_OFFSET (0)
#define MXC_CCM_CACRR_ARM_PODF_MASK (0x7)
/* Define the bits in register CBCDR */
#define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26)
#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25)
#define MXC_CCM_CBCDR_DDR_HF_SEL_OFFSET (30)
#define MXC_CCM_CBCDR_DDR_HF_SEL (0x1 << 30)
#define MXC_CCM_CBCDR_DDR_PODF_OFFSET (27)
#define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27)
#define MXC_CCM_CBCDR_EMI_PODF_OFFSET (22)
#define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22)
#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET (19)
#define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19)
#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET (16)
#define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16)
#define MXC_CCM_CBCDR_NFC_PODF_OFFSET (13)
#define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13)
#define MXC_CCM_CBCDR_AHB_PODF_OFFSET (10)
#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
#define MXC_CCM_CBCDR_IPG_PODF_OFFSET (8)
#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET (6)
#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6)
#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET (3)
#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3)
#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET (0)
#define MXC_CCM_CBCDR_PERCLK_PODF_MASK (0x7)
/* Define the bits in register CBCMR */
#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET (14)
#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET (12)
#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12)
#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET (10)
#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10)
#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET (8)
#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8)
#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET (6)
#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6)
#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET (4)
#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4)
#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET (14)
#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 14)
#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1)
#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0)
/* Define the bits in register CSCMR1 */
#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET (30)
#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30)
#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET (28)
#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28)
#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET (26)
#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26)
#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET (24)
#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24)
#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET (22)
#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22)
#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET (20)
#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20)
#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19)
#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL (0x1 << 19)
#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18)
#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET (16)
#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16)
#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_OFFSET (16)
#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_MASK (0x3 << 16)
#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14)
#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14)
#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12)
#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
#define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11)
#define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10)
#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET (8)
#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8)
#define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7)
#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6)
#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET (4)
#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4)
#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET (2)
#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2)
#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1)
#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL (0x1)
/* Define the bits in register CSCMR2 */
#define MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(n) (26+n*3)
#define MXC_CCM_CSCMR2_DI_CLK_SEL_MASK(n) (0x7 << (26+n*3))
#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET (24)
#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK (0x3 << 24)
#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET (22)
#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK (0x3 << 22)
#define MXC_CCM_CSCMR2_ESC_CLK_SEL_OFFSET (20)
#define MXC_CCM_CSCMR2_ESC_CLK_SEL_MASK (0x3 << 20)
#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_OFFSET (18)
#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_MASK (0x3 << 18)
#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_OFFSET (16)
#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_MASK (0x3 << 16)
#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_OFFSET (14)
#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_MASK (0x3 << 14)
#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_OFFSET (12)
#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_MASK (0x3 << 12)
#define MXC_CCM_CSCMR2_SIM_CLK_SEL_OFFSET (10)
#define MXC_CCM_CSCMR2_SIM_CLK_SEL_MASK (0x3 << 10)
#define MXC_CCM_CSCMR2_SLIMBUS_COM (0x1 << 9)
#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_OFFSET (6)
#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_MASK (0x7 << 6)
#define MXC_CCM_CSCMR2_SPDIF1_COM (1 << 5)
#define MXC_CCM_CSCMR2_SPDIF0_COM (1 << 4)
#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET (2)
#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK (0x3 << 2)
#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET (0)
#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK (0x3)
/* Define the bits in register CSCDR1 */
#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET (22)
#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22)
#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET (19)
#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19)
#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_OFFSET (22)
#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_MASK (0x7 << 22)
#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_OFFSET (19)
#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_MASK (0x7 << 19)
#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET (16)
#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16)
#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14)
#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14)
#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET (11)
#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11)
#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET (8)
#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET (6)
#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET (3)
#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3)
#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET (0)
#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x7)
/* Define the bits in register CS1CDR and CS2CDR */
#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET (22)
#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK (0x7 << 22)
#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET (16)
#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK (0x3F << 16)
#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET (6)
#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6)
#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET (0)
#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F)
#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET (22)
#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK (0x7 << 22)
#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET (16)
#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK (0x3F << 16)
#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET (6)
#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6)
#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET (0)
#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F)
/* Define the bits in register CDCDR */
#define MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET (28)
#define MXC_CCM_CDCDR_TVE_CLK_PRED_MASK (0x7 << 28)
#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET (25)
#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25)
#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET (19)
#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x3F << 19)
#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET (16)
#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 16)
#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET (9)
#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x3F << 9)
#define MXC_CCM_CDCDR_DI_CLK_PRED_OFFSET (6)
#define MXC_CCM_CDCDR_DI_CLK_PRED_MASK (0x7 << 6)
#define MXC_CCM_CDCDR_USB_PHY_PRED_OFFSET (3)
#define MXC_CCM_CDCDR_USB_PHY_PRED_MASK (0x7 << 3)
#define MXC_CCM_CDCDR_USB_PHY_PODF_OFFSET (0)
#define MXC_CCM_CDCDR_USB_PHY_PODF_MASK (0x7)
/* Define the bits in register CHSCCDR */
#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_OFFSET (12)
#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_MASK (0x7 << 12)
#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_OFFSET (6)
#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_MASK (0x3F << 6)
#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_OFFSET (3)
#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_MASK (0x7 << 3)
#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_OFFSET (0)
#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_MASK (0x7)
/* Define the bits in register CSCDR2 */
#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET (25)
#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25)
#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET (19)
#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19)
#define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET (16)
#define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16)
#define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET (9)
#define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9)
#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET (6)
#define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK (0x7 << 6)
#define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET (0)
#define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK (0x3F)
/* Define the bits in register CSCDR3 */
#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET (16)
#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_MASK (0x7 << 16)
#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET (9)
#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_MASK (0x3F << 9)
#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_OFFSET (6)
#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_MASK (0x7 << 6)
#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_OFFSET (0)
#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_MASK (0x3F)
/* Define the bits in register CSCDR4 */
#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET (16)
#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK (0x7 << 16)
#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET (9)
#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK (0x3F << 9)
#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET (6)
#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK (0x7 << 6)
#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET (0)
#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK (0x3F)
/* Define the bits in register CDHIPR */
#define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
#define MXC_CCM_CDHIPR_DDR_HF_CLK_SEL_BUSY (1 << 8)
#define MXC_CCM_CDHIPR_DDR_PODF_BUSY (1 << 7)
#define MXC_CCM_CDHIPR_EMI_CLK_SEL_BUSY (1 << 6)
#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5)
#define MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY (1 << 4)
#define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 3)
#define MXC_CCM_CDHIPR_EMI_PODF_BUSY (1 << 2)
#define MXC_CCM_CDHIPR_AXI_B_PODF_BUSY (1 << 1)
#define MXC_CCM_CDHIPR_AXI_A_PODF_BUSY (1 << 0)
/* Define the bits in register CDCR */
#define MXC_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER (0x1 << 2)
#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET (0)
#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK (0x3)
/* Define the bits in register CLPCR */
#define MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS (0x1 << 23)
#define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS (0x1 << 22)
#define MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 21)
#define MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 25)
#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 20)
#define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS (0x1 << 19)
#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18)
#define MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS (0x1 << 17)
#define MXC_CCM_CLPCR_BYPASS_RNGC_LPM_HS (0x1 << 16)
#define MXC_CCM_CLPCR_COSC_PWRDOWN (0x1 << 11)
#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET (9)
#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9)
#define MXC_CCM_CLPCR_VSTBY (0x1 << 8)
#define MXC_CCM_CLPCR_DIS_REF_OSC (0x1 << 7)
#define MXC_CCM_CLPCR_SBYOS (0x1 << 6)
#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)
#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET (3)
#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3)
#define MXC_CCM_CLPCR_LPM_OFFSET (0)
#define MXC_CCM_CLPCR_LPM_MASK (0x3)
/* Define the bits in register CISR */
#define MXC_CCM_CISR_ARM_PODF_LOADED (0x1 << 25)
#define MXC_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21)
#define MXC_CCM_CISR_AHB_PODF_LOADED (0x1 << 20)
#define MXC_CCM_CISR_EMI_PODF_LOADED (0x1 << 19)
#define MXC_CCM_CISR_AXI_B_PODF_LOADED (0x1 << 18)
#define MXC_CCM_CISR_AXI_A_PODF_LOADED (0x1 << 17)
#define MXC_CCM_CISR_DIVIDER_LOADED (0x1 << 16)
#define MXC_CCM_CISR_COSC_READY (0x1 << 6)
#define MXC_CCM_CISR_CKIH2_READY (0x1 << 5)
#define MXC_CCM_CISR_CKIH_READY (0x1 << 4)
#define MXC_CCM_CISR_FPM_READY (0x1 << 3)
#define MXC_CCM_CISR_LRF_PLL3 (0x1 << 2)
#define MXC_CCM_CISR_LRF_PLL2 (0x1 << 1)
#define MXC_CCM_CISR_LRF_PLL1 (0x1)
/* Define the bits in register CIMR */
#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (0x1 << 25)
#define MXC_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21)
#define MXC_CCM_CIMR_MASK_EMI_PODF_LOADED (0x1 << 20)
#define MXC_CCM_CIMR_MASK_AXI_C_PODF_LOADED (0x1 << 19)
#define MXC_CCM_CIMR_MASK_AXI_B_PODF_LOADED (0x1 << 18)
#define MXC_CCM_CIMR_MASK_AXI_A_PODF_LOADED (0x1 << 17)
#define MXC_CCM_CIMR_MASK_DIVIDER_LOADED (0x1 << 16)
#define MXC_CCM_CIMR_MASK_COSC_READY (0x1 << 5)
#define MXC_CCM_CIMR_MASK_CKIH_READY (0x1 << 4)
#define MXC_CCM_CIMR_MASK_FPM_READY (0x1 << 3)
#define MXC_CCM_CIMR_MASK_LRF_PLL3 (0x1 << 2)
#define MXC_CCM_CIMR_MASK_LRF_PLL2 (0x1 << 1)
#define MXC_CCM_CIMR_MASK_LRF_PLL1 (0x1)
/* Define the bits in register CCOSR */
#define MXC_CCM_CCOSR_CKO2_EN_OFFSET (0x1 << 24)
#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET (21)
#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21)
#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET (16)
#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16)
#define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7)
#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET (4)
#define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4)
#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET (0)
#define MXC_CCM_CCOSR_CKOL_SEL_MASK (0xF)
/* Define the bits in registers CGPR */
#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (0x1 << 4)
#define MXC_CCM_CGPR_FPM_SEL (0x1 << 3)
#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET (0)
#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_MASK (0x7)
/* Define the bits in registers CCGRx */
#define MXC_CCM_CCGRx_CG_MASK 0x3
#define MXC_CCM_CCGRx_MOD_OFF 0x0
#define MXC_CCM_CCGRx_MOD_ON 0x3
#define MXC_CCM_CCGRx_MOD_IDLE 0x1
#define MXC_CCM_CCGRx_CG15_MASK (0x3 << 30)
#define MXC_CCM_CCGRx_CG14_MASK (0x3 << 28)
#define MXC_CCM_CCGRx_CG13_MASK (0x3 << 26)
#define MXC_CCM_CCGRx_CG12_MASK (0x3 << 24)
#define MXC_CCM_CCGRx_CG11_MASK (0x3 << 22)
#define MXC_CCM_CCGRx_CG10_MASK (0x3 << 20)
#define MXC_CCM_CCGRx_CG9_MASK (0x3 << 18)
#define MXC_CCM_CCGRx_CG8_MASK (0x3 << 16)
#define MXC_CCM_CCGRx_CG5_MASK (0x3 << 10)
#define MXC_CCM_CCGRx_CG4_MASK (0x3 << 8)
#define MXC_CCM_CCGRx_CG3_MASK (0x3 << 6)
#define MXC_CCM_CCGRx_CG2_MASK (0x3 << 4)
#define MXC_CCM_CCGRx_CG1_MASK (0x3 << 2)
#define MXC_CCM_CCGRx_CG0_MASK (0x3 << 0)
#define MXC_CCM_CCGRx_CG15_OFFSET 30
#define MXC_CCM_CCGRx_CG14_OFFSET 28
#define MXC_CCM_CCGRx_CG13_OFFSET 26
#define MXC_CCM_CCGRx_CG12_OFFSET 24
#define MXC_CCM_CCGRx_CG11_OFFSET 22
#define MXC_CCM_CCGRx_CG10_OFFSET 20
#define MXC_CCM_CCGRx_CG9_OFFSET 18
#define MXC_CCM_CCGRx_CG8_OFFSET 16
#define MXC_CCM_CCGRx_CG7_OFFSET 14
#define MXC_CCM_CCGRx_CG6_OFFSET 12
#define MXC_CCM_CCGRx_CG5_OFFSET 10
#define MXC_CCM_CCGRx_CG4_OFFSET 8
#define MXC_CCM_CCGRx_CG3_OFFSET 6
#define MXC_CCM_CCGRx_CG2_OFFSET 4
#define MXC_CCM_CCGRx_CG1_OFFSET 2
#define MXC_CCM_CCGRx_CG0_OFFSET 0
#define MXC_DPTC_LP_BASE (MX51_GPC_BASE + 0x80)
#define MXC_DPTC_GP_BASE (MX51_GPC_BASE + 0x100)
#define MXC_DVFS_CORE_BASE (MX51_GPC_BASE + 0x180)
#define MXC_DPTC_PER_BASE (MX51_GPC_BASE + 0x1C0)
#define MXC_PGC_IPU_BASE (MX51_GPC_BASE + 0x220)
#define MXC_PGC_VPU_BASE (MX51_GPC_BASE + 0x240)
#define MXC_PGC_GPU_BASE (MX51_GPC_BASE + 0x260)
#define MXC_SRPG_NEON_BASE (MX51_GPC_BASE + 0x280)
#define MXC_SRPG_ARM_BASE (MX51_GPC_BASE + 0x2A0)
#define MXC_SRPG_EMPGC0_BASE (MX51_GPC_BASE + 0x2C0)
#define MXC_SRPG_EMPGC1_BASE (MX51_GPC_BASE + 0x2D0)
#define MXC_SRPG_MEGAMIX_BASE (MX51_GPC_BASE + 0x2E0)
#define MXC_SRPG_EMI_BASE (MX51_GPC_BASE + 0x300)
/* CORTEXA8 platform */
#define MXC_CORTEXA8_PLAT_PVID (MX51_CORTEXA8_BASE + 0x0)
#define MXC_CORTEXA8_PLAT_GPC (MX51_CORTEXA8_BASE + 0x4)
#define MXC_CORTEXA8_PLAT_PIC (MX51_CORTEXA8_BASE + 0x8)
#define MXC_CORTEXA8_PLAT_LPC (MX51_CORTEXA8_BASE + 0xC)
#define MXC_CORTEXA8_PLAT_NEON_LPC (MX51_CORTEXA8_BASE + 0x10)
#define MXC_CORTEXA8_PLAT_ICGC (MX51_CORTEXA8_BASE + 0x14)
#define MXC_CORTEXA8_PLAT_AMC (MX51_CORTEXA8_BASE + 0x18)
#define MXC_CORTEXA8_PLAT_NMC (MX51_CORTEXA8_BASE + 0x20)
#define MXC_CORTEXA8_PLAT_NMS (MX51_CORTEXA8_BASE + 0x24)
/* DVFS CORE */
#define MXC_DVFSTHRS (MXC_DVFS_CORE_BASE + 0x00)
#define MXC_DVFSCOUN (MXC_DVFS_CORE_BASE + 0x04)
#define MXC_DVFSSIG1 (MXC_DVFS_CORE_BASE + 0x08)
#define MXC_DVFSSIG0 (MXC_DVFS_CORE_BASE + 0x0C)
#define MXC_DVFSGPC0 (MXC_DVFS_CORE_BASE + 0x10)
#define MXC_DVFSGPC1 (MXC_DVFS_CORE_BASE + 0x14)
#define MXC_DVFSGPBT (MXC_DVFS_CORE_BASE + 0x18)
#define MXC_DVFSEMAC (MXC_DVFS_CORE_BASE + 0x1C)
#define MXC_DVFSCNTR (MXC_DVFS_CORE_BASE + 0x20)
#define MXC_DVFSLTR0_0 (MXC_DVFS_CORE_BASE + 0x24)
#define MXC_DVFSLTR0_1 (MXC_DVFS_CORE_BASE + 0x28)
#define MXC_DVFSLTR1_0 (MXC_DVFS_CORE_BASE + 0x2C)
#define MXC_DVFSLTR1_1 (MXC_DVFS_CORE_BASE + 0x30)
#define MXC_DVFSPT0 (MXC_DVFS_CORE_BASE + 0x34)
#define MXC_DVFSPT1 (MXC_DVFS_CORE_BASE + 0x38)
#define MXC_DVFSPT2 (MXC_DVFS_CORE_BASE + 0x3C)
#define MXC_DVFSPT3 (MXC_DVFS_CORE_BASE + 0x40)
/* GPC */
#define MXC_GPC_CNTR (MX51_GPC_BASE + 0x0)
#define MXC_GPC_PGR (MX51_GPC_BASE + 0x4)
#define MXC_GPC_VCR (MX51_GPC_BASE + 0x8)
#define MXC_GPC_ALL_PU (MX51_GPC_BASE + 0xC)
#define MXC_GPC_NEON (MX51_GPC_BASE + 0x10)
#define MXC_GPC_PGR_ARMPG_OFFSET 8
#define MXC_GPC_PGR_ARMPG_MASK (3 << 8)
/* PGC */
#define MXC_PGC_IPU_PGCR (MXC_PGC_IPU_BASE + 0x0)
#define MXC_PGC_IPU_PGSR (MXC_PGC_IPU_BASE + 0xC)
#define MXC_PGC_VPU_PGCR (MXC_PGC_VPU_BASE + 0x0)
#define MXC_PGC_VPU_PGSR (MXC_PGC_VPU_BASE + 0xC)
#define MXC_PGC_GPU_PGCR (MXC_PGC_GPU_BASE + 0x0)
#define MXC_PGC_GPU_PGSR (MXC_PGC_GPU_BASE + 0xC)
#define MXC_PGCR_PCR 1
#define MXC_SRPGCR_PCR 1
#define MXC_EMPGCR_PCR 1
#define MXC_PGSR_PSR 1
#define MXC_CORTEXA8_PLAT_LPC_DSM (1 << 0)
#define MXC_CORTEXA8_PLAT_LPC_DBG_DSM (1 << 1)
/* SRPG */
#define MXC_SRPG_NEON_SRPGCR (MXC_SRPG_NEON_BASE + 0x0)
#define MXC_SRPG_NEON_PUPSCR (MXC_SRPG_NEON_BASE + 0x4)
#define MXC_SRPG_NEON_PDNSCR (MXC_SRPG_NEON_BASE + 0x8)
#define MXC_SRPG_ARM_SRPGCR (MXC_SRPG_ARM_BASE + 0x0)
#define MXC_SRPG_ARM_PUPSCR (MXC_SRPG_ARM_BASE + 0x4)
#define MXC_SRPG_ARM_PDNSCR (MXC_SRPG_ARM_BASE + 0x8)
#define MXC_SRPG_EMPGC0_SRPGCR (MXC_SRPG_EMPGC0_BASE + 0x0)
#define MXC_SRPG_EMPGC0_PUPSCR (MXC_SRPG_EMPGC0_BASE + 0x4)
#define MXC_SRPG_EMPGC0_PDNSCR (MXC_SRPG_EMPGC0_BASE + 0x8)
#define MXC_SRPG_EMPGC1_SRPGCR (MXC_SRPG_EMPGC1_BASE + 0x0)
#define MXC_SRPG_EMPGC1_PUPSCR (MXC_SRPG_EMPGC1_BASE + 0x4)
#define MXC_SRPG_EMPGC1_PDNSCR (MXC_SRPG_EMPGC1_BASE + 0x8)
#define MXC_SRPG_MEGAMIX_SRPGCR (MXC_SRPG_MEGAMIX_BASE + 0x0)
#define MXC_SRPG_MEGAMIX_PUPSCR (MXC_SRPG_MEGAMIX_BASE + 0x4)
#define MXC_SRPG_MEGAMIX_PDNSCR (MXC_SRPG_MEGAMIX_BASE + 0x8)
#define MXC_SRPGC_EMI_SRPGCR (MXC_SRPGC_EMI_BASE + 0x0)
#define MXC_SRPGC_EMI_PUPSCR (MXC_SRPGC_EMI_BASE + 0x4)
#define MXC_SRPGC_EMI_PDNSCR (MXC_SRPGC_EMI_BASE + 0x8)
#endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */

66
arch/arm/mach-imx/devices-imx51.h
View File

@ -1,66 +0,0 @@
/*
* Copyright (C) 2010 Pengutronix
* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
*
* This program is free software; you can redistribute it and/or modify it under
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
#include "devices/devices-common.h"
extern const struct imx_fec_data imx51_fec_data;
#define imx51_add_fec(pdata) \
imx_add_fec(&imx51_fec_data, pdata)
extern const struct imx_fsl_usb2_udc_data imx51_fsl_usb2_udc_data;
#define imx51_add_fsl_usb2_udc(pdata) \
imx_add_fsl_usb2_udc(&imx51_fsl_usb2_udc_data, pdata)
extern const struct imx_imx_i2c_data imx51_imx_i2c_data[];
#define imx51_add_imx_i2c(id, pdata) \
imx_add_imx_i2c(&imx51_imx_i2c_data[id], pdata)
#define imx51_add_hsi2c(pdata) \
imx51_add_imx_i2c(2, pdata)
extern const struct imx_imx_ssi_data imx51_imx_ssi_data[];
#define imx51_add_imx_ssi(id, pdata) \
imx_add_imx_ssi(&imx51_imx_ssi_data[id], pdata)
extern const struct imx_imx_uart_1irq_data imx51_imx_uart_data[];
#define imx51_add_imx_uart(id, pdata) \
imx_add_imx_uart_1irq(&imx51_imx_uart_data[id], pdata)
extern const struct imx_mxc_ehci_data imx51_mxc_ehci_otg_data;
#define imx51_add_mxc_ehci_otg(pdata) \
imx_add_mxc_ehci(&imx51_mxc_ehci_otg_data, pdata)
extern const struct imx_mxc_ehci_data imx51_mxc_ehci_hs_data[];
#define imx51_add_mxc_ehci_hs(id, pdata) \
imx_add_mxc_ehci(&imx51_mxc_ehci_hs_data[id - 1], pdata)
extern const struct imx_mxc_nand_data imx51_mxc_nand_data;
#define imx51_add_mxc_nand(pdata) \
imx_add_mxc_nand(&imx51_mxc_nand_data, pdata)
extern const struct imx_sdhci_esdhc_imx_data imx51_sdhci_esdhc_imx_data[];
#define imx51_add_sdhci_esdhc_imx(id, pdata) \
imx_add_sdhci_esdhc_imx(&imx51_sdhci_esdhc_imx_data[id], pdata)
extern const struct imx_spi_imx_data imx51_cspi_data;
#define imx51_add_cspi(pdata) \
imx_add_spi_imx(&imx51_cspi_data, pdata)
extern const struct imx_spi_imx_data imx51_ecspi_data[];
#define imx51_add_ecspi(id, pdata) \
imx_add_spi_imx(&imx51_ecspi_data[id], pdata)
extern const struct imx_imx2_wdt_data imx51_imx2_wdt_data[];
#define imx51_add_imx2_wdt(id) \
imx_add_imx2_wdt(&imx51_imx2_wdt_data[id])
extern const struct imx_imx_keypad_data imx51_imx_keypad_data;
#define imx51_add_imx_keypad(pdata) \
imx_add_imx_keypad(&imx51_imx_keypad_data, pdata)
extern const struct imx_pata_imx_data imx51_pata_imx_data;
#define imx51_add_pata_imx() \
imx_add_pata_imx(&imx51_pata_imx_data)

9
arch/arm/mach-imx/devices/Kconfig
View File

@ -1,6 +1,6 @@
config IMX_HAVE_PLATFORM_FEC
bool
default y if ARCH_MX25 || SOC_IMX27 || SOC_IMX35 || SOC_IMX51 || SOC_IMX53
default y if SOC_IMX25 || SOC_IMX27 || SOC_IMX35
config IMX_HAVE_PLATFORM_FLEXCAN
bool
@ -10,7 +10,6 @@ config IMX_HAVE_PLATFORM_FSL_USB2_UDC
config IMX_HAVE_PLATFORM_GPIO_KEYS
bool
default y if SOC_IMX51
config IMX_HAVE_PLATFORM_IMX21_HCD
bool
@ -43,15 +42,9 @@ config IMX_HAVE_PLATFORM_IMX_SSI
config IMX_HAVE_PLATFORM_IMX_UART
bool
config IMX_HAVE_PLATFORM_IMX_UDC
bool
config IMX_HAVE_PLATFORM_IPU_CORE
bool
config IMX_HAVE_PLATFORM_MX1_CAMERA
bool
config IMX_HAVE_PLATFORM_MX2_CAMERA
bool

2
arch/arm/mach-imx/devices/Makefile
View File

@ -16,9 +16,7 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_KEYPAD) += platform-imx-keypad.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_PATA_IMX) += platform-pata_imx.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SSI) += platform-imx-ssi.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UDC) += platform-imx_udc.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_IPU_CORE) += platform-ipu-core.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_MX1_CAMERA) += platform-mx1-camera.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_CAMERA) += platform-mx2-camera.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI) += platform-mxc-ehci.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_MMC) += platform-mxc-mmc.o

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