MLK-23917-3 phy: freescale: imx8mq-usb: disable alternate clock

As we use internal MPLL clocks instead of alternate clocks, so
disable alternate clock to save the PHY power when SS PHY at P3.

Reviewed-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Li Jun <jun.li@nxp.com>

drivers/phy/freescale/phy-fsl-imx8mq-usb.c

@@ -31,6 +31,7 @@
 
 #define PHY_CTRL6			0x18
 #define PHY_CTRL6_RXTERM_OVERRIDE_SEL	BIT(29)
+#define PHY_CTRL6_ALT_CLK_EN		BIT(1)
 #define PHY_CTRL6_ALT_CLK_SEL		BIT(0)
 
 struct imx8mq_usb_phy {
@@ -79,9 +80,9 @@ static int imx8mp_usb_phy_init(struct phy *phy)
 	value |= (PHY_CTRL0_FSEL_24M << 5);
 	writel(value, imx_phy->base + PHY_CTRL0);
 
-	/* disable alt_clk_sel */
+	/* Disable alt_clk_en and use internal MPLL clocks */
 	value = readl(imx_phy->base + PHY_CTRL6);
-	value &= ~PHY_CTRL6_ALT_CLK_SEL;
+	value &= ~(PHY_CTRL6_ALT_CLK_SEL | PHY_CTRL6_ALT_CLK_EN);
 	writel(value, imx_phy->base + PHY_CTRL6);
 
 	value = readl(imx_phy->base + PHY_CTRL1);