Merge pull request #60 from zandrey/4.19.x+fslc
4.19.x+fslc: upgrade 4.19.78 to 4.19.107
This commit is contained in:
Otavio Salvador
GitHub
commit
a764f56c76
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@ -199,7 +199,7 @@ Description:
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What: /sys/bus/iio/devices/iio:deviceX/in_positionrelative_x_raw
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What: /sys/bus/iio/devices/iio:deviceX/in_positionrelative_y_raw
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KernelVersion: 4.18
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KernelVersion: 4.19
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Contact: linux-iio@vger.kernel.org
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Description:
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Relative position in direction x or y on a pad (may be
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@ -4,7 +4,7 @@ KernelVersion: 3.10
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Contact: Samuel Ortiz <sameo@linux.intel.com>
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linux-mei@linux.intel.com
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Description: Stores the same MODALIAS value emitted by uevent
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Format: mei:<mei device name>:<device uuid>:
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Format: mei:<mei device name>:<device uuid>:<protocol version>
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What: /sys/bus/mei/devices/.../name
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Date: May 2015
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@ -7,6 +7,13 @@ Description:
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The name of devfreq object denoted as ... is same as the
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name of device using devfreq.
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What: /sys/class/devfreq/.../name
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Date: November 2019
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Contact: Chanwoo Choi <cw00.choi@samsung.com>
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Description:
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The /sys/class/devfreq/.../name shows the name of device
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of the corresponding devfreq object.
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What: /sys/class/devfreq/.../governor
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Date: September 2011
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Contact: MyungJoo Ham <myungjoo.ham@samsung.com>
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@ -478,6 +478,8 @@ What: /sys/devices/system/cpu/vulnerabilities
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/sys/devices/system/cpu/vulnerabilities/spec_store_bypass
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/sys/devices/system/cpu/vulnerabilities/l1tf
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/sys/devices/system/cpu/vulnerabilities/mds
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/sys/devices/system/cpu/vulnerabilities/tsx_async_abort
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/sys/devices/system/cpu/vulnerabilities/itlb_multihit
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Date: January 2018
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Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org>
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Description: Information about CPU vulnerabilities
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@ -12,3 +12,5 @@ are configurable at compile, boot or run time.
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spectre
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l1tf
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mds
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tsx_async_abort
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multihit.rst
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@ -265,8 +265,11 @@ time with the option "mds=". The valid arguments for this option are:
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============ =============================================================
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Not specifying this option is equivalent to "mds=full".
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Not specifying this option is equivalent to "mds=full". For processors
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that are affected by both TAA (TSX Asynchronous Abort) and MDS,
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specifying just "mds=off" without an accompanying "tsx_async_abort=off"
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will have no effect as the same mitigation is used for both
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vulnerabilities.
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Mitigation selection guide
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--------------------------
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@ -0,0 +1,163 @@
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iTLB multihit
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=============
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iTLB multihit is an erratum where some processors may incur a machine check
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error, possibly resulting in an unrecoverable CPU lockup, when an
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instruction fetch hits multiple entries in the instruction TLB. This can
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occur when the page size is changed along with either the physical address
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or cache type. A malicious guest running on a virtualized system can
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exploit this erratum to perform a denial of service attack.
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Affected processors
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-------------------
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Variations of this erratum are present on most Intel Core and Xeon processor
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models. The erratum is not present on:
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- non-Intel processors
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- Some Atoms (Airmont, Bonnell, Goldmont, GoldmontPlus, Saltwell, Silvermont)
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- Intel processors that have the PSCHANGE_MC_NO bit set in the
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IA32_ARCH_CAPABILITIES MSR.
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Related CVEs
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------------
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The following CVE entry is related to this issue:
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============== =================================================
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CVE-2018-12207 Machine Check Error Avoidance on Page Size Change
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============== =================================================
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Problem
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-------
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Privileged software, including OS and virtual machine managers (VMM), are in
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charge of memory management. A key component in memory management is the control
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of the page tables. Modern processors use virtual memory, a technique that creates
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the illusion of a very large memory for processors. This virtual space is split
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into pages of a given size. Page tables translate virtual addresses to physical
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addresses.
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To reduce latency when performing a virtual to physical address translation,
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processors include a structure, called TLB, that caches recent translations.
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There are separate TLBs for instruction (iTLB) and data (dTLB).
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Under this errata, instructions are fetched from a linear address translated
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using a 4 KB translation cached in the iTLB. Privileged software modifies the
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paging structure so that the same linear address using large page size (2 MB, 4
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MB, 1 GB) with a different physical address or memory type. After the page
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structure modification but before the software invalidates any iTLB entries for
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the linear address, a code fetch that happens on the same linear address may
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cause a machine-check error which can result in a system hang or shutdown.
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Attack scenarios
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----------------
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Attacks against the iTLB multihit erratum can be mounted from malicious
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guests in a virtualized system.
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iTLB multihit system information
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--------------------------------
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The Linux kernel provides a sysfs interface to enumerate the current iTLB
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multihit status of the system:whether the system is vulnerable and which
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mitigations are active. The relevant sysfs file is:
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/sys/devices/system/cpu/vulnerabilities/itlb_multihit
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The possible values in this file are:
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.. list-table::
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* - Not affected
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- The processor is not vulnerable.
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* - KVM: Mitigation: Split huge pages
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- Software changes mitigate this issue.
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* - KVM: Vulnerable
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- The processor is vulnerable, but no mitigation enabled
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Enumeration of the erratum
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--------------------------------
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A new bit has been allocated in the IA32_ARCH_CAPABILITIES (PSCHANGE_MC_NO) msr
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and will be set on CPU's which are mitigated against this issue.
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======================================= =========== ===============================
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IA32_ARCH_CAPABILITIES MSR Not present Possibly vulnerable,check model
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IA32_ARCH_CAPABILITIES[PSCHANGE_MC_NO] '0' Likely vulnerable,check model
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IA32_ARCH_CAPABILITIES[PSCHANGE_MC_NO] '1' Not vulnerable
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======================================= =========== ===============================
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Mitigation mechanism
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-------------------------
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This erratum can be mitigated by restricting the use of large page sizes to
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non-executable pages. This forces all iTLB entries to be 4K, and removes
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the possibility of multiple hits.
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In order to mitigate the vulnerability, KVM initially marks all huge pages
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as non-executable. If the guest attempts to execute in one of those pages,
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the page is broken down into 4K pages, which are then marked executable.
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If EPT is disabled or not available on the host, KVM is in control of TLB
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flushes and the problematic situation cannot happen. However, the shadow
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EPT paging mechanism used by nested virtualization is vulnerable, because
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the nested guest can trigger multiple iTLB hits by modifying its own
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(non-nested) page tables. For simplicity, KVM will make large pages
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non-executable in all shadow paging modes.
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Mitigation control on the kernel command line and KVM - module parameter
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------------------------------------------------------------------------
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The KVM hypervisor mitigation mechanism for marking huge pages as
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non-executable can be controlled with a module parameter "nx_huge_pages=".
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The kernel command line allows to control the iTLB multihit mitigations at
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boot time with the option "kvm.nx_huge_pages=".
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The valid arguments for these options are:
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========== ================================================================
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force Mitigation is enabled. In this case, the mitigation implements
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non-executable huge pages in Linux kernel KVM module. All huge
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pages in the EPT are marked as non-executable.
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If a guest attempts to execute in one of those pages, the page is
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broken down into 4K pages, which are then marked executable.
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off Mitigation is disabled.
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auto Enable mitigation only if the platform is affected and the kernel
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was not booted with the "mitigations=off" command line parameter.
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This is the default option.
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========== ================================================================
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Mitigation selection guide
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--------------------------
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1. No virtualization in use
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^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The system is protected by the kernel unconditionally and no further
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action is required.
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2. Virtualization with trusted guests
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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If the guest comes from a trusted source, you may assume that the guest will
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not attempt to maliciously exploit these errata and no further action is
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required.
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3. Virtualization with untrusted guests
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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If the guest comes from an untrusted source, the guest host kernel will need
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to apply iTLB multihit mitigation via the kernel command line or kvm
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module parameter.
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@ -0,0 +1,279 @@
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.. SPDX-License-Identifier: GPL-2.0
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TAA - TSX Asynchronous Abort
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======================================
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TAA is a hardware vulnerability that allows unprivileged speculative access to
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data which is available in various CPU internal buffers by using asynchronous
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aborts within an Intel TSX transactional region.
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Affected processors
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-------------------
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This vulnerability only affects Intel processors that support Intel
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Transactional Synchronization Extensions (TSX) when the TAA_NO bit (bit 8)
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is 0 in the IA32_ARCH_CAPABILITIES MSR. On processors where the MDS_NO bit
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(bit 5) is 0 in the IA32_ARCH_CAPABILITIES MSR, the existing MDS mitigations
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also mitigate against TAA.
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Whether a processor is affected or not can be read out from the TAA
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vulnerability file in sysfs. See :ref:`tsx_async_abort_sys_info`.
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Related CVEs
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------------
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The following CVE entry is related to this TAA issue:
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============== ===== ===================================================
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CVE-2019-11135 TAA TSX Asynchronous Abort (TAA) condition on some
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microprocessors utilizing speculative execution may
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allow an authenticated user to potentially enable
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information disclosure via a side channel with
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local access.
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============== ===== ===================================================
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Problem
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-------
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When performing store, load or L1 refill operations, processors write
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data into temporary microarchitectural structures (buffers). The data in
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those buffers can be forwarded to load operations as an optimization.
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Intel TSX is an extension to the x86 instruction set architecture that adds
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hardware transactional memory support to improve performance of multi-threaded
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software. TSX lets the processor expose and exploit concurrency hidden in an
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application due to dynamically avoiding unnecessary synchronization.
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TSX supports atomic memory transactions that are either committed (success) or
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aborted. During an abort, operations that happened within the transactional region
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are rolled back. An asynchronous abort takes place, among other options, when a
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different thread accesses a cache line that is also used within the transactional
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region when that access might lead to a data race.
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Immediately after an uncompleted asynchronous abort, certain speculatively
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executed loads may read data from those internal buffers and pass it to dependent
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operations. This can be then used to infer the value via a cache side channel
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attack.
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Because the buffers are potentially shared between Hyper-Threads cross
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Hyper-Thread attacks are possible.
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The victim of a malicious actor does not need to make use of TSX. Only the
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attacker needs to begin a TSX transaction and raise an asynchronous abort
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which in turn potenitally leaks data stored in the buffers.
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More detailed technical information is available in the TAA specific x86
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architecture section: :ref:`Documentation/x86/tsx_async_abort.rst <tsx_async_abort>`.
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Attack scenarios
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----------------
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Attacks against the TAA vulnerability can be implemented from unprivileged
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applications running on hosts or guests.
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As for MDS, the attacker has no control over the memory addresses that can
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be leaked. Only the victim is responsible for bringing data to the CPU. As
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a result, the malicious actor has to sample as much data as possible and
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then postprocess it to try to infer any useful information from it.
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A potential attacker only has read access to the data. Also, there is no direct
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privilege escalation by using this technique.
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.. _tsx_async_abort_sys_info:
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TAA system information
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-----------------------
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The Linux kernel provides a sysfs interface to enumerate the current TAA status
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of mitigated systems. The relevant sysfs file is:
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/sys/devices/system/cpu/vulnerabilities/tsx_async_abort
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The possible values in this file are:
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.. list-table::
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* - 'Vulnerable'
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- The CPU is affected by this vulnerability and the microcode and kernel mitigation are not applied.
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* - 'Vulnerable: Clear CPU buffers attempted, no microcode'
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- The system tries to clear the buffers but the microcode might not support the operation.
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* - 'Mitigation: Clear CPU buffers'
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- The microcode has been updated to clear the buffers. TSX is still enabled.
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* - 'Mitigation: TSX disabled'
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- TSX is disabled.
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* - 'Not affected'
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- The CPU is not affected by this issue.
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.. _ucode_needed:
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Best effort mitigation mode
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^^^^^^^^^^^^^^^^^^^^^^^^^^^
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If the processor is vulnerable, but the availability of the microcode-based
|
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mitigation mechanism is not advertised via CPUID the kernel selects a best
|
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effort mitigation mode. This mode invokes the mitigation instructions
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without a guarantee that they clear the CPU buffers.
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This is done to address virtualization scenarios where the host has the
|
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microcode update applied, but the hypervisor is not yet updated to expose the
|
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CPUID to the guest. If the host has updated microcode the protection takes
|
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effect; otherwise a few CPU cycles are wasted pointlessly.
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|
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The state in the tsx_async_abort sysfs file reflects this situation
|
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accordingly.
|
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|
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Mitigation mechanism
|
||||
--------------------
|
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|
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The kernel detects the affected CPUs and the presence of the microcode which is
|
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required. If a CPU is affected and the microcode is available, then the kernel
|
||||
enables the mitigation by default.
|
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|
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|
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The mitigation can be controlled at boot time via a kernel command line option.
|
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See :ref:`taa_mitigation_control_command_line`.
|
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|
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.. _virt_mechanism:
|
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|
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Virtualization mitigation
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
Affected systems where the host has TAA microcode and TAA is mitigated by
|
||||
having disabled TSX previously, are not vulnerable regardless of the status
|
||||
of the VMs.
|
||||
|
||||
In all other cases, if the host either does not have the TAA microcode or
|
||||
the kernel is not mitigated, the system might be vulnerable.
|
||||
|
||||
|
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.. _taa_mitigation_control_command_line:
|
||||
|
||||
Mitigation control on the kernel command line
|
||||
---------------------------------------------
|
||||
|
||||
The kernel command line allows to control the TAA mitigations at boot time with
|
||||
the option "tsx_async_abort=". The valid arguments for this option are:
|
||||
|
||||
============ =============================================================
|
||||
off This option disables the TAA mitigation on affected platforms.
|
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If the system has TSX enabled (see next parameter) and the CPU
|
||||
is affected, the system is vulnerable.
|
||||
|
||||
full TAA mitigation is enabled. If TSX is enabled, on an affected
|
||||
system it will clear CPU buffers on ring transitions. On
|
||||
systems which are MDS-affected and deploy MDS mitigation,
|
||||
TAA is also mitigated. Specifying this option on those
|
||||
systems will have no effect.
|
||||
|
||||
full,nosmt The same as tsx_async_abort=full, with SMT disabled on
|
||||
vulnerable CPUs that have TSX enabled. This is the complete
|
||||
mitigation. When TSX is disabled, SMT is not disabled because
|
||||
CPU is not vulnerable to cross-thread TAA attacks.
|
||||
============ =============================================================
|
||||
|
||||
Not specifying this option is equivalent to "tsx_async_abort=full". For
|
||||
processors that are affected by both TAA and MDS, specifying just
|
||||
"tsx_async_abort=off" without an accompanying "mds=off" will have no
|
||||
effect as the same mitigation is used for both vulnerabilities.
|
||||
|
||||
The kernel command line also allows to control the TSX feature using the
|
||||
parameter "tsx=" on CPUs which support TSX control. MSR_IA32_TSX_CTRL is used
|
||||
to control the TSX feature and the enumeration of the TSX feature bits (RTM
|
||||
and HLE) in CPUID.
|
||||
|
||||
The valid options are:
|
||||
|
||||
============ =============================================================
|
||||
off Disables TSX on the system.
|
||||
|
||||
Note that this option takes effect only on newer CPUs which are
|
||||
not vulnerable to MDS, i.e., have MSR_IA32_ARCH_CAPABILITIES.MDS_NO=1
|
||||
and which get the new IA32_TSX_CTRL MSR through a microcode
|
||||
update. This new MSR allows for the reliable deactivation of
|
||||
the TSX functionality.
|
||||
|
||||
on Enables TSX.
|
||||
|
||||
Although there are mitigations for all known security
|
||||
vulnerabilities, TSX has been known to be an accelerator for
|
||||
several previous speculation-related CVEs, and so there may be
|
||||
unknown security risks associated with leaving it enabled.
|
||||
|
||||
auto Disables TSX if X86_BUG_TAA is present, otherwise enables TSX
|
||||
on the system.
|
||||
============ =============================================================
|
||||
|
||||
Not specifying this option is equivalent to "tsx=off".
|
||||
|
||||
The following combinations of the "tsx_async_abort" and "tsx" are possible. For
|
||||
affected platforms tsx=auto is equivalent to tsx=off and the result will be:
|
||||
|
||||
========= ========================== =========================================
|
||||
tsx=on tsx_async_abort=full The system will use VERW to clear CPU
|
||||
buffers. Cross-thread attacks are still
|
||||
possible on SMT machines.
|
||||
tsx=on tsx_async_abort=full,nosmt As above, cross-thread attacks on SMT
|
||||
mitigated.
|
||||
tsx=on tsx_async_abort=off The system is vulnerable.
|
||||
tsx=off tsx_async_abort=full TSX might be disabled if microcode
|
||||
provides a TSX control MSR. If so,
|
||||
system is not vulnerable.
|
||||
tsx=off tsx_async_abort=full,nosmt Ditto
|
||||
tsx=off tsx_async_abort=off ditto
|
||||
========= ========================== =========================================
|
||||
|
||||
|
||||
For unaffected platforms "tsx=on" and "tsx_async_abort=full" does not clear CPU
|
||||
buffers. For platforms without TSX control (MSR_IA32_ARCH_CAPABILITIES.MDS_NO=0)
|
||||
"tsx" command line argument has no effect.
|
||||
|
||||
For the affected platforms below table indicates the mitigation status for the
|
||||
combinations of CPUID bit MD_CLEAR and IA32_ARCH_CAPABILITIES MSR bits MDS_NO
|
||||
and TSX_CTRL_MSR.
|
||||
|
||||
======= ========= ============= ========================================
|
||||
MDS_NO MD_CLEAR TSX_CTRL_MSR Status
|
||||
======= ========= ============= ========================================
|
||||
0 0 0 Vulnerable (needs microcode)
|
||||
0 1 0 MDS and TAA mitigated via VERW
|
||||
1 1 0 MDS fixed, TAA vulnerable if TSX enabled
|
||||
because MD_CLEAR has no meaning and
|
||||
VERW is not guaranteed to clear buffers
|
||||
1 X 1 MDS fixed, TAA can be mitigated by
|
||||
VERW or TSX_CTRL_MSR
|
||||
======= ========= ============= ========================================
|
||||
|
||||
Mitigation selection guide
|
||||
--------------------------
|
||||
|
||||
1. Trusted userspace and guests
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
If all user space applications are from a trusted source and do not execute
|
||||
untrusted code which is supplied externally, then the mitigation can be
|
||||
disabled. The same applies to virtualized environments with trusted guests.
|
||||
|
||||
|
||||
2. Untrusted userspace and guests
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
If there are untrusted applications or guests on the system, enabling TSX
|
||||
might allow a malicious actor to leak data from the host or from other
|
||||
processes running on the same physical core.
|
||||
|
||||
If the microcode is available and the TSX is disabled on the host, attacks
|
||||
are prevented in a virtualized environment as well, even if the VMs do not
|
||||
explicitly enable the mitigation.
|
||||
|
||||
|
||||
.. _taa_default_mitigations:
|
||||
|
||||
Default mitigations
|
||||
-------------------
|
||||
|
||||
The kernel's default action for vulnerable processors is:
|
||||
|
||||
- Deploy TSX disable mitigation (tsx_async_abort=full tsx=off).
|
||||
|
|
@ -113,7 +113,7 @@
|
|||
the GPE dispatcher.
|
||||
This facility can be used to prevent such uncontrolled
|
||||
GPE floodings.
|
||||
Format: <int>
|
||||
Format: <byte>
|
||||
|
||||
acpi_no_auto_serialize [HW,ACPI]
|
||||
Disable auto-serialization of AML methods
|
||||
|
|
@ -1946,6 +1946,12 @@
|
|||
Built with CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF=y,
|
||||
the default is off.
|
||||
|
||||
kpti= [ARM64] Control page table isolation of user
|
||||
and kernel address spaces.
|
||||
Default: enabled on cores which need mitigation.
|
||||
0: force disabled
|
||||
1: force enabled
|
||||
|
||||
kvm.ignore_msrs=[KVM] Ignore guest accesses to unhandled MSRs.
|
||||
Default is 0 (don't ignore, but inject #GP)
|
||||
|
||||
|
|
@ -1956,6 +1962,25 @@
|
|||
KVM MMU at runtime.
|
||||
Default is 0 (off)
|
||||
|
||||
kvm.nx_huge_pages=
|
||||
[KVM] Controls the software workaround for the
|
||||
X86_BUG_ITLB_MULTIHIT bug.
|
||||
force : Always deploy workaround.
|
||||
off : Never deploy workaround.
|
||||
auto : Deploy workaround based on the presence of
|
||||
X86_BUG_ITLB_MULTIHIT.
|
||||
|
||||
Default is 'auto'.
|
||||
|
||||
If the software workaround is enabled for the host,
|
||||
guests do need not to enable it for nested guests.
|
||||
|
||||
kvm.nx_huge_pages_recovery_ratio=
|
||||
[KVM] Controls how many 4KiB pages are periodically zapped
|
||||
back to huge pages. 0 disables the recovery, otherwise if
|
||||
the value is N KVM will zap 1/Nth of the 4KiB pages every
|
||||
minute. The default is 60.
|
||||
|
||||
kvm-amd.nested= [KVM,AMD] Allow nested virtualization in KVM/SVM.
|
||||
Default is 1 (enabled)
|
||||
|
||||
|
|
@ -2340,6 +2365,12 @@
|
|||
SMT on vulnerable CPUs
|
||||
off - Unconditionally disable MDS mitigation
|
||||
|
||||
On TAA-affected machines, mds=off can be prevented by
|
||||
an active TAA mitigation as both vulnerabilities are
|
||||
mitigated with the same mechanism so in order to disable
|
||||
this mitigation, you need to specify tsx_async_abort=off
|
||||
too.
|
||||
|
||||
Not specifying this option is equivalent to
|
||||
mds=full.
|
||||
|
||||
|
|
@ -2503,8 +2534,8 @@
|
|||
http://repo.or.cz/w/linux-2.6/mini2440.git
|
||||
|
||||
mitigations=
|
||||
[X86,PPC,S390] Control optional mitigations for CPU
|
||||
vulnerabilities. This is a set of curated,
|
||||
[X86,PPC,S390,ARM64] Control optional mitigations for
|
||||
CPU vulnerabilities. This is a set of curated,
|
||||
arch-independent options, each of which is an
|
||||
aggregation of existing arch-specific options.
|
||||
|
||||
|
|
@ -2513,14 +2544,23 @@
|
|||
improves system performance, but it may also
|
||||
expose users to several CPU vulnerabilities.
|
||||
Equivalent to: nopti [X86,PPC]
|
||||
kpti=0 [ARM64]
|
||||
nospectre_v1 [PPC]
|
||||
nobp=0 [S390]
|
||||
nospectre_v1 [X86]
|
||||
nospectre_v2 [X86,PPC,S390]
|
||||
nospectre_v2 [X86,PPC,S390,ARM64]
|
||||
spectre_v2_user=off [X86]
|
||||
spec_store_bypass_disable=off [X86,PPC]
|
||||
ssbd=force-off [ARM64]
|
||||
l1tf=off [X86]
|
||||
mds=off [X86]
|
||||
tsx_async_abort=off [X86]
|
||||
kvm.nx_huge_pages=off [X86]
|
||||
|
||||
Exceptions:
|
||||
This does not have any effect on
|
||||
kvm.nx_huge_pages when
|
||||
kvm.nx_huge_pages=force.
|
||||
|
||||
auto (default)
|
||||
Mitigate all CPU vulnerabilities, but leave SMT
|
||||
|
|
@ -2536,6 +2576,7 @@
|
|||
be fully mitigated, even if it means losing SMT.
|
||||
Equivalent to: l1tf=flush,nosmt [X86]
|
||||
mds=full,nosmt [X86]
|
||||
tsx_async_abort=full,nosmt [X86]
|
||||
|
||||
mminit_loglevel=
|
||||
[KNL] When CONFIG_DEBUG_MEMORY_INIT is set, this
|
||||
|
|
@ -2866,10 +2907,10 @@
|
|||
(bounds check bypass). With this option data leaks
|
||||
are possible in the system.
|
||||
|
||||
nospectre_v2 [X86,PPC_FSL_BOOK3E] Disable all mitigations for the Spectre variant 2
|
||||
(indirect branch prediction) vulnerability. System may
|
||||
allow data leaks with this option, which is equivalent
|
||||
to spectre_v2=off.
|
||||
nospectre_v2 [X86,PPC_FSL_BOOK3E,ARM64] Disable all mitigations for
|
||||
the Spectre variant 2 (indirect branch prediction)
|
||||
vulnerability. System may allow data leaks with this
|
||||
option.
|
||||
|
||||
nospec_store_bypass_disable
|
||||
[HW] Disable all mitigations for the Speculative Store Bypass vulnerability
|
||||
|
|
@ -4688,6 +4729,76 @@
|
|||
marks the TSC unconditionally unstable at bootup and
|
||||
avoids any further wobbles once the TSC watchdog notices.
|
||||
|
||||
tsx= [X86] Control Transactional Synchronization
|
||||
Extensions (TSX) feature in Intel processors that
|
||||
support TSX control.
|
||||
|
||||
This parameter controls the TSX feature. The options are:
|
||||
|
||||
on - Enable TSX on the system. Although there are
|
||||
mitigations for all known security vulnerabilities,
|
||||
TSX has been known to be an accelerator for
|
||||
several previous speculation-related CVEs, and
|
||||
so there may be unknown security risks associated
|
||||
with leaving it enabled.
|
||||
|
||||
off - Disable TSX on the system. (Note that this
|
||||
option takes effect only on newer CPUs which are
|
||||
not vulnerable to MDS, i.e., have
|
||||
MSR_IA32_ARCH_CAPABILITIES.MDS_NO=1 and which get
|
||||
the new IA32_TSX_CTRL MSR through a microcode
|
||||
update. This new MSR allows for the reliable
|
||||
deactivation of the TSX functionality.)
|
||||
|
||||
auto - Disable TSX if X86_BUG_TAA is present,
|
||||
otherwise enable TSX on the system.
|
||||
|
||||
Not specifying this option is equivalent to tsx=off.
|
||||
|
||||
See Documentation/admin-guide/hw-vuln/tsx_async_abort.rst
|
||||
for more details.
|
||||
|
||||
tsx_async_abort= [X86,INTEL] Control mitigation for the TSX Async
|
||||
Abort (TAA) vulnerability.
|
||||
|
||||
Similar to Micro-architectural Data Sampling (MDS)
|
||||
certain CPUs that support Transactional
|
||||
Synchronization Extensions (TSX) are vulnerable to an
|
||||
exploit against CPU internal buffers which can forward
|
||||
information to a disclosure gadget under certain
|
||||
conditions.
|
||||
|
||||
In vulnerable processors, the speculatively forwarded
|
||||
data can be used in a cache side channel attack, to
|
||||
access data to which the attacker does not have direct
|
||||
access.
|
||||
|
||||
This parameter controls the TAA mitigation. The
|
||||
options are:
|
||||
|
||||
full - Enable TAA mitigation on vulnerable CPUs
|
||||
if TSX is enabled.
|
||||
|
||||
full,nosmt - Enable TAA mitigation and disable SMT on
|
||||
vulnerable CPUs. If TSX is disabled, SMT
|
||||
is not disabled because CPU is not
|
||||
vulnerable to cross-thread TAA attacks.
|
||||
off - Unconditionally disable TAA mitigation
|
||||
|
||||
On MDS-affected machines, tsx_async_abort=off can be
|
||||
prevented by an active MDS mitigation as both vulnerabilities
|
||||
are mitigated with the same mechanism so in order to disable
|
||||
this mitigation, you need to specify mds=off too.
|
||||
|
||||
Not specifying this option is equivalent to
|
||||
tsx_async_abort=full. On CPUs which are MDS affected
|
||||
and deploy MDS mitigation, TAA mitigation is not
|
||||
required and doesn't provide any additional
|
||||
mitigation.
|
||||
|
||||
For details see:
|
||||
Documentation/admin-guide/hw-vuln/tsx_async_abort.rst
|
||||
|
||||
turbografx.map[2|3]= [HW,JOY]
|
||||
TurboGraFX parallel port interface
|
||||
Format:
|
||||
|
|
@ -4836,13 +4947,13 @@
|
|||
Flags is a set of characters, each corresponding
|
||||
to a common usb-storage quirk flag as follows:
|
||||
a = SANE_SENSE (collect more than 18 bytes
|
||||
of sense data);
|
||||
of sense data, not on uas);
|
||||
b = BAD_SENSE (don't collect more than 18
|
||||
bytes of sense data);
|
||||
bytes of sense data, not on uas);
|
||||
c = FIX_CAPACITY (decrease the reported
|
||||
device capacity by one sector);
|
||||
d = NO_READ_DISC_INFO (don't use
|
||||
READ_DISC_INFO command);
|
||||
READ_DISC_INFO command, not on uas);
|
||||
e = NO_READ_CAPACITY_16 (don't use
|
||||
READ_CAPACITY_16 command);
|
||||
f = NO_REPORT_OPCODES (don't use report opcodes
|
||||
|
|
@ -4857,17 +4968,18 @@
|
|||
j = NO_REPORT_LUNS (don't use report luns
|
||||
command, uas only);
|
||||
l = NOT_LOCKABLE (don't try to lock and
|
||||
unlock ejectable media);
|
||||
unlock ejectable media, not on uas);
|
||||
m = MAX_SECTORS_64 (don't transfer more
|
||||
than 64 sectors = 32 KB at a time);
|
||||
than 64 sectors = 32 KB at a time,
|
||||
not on uas);
|
||||
n = INITIAL_READ10 (force a retry of the
|
||||
initial READ(10) command);
|
||||
initial READ(10) command, not on uas);
|
||||
o = CAPACITY_OK (accept the capacity
|
||||
reported by the device);
|
||||
reported by the device, not on uas);
|
||||
p = WRITE_CACHE (the device cache is ON
|
||||
by default);
|
||||
by default, not on uas);
|
||||
r = IGNORE_RESIDUE (the device reports
|
||||
bogus residue values);
|
||||
bogus residue values, not on uas);
|
||||
s = SINGLE_LUN (the device has only one
|
||||
Logical Unit);
|
||||
t = NO_ATA_1X (don't allow ATA(12) and ATA(16)
|
||||
|
|
@ -4876,7 +4988,8 @@
|
|||
w = NO_WP_DETECT (don't test whether the
|
||||
medium is write-protected).
|
||||
y = ALWAYS_SYNC (issue a SYNCHRONIZE_CACHE
|
||||
even if the device claims no cache)
|
||||
even if the device claims no cache,
|
||||
not on uas)
|
||||
Example: quirks=0419:aaf5:rl,0421:0433:rc
|
||||
|
||||
user_debug= [KNL,ARM]
|
||||
|
|
@ -5115,6 +5228,10 @@
|
|||
the unplug protocol
|
||||
never -- do not unplug even if version check succeeds
|
||||
|
||||
xen_legacy_crash [X86,XEN]
|
||||
Crash from Xen panic notifier, without executing late
|
||||
panic() code such as dumping handler.
|
||||
|
||||
xen_nopvspin [X86,XEN]
|
||||
Disables the ticketlock slowpath using Xen PV
|
||||
optimizations.
|
||||
|
|
|
|||
|
|
@ -178,3 +178,7 @@ HWCAP_ILRCPC
|
|||
HWCAP_FLAGM
|
||||
|
||||
Functionality implied by ID_AA64ISAR0_EL1.TS == 0b0001.
|
||||
|
||||
HWCAP_SSBS
|
||||
|
||||
Functionality implied by ID_AA64PFR1_EL1.SSBS == 0b0010.
|
||||
|
|
|
|||
|
|
@ -35,6 +35,7 @@ Required standard properties:
|
|||
"ti,sysc-omap3-sham"
|
||||
"ti,sysc-omap-aes"
|
||||
"ti,sysc-mcasp"
|
||||
"ti,sysc-dra7-mcasp"
|
||||
"ti,sysc-usb-host-fs"
|
||||
"ti,sysc-dra7-mcan"
|
||||
|
||||
|
|
|
|||
|
|
@ -46,7 +46,7 @@ Required properties:
|
|||
Example (R-Car H3):
|
||||
|
||||
usb2_clksel: clock-controller@e6590630 {
|
||||
compatible = "renesas,r8a77950-rcar-usb2-clock-sel",
|
||||
compatible = "renesas,r8a7795-rcar-usb2-clock-sel",
|
||||
"renesas,rcar-gen3-usb2-clock-sel";
|
||||
reg = <0 0xe6590630 0 0x02>;
|
||||
clocks = <&cpg CPG_MOD 703>, <&usb_extal>, <&usb_xtal>;
|
||||
|
|
|
|||
|
|
@ -73,7 +73,7 @@ Example:
|
|||
};
|
||||
};
|
||||
|
||||
port@10 {
|
||||
port@a {
|
||||
reg = <10>;
|
||||
|
||||
adv7482_txa: endpoint {
|
||||
|
|
@ -83,7 +83,7 @@ Example:
|
|||
};
|
||||
};
|
||||
|
||||
port@11 {
|
||||
port@b {
|
||||
reg = <11>;
|
||||
|
||||
adv7482_txb: endpoint {
|
||||
|
|
|
|||
|
|
@ -19,6 +19,9 @@ Optional properties:
|
|||
- interrupt-names: must be "mdio_done_error" when there is a share interrupt fed
|
||||
to this hardware block, or must be "mdio_done" for the first interrupt and
|
||||
"mdio_error" for the second when there are separate interrupts
|
||||
- clocks: A reference to the clock supplying the MDIO bus controller
|
||||
- clock-frequency: the MDIO bus clock that must be output by the MDIO bus
|
||||
hardware, if absent, the default hardware values are used
|
||||
|
||||
Child nodes of this MDIO bus controller node are standard Ethernet PHY device
|
||||
nodes as described in Documentation/devicetree/bindings/net/phy.txt
|
||||
|
|
|
|||
|
|
@ -0,0 +1,27 @@
|
|||
OMAP ROM RNG driver binding
|
||||
|
||||
Secure SoCs may provide RNG via secure ROM calls like Nokia N900 does. The
|
||||
implementation can depend on the SoC secure ROM used.
|
||||
|
||||
- compatible:
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: must be "nokia,n900-rom-rng"
|
||||
|
||||
- clocks:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: reference to the the RNG interface clock
|
||||
|
||||
- clock-names:
|
||||
Usage: required
|
||||
Value type: <stringlist>
|
||||
Definition: must be "ick"
|
||||
|
||||
Example:
|
||||
|
||||
rom_rng: rng {
|
||||
compatible = "nokia,n900-rom-rng";
|
||||
clocks = <&rng_ick>;
|
||||
clock-names = "ick";
|
||||
};
|
||||
|
|
@ -27,4 +27,4 @@ and valid to enable charging:
|
|||
|
||||
- "abracon,tc-diode": should be "standard" (0.6V) or "schottky" (0.3V)
|
||||
- "abracon,tc-resistor": should be <0>, <3>, <6> or <11>. 0 disables the output
|
||||
resistor, the other values are in ohm.
|
||||
resistor, the other values are in kOhm.
|
||||
|
|
|
|||
|
|
@ -5,18 +5,20 @@ UniPhier SoCs have SCSSI which supports SPI single channel.
|
|||
Required properties:
|
||||
- compatible: should be "socionext,uniphier-scssi"
|
||||
- reg: address and length of the spi master registers
|
||||
- #address-cells: must be <1>, see spi-bus.txt
|
||||
- #size-cells: must be <0>, see spi-bus.txt
|
||||
- clocks: A phandle to the clock for the device.
|
||||
- resets: A phandle to the reset control for the device.
|
||||
- interrupts: a single interrupt specifier
|
||||
- pinctrl-names: should be "default"
|
||||
- pinctrl-0: pin control state for the default mode
|
||||
- clocks: a phandle to the clock for the device
|
||||
- resets: a phandle to the reset control for the device
|
||||
|
||||
Example:
|
||||
|
||||
spi0: spi@54006000 {
|
||||
compatible = "socionext,uniphier-scssi";
|
||||
reg = <0x54006000 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 39 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi0>;
|
||||
clocks = <&peri_clk 11>;
|
||||
resets = <&peri_rst 11>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -425,6 +425,7 @@ SwapPss: 0 kB
|
|||
KernelPageSize: 4 kB
|
||||
MMUPageSize: 4 kB
|
||||
Locked: 0 kB
|
||||
THPeligible: 0
|
||||
VmFlags: rd ex mr mw me dw
|
||||
|
||||
the first of these lines shows the same information as is displayed for the
|
||||
|
|
@ -462,6 +463,8 @@ replaced by copy-on-write) part of the underlying shmem object out on swap.
|
|||
"SwapPss" shows proportional swap share of this mapping. Unlike "Swap", this
|
||||
does not take into account swapped out page of underlying shmem objects.
|
||||
"Locked" indicates whether the mapping is locked in memory or not.
|
||||
"THPeligible" indicates whether the mapping is eligible for THP pages - 1 if
|
||||
true, 0 otherwise.
|
||||
|
||||
"VmFlags" field deserves a separate description. This member represents the kernel
|
||||
flags associated with the particular virtual memory area in two letter encoded
|
||||
|
|
|
|||
|
|
@ -160,7 +160,7 @@ them but you should handle them according to your needs.
|
|||
UHID_OUTPUT:
|
||||
This is sent if the HID device driver wants to send raw data to the I/O
|
||||
device on the interrupt channel. You should read the payload and forward it to
|
||||
the device. The payload is of type "struct uhid_data_req".
|
||||
the device. The payload is of type "struct uhid_output_req".
|
||||
This may be received even though you haven't received UHID_OPEN, yet.
|
||||
|
||||
UHID_GET_REPORT:
|
||||
|
|
|
|||
|
|
@ -90,6 +90,51 @@ There are two ways in which a group may become throttled:
|
|||
In case b) above, even though the child may have runtime remaining it will not
|
||||
be allowed to until the parent's runtime is refreshed.
|
||||
|
||||
CFS Bandwidth Quota Caveats
|
||||
---------------------------
|
||||
Once a slice is assigned to a cpu it does not expire. However all but 1ms of
|
||||
the slice may be returned to the global pool if all threads on that cpu become
|
||||
unrunnable. This is configured at compile time by the min_cfs_rq_runtime
|
||||
variable. This is a performance tweak that helps prevent added contention on
|
||||
the global lock.
|
||||
|
||||
The fact that cpu-local slices do not expire results in some interesting corner
|
||||
cases that should be understood.
|
||||
|
||||
For cgroup cpu constrained applications that are cpu limited this is a
|
||||
relatively moot point because they will naturally consume the entirety of their
|
||||
quota as well as the entirety of each cpu-local slice in each period. As a
|
||||
result it is expected that nr_periods roughly equal nr_throttled, and that
|
||||
cpuacct.usage will increase roughly equal to cfs_quota_us in each period.
|
||||
|
||||
For highly-threaded, non-cpu bound applications this non-expiration nuance
|
||||
allows applications to briefly burst past their quota limits by the amount of
|
||||
unused slice on each cpu that the task group is running on (typically at most
|
||||
1ms per cpu or as defined by min_cfs_rq_runtime). This slight burst only
|
||||
applies if quota had been assigned to a cpu and then not fully used or returned
|
||||
in previous periods. This burst amount will not be transferred between cores.
|
||||
As a result, this mechanism still strictly limits the task group to quota
|
||||
average usage, albeit over a longer time window than a single period. This
|
||||
also limits the burst ability to no more than 1ms per cpu. This provides
|
||||
better more predictable user experience for highly threaded applications with
|
||||
small quota limits on high core count machines. It also eliminates the
|
||||
propensity to throttle these applications while simultanously using less than
|
||||
quota amounts of cpu. Another way to say this, is that by allowing the unused
|
||||
portion of a slice to remain valid across periods we have decreased the
|
||||
possibility of wastefully expiring quota on cpu-local silos that don't need a
|
||||
full slice's amount of cpu time.
|
||||
|
||||
The interaction between cpu-bound and non-cpu-bound-interactive applications
|
||||
should also be considered, especially when single core usage hits 100%. If you
|
||||
gave each of these applications half of a cpu-core and they both got scheduled
|
||||
on the same CPU it is theoretically possible that the non-cpu bound application
|
||||
will use up to 1ms additional quota in some periods, thereby preventing the
|
||||
cpu-bound application from fully using its quota by that same amount. In these
|
||||
instances it will be up to the CFS algorithm (see sched-design-CFS.rst) to
|
||||
decide which application is chosen to run, as they will both be runnable and
|
||||
have remaining quota. This runtime discrepancy will be made up in the following
|
||||
periods when the interactive application idles.
|
||||
|
||||
Examples
|
||||
--------
|
||||
1. Limit a group to 1 CPU worth of runtime.
|
||||
|
|
|
|||
|
|
@ -1,138 +0,0 @@
|
|||
Copyright (C) 1999, 2000 Bruce Tenison
|
||||
Portions Copyright (C) 1999, 2000 David Nelson
|
||||
Thanks to David Nelson for guidance and the usage of the scanner.txt
|
||||
and scanner.c files to model our driver and this informative file.
|
||||
|
||||
Mar. 2, 2000
|
||||
|
||||
CHANGES
|
||||
|
||||
- Initial Revision
|
||||
|
||||
|
||||
OVERVIEW
|
||||
|
||||
This README will address issues regarding how to configure the kernel
|
||||
to access a RIO 500 mp3 player.
|
||||
Before I explain how to use this to access the Rio500 please be warned:
|
||||
|
||||
W A R N I N G:
|
||||
--------------
|
||||
|
||||
Please note that this software is still under development. The authors
|
||||
are in no way responsible for any damage that may occur, no matter how
|
||||
inconsequential.
|
||||
|
||||
It seems that the Rio has a problem when sending .mp3 with low batteries.
|
||||
I suggest when the batteries are low and you want to transfer stuff that you
|
||||
replace it with a fresh one. In my case, what happened is I lost two 16kb
|
||||
blocks (they are no longer usable to store information to it). But I don't
|
||||
know if that's normal or not; it could simply be a problem with the flash
|
||||
memory.
|
||||
|
||||
In an extreme case, I left my Rio playing overnight and the batteries wore
|
||||
down to nothing and appear to have corrupted the flash memory. My RIO
|
||||
needed to be replaced as a result. Diamond tech support is aware of the
|
||||
problem. Do NOT allow your batteries to wear down to nothing before
|
||||
changing them. It appears RIO 500 firmware does not handle low battery
|
||||
power well at all.
|
||||
|
||||
On systems with OHCI controllers, the kernel OHCI code appears to have
|
||||
power on problems with some chipsets. If you are having problems
|
||||
connecting to your RIO 500, try turning it on first and then plugging it
|
||||
into the USB cable.
|
||||
|
||||
Contact information:
|
||||
--------------------
|
||||
|
||||
The main page for the project is hosted at sourceforge.net in the following
|
||||
URL: <http://rio500.sourceforge.net>. You can also go to the project's
|
||||
sourceforge home page at: <http://sourceforge.net/projects/rio500/>.
|
||||
There is also a mailing list: rio500-users@lists.sourceforge.net
|
||||
|
||||
Authors:
|
||||
-------
|
||||
|
||||
Most of the code was written by Cesar Miquel <miquel@df.uba.ar>. Keith
|
||||
Clayton <kclayton@jps.net> is incharge of the PPC port and making sure
|
||||
things work there. Bruce Tenison <btenison@dibbs.net> is adding support
|
||||
for .fon files and also does testing. The program will mostly sure be
|
||||
re-written and Pete Ikusz along with the rest will re-design it. I would
|
||||
also like to thank Tri Nguyen <tmn_3022000@hotmail.com> who provided use
|
||||
with some important information regarding the communication with the Rio.
|
||||
|
||||
ADDITIONAL INFORMATION and Userspace tools
|
||||
|
||||
http://rio500.sourceforge.net/
|
||||
|
||||
|
||||
REQUIREMENTS
|
||||
|
||||
A host with a USB port. Ideally, either a UHCI (Intel) or OHCI
|
||||
(Compaq and others) hardware port should work.
|
||||
|
||||
A Linux development kernel (2.3.x) with USB support enabled or a
|
||||
backported version to linux-2.2.x. See http://www.linux-usb.org for
|
||||
more information on accomplishing this.
|
||||
|
||||
A Linux kernel with RIO 500 support enabled.
|
||||
|
||||
'lspci' which is only needed to determine the type of USB hardware
|
||||
available in your machine.
|
||||
|
||||
CONFIGURATION
|
||||
|
||||
Using `lspci -v`, determine the type of USB hardware available.
|
||||
|
||||
If you see something like:
|
||||
|
||||
USB Controller: ......
|
||||
Flags: .....
|
||||
I/O ports at ....
|
||||
|
||||
Then you have a UHCI based controller.
|
||||
|
||||
If you see something like:
|
||||
|
||||
USB Controller: .....
|
||||
Flags: ....
|
||||
Memory at .....
|
||||
|
||||
Then you have a OHCI based controller.
|
||||
|
||||
Using `make menuconfig` or your preferred method for configuring the
|
||||
kernel, select 'Support for USB', 'OHCI/UHCI' depending on your
|
||||
hardware (determined from the steps above), 'USB Diamond Rio500 support', and
|
||||
'Preliminary USB device filesystem'. Compile and install the modules
|
||||
(you may need to execute `depmod -a` to update the module
|
||||
dependencies).
|
||||
|
||||
Add a device for the USB rio500:
|
||||
`mknod /dev/usb/rio500 c 180 64`
|
||||
|
||||
Set appropriate permissions for /dev/usb/rio500 (don't forget about
|
||||
group and world permissions). Both read and write permissions are
|
||||
required for proper operation.
|
||||
|
||||
Load the appropriate modules (if compiled as modules):
|
||||
|
||||
OHCI:
|
||||
modprobe usbcore
|
||||
modprobe usb-ohci
|
||||
modprobe rio500
|
||||
|
||||
UHCI:
|
||||
modprobe usbcore
|
||||
modprobe usb-uhci (or uhci)
|
||||
modprobe rio500
|
||||
|
||||
That's it. The Rio500 Utils at: http://rio500.sourceforge.net should
|
||||
be able to access the rio500.
|
||||
|
||||
BUGS
|
||||
|
||||
If you encounter any problems feel free to drop me an email.
|
||||
|
||||
Bruce Tenison
|
||||
btenison@dibbs.net
|
||||
|
||||
|
|
@ -15,8 +15,6 @@ The acquisition orders for mutexes are as follows:
|
|||
|
||||
On x86, vcpu->mutex is taken outside kvm->arch.hyperv.hv_lock.
|
||||
|
||||
For spinlocks, kvm_lock is taken outside kvm->mmu_lock.
|
||||
|
||||
Everything else is a leaf: no other lock is taken inside the critical
|
||||
sections.
|
||||
|
||||
|
|
@ -169,7 +167,7 @@ which time it will be set using the Dirty tracking mechanism described above.
|
|||
------------
|
||||
|
||||
Name: kvm_lock
|
||||
Type: spinlock_t
|
||||
Type: mutex
|
||||
Arch: any
|
||||
Protects: - vm_list
|
||||
|
||||
|
|
|
|||
|
|
@ -6,3 +6,4 @@ x86 architecture specifics
|
|||
:maxdepth: 1
|
||||
|
||||
mds
|
||||
tsx_async_abort
|
||||
|
|
|
|||
|
|
@ -0,0 +1,117 @@
|
|||
.. SPDX-License-Identifier: GPL-2.0
|
||||
|
||||
TSX Async Abort (TAA) mitigation
|
||||
================================
|
||||
|
||||
.. _tsx_async_abort:
|
||||
|
||||
Overview
|
||||
--------
|
||||
|
||||
TSX Async Abort (TAA) is a side channel attack on internal buffers in some
|
||||
Intel processors similar to Microachitectural Data Sampling (MDS). In this
|
||||
case certain loads may speculatively pass invalid data to dependent operations
|
||||
when an asynchronous abort condition is pending in a Transactional
|
||||
Synchronization Extensions (TSX) transaction. This includes loads with no
|
||||
fault or assist condition. Such loads may speculatively expose stale data from
|
||||
the same uarch data structures as in MDS, with same scope of exposure i.e.
|
||||
same-thread and cross-thread. This issue affects all current processors that
|
||||
support TSX.
|
||||
|
||||
Mitigation strategy
|
||||
-------------------
|
||||
|
||||
a) TSX disable - one of the mitigations is to disable TSX. A new MSR
|
||||
IA32_TSX_CTRL will be available in future and current processors after
|
||||
microcode update which can be used to disable TSX. In addition, it
|
||||
controls the enumeration of the TSX feature bits (RTM and HLE) in CPUID.
|
||||
|
||||
b) Clear CPU buffers - similar to MDS, clearing the CPU buffers mitigates this
|
||||
vulnerability. More details on this approach can be found in
|
||||
:ref:`Documentation/admin-guide/hw-vuln/mds.rst <mds>`.
|
||||
|
||||
Kernel internal mitigation modes
|
||||
--------------------------------
|
||||
|
||||
============= ============================================================
|
||||
off Mitigation is disabled. Either the CPU is not affected or
|
||||
tsx_async_abort=off is supplied on the kernel command line.
|
||||
|
||||
tsx disabled Mitigation is enabled. TSX feature is disabled by default at
|
||||
bootup on processors that support TSX control.
|
||||
|
||||
verw Mitigation is enabled. CPU is affected and MD_CLEAR is
|
||||
advertised in CPUID.
|
||||
|
||||
ucode needed Mitigation is enabled. CPU is affected and MD_CLEAR is not
|
||||
advertised in CPUID. That is mainly for virtualization
|
||||
scenarios where the host has the updated microcode but the
|
||||
hypervisor does not expose MD_CLEAR in CPUID. It's a best
|
||||
effort approach without guarantee.
|
||||
============= ============================================================
|
||||
|
||||
If the CPU is affected and the "tsx_async_abort" kernel command line parameter is
|
||||
not provided then the kernel selects an appropriate mitigation depending on the
|
||||
status of RTM and MD_CLEAR CPUID bits.
|
||||
|
||||
Below tables indicate the impact of tsx=on|off|auto cmdline options on state of
|
||||
TAA mitigation, VERW behavior and TSX feature for various combinations of
|
||||
MSR_IA32_ARCH_CAPABILITIES bits.
|
||||
|
||||
1. "tsx=off"
|
||||
|
||||
========= ========= ============ ============ ============== =================== ======================
|
||||
MSR_IA32_ARCH_CAPABILITIES bits Result with cmdline tsx=off
|
||||
---------------------------------- -------------------------------------------------------------------------
|
||||
TAA_NO MDS_NO TSX_CTRL_MSR TSX state VERW can clear TAA mitigation TAA mitigation
|
||||
after bootup CPU buffers tsx_async_abort=off tsx_async_abort=full
|
||||
========= ========= ============ ============ ============== =================== ======================
|
||||
0 0 0 HW default Yes Same as MDS Same as MDS
|
||||
0 0 1 Invalid case Invalid case Invalid case Invalid case
|
||||
0 1 0 HW default No Need ucode update Need ucode update
|
||||
0 1 1 Disabled Yes TSX disabled TSX disabled
|
||||
1 X 1 Disabled X None needed None needed
|
||||
========= ========= ============ ============ ============== =================== ======================
|
||||
|
||||
2. "tsx=on"
|
||||
|
||||
========= ========= ============ ============ ============== =================== ======================
|
||||
MSR_IA32_ARCH_CAPABILITIES bits Result with cmdline tsx=on
|
||||
---------------------------------- -------------------------------------------------------------------------
|
||||
TAA_NO MDS_NO TSX_CTRL_MSR TSX state VERW can clear TAA mitigation TAA mitigation
|
||||
after bootup CPU buffers tsx_async_abort=off tsx_async_abort=full
|
||||
========= ========= ============ ============ ============== =================== ======================
|
||||
0 0 0 HW default Yes Same as MDS Same as MDS
|
||||
0 0 1 Invalid case Invalid case Invalid case Invalid case
|
||||
0 1 0 HW default No Need ucode update Need ucode update
|
||||
0 1 1 Enabled Yes None Same as MDS
|
||||
1 X 1 Enabled X None needed None needed
|
||||
========= ========= ============ ============ ============== =================== ======================
|
||||
|
||||
3. "tsx=auto"
|
||||
|
||||
========= ========= ============ ============ ============== =================== ======================
|
||||
MSR_IA32_ARCH_CAPABILITIES bits Result with cmdline tsx=auto
|
||||
---------------------------------- -------------------------------------------------------------------------
|
||||
TAA_NO MDS_NO TSX_CTRL_MSR TSX state VERW can clear TAA mitigation TAA mitigation
|
||||
after bootup CPU buffers tsx_async_abort=off tsx_async_abort=full
|
||||
========= ========= ============ ============ ============== =================== ======================
|
||||
0 0 0 HW default Yes Same as MDS Same as MDS
|
||||
0 0 1 Invalid case Invalid case Invalid case Invalid case
|
||||
0 1 0 HW default No Need ucode update Need ucode update
|
||||
0 1 1 Disabled Yes TSX disabled TSX disabled
|
||||
1 X 1 Enabled X None needed None needed
|
||||
========= ========= ============ ============ ============== =================== ======================
|
||||
|
||||
In the tables, TSX_CTRL_MSR is a new bit in MSR_IA32_ARCH_CAPABILITIES that
|
||||
indicates whether MSR_IA32_TSX_CTRL is supported.
|
||||
|
||||
There are two control bits in IA32_TSX_CTRL MSR:
|
||||
|
||||
Bit 0: When set it disables the Restricted Transactional Memory (RTM)
|
||||
sub-feature of TSX (will force all transactions to abort on the
|
||||
XBEGIN instruction).
|
||||
|
||||
Bit 1: When set it disables the enumeration of the RTM and HLE feature
|
||||
(i.e. it will make CPUID(EAX=7).EBX{bit4} and
|
||||
CPUID(EAX=7).EBX{bit11} read as 0).
|
||||
|
|
@ -7340,7 +7340,7 @@ M: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
|
|||
M: Rodrigo Vivi <rodrigo.vivi@intel.com>
|
||||
L: intel-gfx@lists.freedesktop.org
|
||||
W: https://01.org/linuxgraphics/
|
||||
B: https://01.org/linuxgraphics/documentation/how-report-bugs
|
||||
B: https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs
|
||||
C: irc://chat.freenode.net/intel-gfx
|
||||
Q: http://patchwork.freedesktop.org/project/intel-gfx/
|
||||
T: git git://anongit.freedesktop.org/drm-intel
|
||||
|
|
@ -15117,13 +15117,6 @@ W: http://www.linux-usb.org/usbnet
|
|||
S: Maintained
|
||||
F: drivers/net/usb/dm9601.c
|
||||
|
||||
USB DIAMOND RIO500 DRIVER
|
||||
M: Cesar Miquel <miquel@df.uba.ar>
|
||||
L: rio500-users@lists.sourceforge.net
|
||||
W: http://rio500.sourceforge.net
|
||||
S: Maintained
|
||||
F: drivers/usb/misc/rio500*
|
||||
|
||||
USB EHCI DRIVER
|
||||
M: Alan Stern <stern@rowland.harvard.edu>
|
||||
L: linux-usb@vger.kernel.org
|
||||
|
|
|
|||
23
Makefile
23
Makefile
|
|
@ -1,7 +1,7 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
VERSION = 4
|
||||
PATCHLEVEL = 19
|
||||
SUBLEVEL = 78
|
||||
SUBLEVEL = 107
|
||||
EXTRAVERSION =
|
||||
NAME = "People's Front"
|
||||
|
||||
|
|
@ -835,6 +835,12 @@ KBUILD_CFLAGS += $(call cc-option,-Werror=designated-init)
|
|||
# change __FILE__ to the relative path from the srctree
|
||||
KBUILD_CFLAGS += $(call cc-option,-fmacro-prefix-map=$(srctree)/=)
|
||||
|
||||
# ensure -fcf-protection is disabled when using retpoline as it is
|
||||
# incompatible with -mindirect-branch=thunk-extern
|
||||
ifdef CONFIG_RETPOLINE
|
||||
KBUILD_CFLAGS += $(call cc-option,-fcf-protection=none)
|
||||
endif
|
||||
|
||||
# use the deterministic mode of AR if available
|
||||
KBUILD_ARFLAGS := $(call ar-option,D)
|
||||
|
||||
|
|
@ -958,6 +964,7 @@ ifdef CONFIG_STACK_VALIDATION
|
|||
endif
|
||||
endif
|
||||
|
||||
PHONY += prepare0
|
||||
|
||||
ifeq ($(KBUILD_EXTMOD),)
|
||||
core-y += kernel/ certs/ mm/ fs/ ipc/ security/ crypto/ block/
|
||||
|
|
@ -1066,8 +1073,7 @@ scripts: scripts_basic asm-generic gcc-plugins $(autoksyms_h)
|
|||
# archprepare is used in arch Makefiles and when processed asm symlink,
|
||||
# version.h and scripts_basic is processed / created.
|
||||
|
||||
# Listed in dependency order
|
||||
PHONY += prepare archprepare prepare0 prepare1 prepare2 prepare3
|
||||
PHONY += prepare archprepare prepare1 prepare2 prepare3
|
||||
|
||||
# prepare3 is used to check if we are building in a separate output directory,
|
||||
# and if so do:
|
||||
|
|
@ -1501,9 +1507,6 @@ else # KBUILD_EXTMOD
|
|||
|
||||
# We are always building modules
|
||||
KBUILD_MODULES := 1
|
||||
PHONY += crmodverdir
|
||||
crmodverdir:
|
||||
$(cmd_crmodverdir)
|
||||
|
||||
PHONY += $(objtree)/Module.symvers
|
||||
$(objtree)/Module.symvers:
|
||||
|
|
@ -1515,7 +1518,7 @@ $(objtree)/Module.symvers:
|
|||
|
||||
module-dirs := $(addprefix _module_,$(KBUILD_EXTMOD))
|
||||
PHONY += $(module-dirs) modules
|
||||
$(module-dirs): crmodverdir $(objtree)/Module.symvers
|
||||
$(module-dirs): prepare $(objtree)/Module.symvers
|
||||
$(Q)$(MAKE) $(build)=$(patsubst _module_%,%,$@)
|
||||
|
||||
modules: $(module-dirs)
|
||||
|
|
@ -1556,7 +1559,8 @@ help:
|
|||
|
||||
# Dummies...
|
||||
PHONY += prepare scripts
|
||||
prepare: ;
|
||||
prepare:
|
||||
$(cmd_crmodverdir)
|
||||
scripts: ;
|
||||
endif # KBUILD_EXTMOD
|
||||
|
||||
|
|
@ -1683,17 +1687,14 @@ endif
|
|||
|
||||
# Modules
|
||||
/: prepare scripts FORCE
|
||||
$(cmd_crmodverdir)
|
||||
$(Q)$(MAKE) KBUILD_MODULES=$(if $(CONFIG_MODULES),1) \
|
||||
$(build)=$(build-dir)
|
||||
# Make sure the latest headers are built for Documentation
|
||||
Documentation/ samples/: headers_install
|
||||
%/: prepare scripts FORCE
|
||||
$(cmd_crmodverdir)
|
||||
$(Q)$(MAKE) KBUILD_MODULES=$(if $(CONFIG_MODULES),1) \
|
||||
$(build)=$(build-dir)
|
||||
%.ko: prepare scripts FORCE
|
||||
$(cmd_crmodverdir)
|
||||
$(Q)$(MAKE) KBUILD_MODULES=$(if $(CONFIG_MODULES),1) \
|
||||
$(build)=$(build-dir) $(@:.ko=.o)
|
||||
$(Q)$(MAKE) -f $(srctree)/scripts/Makefile.modpost
|
||||
|
|
|
|||
|
|
@ -80,6 +80,7 @@
|
|||
interrupt-names = "macirq";
|
||||
phy-mode = "rgmii";
|
||||
snps,pbl = < 32 >;
|
||||
snps,multicast-filter-bins = <256>;
|
||||
clocks = <&apbclk>;
|
||||
clock-names = "stmmaceth";
|
||||
max-speed = <100>;
|
||||
|
|
|
|||
|
|
@ -124,7 +124,9 @@ extern unsigned long perip_base, perip_end;
|
|||
|
||||
/* IO coherency related Auxiliary registers */
|
||||
#define ARC_REG_IO_COH_ENABLE 0x500
|
||||
#define ARC_IO_COH_ENABLE_BIT BIT(0)
|
||||
#define ARC_REG_IO_COH_PARTIAL 0x501
|
||||
#define ARC_IO_COH_PARTIAL_BIT BIT(0)
|
||||
#define ARC_REG_IO_COH_AP0_BASE 0x508
|
||||
#define ARC_REG_IO_COH_AP0_SIZE 0x509
|
||||
|
||||
|
|
|
|||
|
|
@ -490,8 +490,8 @@ static int arc_pmu_device_probe(struct platform_device *pdev)
|
|||
/* loop thru all available h/w condition indexes */
|
||||
for (j = 0; j < cc_bcr.c; j++) {
|
||||
write_aux_reg(ARC_REG_CC_INDEX, j);
|
||||
cc_name.indiv.word0 = read_aux_reg(ARC_REG_CC_NAME0);
|
||||
cc_name.indiv.word1 = read_aux_reg(ARC_REG_CC_NAME1);
|
||||
cc_name.indiv.word0 = le32_to_cpu(read_aux_reg(ARC_REG_CC_NAME0));
|
||||
cc_name.indiv.word1 = le32_to_cpu(read_aux_reg(ARC_REG_CC_NAME1));
|
||||
|
||||
/* See if it has been mapped to a perf event_id */
|
||||
for (i = 0; i < ARRAY_SIZE(arc_pmu_ev_hw_map); i++) {
|
||||
|
|
|
|||
|
|
@ -1144,6 +1144,20 @@ noinline void __init arc_ioc_setup(void)
|
|||
{
|
||||
unsigned int ioc_base, mem_sz;
|
||||
|
||||
/*
|
||||
* If IOC was already enabled (due to bootloader) it technically needs to
|
||||
* be reconfigured with aperture base,size corresponding to Linux memory map
|
||||
* which will certainly be different than uboot's. But disabling and
|
||||
* reenabling IOC when DMA might be potentially active is tricky business.
|
||||
* To avoid random memory issues later, just panic here and ask user to
|
||||
* upgrade bootloader to one which doesn't enable IOC
|
||||
*/
|
||||
if (read_aux_reg(ARC_REG_IO_COH_ENABLE) & ARC_IO_COH_ENABLE_BIT)
|
||||
panic("IOC already enabled, please upgrade bootloader!\n");
|
||||
|
||||
if (!ioc_enable)
|
||||
return;
|
||||
|
||||
/*
|
||||
* As for today we don't support both IOC and ZONE_HIGHMEM enabled
|
||||
* simultaneously. This happens because as of today IOC aperture covers
|
||||
|
|
@ -1187,8 +1201,8 @@ noinline void __init arc_ioc_setup(void)
|
|||
panic("IOC Aperture start must be aligned to the size of the aperture");
|
||||
|
||||
write_aux_reg(ARC_REG_IO_COH_AP0_BASE, ioc_base >> 12);
|
||||
write_aux_reg(ARC_REG_IO_COH_PARTIAL, 1);
|
||||
write_aux_reg(ARC_REG_IO_COH_ENABLE, 1);
|
||||
write_aux_reg(ARC_REG_IO_COH_PARTIAL, ARC_IO_COH_PARTIAL_BIT);
|
||||
write_aux_reg(ARC_REG_IO_COH_ENABLE, ARC_IO_COH_ENABLE_BIT);
|
||||
|
||||
/* Re-enable L1 dcache */
|
||||
__dc_enable();
|
||||
|
|
@ -1265,7 +1279,7 @@ void __init arc_cache_init_master(void)
|
|||
if (is_isa_arcv2() && l2_line_sz && !slc_enable)
|
||||
arc_slc_disable();
|
||||
|
||||
if (is_isa_arcv2() && ioc_enable)
|
||||
if (is_isa_arcv2() && ioc_exists)
|
||||
arc_ioc_setup();
|
||||
|
||||
if (is_isa_arcv2() && l2_line_sz && slc_enable) {
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@
|
|||
menuconfig ARC_PLAT_EZNPS
|
||||
bool "\"EZchip\" ARC dev platform"
|
||||
select CPU_BIG_ENDIAN
|
||||
select CLKSRC_NPS
|
||||
select CLKSRC_NPS if !PHYS_ADDR_T_64BIT
|
||||
select EZNPS_GIC
|
||||
select EZCHIP_NPS_MANAGEMENT_ENET if ETHERNET
|
||||
help
|
||||
|
|
|
|||
|
|
@ -61,7 +61,7 @@ config ARM
|
|||
select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
|
||||
select HAVE_CONTEXT_TRACKING
|
||||
select HAVE_C_RECORDMCOUNT
|
||||
select HAVE_DEBUG_KMEMLEAK
|
||||
select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL
|
||||
select HAVE_DMA_CONTIGUOUS if MMU
|
||||
select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU
|
||||
select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
|
||||
|
|
@ -2008,7 +2008,7 @@ config XIP_DEFLATED_DATA
|
|||
config KEXEC
|
||||
bool "Kexec system call (EXPERIMENTAL)"
|
||||
depends on (!SMP || PM_SLEEP_SMP)
|
||||
depends on !CPU_V7M
|
||||
depends on MMU
|
||||
select KEXEC_CORE
|
||||
help
|
||||
kexec is a system call that implements the ability to shutdown your
|
||||
|
|
|
|||
|
|
@ -1079,14 +1079,21 @@ choice
|
|||
Say Y here if you want kernel low-level debugging support
|
||||
on SOCFPGA(Cyclone 5 and Arria 5) based platforms.
|
||||
|
||||
config DEBUG_SOCFPGA_UART1
|
||||
config DEBUG_SOCFPGA_ARRIA10_UART1
|
||||
depends on ARCH_SOCFPGA
|
||||
bool "Use SOCFPGA UART1 for low-level debug"
|
||||
bool "Use SOCFPGA Arria10 UART1 for low-level debug"
|
||||
select DEBUG_UART_8250
|
||||
help
|
||||
Say Y here if you want kernel low-level debugging support
|
||||
on SOCFPGA(Arria 10) based platforms.
|
||||
|
||||
config DEBUG_SOCFPGA_CYCLONE5_UART1
|
||||
depends on ARCH_SOCFPGA
|
||||
bool "Use SOCFPGA Cyclone 5 UART1 for low-level debug"
|
||||
select DEBUG_UART_8250
|
||||
help
|
||||
Say Y here if you want kernel low-level debugging support
|
||||
on SOCFPGA(Cyclone 5 and Arria 5) based platforms.
|
||||
|
||||
config DEBUG_SUN9I_UART0
|
||||
bool "Kernel low-level debugging messages via sun9i UART0"
|
||||
|
|
@ -1432,21 +1439,21 @@ config DEBUG_OMAP2PLUS_UART
|
|||
depends on ARCH_OMAP2PLUS
|
||||
|
||||
config DEBUG_IMX_UART_PORT
|
||||
int "i.MX Debug UART Port Selection" if DEBUG_IMX1_UART || \
|
||||
DEBUG_IMX25_UART || \
|
||||
DEBUG_IMX21_IMX27_UART || \
|
||||
DEBUG_IMX31_UART || \
|
||||
DEBUG_IMX35_UART || \
|
||||
DEBUG_IMX50_UART || \
|
||||
DEBUG_IMX51_UART || \
|
||||
DEBUG_IMX53_UART || \
|
||||
DEBUG_IMX6Q_UART || \
|
||||
DEBUG_IMX6SL_UART || \
|
||||
DEBUG_IMX6SX_UART || \
|
||||
DEBUG_IMX6UL_UART || \
|
||||
DEBUG_IMX7D_UART
|
||||
int "i.MX Debug UART Port Selection"
|
||||
depends on DEBUG_IMX1_UART || \
|
||||
DEBUG_IMX25_UART || \
|
||||
DEBUG_IMX21_IMX27_UART || \
|
||||
DEBUG_IMX31_UART || \
|
||||
DEBUG_IMX35_UART || \
|
||||
DEBUG_IMX50_UART || \
|
||||
DEBUG_IMX51_UART || \
|
||||
DEBUG_IMX53_UART || \
|
||||
DEBUG_IMX6Q_UART || \
|
||||
DEBUG_IMX6SL_UART || \
|
||||
DEBUG_IMX6SX_UART || \
|
||||
DEBUG_IMX6UL_UART || \
|
||||
DEBUG_IMX7D_UART
|
||||
default 1
|
||||
depends on ARCH_MXC
|
||||
help
|
||||
Choose UART port on which kernel low-level debug messages
|
||||
should be output.
|
||||
|
|
@ -1647,7 +1654,8 @@ config DEBUG_UART_PHYS
|
|||
default 0xfe800000 if ARCH_IOP32X
|
||||
default 0xff690000 if DEBUG_RK32_UART2
|
||||
default 0xffc02000 if DEBUG_SOCFPGA_UART0
|
||||
default 0xffc02100 if DEBUG_SOCFPGA_UART1
|
||||
default 0xffc02100 if DEBUG_SOCFPGA_ARRIA10_UART1
|
||||
default 0xffc03000 if DEBUG_SOCFPGA_CYCLONE5_UART1
|
||||
default 0xffd82340 if ARCH_IOP13XX
|
||||
default 0xffe40000 if DEBUG_RCAR_GEN1_SCIF0
|
||||
default 0xffe42000 if DEBUG_RCAR_GEN1_SCIF2
|
||||
|
|
@ -1754,7 +1762,8 @@ config DEBUG_UART_VIRT
|
|||
default 0xfeb30c00 if DEBUG_KEYSTONE_UART0
|
||||
default 0xfeb31000 if DEBUG_KEYSTONE_UART1
|
||||
default 0xfec02000 if DEBUG_SOCFPGA_UART0
|
||||
default 0xfec02100 if DEBUG_SOCFPGA_UART1
|
||||
default 0xfec02100 if DEBUG_SOCFPGA_ARRIA10_UART1
|
||||
default 0xfec03000 if DEBUG_SOCFPGA_CYCLONE5_UART1
|
||||
default 0xfec12000 if (DEBUG_MVEBU_UART0 || DEBUG_MVEBU_UART0_ALTERNATE) && ARCH_MVEBU
|
||||
default 0xfec12100 if DEBUG_MVEBU_UART1_ALTERNATE
|
||||
default 0xfec10000 if DEBUG_SIRFATLAS7_UART0
|
||||
|
|
@ -1803,9 +1812,9 @@ config DEBUG_UART_8250_WORD
|
|||
depends on DEBUG_LL_UART_8250 || DEBUG_UART_8250
|
||||
depends on DEBUG_UART_8250_SHIFT >= 2
|
||||
default y if DEBUG_PICOXCELL_UART || \
|
||||
DEBUG_SOCFPGA_UART0 || DEBUG_SOCFPGA_UART1 || \
|
||||
DEBUG_KEYSTONE_UART0 || DEBUG_KEYSTONE_UART1 || \
|
||||
DEBUG_ALPINE_UART0 || \
|
||||
DEBUG_SOCFPGA_UART0 || DEBUG_SOCFPGA_ARRIA10_UART1 || \
|
||||
DEBUG_SOCFPGA_CYCLONE5_UART1 || DEBUG_KEYSTONE_UART0 || \
|
||||
DEBUG_KEYSTONE_UART1 || DEBUG_ALPINE_UART0 || \
|
||||
DEBUG_DAVINCI_DMx_UART0 || DEBUG_DAVINCI_DA8XX_UART1 || \
|
||||
DEBUG_DAVINCI_DA8XX_UART2 || DEBUG_BCM_IPROC_UART3 || \
|
||||
DEBUG_BCM_KONA_UART || DEBUG_RK32_UART2
|
||||
|
|
|
|||
|
|
@ -2,10 +2,14 @@
|
|||
#ifndef _ARM_LIBFDT_ENV_H
|
||||
#define _ARM_LIBFDT_ENV_H
|
||||
|
||||
#include <linux/limits.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/string.h>
|
||||
#include <asm/byteorder.h>
|
||||
|
||||
#define INT32_MAX S32_MAX
|
||||
#define UINT32_MAX U32_MAX
|
||||
|
||||
typedef __be16 fdt16_t;
|
||||
typedef __be32 fdt32_t;
|
||||
typedef __be64 fdt64_t;
|
||||
|
|
|
|||
|
|
@ -88,7 +88,7 @@
|
|||
};
|
||||
|
||||
&i2c0 {
|
||||
tda19988: tda19988 {
|
||||
tda19988: tda19988@70 {
|
||||
compatible = "nxp,tda998x";
|
||||
reg = <0x70>;
|
||||
|
||||
|
|
@ -131,6 +131,11 @@
|
|||
};
|
||||
|
||||
/ {
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x20000000>; /* 512 MB */
|
||||
};
|
||||
|
||||
clk_mcasp0_fixed: clk_mcasp0_fixed {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
|
|
|
|||
|
|
@ -731,6 +731,7 @@
|
|||
pinctrl-0 = <&cpsw_default>;
|
||||
pinctrl-1 = <&cpsw_sleep>;
|
||||
status = "okay";
|
||||
slaves = <1>;
|
||||
};
|
||||
|
||||
&davinci_mdio {
|
||||
|
|
@ -738,15 +739,14 @@
|
|||
pinctrl-0 = <&davinci_mdio_default>;
|
||||
pinctrl-1 = <&davinci_mdio_sleep>;
|
||||
status = "okay";
|
||||
|
||||
ethphy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&cpsw_emac0 {
|
||||
phy_id = <&davinci_mdio>, <0>;
|
||||
phy-mode = "rgmii-txid";
|
||||
};
|
||||
|
||||
&cpsw_emac1 {
|
||||
phy_id = <&davinci_mdio>, <1>;
|
||||
phy-handle = <ðphy0>;
|
||||
phy-mode = "rgmii-txid";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -161,7 +161,7 @@
|
|||
invensense,key = [4e cc 7e eb f6 1e 35 22 00 34 0d 65 32 e9 94 89];*/
|
||||
};
|
||||
|
||||
bmp280: pressure@78 {
|
||||
bmp280: pressure@76 {
|
||||
compatible = "bosch,bmp280";
|
||||
reg = <0x76>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -373,7 +373,7 @@
|
|||
ti,pindir-d0-out-d1-in;
|
||||
status = "okay";
|
||||
|
||||
cfaf240320a032t {
|
||||
display-controller@0 {
|
||||
compatible = "orisetech,otm3225a";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <1000000>;
|
||||
|
|
@ -577,7 +577,7 @@
|
|||
bus-width = <4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc2_pins>;
|
||||
cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
|
||||
cd-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&sham {
|
||||
|
|
|
|||
|
|
@ -1101,7 +1101,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
qspi: qspi@47900000 {
|
||||
qspi: spi@47900000 {
|
||||
compatible = "ti,am4372-qspi";
|
||||
reg = <0x47900000 0x100>,
|
||||
<0x30000000 0x4000000>;
|
||||
|
|
@ -1142,6 +1142,8 @@
|
|||
ti,hwmods = "dss_dispc";
|
||||
clocks = <&disp_clk>;
|
||||
clock-names = "fck";
|
||||
|
||||
max-memory-bandwidth = <230000000>;
|
||||
};
|
||||
|
||||
rfbi: rfbi@4832a800 {
|
||||
|
|
|
|||
|
|
@ -83,7 +83,7 @@
|
|||
};
|
||||
|
||||
lcd0: display {
|
||||
compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
|
||||
compatible = "osddisplays,osd070t1718-19ts", "panel-dpi";
|
||||
label = "lcd";
|
||||
|
||||
backlight = <&lcd_bl>;
|
||||
|
|
|
|||
|
|
@ -45,7 +45,7 @@
|
|||
};
|
||||
|
||||
lcd0: display {
|
||||
compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
|
||||
compatible = "osddisplays,osd070t1718-19ts", "panel-dpi";
|
||||
label = "lcd";
|
||||
|
||||
backlight = <&lcd_bl>;
|
||||
|
|
@ -839,6 +839,7 @@
|
|||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&spi0_pins_default>;
|
||||
pinctrl-1 = <&spi0_pins_sleep>;
|
||||
ti,pindir-d0-out-d1-in = <1>;
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
|
|
@ -846,6 +847,7 @@
|
|||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&spi1_pins_default>;
|
||||
pinctrl-1 = <&spi1_pins_sleep>;
|
||||
ti,pindir-d0-out-d1-in = <1>;
|
||||
};
|
||||
|
||||
&usb2_phy1 {
|
||||
|
|
|
|||
|
|
@ -707,6 +707,60 @@
|
|||
ti,bit-shift = <8>;
|
||||
reg = <0x2a48>;
|
||||
};
|
||||
|
||||
clkout1_osc_div_ck: clkout1-osc-div-ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
ti,bit-shift = <20>;
|
||||
ti,max-div = <4>;
|
||||
reg = <0x4100>;
|
||||
};
|
||||
|
||||
clkout1_src2_mux_ck: clkout1-src2-mux-ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>,
|
||||
<&dpll_per_m2_ck>, <&dpll_disp_m2_ck>,
|
||||
<&dpll_mpu_m2_ck>;
|
||||
reg = <0x4100>;
|
||||
};
|
||||
|
||||
clkout1_src2_pre_div_ck: clkout1-src2-pre-div-ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&clkout1_src2_mux_ck>;
|
||||
ti,bit-shift = <4>;
|
||||
ti,max-div = <8>;
|
||||
reg = <0x4100>;
|
||||
};
|
||||
|
||||
clkout1_src2_post_div_ck: clkout1-src2-post-div-ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&clkout1_src2_pre_div_ck>;
|
||||
ti,bit-shift = <8>;
|
||||
ti,max-div = <32>;
|
||||
ti,index-power-of-two;
|
||||
reg = <0x4100>;
|
||||
};
|
||||
|
||||
clkout1_mux_ck: clkout1-mux-ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&clkout1_osc_div_ck>, <&clk_rc32k_ck>,
|
||||
<&clkout1_src2_post_div_ck>, <&dpll_extdev_m2_ck>;
|
||||
ti,bit-shift = <16>;
|
||||
reg = <0x4100>;
|
||||
};
|
||||
|
||||
clkout1_ck: clkout1-ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&clkout1_mux_ck>;
|
||||
ti,bit-shift = <23>;
|
||||
reg = <0x4100>;
|
||||
};
|
||||
};
|
||||
|
||||
&prcm {
|
||||
|
|
|
|||
|
|
@ -90,11 +90,7 @@
|
|||
|
||||
&pcie1_rc {
|
||||
status = "okay";
|
||||
gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&pcie1_ep {
|
||||
gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
|
||||
gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
|
|
|
|||
|
|
@ -71,10 +71,6 @@
|
|||
gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&pcie1_ep {
|
||||
gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&mailbox5 {
|
||||
status = "okay";
|
||||
mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
|
||||
|
|
|
|||
|
|
@ -32,6 +32,27 @@
|
|||
reg = <0x0 0x80000000 0x0 0x80000000>;
|
||||
};
|
||||
|
||||
main_12v0: fixedregulator-main_12v0 {
|
||||
/* main supply */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "main_12v0";
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
evm_5v0: fixedregulator-evm_5v0 {
|
||||
/* Output of TPS54531D */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "evm_5v0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&main_12v0>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vdd_3v3: fixedregulator-vdd_3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdd_3v3";
|
||||
|
|
@ -550,10 +571,6 @@
|
|||
gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&pcie1_ep {
|
||||
gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&mcasp3 {
|
||||
#sound-dai-cells = <0>;
|
||||
assigned-clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>;
|
||||
|
|
|
|||
|
|
@ -518,7 +518,7 @@
|
|||
};
|
||||
|
||||
/* touch controller */
|
||||
ads7846@0 {
|
||||
touchscreen@1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ads7846_pins>;
|
||||
|
||||
|
|
|
|||
|
|
@ -371,7 +371,7 @@
|
|||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
ssp: ssp@1000d000 {
|
||||
ssp: spi@1000d000 {
|
||||
compatible = "arm,pl022", "arm,primecell";
|
||||
reg = <0x1000d000 0x1000>;
|
||||
clocks = <&sspclk>, <&pclk>;
|
||||
|
|
|
|||
|
|
@ -45,7 +45,7 @@
|
|||
};
|
||||
|
||||
/* The voltage to the MMC card is hardwired at 3.3V */
|
||||
vmmc: fixedregulator@0 {
|
||||
vmmc: regulator-vmmc {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vmmc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
|
|
@ -53,7 +53,7 @@
|
|||
regulator-boot-on;
|
||||
};
|
||||
|
||||
veth: fixedregulator@0 {
|
||||
veth: regulator-veth {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "veth";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
|
|
@ -380,7 +380,7 @@
|
|||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
pb1176_ssp: ssp@1010b000 {
|
||||
pb1176_ssp: spi@1010b000 {
|
||||
compatible = "arm,pl022", "arm,primecell";
|
||||
reg = <0x1010b000 0x1000>;
|
||||
interrupt-parent = <&intc_dc1176>;
|
||||
|
|
|
|||
|
|
@ -145,7 +145,7 @@
|
|||
};
|
||||
|
||||
/* The voltage to the MMC card is hardwired at 3.3V */
|
||||
vmmc: fixedregulator@0 {
|
||||
vmmc: regulator-vmmc {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vmmc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
|
|
@ -153,7 +153,7 @@
|
|||
regulator-boot-on;
|
||||
};
|
||||
|
||||
veth: fixedregulator@0 {
|
||||
veth: regulator-veth {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "veth";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
|
|
@ -523,7 +523,7 @@
|
|||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
ssp@1000d000 {
|
||||
spi@1000d000 {
|
||||
compatible = "arm,pl022", "arm,primecell";
|
||||
reg = <0x1000d000 0x1000>;
|
||||
interrupt-parent = <&intc_pb11mp>;
|
||||
|
|
|
|||
|
|
@ -44,7 +44,7 @@
|
|||
};
|
||||
|
||||
/* The voltage to the MMC card is hardwired at 3.3V */
|
||||
vmmc: fixedregulator@0 {
|
||||
vmmc: regulator-vmmc {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vmmc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
|
|
@ -52,7 +52,7 @@
|
|||
regulator-boot-on;
|
||||
};
|
||||
|
||||
veth: fixedregulator@0 {
|
||||
veth: regulator-veth {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "veth";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
|
|
@ -362,7 +362,7 @@
|
|||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
ssp: ssp@1000d000 {
|
||||
ssp: spi@1000d000 {
|
||||
compatible = "arm,pl022", "arm,primecell";
|
||||
reg = <0x1000d000 0x1000>;
|
||||
clocks = <&sspclk>, <&pclk>;
|
||||
|
|
@ -567,4 +567,3 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -48,7 +48,7 @@
|
|||
&clearfog_sdhci_cd_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
vmmc = <®_3p3v>;
|
||||
vmmc-supply = <®_3p3v>;
|
||||
wp-inverted;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -350,7 +350,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c: i2c@1e78a000 {
|
||||
i2c: bus@1e78a000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -247,7 +247,7 @@
|
|||
compatible = "aspeed,ast2500-gpio";
|
||||
reg = <0x1e780000 0x1000>;
|
||||
interrupts = <20>;
|
||||
gpio-ranges = <&pinctrl 0 0 220>;
|
||||
gpio-ranges = <&pinctrl 0 0 232>;
|
||||
clocks = <&syscon ASPEED_CLK_APB>;
|
||||
interrupt-controller;
|
||||
};
|
||||
|
|
@ -410,7 +410,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c: i2c@1e78a000 {
|
||||
i2c: bus@1e78a000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -70,9 +70,9 @@
|
|||
&i2c1 {
|
||||
status = "okay";
|
||||
|
||||
eeprom@87 {
|
||||
eeprom@57 {
|
||||
compatible = "giantec,gt24c32a", "atmel,24c32";
|
||||
reg = <87>;
|
||||
reg = <0x57>;
|
||||
pagesize = <32>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -59,9 +59,9 @@
|
|||
&i2c1 {
|
||||
status = "okay";
|
||||
|
||||
ft5426@56 {
|
||||
ft5426@38 {
|
||||
compatible = "focaltech,ft5426", "edt,edt-ft5406";
|
||||
reg = <56>;
|
||||
reg = <0x38>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lcd_ctp_int>;
|
||||
|
||||
|
|
|
|||
|
|
@ -38,14 +38,16 @@
|
|||
atmel,pins =
|
||||
<AT91_PIOA 21
|
||||
AT91_PERIPH_GPIO
|
||||
AT91_PINCTRL_OUTPUT_VAL(0)>;
|
||||
(AT91_PINCTRL_OUTPUT |
|
||||
AT91_PINCTRL_OUTPUT_VAL(0))>;
|
||||
};
|
||||
|
||||
pinctrl_lcd_hipow0: lcd_hipow0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 23
|
||||
AT91_PERIPH_GPIO
|
||||
AT91_PINCTRL_OUTPUT_VAL(0)>;
|
||||
(AT91_PINCTRL_OUTPUT |
|
||||
AT91_PINCTRL_OUTPUT_VAL(0))>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -219,6 +221,7 @@
|
|||
reg = <0>;
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>;
|
||||
cd-inverted;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -92,13 +92,13 @@
|
|||
reg = <0x40000 0xc0000>;
|
||||
};
|
||||
|
||||
bootloaderenv@0x100000 {
|
||||
label = "bootloader env";
|
||||
bootloaderenvred@0x100000 {
|
||||
label = "bootloader env redundant";
|
||||
reg = <0x100000 0x40000>;
|
||||
};
|
||||
|
||||
bootloaderenvred@0x140000 {
|
||||
label = "bootloader env redundant";
|
||||
bootloaderenv@0x140000 {
|
||||
label = "bootloader env";
|
||||
reg = <0x140000 0x40000>;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -252,7 +252,7 @@
|
|||
|
||||
rootfs@800000 {
|
||||
label = "rootfs";
|
||||
reg = <0x800000 0x0f800000>;
|
||||
reg = <0x800000 0x1f800000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -128,7 +128,7 @@
|
|||
i2c2: i2c@f8024000 {
|
||||
status = "okay";
|
||||
|
||||
rtc1: rtc@64 {
|
||||
rtc1: rtc@32 {
|
||||
compatible = "epson,rx8900";
|
||||
reg = <0x32>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -434,7 +434,7 @@
|
|||
usart0 {
|
||||
pinctrl_usart0: usart0-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE
|
||||
<AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
|
||||
AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
|
||||
};
|
||||
|
||||
|
|
@ -468,7 +468,7 @@
|
|||
usart1 {
|
||||
pinctrl_usart1: usart1-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE
|
||||
<AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
|
||||
AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
|
||||
};
|
||||
|
||||
|
|
@ -486,7 +486,7 @@
|
|||
usart2 {
|
||||
pinctrl_usart2: usart2-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE
|
||||
<AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
|
||||
AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
|
||||
};
|
||||
|
||||
|
|
@ -504,7 +504,7 @@
|
|||
usart3 {
|
||||
pinctrl_usart3: usart3-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE
|
||||
<AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
|
||||
AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
|
||||
};
|
||||
|
||||
|
|
@ -522,7 +522,7 @@
|
|||
uart0 {
|
||||
pinctrl_uart0: uart0-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_NONE
|
||||
<AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP
|
||||
AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;
|
||||
};
|
||||
};
|
||||
|
|
@ -530,7 +530,7 @@
|
|||
uart1 {
|
||||
pinctrl_uart1: uart1-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE
|
||||
<AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
|
||||
AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -127,7 +127,7 @@
|
|||
|
||||
spi0: spi@fffc8000 {
|
||||
cs-gpios = <0>, <&pioC 11 0>, <0>, <0>;
|
||||
mtd_dataflash@0 {
|
||||
mtd_dataflash@1 {
|
||||
compatible = "atmel,at45", "atmel,dataflash";
|
||||
spi-max-frequency = <50000000>;
|
||||
reg = <1>;
|
||||
|
|
|
|||
|
|
@ -328,7 +328,7 @@
|
|||
usart0 {
|
||||
pinctrl_usart0: usart0-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE>,
|
||||
<AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
|
||||
<AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
|
||||
};
|
||||
|
||||
|
|
@ -346,7 +346,7 @@
|
|||
usart1 {
|
||||
pinctrl_usart1: usart1-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>,
|
||||
<AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
|
||||
<AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
|
||||
};
|
||||
|
||||
|
|
@ -364,7 +364,7 @@
|
|||
usart2 {
|
||||
pinctrl_usart2: usart2-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE>,
|
||||
<AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
|
||||
<AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -160,7 +160,7 @@
|
|||
spi-max-frequency = <15000000>;
|
||||
};
|
||||
|
||||
tsc2046@0 {
|
||||
tsc2046@2 {
|
||||
reg = <2>;
|
||||
compatible = "ti,ads7843";
|
||||
interrupts-extended = <&pioC 2 IRQ_TYPE_EDGE_BOTH>;
|
||||
|
|
|
|||
|
|
@ -437,7 +437,7 @@
|
|||
usart0 {
|
||||
pinctrl_usart0: usart0-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE
|
||||
<AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
|
||||
AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
|
||||
};
|
||||
|
||||
|
|
@ -455,7 +455,7 @@
|
|||
usart1 {
|
||||
pinctrl_usart1: usart1-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE
|
||||
<AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
|
||||
AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
|
||||
};
|
||||
|
||||
|
|
@ -473,7 +473,7 @@
|
|||
usart2 {
|
||||
pinctrl_usart2: usart2-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE
|
||||
<AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
|
||||
AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -109,7 +109,7 @@
|
|||
|
||||
spi0: spi@fffc8000 {
|
||||
cs-gpios = <0>, <&pioC 11 0>, <0>, <0>;
|
||||
mtd_dataflash@0 {
|
||||
mtd_dataflash@1 {
|
||||
compatible = "atmel,at45", "atmel,dataflash";
|
||||
spi-max-frequency = <50000000>;
|
||||
reg = <1>;
|
||||
|
|
|
|||
|
|
@ -555,7 +555,7 @@
|
|||
usart0 {
|
||||
pinctrl_usart0: usart0-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE
|
||||
<AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
|
||||
AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
|
||||
};
|
||||
|
||||
|
|
@ -570,10 +570,10 @@
|
|||
};
|
||||
};
|
||||
|
||||
uart1 {
|
||||
usart1 {
|
||||
pinctrl_usart1: usart1-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE
|
||||
<AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
|
||||
AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
|
||||
};
|
||||
|
||||
|
|
@ -591,7 +591,7 @@
|
|||
usart2 {
|
||||
pinctrl_usart2: usart2-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE
|
||||
<AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
|
||||
AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
|
||||
};
|
||||
|
||||
|
|
@ -609,7 +609,7 @@
|
|||
usart3 {
|
||||
pinctrl_usart3: usart3-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE
|
||||
<AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
|
||||
AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -681,7 +681,7 @@
|
|||
usart0 {
|
||||
pinctrl_usart0: usart0-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE>,
|
||||
<AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
|
||||
<AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
|
||||
};
|
||||
|
||||
|
|
@ -720,7 +720,7 @@
|
|||
usart1 {
|
||||
pinctrl_usart1: usart1-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE>,
|
||||
<AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
|
||||
<AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
|
||||
};
|
||||
|
||||
|
|
@ -743,7 +743,7 @@
|
|||
usart2 {
|
||||
pinctrl_usart2: usart2-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>,
|
||||
<AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
|
||||
<AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
|
||||
};
|
||||
|
||||
|
|
@ -766,7 +766,7 @@
|
|||
usart3 {
|
||||
pinctrl_usart3: usart3-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE>,
|
||||
<AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
|
||||
<AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -100,7 +100,7 @@
|
|||
|
||||
rootfs@800000 {
|
||||
label = "rootfs";
|
||||
reg = <0x800000 0x1f800000>;
|
||||
reg = <0x800000 0x0f800000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -169,8 +169,8 @@
|
|||
mdio: mdio@18002000 {
|
||||
compatible = "brcm,iproc-mdio";
|
||||
reg = <0x18002000 0x8>;
|
||||
#size-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
status = "disabled";
|
||||
|
||||
gphy0: ethernet-phy@0 {
|
||||
|
|
|
|||
|
|
@ -216,7 +216,7 @@
|
|||
reg = <0x33000 0x14>;
|
||||
};
|
||||
|
||||
qspi: qspi@27200 {
|
||||
qspi: spi@27200 {
|
||||
compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi";
|
||||
reg = <0x027200 0x184>,
|
||||
<0x027000 0x124>,
|
||||
|
|
|
|||
|
|
@ -273,7 +273,7 @@
|
|||
brcm,nand-has-wp;
|
||||
};
|
||||
|
||||
qspi: qspi@27200 {
|
||||
qspi: spi@27200 {
|
||||
compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi";
|
||||
reg = <0x027200 0x184>,
|
||||
<0x027000 0x124>,
|
||||
|
|
|
|||
|
|
@ -32,7 +32,7 @@
|
|||
|
||||
mailbox@7e00b840 {
|
||||
compatible = "brcm,bcm2835-vchiq";
|
||||
reg = <0x7e00b840 0xf>;
|
||||
reg = <0x7e00b840 0x3c>;
|
||||
interrupts = <0 2>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -39,7 +39,7 @@
|
|||
|
||||
trips {
|
||||
cpu-crit {
|
||||
temperature = <80000>;
|
||||
temperature = <90000>;
|
||||
hysteresis = <0>;
|
||||
type = "critical";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -350,8 +350,8 @@
|
|||
mdio: mdio@18003000 {
|
||||
compatible = "brcm,iproc-mdio";
|
||||
reg = <0x18003000 0x8>;
|
||||
#size-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
};
|
||||
|
||||
mdio-bus-mux {
|
||||
|
|
|
|||
|
|
@ -87,7 +87,7 @@
|
|||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
|
||||
si5351: clock-generator {
|
||||
si5351: clock-generator@60 {
|
||||
compatible = "silabs,si5351a-msop";
|
||||
reg = <0x60>;
|
||||
#address-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -155,7 +155,7 @@
|
|||
0xffffe000 MBUS_ID(0x03, 0x01) 0 0x0000800 /* CESA SRAM 2k */
|
||||
0xfffff000 MBUS_ID(0x0d, 0x00) 0 0x0000800>; /* PMU SRAM 2k */
|
||||
|
||||
spi0: spi-ctrl@10600 {
|
||||
spi0: spi@10600 {
|
||||
compatible = "marvell,orion-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -168,7 +168,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c: i2c-ctrl@11000 {
|
||||
i2c: i2c@11000 {
|
||||
compatible = "marvell,mv64xxx-i2c";
|
||||
reg = <0x11000 0x20>;
|
||||
#address-cells = <1>;
|
||||
|
|
@ -218,7 +218,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
spi1: spi-ctrl@14600 {
|
||||
spi1: spi@14600 {
|
||||
compatible = "marvell,orion-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
|
|||
|
|
@ -336,6 +336,7 @@
|
|||
<0 0 0 2 &pcie1_intc 2>,
|
||||
<0 0 0 3 &pcie1_intc 3>,
|
||||
<0 0 0 4 &pcie1_intc 4>;
|
||||
ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
|
||||
status = "disabled";
|
||||
pcie1_intc: interrupt-controller {
|
||||
interrupt-controller;
|
||||
|
|
@ -387,6 +388,7 @@
|
|||
<0 0 0 2 &pcie2_intc 2>,
|
||||
<0 0 0 3 &pcie2_intc 3>,
|
||||
<0 0 0 4 &pcie2_intc 4>;
|
||||
ti,syscon-unaligned-access = <&scm_conf1 0x14 2>;
|
||||
pcie2_intc: interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
|
|
@ -1369,7 +1371,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
qspi: qspi@4b300000 {
|
||||
qspi: spi@4b300000 {
|
||||
compatible = "ti,dra7xxx-qspi";
|
||||
reg = <0x4b300000 0x100>,
|
||||
<0x5c000000 0x4000000>;
|
||||
|
|
|
|||
|
|
@ -69,6 +69,8 @@
|
|||
compatible = "samsung,s2mps14-pmic";
|
||||
interrupt-parent = <&gpx3>;
|
||||
interrupts = <5 IRQ_TYPE_NONE>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&s2mps14_irq>;
|
||||
reg = <0x66>;
|
||||
|
||||
s2mps14_osc: clocks {
|
||||
|
|
@ -350,6 +352,11 @@
|
|||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV3>;
|
||||
samsung,pin-val = <1>;
|
||||
};
|
||||
|
||||
s2mps14_irq: s2mps14-irq {
|
||||
samsung,pins = "gpx3-5";
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
|
||||
};
|
||||
};
|
||||
|
||||
&rtc {
|
||||
|
|
|
|||
|
|
@ -360,7 +360,7 @@
|
|||
};
|
||||
|
||||
hsotg: hsotg@12480000 {
|
||||
compatible = "snps,dwc2";
|
||||
compatible = "samsung,s3c6400-hsotg", "snps,dwc2";
|
||||
reg = <0x12480000 0x20000>;
|
||||
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cmu CLK_USBOTG>;
|
||||
|
|
|
|||
|
|
@ -149,9 +149,11 @@
|
|||
};
|
||||
|
||||
&hdmi {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hdmi_hpd>;
|
||||
status = "okay";
|
||||
ddc = <&i2c_2>;
|
||||
hpd-gpios = <&gpx3 7 GPIO_ACTIVE_LOW>;
|
||||
ddc = <&i2c_ddc>;
|
||||
hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>;
|
||||
vdd_osc-supply = <&ldo10_reg>;
|
||||
vdd_pll-supply = <&ldo8_reg>;
|
||||
vdd-supply = <&ldo8_reg>;
|
||||
|
|
@ -168,6 +170,8 @@
|
|||
reg = <0x66>;
|
||||
interrupt-parent = <&gpx3>;
|
||||
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&s5m8767_irq>;
|
||||
|
||||
vinb1-supply = <&main_dc_reg>;
|
||||
vinb2-supply = <&main_dc_reg>;
|
||||
|
|
@ -452,13 +456,6 @@
|
|||
};
|
||||
};
|
||||
|
||||
&i2c_2 {
|
||||
status = "okay";
|
||||
/* used by HDMI DDC */
|
||||
samsung,i2c-sda-delay = <100>;
|
||||
samsung,i2c-max-bus-freq = <66000>;
|
||||
};
|
||||
|
||||
&i2c_3 {
|
||||
status = "okay";
|
||||
|
||||
|
|
@ -535,6 +532,13 @@
|
|||
cap-sd-highspeed;
|
||||
};
|
||||
|
||||
&pinctrl_0 {
|
||||
s5m8767_irq: s5m8767-irq {
|
||||
samsung,pins = "gpx3-2";
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
|
||||
};
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -547,3 +551,22 @@
|
|||
status = "okay";
|
||||
samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
|
||||
};
|
||||
|
||||
&soc {
|
||||
/*
|
||||
* For unknown reasons HDMI-DDC does not work with Exynos I2C
|
||||
* controllers. Lets use software I2C over GPIO pins as a workaround.
|
||||
*/
|
||||
i2c_ddc: i2c-gpio {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c2_gpio_bus>;
|
||||
status = "okay";
|
||||
compatible = "i2c-gpio";
|
||||
gpios = <&gpa0 6 0 /* sda */
|
||||
&gpa0 7 0 /* scl */
|
||||
>;
|
||||
i2c-gpio,delay-us = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -225,6 +225,12 @@
|
|||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
i2c2_gpio_bus: i2c2-gpio-bus {
|
||||
samsung,pins = "gpa0-6", "gpa0-7";
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
uart2_data: uart2-data {
|
||||
samsung,pins = "gpa1-0", "gpa1-1";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
|
|
@ -593,6 +599,11 @@
|
|||
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
hdmi_hpd: hdmi-hpd {
|
||||
samsung,pins = "gpx3-7";
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl_1 {
|
||||
|
|
|
|||
|
|
@ -20,6 +20,14 @@
|
|||
|
||||
samsung,model = "Snow-I2S-MAX98090";
|
||||
samsung,audio-codec = <&max98090>;
|
||||
|
||||
cpu {
|
||||
sound-dai = <&i2s0 0>;
|
||||
};
|
||||
|
||||
codec {
|
||||
sound-dai = <&max98090 0>, <&hdmi>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -31,6 +39,9 @@
|
|||
interrupt-parent = <&gpx0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&max98090_irq>;
|
||||
clocks = <&pmu_system_controller 0>;
|
||||
clock-names = "mclk";
|
||||
#sound-dai-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -153,7 +153,7 @@
|
|||
|
||||
&clock_audss {
|
||||
assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>;
|
||||
assigned-clock-parents = <&clock CLK_FOUT_EPLL>;
|
||||
assigned-clock-parents = <&clock CLK_MAU_EPLL>;
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
|
|
@ -312,6 +312,7 @@
|
|||
regulator-name = "vdd_1v35";
|
||||
regulator-min-microvolt = <1350000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
|
|
@ -333,6 +334,7 @@
|
|||
regulator-name = "vdd_2v";
|
||||
regulator-min-microvolt = <2000000>;
|
||||
regulator-max-microvolt = <2000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
|
|
@ -343,6 +345,7 @@
|
|||
regulator-name = "vdd_1v8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
|
|
|
|||
|
|
@ -224,7 +224,7 @@
|
|||
|
||||
ldo13_reg: LDO13 {
|
||||
regulator-name = "vddq_mmc2";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -153,7 +153,7 @@
|
|||
|
||||
&clock_audss {
|
||||
assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>;
|
||||
assigned-clock-parents = <&clock CLK_FOUT_EPLL>;
|
||||
assigned-clock-parents = <&clock CLK_MAU_EPLL>;
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
|
|
@ -312,6 +312,7 @@
|
|||
regulator-name = "vdd_1v35";
|
||||
regulator-min-microvolt = <1350000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
|
|
@ -333,6 +334,7 @@
|
|||
regulator-name = "vdd_2v";
|
||||
regulator-min-microvolt = <2000000>;
|
||||
regulator-max-microvolt = <2000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
|
|
@ -343,6 +345,7 @@
|
|||
regulator-name = "vdd_1v8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
|
|
|
|||
|
|
@ -20,7 +20,7 @@
|
|||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200n8";
|
||||
bootargs = "console=ttyS0,115200n8 root=/dev/mtdblock2 rw rootfstype=squashfs,jffs2 rootwait";
|
||||
stdout-path = &uart0;
|
||||
};
|
||||
|
||||
|
|
@ -138,37 +138,10 @@
|
|||
/* 16MB of flash */
|
||||
reg = <0x30000000 0x01000000>;
|
||||
|
||||
partition@0 {
|
||||
label = "RedBoot";
|
||||
reg = <0x00000000 0x00120000>;
|
||||
read-only;
|
||||
};
|
||||
partition@120000 {
|
||||
label = "Kernel";
|
||||
reg = <0x00120000 0x00200000>;
|
||||
};
|
||||
partition@320000 {
|
||||
label = "Ramdisk";
|
||||
reg = <0x00320000 0x00600000>;
|
||||
};
|
||||
partition@920000 {
|
||||
label = "Application";
|
||||
reg = <0x00920000 0x00600000>;
|
||||
};
|
||||
partition@f20000 {
|
||||
label = "VCTL";
|
||||
reg = <0x00f20000 0x00020000>;
|
||||
read-only;
|
||||
};
|
||||
partition@f40000 {
|
||||
label = "CurConf";
|
||||
reg = <0x00f40000 0x000a0000>;
|
||||
read-only;
|
||||
};
|
||||
partition@fe0000 {
|
||||
label = "FIS directory";
|
||||
reg = <0x00fe0000 0x00020000>;
|
||||
read-only;
|
||||
partitions {
|
||||
compatible = "redboot-fis";
|
||||
/* Eraseblock at 0xfe0000 */
|
||||
fis-index-block = <0x1fc>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -21,6 +21,7 @@
|
|||
};
|
||||
|
||||
memory@8000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x08000000 0x04000000>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -21,6 +21,7 @@
|
|||
};
|
||||
|
||||
memory@8000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x08000000 0x00800000>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -15,10 +15,8 @@
|
|||
* The decompressor and also some bootloaders rely on a
|
||||
* pre-existing /chosen node to be available to insert the
|
||||
* command line and merge other ATAGS info.
|
||||
* Also for U-Boot there must be a pre-existing /memory node.
|
||||
*/
|
||||
chosen {};
|
||||
memory { device_type = "memory"; };
|
||||
|
||||
aliases {
|
||||
gpio0 = &gpio1;
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@
|
|||
compatible = "fsl,imx23-evk", "fsl,imx23";
|
||||
|
||||
memory@40000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x40000000 0x08000000>;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -20,6 +20,7 @@
|
|||
compatible = "olimex,imx23-olinuxino", "fsl,imx23";
|
||||
|
||||
memory@40000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x40000000 0x04000000>;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -50,6 +50,7 @@
|
|||
compatible = "sandisk,sansa_fuze_plus", "fsl,imx23";
|
||||
|
||||
memory@40000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x40000000 0x04000000>;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@
|
|||
compatible = "fsl,stmp378x-devb", "fsl,imx23";
|
||||
|
||||
memory@40000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x40000000 0x04000000>;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -49,6 +49,7 @@
|
|||
compatible = "creative,x-fi3", "fsl,imx23";
|
||||
|
||||
memory@40000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x40000000 0x04000000>;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -13,10 +13,8 @@
|
|||
* The decompressor and also some bootloaders rely on a
|
||||
* pre-existing /chosen node to be available to insert the
|
||||
* command line and merge other ATAGS info.
|
||||
* Also for U-Boot there must be a pre-existing /memory node.
|
||||
*/
|
||||
chosen {};
|
||||
memory { device_type = "memory"; };
|
||||
|
||||
aliases {
|
||||
gpio0 = &gpio0;
|
||||
|
|
|
|||
|
|
@ -18,6 +18,7 @@
|
|||
compatible = "eukrea,cpuimx25", "fsl,imx25";
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x4000000>; /* 64M */
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -37,6 +37,7 @@
|
|||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x02000000 0x90000000 0x02000000>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -12,6 +12,7 @@
|
|||
compatible = "fsl,imx25-pdk", "fsl,imx25";
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x4000000>;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -12,10 +12,8 @@
|
|||
* The decompressor and also some bootloaders rely on a
|
||||
* pre-existing /chosen node to be available to insert the
|
||||
* command line and merge other ATAGS info.
|
||||
* Also for U-Boot there must be a pre-existing /memory node.
|
||||
*/
|
||||
chosen {};
|
||||
memory { device_type = "memory"; };
|
||||
|
||||
aliases {
|
||||
ethernet0 = &fec;
|
||||
|
|
|
|||
|
|
@ -20,6 +20,7 @@
|
|||
compatible = "armadeus,imx27-apf27", "fsl,imx27";
|
||||
|
||||
memory@a0000000 {
|
||||
device_type = "memory";
|
||||
reg = <0xa0000000 0x04000000>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue