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Add MU module for vpu dependence on QXP/QM 

Add MU module:
drivers/soc/imx/Makefile
drivers/soc/imx/mu/Makefile
drivers/soc/imx/mu/mx8_mu.c
include/linux/mx8_mu.h

Signed-off-by: Zhou Peng <eagle.zhou@nxp.com>
This commit is contained in:
Zhou Peng 2019-01-24 12:03:15 +08:00 committed by Dong Aisheng
parent 0cc4444a6d
commit a4f408b44e
4 changed files with 237 additions and 0 deletions
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1
drivers/soc/imx/Makefile
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@ -3,3 +3,4 @@ obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
obj-$(CONFIG_IMX_GPCV2_PM_DOMAINS) += gpcv2.o
obj-$(CONFIG_ARCH_MXC) += soc-imx8.o
obj-$(CONFIG_IMX_SCU_SOC) += soc-imx-scu.o
obj-y += mu/

1
drivers/soc/imx/mu/Makefile Normal file
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@ -0,0 +1 @@
obj-y += mx8_mu.o

187
drivers/soc/imx/mu/mx8_mu.c Normal file
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@ -0,0 +1,187 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/mx8_mu.h>
#include <linux/of.h>
static int version;
/*!
* This function sets the Flag n of the MU.
*/
int32_t MU_SetFn(void __iomem *base, uint32_t Fn)
{
uint32_t reg, offset;
reg = Fn & (~MU_CR_Fn_MASK1);
if (reg > 0)
return -EINVAL;
offset = unlikely(version == MU_VER_ID_V10)
? MU_V10_ACR_OFFSET1 : MU_ACR_OFFSET1;
reg = readl_relaxed(base + offset);
/* Clear ABFn. */
reg &= ~MU_CR_Fn_MASK1;
reg |= Fn;
writel_relaxed(reg, base + offset);
return 0;
}
/*!
* This function reads the status from status register.
*/
uint32_t MU_ReadStatus(void __iomem *base)
{
uint32_t reg, offset;
offset = unlikely(version == MU_VER_ID_V10)
? MU_V10_ASR_OFFSET1 : MU_ASR_OFFSET1;
reg = readl_relaxed(base + offset);
return reg;
}
/*!
* This function enables specific RX full interrupt.
*/
void MU_EnableRxFullInt(void __iomem *base, uint32_t index)
{
uint32_t reg, offset;
offset = unlikely(version == MU_VER_ID_V10)
? MU_V10_ACR_OFFSET1 : MU_ACR_OFFSET1;
reg = readl_relaxed(base + offset);
reg &= ~(MU_CR_GIRn_MASK1 | MU_CR_NMI_MASK1);
reg |= MU_CR_RIE0_MASK1 >> index;
writel_relaxed(reg, base + offset);
}
/*!
* This function enables specific general purpose interrupt.
*/
void MU_EnableGeneralInt(void __iomem *base, uint32_t index)
{
uint32_t reg, offset;
offset = unlikely(version == MU_VER_ID_V10)
? MU_V10_ACR_OFFSET1 : MU_ACR_OFFSET1;
reg = readl_relaxed(base + offset);
reg &= ~(MU_CR_GIRn_MASK1 | MU_CR_NMI_MASK1);
reg |= MU_CR_GIE0_MASK1 >> index;
writel_relaxed(reg, base + offset);
}
/*
* Wait and send message to the other core.
*/
void MU_SendMessage(void __iomem *base, uint32_t regIndex, uint32_t msg)
{
uint32_t mask = MU_SR_TE0_MASK1 >> regIndex;
if (unlikely(version == MU_VER_ID_V10)) {
/* Wait TX register to be empty. */
while (!(readl_relaxed(base + MU_V10_ASR_OFFSET1) & mask))
;
writel_relaxed(msg, base + MU_V10_ATR0_OFFSET1
+ (regIndex * 4));
} else {
/* Wait TX register to be empty. */
while (!(readl_relaxed(base + MU_ASR_OFFSET1) & mask))
;
writel_relaxed(msg, base + MU_ATR0_OFFSET1 + (regIndex * 4));
}
}
/*
* Wait and send message to the other core with timeout mechanism.
*/
void MU_SendMessageTimeout(void __iomem *base, uint32_t regIndex, uint32_t msg,
uint32_t t)
{
uint32_t mask = MU_SR_TE0_MASK1 >> regIndex;
uint32_t timeout = t;
if (unlikely(version == MU_VER_ID_V10)) {
/* Wait TX register to be empty. */
while (!(readl_relaxed(base + MU_V10_ASR_OFFSET1) & mask)) {
udelay(10);
if (timeout-- == 0)
return;
};
writel_relaxed(msg, base + MU_V10_ATR0_OFFSET1
+ (regIndex * 4));
} else {
/* Wait TX register to be empty. */
while (!(readl_relaxed(base + MU_ASR_OFFSET1) & mask)) {
udelay(10);
if (timeout-- == 0)
return;
};
writel_relaxed(msg, base + MU_ATR0_OFFSET1 + (regIndex * 4));
}
}
/*
* Wait to receive message from the other core.
*/
void MU_ReceiveMsg(void __iomem *base, uint32_t regIndex, uint32_t *msg)
{
uint32_t mask = MU_SR_RF0_MASK1 >> regIndex;
if (unlikely(version == MU_VER_ID_V10)) {
/* Wait RX register to be full. */
while (!(readl_relaxed(base + MU_V10_ASR_OFFSET1) & mask))
;
*msg = readl_relaxed(base + MU_V10_ARR0_OFFSET1
+ (regIndex * 4));
} else {
/* Wait RX register to be full. */
while (!(readl_relaxed(base + MU_ASR_OFFSET1) & mask))
;
*msg = readl_relaxed(base + MU_ARR0_OFFSET1 + (regIndex * 4));
}
}
void MU_Init(void __iomem *base)
{
uint32_t reg, offset;
version = readl_relaxed(base) >> 16;
offset = unlikely(version == MU_VER_ID_V10)
? MU_V10_ACR_OFFSET1 : MU_ACR_OFFSET1;
reg = readl_relaxed(base + offset);
/* Clear GIEn, TIEn, GIRn and ABFn. */
reg &= ~(MU_CR_GIEn_MASK1 | MU_CR_TIEn_MASK1
| MU_CR_GIRn_MASK1 | MU_CR_NMI_MASK1 | MU_CR_Fn_MASK1);
/*
* i.MX6SX and i.MX7D have multi-core power management which need
* to use RIE interrupts.
*/
if (!(of_machine_is_compatible("fsl,imx6sx") ||
of_machine_is_compatible("fsl,imx7d")))
reg &= ~MU_CR_RIEn_MASK1;
writel_relaxed(reg, base + offset);
}
/**@}*/

48
include/linux/mx8_mu.h Normal file
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@ -0,0 +1,48 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
#define MU_ATR0_OFFSET1 0x0
#define MU_ARR0_OFFSET1 0x10
#define MU_ASR_OFFSET1 0x20
#define MU_ACR_OFFSET1 0x24
/* Registers offsets of the MU Version 1.0 */
#define MU_V10_VER_OFFSET1 0x0
#define MU_V10_ATR0_OFFSET1 0x20
#define MU_V10_ARR0_OFFSET1 0x40
#define MU_V10_ASR_OFFSET1 0x60
#define MU_V10_ACR_OFFSET1 0x64
#define MU_VER_ID_V10 0x0100 /* Version 1.0 */
#define MU_TR_COUNT1 4
#define MU_RR_COUNT1 4
#define MU_CR_GIEn_MASK1 (0xF << 28)
#define MU_CR_RIEn_MASK1 (0xF << 24)
#define MU_CR_TIEn_MASK1 (0xF << 20)
#define MU_CR_GIRn_MASK1 (0xF << 16)
#define MU_CR_NMI_MASK1 (1 << 3)
#define MU_CR_Fn_MASK1 0x7
#define MU_SR_TE0_MASK1 (1 << 23)
#define MU_SR_RF0_MASK1 (1 << 27)
#define MU_CR_RIE0_MASK1 (1 << 27)
#define MU_CR_GIE0_MASK1 (1 << 31)
#define MU_TR_COUNT 4
#define MU_RR_COUNT 4
void MU_Init(void __iomem *base);
void MU_SendMessage(void __iomem *base, uint32_t regIndex, uint32_t msg);
void MU_SendMessageTimeout(void __iomem *base, uint32_t regIndex, uint32_t msg, uint32_t t);
void MU_ReceiveMsg(void __iomem *base, uint32_t regIndex, uint32_t *msg);
void MU_EnableGeneralInt(void __iomem *base, uint32_t index);
void MU_EnableRxFullInt(void __iomem *base, uint32_t index);
uint32_t MU_ReadStatus(void __iomem *base);
int32_t MU_SetFn(void __iomem *base, uint32_t Fn);