Merge branches 'clk-init-destroy', 'clk-doc', 'clk-imx' and 'clk-allwinner' into clk-next
- Set clk_init_data pointer inside clk_hw to NULL after registration * clk-init-destroy: clk: Overwrite clk_hw::init with NULL during clk_register() clk: sunxi: Don't call clk_hw_get_name() on a hw that isn't registered clk: ti: Don't reference clk_init_data after registration clk: qcom: Remove error prints from DFS registration rtc: sun6i: Don't reference clk_init_data after registration clk: zx296718: Don't reference clk_init_data after registration clk: milbeaut: Don't reference clk_init_data after registration clk: socfpga: deindent code to proper indentation phy: ti: am654-serdes: Don't reference clk_init_data after registration clk: sprd: Don't reference clk_init_data after registration clk: socfpga: Don't reference clk_init_data after registration clk: sirf: Don't reference clk_init_data after registration clk: qcom: Don't reference clk_init_data after registration clk: meson: axg-audio: Don't reference clk_init_data after registration clk: lochnagar: Don't reference clk_init_data after registration clk: actions: Don't reference clk_init_data after registration * clk-doc: clk: remove extra ---help--- tags in Kconfig clk: add include guard to clk-conf.h clk: Document of_parse_clkspec() some more clk: Remove extraneous 'for' word in comments * clk-imx: (32 commits) clk: imx: imx8mn: fix pll mux bit clk: imx: imx8mm: fix pll mux bit clk: imx: clk-pll14xx: unbypass PLL by default clk: imx: pll14xx: avoid glitch when set rate clk: imx: imx8mn: fix audio pll setting clk: imx8mn: Add necessary frequency support for ARM PLL table clk: imx8mn: Add missing rate_count assignment for each PLL structure clk: imx8mn: fix int pll clk gate clk: imx8mn: Add GIC clock clk: imx8mn: Fix incorrect parents clk: imx8mm: Fix incorrect parents clk: imx8mq: Fix sys3 pll references clk: imx8mq: Unregister clks when of_clk_add_provider failed clk: imx8mm: Unregister clks when of_clk_add_provider failed clk: imx8mq: Mark AHB clock as critical clk: imx8mn: Keep uart clocks on for early console clk: imx: Remove unused function statement clk: imx7ulp: Make sure earlycon's clock is enabled clk: imx8mm: Switch to platform driver clk: imx: imx8mm: fix audio pll setting ... * clk-allwinner: clk: sunxi-ng: h6: Allow I2S to change parent rate clk: sunxi-ng: v3s: add Allwinner V3 support clk: sunxi-ng: v3s: add missing clock slices for MMC2 module clocks dt-bindings: clk: sunxi-ccu: add compatible string for V3 CCU clk: sunxi-ng: v3s: add the missing PLL_DDR1
This commit is contained in:
Stephen Boyd
commit
a1ff1ce300
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@ -31,6 +31,7 @@ properties:
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- allwinner,sun8i-h3-ccu
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- allwinner,sun8i-h3-r-ccu
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- allwinner,sun8i-r40-ccu
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- allwinner,sun8i-v3-ccu
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- allwinner,sun8i-v3s-ccu
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- allwinner,sun9i-a80-ccu
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- allwinner,sun50i-a64-ccu
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|
|
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@ -0,0 +1,112 @@
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/bindings/clock/imx8mn-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NXP i.MX8M Nano Clock Control Module Binding
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maintainers:
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- Anson Huang <Anson.Huang@nxp.com>
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description: |
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NXP i.MX8M Nano clock control module is an integrated clock controller, which
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generates and supplies to all modules.
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properties:
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compatible:
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const: fsl,imx8mn-ccm
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reg:
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maxItems: 1
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clocks:
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items:
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- description: 32k osc
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- description: 24m osc
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- description: ext1 clock input
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- description: ext2 clock input
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- description: ext3 clock input
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- description: ext4 clock input
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clock-names:
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items:
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- const: osc_32k
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- const: osc_24m
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- const: clk_ext1
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- const: clk_ext2
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- const: clk_ext3
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- const: clk_ext4
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'#clock-cells':
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const: 1
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description: |
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mn-clock.h
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for the full list of i.MX8M Nano clock IDs.
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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examples:
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# Clock Control Module node:
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- |
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clk: clock-controller@30380000 {
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compatible = "fsl,imx8mn-ccm";
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reg = <0x0 0x30380000 0x0 0x10000>;
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#clock-cells = <1>;
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clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>,
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<&clk_ext2>, <&clk_ext3>, <&clk_ext4>;
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clock-names = "osc_32k", "osc_24m", "clk_ext1",
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"clk_ext2", "clk_ext3", "clk_ext4";
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};
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# Required external clocks for Clock Control Module node:
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- |
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osc_32k: clock-osc-32k {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "osc_32k";
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};
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osc_24m: clock-osc-24m {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "osc_24m";
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};
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clk_ext1: clock-ext1 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <133000000>;
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clock-output-names = "clk_ext1";
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};
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clk_ext2: clock-ext2 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <133000000>;
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clock-output-names = "clk_ext2";
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};
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|
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clk_ext3: clock-ext3 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <133000000>;
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clock-output-names = "clk_ext3";
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};
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clk_ext4: clock-ext4 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency= <133000000>;
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clock-output-names = "clk_ext4";
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};
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...
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|
|
@ -116,7 +116,6 @@ config COMMON_CLK_SI514
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depends on OF
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select REGMAP_I2C
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help
|
||||
---help---
|
||||
This driver supports the Silicon Labs 514 programmable clock
|
||||
generator.
|
||||
|
||||
|
|
@ -125,7 +124,6 @@ config COMMON_CLK_SI544
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|||
depends on I2C
|
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select REGMAP_I2C
|
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help
|
||||
---help---
|
||||
This driver supports the Silicon Labs 544 programmable clock
|
||||
generator.
|
||||
|
||||
|
|
@ -135,7 +133,6 @@ config COMMON_CLK_SI570
|
|||
depends on OF
|
||||
select REGMAP_I2C
|
||||
help
|
||||
---help---
|
||||
This driver supports Silicon Labs 570/571/598/599 programmable
|
||||
clock generators.
|
||||
|
||||
|
|
@ -153,7 +150,6 @@ config COMMON_CLK_CDCE925
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|||
depends on OF
|
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select REGMAP_I2C
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||||
help
|
||||
---help---
|
||||
This driver supports the TI CDCE913/925/937/949 programmable clock
|
||||
synthesizer. Each chip has different number of PLLs and outputs.
|
||||
For example, the CDCE925 contains two PLLs with spread-spectrum
|
||||
|
|
@ -212,7 +208,6 @@ config COMMON_CLK_AXI_CLKGEN
|
|||
tristate "AXI clkgen driver"
|
||||
depends on ARCH_ZYNQ || MICROBLAZE || COMPILE_TEST
|
||||
help
|
||||
---help---
|
||||
Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx
|
||||
FPGAs. It is commonly used in Analog Devices' reference designs.
|
||||
|
||||
|
|
@ -279,26 +274,22 @@ config COMMON_CLK_VC5
|
|||
depends on OF
|
||||
select REGMAP_I2C
|
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help
|
||||
---help---
|
||||
This driver supports the IDT VersaClock 5 and VersaClock 6
|
||||
programmable clock generators.
|
||||
|
||||
config COMMON_CLK_STM32MP157
|
||||
def_bool COMMON_CLK && MACH_STM32MP157
|
||||
help
|
||||
---help---
|
||||
Support for stm32mp157 SoC family clocks
|
||||
|
||||
config COMMON_CLK_STM32F
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||||
def_bool COMMON_CLK && (MACH_STM32F429 || MACH_STM32F469 || MACH_STM32F746)
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||||
help
|
||||
---help---
|
||||
Support for stm32f4 and stm32f7 SoC families clocks
|
||||
|
||||
config COMMON_CLK_STM32H7
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def_bool COMMON_CLK && MACH_STM32H743
|
||||
help
|
||||
---help---
|
||||
Support for stm32h7 SoC family clocks
|
||||
|
||||
config COMMON_CLK_BD718XX
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||||
|
|
|
|||
|
|
@ -68,16 +68,17 @@ int owl_clk_probe(struct device *dev, struct clk_hw_onecell_data *hw_clks)
|
|||
struct clk_hw *hw;
|
||||
|
||||
for (i = 0; i < hw_clks->num; i++) {
|
||||
const char *name;
|
||||
|
||||
hw = hw_clks->hws[i];
|
||||
|
||||
if (IS_ERR_OR_NULL(hw))
|
||||
continue;
|
||||
|
||||
name = hw->init->name;
|
||||
ret = devm_clk_hw_register(dev, hw);
|
||||
if (ret) {
|
||||
dev_err(dev, "Couldn't register clock %d - %s\n",
|
||||
i, hw->init->name);
|
||||
i, name);
|
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return ret;
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}
|
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}
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|
|
|
|||
|
|
@ -198,7 +198,7 @@ static u8 lochnagar_clk_get_parent(struct clk_hw *hw)
|
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if (ret < 0) {
|
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dev_dbg(priv->dev, "Failed to read parent of %s: %d\n",
|
||||
lclk->name, ret);
|
||||
return hw->init->num_parents;
|
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return clk_hw_get_num_parents(hw);
|
||||
}
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||||
|
||||
val &= lclk->src_mask;
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||||
|
|
|
|||
|
|
@ -437,7 +437,7 @@ static int m10v_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
|
|||
if (readl_poll_timeout(divider->write_valid_reg, val,
|
||||
!val, M10V_UPOLL_RATE, M10V_UTIMEOUT))
|
||||
pr_err("%s:%s couldn't stabilize\n",
|
||||
__func__, divider->hw.init->name);
|
||||
__func__, clk_hw_get_name(hw));
|
||||
}
|
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|
||||
if (divider->lock)
|
||||
|
|
|
|||
|
|
@ -2439,7 +2439,7 @@ static int clk_core_set_parent_nolock(struct clk_core *core,
|
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if (core->parent == parent)
|
||||
return 0;
|
||||
|
||||
/* verify ops for for multi-parent clks */
|
||||
/* verify ops for multi-parent clks */
|
||||
if (core->num_parents > 1 && !core->ops->set_parent)
|
||||
return -EPERM;
|
||||
|
||||
|
|
@ -3516,9 +3516,9 @@ static int clk_cpy_name(const char **dst_p, const char *src, bool must_exist)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int clk_core_populate_parent_map(struct clk_core *core)
|
||||
static int clk_core_populate_parent_map(struct clk_core *core,
|
||||
const struct clk_init_data *init)
|
||||
{
|
||||
const struct clk_init_data *init = core->hw->init;
|
||||
u8 num_parents = init->num_parents;
|
||||
const char * const *parent_names = init->parent_names;
|
||||
const struct clk_hw **parent_hws = init->parent_hws;
|
||||
|
|
@ -3598,6 +3598,14 @@ __clk_register(struct device *dev, struct device_node *np, struct clk_hw *hw)
|
|||
{
|
||||
int ret;
|
||||
struct clk_core *core;
|
||||
const struct clk_init_data *init = hw->init;
|
||||
|
||||
/*
|
||||
* The init data is not supposed to be used outside of registration path.
|
||||
* Set it to NULL so that provider drivers can't use it either and so that
|
||||
* we catch use of hw->init early on in the core.
|
||||
*/
|
||||
hw->init = NULL;
|
||||
|
||||
core = kzalloc(sizeof(*core), GFP_KERNEL);
|
||||
if (!core) {
|
||||
|
|
@ -3605,17 +3613,17 @@ __clk_register(struct device *dev, struct device_node *np, struct clk_hw *hw)
|
|||
goto fail_out;
|
||||
}
|
||||
|
||||
core->name = kstrdup_const(hw->init->name, GFP_KERNEL);
|
||||
core->name = kstrdup_const(init->name, GFP_KERNEL);
|
||||
if (!core->name) {
|
||||
ret = -ENOMEM;
|
||||
goto fail_name;
|
||||
}
|
||||
|
||||
if (WARN_ON(!hw->init->ops)) {
|
||||
if (WARN_ON(!init->ops)) {
|
||||
ret = -EINVAL;
|
||||
goto fail_ops;
|
||||
}
|
||||
core->ops = hw->init->ops;
|
||||
core->ops = init->ops;
|
||||
|
||||
if (dev && pm_runtime_enabled(dev))
|
||||
core->rpm_enabled = true;
|
||||
|
|
@ -3624,13 +3632,13 @@ __clk_register(struct device *dev, struct device_node *np, struct clk_hw *hw)
|
|||
if (dev && dev->driver)
|
||||
core->owner = dev->driver->owner;
|
||||
core->hw = hw;
|
||||
core->flags = hw->init->flags;
|
||||
core->num_parents = hw->init->num_parents;
|
||||
core->flags = init->flags;
|
||||
core->num_parents = init->num_parents;
|
||||
core->min_rate = 0;
|
||||
core->max_rate = ULONG_MAX;
|
||||
hw->core = core;
|
||||
|
||||
ret = clk_core_populate_parent_map(core);
|
||||
ret = clk_core_populate_parent_map(core, init);
|
||||
if (ret)
|
||||
goto fail_parents;
|
||||
|
||||
|
|
@ -4348,12 +4356,43 @@ void devm_of_clk_del_provider(struct device *dev)
|
|||
}
|
||||
EXPORT_SYMBOL(devm_of_clk_del_provider);
|
||||
|
||||
/*
|
||||
* Beware the return values when np is valid, but no clock provider is found.
|
||||
* If name == NULL, the function returns -ENOENT.
|
||||
* If name != NULL, the function returns -EINVAL. This is because
|
||||
* of_parse_phandle_with_args() is called even if of_property_match_string()
|
||||
* returns an error.
|
||||
/**
|
||||
* of_parse_clkspec() - Parse a DT clock specifier for a given device node
|
||||
* @np: device node to parse clock specifier from
|
||||
* @index: index of phandle to parse clock out of. If index < 0, @name is used
|
||||
* @name: clock name to find and parse. If name is NULL, the index is used
|
||||
* @out_args: Result of parsing the clock specifier
|
||||
*
|
||||
* Parses a device node's "clocks" and "clock-names" properties to find the
|
||||
* phandle and cells for the index or name that is desired. The resulting clock
|
||||
* specifier is placed into @out_args, or an errno is returned when there's a
|
||||
* parsing error. The @index argument is ignored if @name is non-NULL.
|
||||
*
|
||||
* Example:
|
||||
*
|
||||
* phandle1: clock-controller@1 {
|
||||
* #clock-cells = <2>;
|
||||
* }
|
||||
*
|
||||
* phandle2: clock-controller@2 {
|
||||
* #clock-cells = <1>;
|
||||
* }
|
||||
*
|
||||
* clock-consumer@3 {
|
||||
* clocks = <&phandle1 1 2 &phandle2 3>;
|
||||
* clock-names = "name1", "name2";
|
||||
* }
|
||||
*
|
||||
* To get a device_node for `clock-controller@2' node you may call this
|
||||
* function a few different ways:
|
||||
*
|
||||
* of_parse_clkspec(clock-consumer@3, -1, "name2", &args);
|
||||
* of_parse_clkspec(clock-consumer@3, 1, NULL, &args);
|
||||
* of_parse_clkspec(clock-consumer@3, 1, "name2", &args);
|
||||
*
|
||||
* Return: 0 upon successfully parsing the clock specifier. Otherwise, -ENOENT
|
||||
* if @name is NULL or -EINVAL if @name is non-NULL and it can't be found in
|
||||
* the "clock-names" property of @np.
|
||||
*/
|
||||
static int of_parse_clkspec(const struct device_node *np, int index,
|
||||
const char *name, struct of_phandle_args *out_args)
|
||||
|
|
|
|||
|
|
@ -14,6 +14,12 @@ config CLK_IMX8MM
|
|||
help
|
||||
Build the driver for i.MX8MM CCM Clock Driver
|
||||
|
||||
config CLK_IMX8MN
|
||||
bool "IMX8MN CCM Clock Driver"
|
||||
depends on ARCH_MXC && ARM64
|
||||
help
|
||||
Build the driver for i.MX8MN CCM Clock Driver
|
||||
|
||||
config CLK_IMX8MQ
|
||||
bool "IMX8MQ CCM Clock Driver"
|
||||
depends on ARCH_MXC && ARM64
|
||||
|
|
|
|||
|
|
@ -26,6 +26,7 @@ obj-$(CONFIG_MXC_CLK_SCU) += \
|
|||
clk-lpcg-scu.o
|
||||
|
||||
obj-$(CONFIG_CLK_IMX8MM) += clk-imx8mm.o
|
||||
obj-$(CONFIG_CLK_IMX8MN) += clk-imx8mn.o
|
||||
obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o
|
||||
obj-$(CONFIG_CLK_IMX8QXP) += clk-imx8qxp.o clk-imx8qxp-lpcg.o
|
||||
|
||||
|
|
|
|||
|
|
@ -42,6 +42,19 @@ static const struct clk_div_table ulp_div_table[] = {
|
|||
{ .val = 7, .div = 64, },
|
||||
};
|
||||
|
||||
static const int pcc2_uart_clk_ids[] __initconst = {
|
||||
IMX7ULP_CLK_LPUART4,
|
||||
IMX7ULP_CLK_LPUART5,
|
||||
};
|
||||
|
||||
static const int pcc3_uart_clk_ids[] __initconst = {
|
||||
IMX7ULP_CLK_LPUART6,
|
||||
IMX7ULP_CLK_LPUART7,
|
||||
};
|
||||
|
||||
static struct clk **pcc2_uart_clks[ARRAY_SIZE(pcc2_uart_clk_ids) + 1] __initdata;
|
||||
static struct clk **pcc3_uart_clks[ARRAY_SIZE(pcc3_uart_clk_ids) + 1] __initdata;
|
||||
|
||||
static void __init imx7ulp_clk_scg1_init(struct device_node *np)
|
||||
{
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
|
|
@ -135,6 +148,7 @@ static void __init imx7ulp_clk_pcc2_init(struct device_node *np)
|
|||
struct clk_hw_onecell_data *clk_data;
|
||||
struct clk_hw **clks;
|
||||
void __iomem *base;
|
||||
int i;
|
||||
|
||||
clk_data = kzalloc(struct_size(clk_data, hws, IMX7ULP_CLK_PCC2_END),
|
||||
GFP_KERNEL);
|
||||
|
|
@ -173,6 +187,14 @@ static void __init imx7ulp_clk_pcc2_init(struct device_node *np)
|
|||
imx_check_clk_hws(clks, clk_data->num);
|
||||
|
||||
of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(pcc2_uart_clk_ids); i++) {
|
||||
int index = pcc2_uart_clk_ids[i];
|
||||
|
||||
pcc2_uart_clks[i] = &clks[index]->clk;
|
||||
}
|
||||
|
||||
imx_register_uart_clocks(pcc2_uart_clks);
|
||||
}
|
||||
CLK_OF_DECLARE(imx7ulp_clk_pcc2, "fsl,imx7ulp-pcc2", imx7ulp_clk_pcc2_init);
|
||||
|
||||
|
|
@ -181,6 +203,7 @@ static void __init imx7ulp_clk_pcc3_init(struct device_node *np)
|
|||
struct clk_hw_onecell_data *clk_data;
|
||||
struct clk_hw **clks;
|
||||
void __iomem *base;
|
||||
int i;
|
||||
|
||||
clk_data = kzalloc(struct_size(clk_data, hws, IMX7ULP_CLK_PCC3_END),
|
||||
GFP_KERNEL);
|
||||
|
|
@ -218,6 +241,14 @@ static void __init imx7ulp_clk_pcc3_init(struct device_node *np)
|
|||
imx_check_clk_hws(clks, clk_data->num);
|
||||
|
||||
of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(pcc3_uart_clk_ids); i++) {
|
||||
int index = pcc3_uart_clk_ids[i];
|
||||
|
||||
pcc3_uart_clks[i] = &clks[index]->clk;
|
||||
}
|
||||
|
||||
imx_register_uart_clocks(pcc3_uart_clks);
|
||||
}
|
||||
CLK_OF_DECLARE(imx7ulp_clk_pcc3, "fsl,imx7ulp-pcc3", imx7ulp_clk_pcc3_init);
|
||||
|
||||
|
|
|
|||
|
|
@ -22,27 +22,10 @@ static u32 share_count_sai3;
|
|||
static u32 share_count_sai4;
|
||||
static u32 share_count_sai5;
|
||||
static u32 share_count_sai6;
|
||||
static u32 share_count_dcss;
|
||||
static u32 share_count_disp;
|
||||
static u32 share_count_pdm;
|
||||
static u32 share_count_nand;
|
||||
|
||||
#define PLL_1416X_RATE(_rate, _m, _p, _s) \
|
||||
{ \
|
||||
.rate = (_rate), \
|
||||
.mdiv = (_m), \
|
||||
.pdiv = (_p), \
|
||||
.sdiv = (_s), \
|
||||
}
|
||||
|
||||
#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
|
||||
{ \
|
||||
.rate = (_rate), \
|
||||
.mdiv = (_m), \
|
||||
.pdiv = (_p), \
|
||||
.sdiv = (_s), \
|
||||
.kdiv = (_k), \
|
||||
}
|
||||
|
||||
static const struct imx_pll14xx_rate_table imx8mm_pll1416x_tbl[] = {
|
||||
PLL_1416X_RATE(1800000000U, 225, 3, 0),
|
||||
PLL_1416X_RATE(1600000000U, 200, 3, 0),
|
||||
|
|
@ -55,8 +38,8 @@ static const struct imx_pll14xx_rate_table imx8mm_pll1416x_tbl[] = {
|
|||
};
|
||||
|
||||
static const struct imx_pll14xx_rate_table imx8mm_audiopll_tbl[] = {
|
||||
PLL_1443X_RATE(786432000U, 655, 5, 2, 23593),
|
||||
PLL_1443X_RATE(722534400U, 301, 5, 1, 3670),
|
||||
PLL_1443X_RATE(393216000U, 262, 2, 3, 9437),
|
||||
PLL_1443X_RATE(361267200U, 361, 3, 3, 17511),
|
||||
};
|
||||
|
||||
static const struct imx_pll14xx_rate_table imx8mm_videopll_tbl[] = {
|
||||
|
|
@ -68,43 +51,43 @@ static const struct imx_pll14xx_rate_table imx8mm_drampll_tbl[] = {
|
|||
PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
|
||||
};
|
||||
|
||||
static struct imx_pll14xx_clk imx8mm_audio_pll __initdata = {
|
||||
static struct imx_pll14xx_clk imx8mm_audio_pll = {
|
||||
.type = PLL_1443X,
|
||||
.rate_table = imx8mm_audiopll_tbl,
|
||||
.rate_count = ARRAY_SIZE(imx8mm_audiopll_tbl),
|
||||
};
|
||||
|
||||
static struct imx_pll14xx_clk imx8mm_video_pll __initdata = {
|
||||
static struct imx_pll14xx_clk imx8mm_video_pll = {
|
||||
.type = PLL_1443X,
|
||||
.rate_table = imx8mm_videopll_tbl,
|
||||
.rate_count = ARRAY_SIZE(imx8mm_videopll_tbl),
|
||||
};
|
||||
|
||||
static struct imx_pll14xx_clk imx8mm_dram_pll __initdata = {
|
||||
static struct imx_pll14xx_clk imx8mm_dram_pll = {
|
||||
.type = PLL_1443X,
|
||||
.rate_table = imx8mm_drampll_tbl,
|
||||
.rate_count = ARRAY_SIZE(imx8mm_drampll_tbl),
|
||||
};
|
||||
|
||||
static struct imx_pll14xx_clk imx8mm_arm_pll __initdata = {
|
||||
static struct imx_pll14xx_clk imx8mm_arm_pll = {
|
||||
.type = PLL_1416X,
|
||||
.rate_table = imx8mm_pll1416x_tbl,
|
||||
.rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
|
||||
};
|
||||
|
||||
static struct imx_pll14xx_clk imx8mm_gpu_pll __initdata = {
|
||||
static struct imx_pll14xx_clk imx8mm_gpu_pll = {
|
||||
.type = PLL_1416X,
|
||||
.rate_table = imx8mm_pll1416x_tbl,
|
||||
.rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
|
||||
};
|
||||
|
||||
static struct imx_pll14xx_clk imx8mm_vpu_pll __initdata = {
|
||||
static struct imx_pll14xx_clk imx8mm_vpu_pll = {
|
||||
.type = PLL_1416X,
|
||||
.rate_table = imx8mm_pll1416x_tbl,
|
||||
.rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
|
||||
};
|
||||
|
||||
static struct imx_pll14xx_clk imx8mm_sys_pll __initdata = {
|
||||
static struct imx_pll14xx_clk imx8mm_sys_pll = {
|
||||
.type = PLL_1416X,
|
||||
.rate_table = imx8mm_pll1416x_tbl,
|
||||
.rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
|
||||
|
|
@ -192,10 +175,10 @@ static const char *imx8mm_vpu_g1_sels[] = {"osc_24m", "vpu_pll_out", "sys_pll1_8
|
|||
static const char *imx8mm_vpu_g2_sels[] = {"osc_24m", "vpu_pll_out", "sys_pll1_800m", "sys_pll2_1000m",
|
||||
"sys_pll1_100m", "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", };
|
||||
|
||||
static const char *imx8mm_disp_dtrc_sels[] = {"osc_24m", "video_pll2_out", "sys_pll1_800m", "sys_pll2_1000m",
|
||||
static const char *imx8mm_disp_dtrc_sels[] = {"osc_24m", "dummy", "sys_pll1_800m", "sys_pll2_1000m",
|
||||
"sys_pll1_160m", "video_pll1_out", "sys_pll3_out", "audio_pll2_out", };
|
||||
|
||||
static const char *imx8mm_disp_dc8000_sels[] = {"osc_24m", "video_pll2_out", "sys_pll1_800m", "sys_pll2_1000m",
|
||||
static const char *imx8mm_disp_dc8000_sels[] = {"osc_24m", "dummy", "sys_pll1_800m", "sys_pll2_1000m",
|
||||
"sys_pll1_160m", "video_pll1_out", "sys_pll3_out", "audio_pll2_out", };
|
||||
|
||||
static const char *imx8mm_pcie1_ctrl_sels[] = {"osc_24m", "sys_pll2_250m", "sys_pll2_200m", "sys_pll1_266m",
|
||||
|
|
@ -249,7 +232,7 @@ static const char *imx8mm_enet_phy_sels[] = {"osc_24m", "sys_pll2_50m", "sys_pll
|
|||
static const char *imx8mm_nand_sels[] = {"osc_24m", "sys_pll2_500m", "audio_pll1_out", "sys_pll1_400m",
|
||||
"audio_pll2_out", "sys_pll3_out", "sys_pll2_250m", "video_pll1_out", };
|
||||
|
||||
static const char *imx8mm_qspi_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
|
||||
static const char *imx8mm_qspi_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll2_333m", "sys_pll2_500m",
|
||||
"audio_pll2_out", "sys_pll1_266m", "sys_pll3_out", "sys_pll1_100m", };
|
||||
|
||||
static const char *imx8mm_usdhc1_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
|
||||
|
|
@ -304,13 +287,13 @@ static const char *imx8mm_pwm2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_1
|
|||
"sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll1_out", };
|
||||
|
||||
static const char *imx8mm_pwm3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
|
||||
"sys3_pll2_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", };
|
||||
"sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", };
|
||||
|
||||
static const char *imx8mm_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
|
||||
"sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", };
|
||||
|
||||
static const char *imx8mm_gpt1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", "sys_pll1_40m",
|
||||
"video_pll1_out", "sys_pll1_800m", "audio_pll1_out", "clk_ext1" };
|
||||
"video_pll1_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext1" };
|
||||
|
||||
static const char *imx8mm_wdog_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_160m", "vpu_pll_out",
|
||||
"sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", };
|
||||
|
|
@ -364,7 +347,7 @@ static const char *imx8mm_pdm_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_
|
|||
"sys_pll2_1000m", "sys_pll3_out", "clk_ext3", "audio_pll2_out", };
|
||||
|
||||
static const char *imx8mm_vpu_h1_sels[] = {"osc_24m", "vpu_pll_out", "sys_pll1_800m", "sys_pll2_1000m",
|
||||
"audio_pll2_out", "sys_pll2_125m", "sys_pll3_clk", "audio_pll1_out", };
|
||||
"audio_pll2_out", "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", };
|
||||
|
||||
static const char *imx8mm_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", };
|
||||
|
||||
|
|
@ -374,7 +357,7 @@ static const char *imx8mm_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "osc_27m",
|
|||
static struct clk *clks[IMX8MM_CLK_END];
|
||||
static struct clk_onecell_data clk_data;
|
||||
|
||||
static struct clk ** const uart_clks[] __initconst = {
|
||||
static struct clk ** const uart_clks[] = {
|
||||
&clks[IMX8MM_CLK_UART1_ROOT],
|
||||
&clks[IMX8MM_CLK_UART2_ROOT],
|
||||
&clks[IMX8MM_CLK_UART3_ROOT],
|
||||
|
|
@ -382,19 +365,20 @@ static struct clk ** const uart_clks[] __initconst = {
|
|||
NULL
|
||||
};
|
||||
|
||||
static int __init imx8mm_clocks_init(struct device_node *ccm_node)
|
||||
static int imx8mm_clocks_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *np;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np = dev->of_node;
|
||||
void __iomem *base;
|
||||
int ret;
|
||||
|
||||
clks[IMX8MM_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
|
||||
clks[IMX8MM_CLK_24M] = of_clk_get_by_name(ccm_node, "osc_24m");
|
||||
clks[IMX8MM_CLK_32K] = of_clk_get_by_name(ccm_node, "osc_32k");
|
||||
clks[IMX8MM_CLK_EXT1] = of_clk_get_by_name(ccm_node, "clk_ext1");
|
||||
clks[IMX8MM_CLK_EXT2] = of_clk_get_by_name(ccm_node, "clk_ext2");
|
||||
clks[IMX8MM_CLK_EXT3] = of_clk_get_by_name(ccm_node, "clk_ext3");
|
||||
clks[IMX8MM_CLK_EXT4] = of_clk_get_by_name(ccm_node, "clk_ext4");
|
||||
clks[IMX8MM_CLK_24M] = of_clk_get_by_name(np, "osc_24m");
|
||||
clks[IMX8MM_CLK_32K] = of_clk_get_by_name(np, "osc_32k");
|
||||
clks[IMX8MM_CLK_EXT1] = of_clk_get_by_name(np, "clk_ext1");
|
||||
clks[IMX8MM_CLK_EXT2] = of_clk_get_by_name(np, "clk_ext2");
|
||||
clks[IMX8MM_CLK_EXT3] = of_clk_get_by_name(np, "clk_ext3");
|
||||
clks[IMX8MM_CLK_EXT4] = of_clk_get_by_name(np, "clk_ext4");
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx8mm-anatop");
|
||||
base = of_iomap(np, 0);
|
||||
|
|
@ -424,28 +408,16 @@ static int __init imx8mm_clocks_init(struct device_node *ccm_node)
|
|||
clks[IMX8MM_SYS_PLL3] = imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114, &imx8mm_sys_pll);
|
||||
|
||||
/* PLL bypass out */
|
||||
clks[IMX8MM_AUDIO_PLL1_BYPASS] = imx_clk_mux_flags("audio_pll1_bypass", base, 4, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MM_AUDIO_PLL2_BYPASS] = imx_clk_mux_flags("audio_pll2_bypass", base + 0x14, 4, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MM_VIDEO_PLL1_BYPASS] = imx_clk_mux_flags("video_pll1_bypass", base + 0x28, 4, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MM_DRAM_PLL_BYPASS] = imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MM_GPU_PLL_BYPASS] = imx_clk_mux_flags("gpu_pll_bypass", base + 0x64, 4, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MM_VPU_PLL_BYPASS] = imx_clk_mux_flags("vpu_pll_bypass", base + 0x74, 4, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MM_ARM_PLL_BYPASS] = imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MM_SYS_PLL1_BYPASS] = imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1, sys_pll1_bypass_sels, ARRAY_SIZE(sys_pll1_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MM_SYS_PLL2_BYPASS] = imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1, sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MM_SYS_PLL3_BYPASS] = imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
|
||||
/* unbypass all the plls */
|
||||
clk_set_parent(clks[IMX8MM_AUDIO_PLL1_BYPASS], clks[IMX8MM_AUDIO_PLL1]);
|
||||
clk_set_parent(clks[IMX8MM_AUDIO_PLL2_BYPASS], clks[IMX8MM_AUDIO_PLL2]);
|
||||
clk_set_parent(clks[IMX8MM_VIDEO_PLL1_BYPASS], clks[IMX8MM_VIDEO_PLL1]);
|
||||
clk_set_parent(clks[IMX8MM_DRAM_PLL_BYPASS], clks[IMX8MM_DRAM_PLL]);
|
||||
clk_set_parent(clks[IMX8MM_GPU_PLL_BYPASS], clks[IMX8MM_GPU_PLL]);
|
||||
clk_set_parent(clks[IMX8MM_VPU_PLL_BYPASS], clks[IMX8MM_VPU_PLL]);
|
||||
clk_set_parent(clks[IMX8MM_ARM_PLL_BYPASS], clks[IMX8MM_ARM_PLL]);
|
||||
clk_set_parent(clks[IMX8MM_SYS_PLL1_BYPASS], clks[IMX8MM_SYS_PLL1]);
|
||||
clk_set_parent(clks[IMX8MM_SYS_PLL2_BYPASS], clks[IMX8MM_SYS_PLL2]);
|
||||
clk_set_parent(clks[IMX8MM_SYS_PLL3_BYPASS], clks[IMX8MM_SYS_PLL3]);
|
||||
clks[IMX8MM_AUDIO_PLL1_BYPASS] = imx_clk_mux_flags("audio_pll1_bypass", base, 16, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MM_AUDIO_PLL2_BYPASS] = imx_clk_mux_flags("audio_pll2_bypass", base + 0x14, 16, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MM_VIDEO_PLL1_BYPASS] = imx_clk_mux_flags("video_pll1_bypass", base + 0x28, 16, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MM_DRAM_PLL_BYPASS] = imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 16, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MM_GPU_PLL_BYPASS] = imx_clk_mux_flags("gpu_pll_bypass", base + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MM_VPU_PLL_BYPASS] = imx_clk_mux_flags("vpu_pll_bypass", base + 0x74, 28, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MM_ARM_PLL_BYPASS] = imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 28, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MM_SYS_PLL1_BYPASS] = imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 28, 1, sys_pll1_bypass_sels, ARRAY_SIZE(sys_pll1_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MM_SYS_PLL2_BYPASS] = imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 28, 1, sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MM_SYS_PLL3_BYPASS] = imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 28, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
|
||||
/* PLL out gate */
|
||||
clks[IMX8MM_AUDIO_PLL1_OUT] = imx_clk_gate("audio_pll1_out", "audio_pll1_bypass", base, 13);
|
||||
|
|
@ -480,10 +452,10 @@ static int __init imx8mm_clocks_init(struct device_node *ccm_node)
|
|||
clks[IMX8MM_SYS_PLL2_500M] = imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2);
|
||||
clks[IMX8MM_SYS_PLL2_1000M] = imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
|
||||
|
||||
np = ccm_node;
|
||||
base = of_iomap(np, 0);
|
||||
if (WARN_ON(!base))
|
||||
return -ENOMEM;
|
||||
np = dev->of_node;
|
||||
base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (WARN_ON(IS_ERR(base)))
|
||||
return PTR_ERR(base);
|
||||
|
||||
/* Core Slice */
|
||||
clks[IMX8MM_CLK_A53_SRC] = imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3, imx8mm_a53_sels, ARRAY_SIZE(imx8mm_a53_sels));
|
||||
|
|
@ -631,7 +603,7 @@ static int __init imx8mm_clocks_init(struct device_node *ccm_node)
|
|||
clks[IMX8MM_CLK_UART2_ROOT] = imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0);
|
||||
clks[IMX8MM_CLK_UART3_ROOT] = imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0);
|
||||
clks[IMX8MM_CLK_UART4_ROOT] = imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0);
|
||||
clks[IMX8MM_CLK_USB1_CTRL_ROOT] = imx_clk_gate4("usb1_ctrl_root_clk", "usb_core_ref", base + 0x44d0, 0);
|
||||
clks[IMX8MM_CLK_USB1_CTRL_ROOT] = imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0);
|
||||
clks[IMX8MM_CLK_GPU3D_ROOT] = imx_clk_gate4("gpu3d_root_clk", "gpu3d_div", base + 0x44f0, 0);
|
||||
clks[IMX8MM_CLK_USDHC1_ROOT] = imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0);
|
||||
clks[IMX8MM_CLK_USDHC2_ROOT] = imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0);
|
||||
|
|
@ -644,10 +616,10 @@ static int __init imx8mm_clocks_init(struct device_node *ccm_node)
|
|||
clks[IMX8MM_CLK_VPU_G2_ROOT] = imx_clk_gate4("vpu_g2_root_clk", "vpu_g2", base + 0x45a0, 0);
|
||||
clks[IMX8MM_CLK_PDM_ROOT] = imx_clk_gate2_shared2("pdm_root_clk", "pdm", base + 0x45b0, 0, &share_count_pdm);
|
||||
clks[IMX8MM_CLK_PDM_IPG] = imx_clk_gate2_shared2("pdm_ipg_clk", "ipg_audio_root", base + 0x45b0, 0, &share_count_pdm);
|
||||
clks[IMX8MM_CLK_DISP_ROOT] = imx_clk_gate2_shared2("disp_root_clk", "disp_dc8000", base + 0x45d0, 0, &share_count_dcss);
|
||||
clks[IMX8MM_CLK_DISP_AXI_ROOT] = imx_clk_gate2_shared2("disp_axi_root_clk", "disp_axi", base + 0x45d0, 0, &share_count_dcss);
|
||||
clks[IMX8MM_CLK_DISP_APB_ROOT] = imx_clk_gate2_shared2("disp_apb_root_clk", "disp_apb", base + 0x45d0, 0, &share_count_dcss);
|
||||
clks[IMX8MM_CLK_DISP_RTRM_ROOT] = imx_clk_gate2_shared2("disp_rtrm_root_clk", "disp_rtrm", base + 0x45d0, 0, &share_count_dcss);
|
||||
clks[IMX8MM_CLK_DISP_ROOT] = imx_clk_gate2_shared2("disp_root_clk", "disp_dc8000", base + 0x45d0, 0, &share_count_disp);
|
||||
clks[IMX8MM_CLK_DISP_AXI_ROOT] = imx_clk_gate2_shared2("disp_axi_root_clk", "disp_axi", base + 0x45d0, 0, &share_count_disp);
|
||||
clks[IMX8MM_CLK_DISP_APB_ROOT] = imx_clk_gate2_shared2("disp_apb_root_clk", "disp_apb", base + 0x45d0, 0, &share_count_disp);
|
||||
clks[IMX8MM_CLK_DISP_RTRM_ROOT] = imx_clk_gate2_shared2("disp_rtrm_root_clk", "disp_rtrm", base + 0x45d0, 0, &share_count_disp);
|
||||
clks[IMX8MM_CLK_USDHC3_ROOT] = imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0);
|
||||
clks[IMX8MM_CLK_TMU_ROOT] = imx_clk_gate4("tmu_root_clk", "ipg_root", base + 0x4620, 0);
|
||||
clks[IMX8MM_CLK_VPU_DEC_ROOT] = imx_clk_gate4("vpu_dec_root_clk", "vpu_bus", base + 0x4630, 0);
|
||||
|
|
@ -675,11 +647,30 @@ static int __init imx8mm_clocks_init(struct device_node *ccm_node)
|
|||
ret = of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
if (ret < 0) {
|
||||
pr_err("failed to register clks for i.MX8MM\n");
|
||||
return -EINVAL;
|
||||
goto unregister_clks;
|
||||
}
|
||||
|
||||
imx_register_uart_clocks(uart_clks);
|
||||
|
||||
return 0;
|
||||
|
||||
unregister_clks:
|
||||
imx_unregister_clocks(clks, ARRAY_SIZE(clks));
|
||||
|
||||
return ret;
|
||||
}
|
||||
CLK_OF_DECLARE_DRIVER(imx8mm, "fsl,imx8mm-ccm", imx8mm_clocks_init);
|
||||
|
||||
static const struct of_device_id imx8mm_clk_of_match[] = {
|
||||
{ .compatible = "fsl,imx8mm-ccm" },
|
||||
{ /* Sentinel */ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, imx8mm_clk_of_match);
|
||||
|
||||
static struct platform_driver imx8mm_clk_driver = {
|
||||
.probe = imx8mm_clocks_probe,
|
||||
.driver = {
|
||||
.name = "imx8mm-ccm",
|
||||
.of_match_table = of_match_ptr(imx8mm_clk_of_match),
|
||||
},
|
||||
};
|
||||
module_platform_driver(imx8mm_clk_driver);
|
||||
|
|
|
|||
|
|
@ -0,0 +1,648 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright 2018-2019 NXP.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/imx8mn-clock.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#include "clk.h"
|
||||
|
||||
static u32 share_count_sai2;
|
||||
static u32 share_count_sai3;
|
||||
static u32 share_count_sai5;
|
||||
static u32 share_count_sai6;
|
||||
static u32 share_count_sai7;
|
||||
static u32 share_count_disp;
|
||||
static u32 share_count_pdm;
|
||||
static u32 share_count_nand;
|
||||
|
||||
enum {
|
||||
ARM_PLL,
|
||||
GPU_PLL,
|
||||
VPU_PLL,
|
||||
SYS_PLL1,
|
||||
SYS_PLL2,
|
||||
SYS_PLL3,
|
||||
DRAM_PLL,
|
||||
AUDIO_PLL1,
|
||||
AUDIO_PLL2,
|
||||
VIDEO_PLL2,
|
||||
NR_PLLS,
|
||||
};
|
||||
|
||||
static const struct imx_pll14xx_rate_table imx8mn_pll1416x_tbl[] = {
|
||||
PLL_1416X_RATE(1800000000U, 225, 3, 0),
|
||||
PLL_1416X_RATE(1600000000U, 200, 3, 0),
|
||||
PLL_1416X_RATE(1500000000U, 375, 3, 1),
|
||||
PLL_1416X_RATE(1400000000U, 350, 3, 1),
|
||||
PLL_1416X_RATE(1200000000U, 300, 3, 1),
|
||||
PLL_1416X_RATE(1000000000U, 250, 3, 1),
|
||||
PLL_1416X_RATE(800000000U, 200, 3, 1),
|
||||
PLL_1416X_RATE(750000000U, 250, 2, 2),
|
||||
PLL_1416X_RATE(700000000U, 350, 3, 2),
|
||||
PLL_1416X_RATE(600000000U, 300, 3, 2),
|
||||
};
|
||||
|
||||
static const struct imx_pll14xx_rate_table imx8mn_audiopll_tbl[] = {
|
||||
PLL_1443X_RATE(393216000U, 262, 2, 3, 9437),
|
||||
PLL_1443X_RATE(361267200U, 361, 3, 3, 17511),
|
||||
};
|
||||
|
||||
static const struct imx_pll14xx_rate_table imx8mn_videopll_tbl[] = {
|
||||
PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
|
||||
PLL_1443X_RATE(594000000U, 198, 2, 2, 0),
|
||||
};
|
||||
|
||||
static const struct imx_pll14xx_rate_table imx8mn_drampll_tbl[] = {
|
||||
PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
|
||||
};
|
||||
|
||||
static struct imx_pll14xx_clk imx8mn_audio_pll = {
|
||||
.type = PLL_1443X,
|
||||
.rate_table = imx8mn_audiopll_tbl,
|
||||
.rate_count = ARRAY_SIZE(imx8mn_audiopll_tbl),
|
||||
};
|
||||
|
||||
static struct imx_pll14xx_clk imx8mn_video_pll = {
|
||||
.type = PLL_1443X,
|
||||
.rate_table = imx8mn_videopll_tbl,
|
||||
.rate_count = ARRAY_SIZE(imx8mn_videopll_tbl),
|
||||
};
|
||||
|
||||
static struct imx_pll14xx_clk imx8mn_dram_pll = {
|
||||
.type = PLL_1443X,
|
||||
.rate_table = imx8mn_drampll_tbl,
|
||||
.rate_count = ARRAY_SIZE(imx8mn_drampll_tbl),
|
||||
};
|
||||
|
||||
static struct imx_pll14xx_clk imx8mn_arm_pll = {
|
||||
.type = PLL_1416X,
|
||||
.rate_table = imx8mn_pll1416x_tbl,
|
||||
.rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
|
||||
};
|
||||
|
||||
static struct imx_pll14xx_clk imx8mn_gpu_pll = {
|
||||
.type = PLL_1416X,
|
||||
.rate_table = imx8mn_pll1416x_tbl,
|
||||
.rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
|
||||
};
|
||||
|
||||
static struct imx_pll14xx_clk imx8mn_vpu_pll = {
|
||||
.type = PLL_1416X,
|
||||
.rate_table = imx8mn_pll1416x_tbl,
|
||||
.rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
|
||||
};
|
||||
|
||||
static struct imx_pll14xx_clk imx8mn_sys_pll = {
|
||||
.type = PLL_1416X,
|
||||
.rate_table = imx8mn_pll1416x_tbl,
|
||||
.rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
|
||||
};
|
||||
|
||||
static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", };
|
||||
static const char * const audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", };
|
||||
static const char * const audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", };
|
||||
static const char * const video_pll1_bypass_sels[] = {"video_pll1", "video_pll1_ref_sel", };
|
||||
static const char * const dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
|
||||
static const char * const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", };
|
||||
static const char * const vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", };
|
||||
static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
|
||||
static const char * const sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", };
|
||||
static const char * const sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", };
|
||||
static const char * const sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
|
||||
|
||||
static const char * const imx8mn_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pll2_500m",
|
||||
"sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m",
|
||||
"audio_pll1_out", "sys_pll3_out", };
|
||||
|
||||
static const char * const imx8mn_gpu_core_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m",
|
||||
"sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
|
||||
"video_pll1_out", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_gpu_shader_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m",
|
||||
"sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
|
||||
"video_pll1_out", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_main_axi_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll1_800m",
|
||||
"sys_pll2_250m", "sys_pll2_1000m", "audio_pll1_out",
|
||||
"video_pll1_out", "sys_pll1_100m",};
|
||||
|
||||
static const char * const imx8mn_enet_axi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m",
|
||||
"sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out",
|
||||
"video_pll1_out", "sys_pll3_out", };
|
||||
|
||||
static const char * const imx8mn_nand_usdhc_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m",
|
||||
"sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out",
|
||||
"sys_pll2_250m", "audio_pll1_out", };
|
||||
|
||||
static const char * const imx8mn_disp_axi_sels[] = {"osc_24m", "sys_pll2_1000m", "sys_pll1_800m",
|
||||
"sys_pll3_out", "sys_pll1_40m", "audio_pll2_out",
|
||||
"clk_ext1", "clk_ext4", };
|
||||
|
||||
static const char * const imx8mn_disp_apb_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll1_800m",
|
||||
"sys_pll3_out", "sys_pll1_40m", "audio_pll2_out",
|
||||
"clk_ext1", "clk_ext3", };
|
||||
|
||||
static const char * const imx8mn_usb_bus_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m",
|
||||
"sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
|
||||
"clk_ext4", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_gpu_axi_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out",
|
||||
"sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
|
||||
"video_pll1_out", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_gpu_ahb_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out",
|
||||
"sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
|
||||
"video_pll1_out", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_noc_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll3_out",
|
||||
"sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out",
|
||||
"video_pll1_out", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_ahb_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_800m",
|
||||
"sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out",
|
||||
"audio_pll1_out", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mn_audio_ahb_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m",
|
||||
"sys_pll2_1000m", "sys_pll2_166m", "sys_pll3_out",
|
||||
"audio_pll1_out", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mn_dram_alt_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll1_100m",
|
||||
"sys_pll2_500m", "sys_pll2_1000m", "sys_pll3_out",
|
||||
"audio_pll1_out", "sys_pll1_266m", };
|
||||
|
||||
static const char * const imx8mn_dram_apb_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
|
||||
"sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
|
||||
"sys_pll2_250m", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_disp_pixel_sels[] = {"osc_24m", "video_pll1_out", "audio_pll2_out",
|
||||
"audio_pll1_out", "sys_pll1_800m", "sys_pll2_1000m",
|
||||
"sys_pll3_out", "clk_ext4", };
|
||||
|
||||
static const char * const imx8mn_sai2_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
|
||||
"video_pll1_out", "sys_pll1_133m", "osc_hdmi",
|
||||
"clk_ext3", "clk_ext4", };
|
||||
|
||||
static const char * const imx8mn_sai3_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
|
||||
"video_pll1_out", "sys_pll1_133m", "osc_hdmi",
|
||||
"clk_ext3", "clk_ext4", };
|
||||
|
||||
static const char * const imx8mn_sai5_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
|
||||
"video_pll1_out", "sys_pll1_133m", "osc_hdmi",
|
||||
"clk_ext2", "clk_ext3", };
|
||||
|
||||
static const char * const imx8mn_sai6_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
|
||||
"video_pll1_out", "sys_pll1_133m", "osc_hdmi",
|
||||
"clk_ext3", "clk_ext4", };
|
||||
|
||||
static const char * const imx8mn_sai7_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
|
||||
"video_pll1_out", "sys_pll1_133m", "osc_hdmi",
|
||||
"clk_ext3", "clk_ext4", };
|
||||
|
||||
static const char * const imx8mn_spdif1_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
|
||||
"video_pll1_out", "sys_pll1_133m", "osc_hdmi",
|
||||
"clk_ext2", "clk_ext3", };
|
||||
|
||||
static const char * const imx8mn_enet_ref_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m",
|
||||
"sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out",
|
||||
"video_pll1_out", "clk_ext4", };
|
||||
|
||||
static const char * const imx8mn_enet_timer_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out",
|
||||
"clk_ext1", "clk_ext2", "clk_ext3",
|
||||
"clk_ext4", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mn_enet_phy_sels[] = {"osc_24m", "sys_pll2_50m", "sys_pll2_125m",
|
||||
"sys_pll2_200m", "sys_pll2_500m", "video_pll1_out",
|
||||
"audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_nand_sels[] = {"osc_24m", "sys_pll2_500m", "audio_pll1_out",
|
||||
"sys_pll1_400m", "audio_pll2_out", "sys_pll3_out",
|
||||
"sys_pll2_250m", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mn_qspi_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll2_333m",
|
||||
"sys_pll2_500m", "audio_pll2_out", "sys_pll1_266m",
|
||||
"sys_pll3_out", "sys_pll1_100m", };
|
||||
|
||||
static const char * const imx8mn_usdhc1_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
|
||||
"sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
|
||||
"audio_pll2_out", "sys_pll1_100m", };
|
||||
|
||||
static const char * const imx8mn_usdhc2_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
|
||||
"sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
|
||||
"audio_pll2_out", "sys_pll1_100m", };
|
||||
|
||||
static const char * const imx8mn_i2c1_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
|
||||
"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
|
||||
"audio_pll2_out", "sys_pll1_133m", };
|
||||
|
||||
static const char * const imx8mn_i2c2_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
|
||||
"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
|
||||
"audio_pll2_out", "sys_pll1_133m", };
|
||||
|
||||
static const char * const imx8mn_i2c3_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
|
||||
"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
|
||||
"audio_pll2_out", "sys_pll1_133m", };
|
||||
|
||||
static const char * const imx8mn_i2c4_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
|
||||
"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
|
||||
"audio_pll2_out", "sys_pll1_133m", };
|
||||
|
||||
static const char * const imx8mn_uart1_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
|
||||
"sys_pll2_100m", "sys_pll3_out", "clk_ext2",
|
||||
"clk_ext4", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_uart2_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
|
||||
"sys_pll2_100m", "sys_pll3_out", "clk_ext2",
|
||||
"clk_ext3", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_uart3_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
|
||||
"sys_pll2_100m", "sys_pll3_out", "clk_ext2",
|
||||
"clk_ext4", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_uart4_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
|
||||
"sys_pll2_100m", "sys_pll3_out", "clk_ext2",
|
||||
"clk_ext3", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_usb_core_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m",
|
||||
"sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
|
||||
"clk_ext3", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_usb_phy_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m",
|
||||
"sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
|
||||
"clk_ext3", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_gic_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
|
||||
"sys_pll2_100m", "sys_pll1_800m", "clk_ext2",
|
||||
"clk_ext4", "audio_pll2_out" };
|
||||
|
||||
static const char * const imx8mn_ecspi1_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
|
||||
"sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
|
||||
"sys_pll2_250m", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
|
||||
"sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
|
||||
"sys_pll2_250m", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_pwm1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
|
||||
"sys_pll1_40m", "sys_pll3_out", "clk_ext1",
|
||||
"sys_pll1_80m", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mn_pwm2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
|
||||
"sys_pll1_40m", "sys_pll3_out", "clk_ext1",
|
||||
"sys_pll1_80m", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mn_pwm3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
|
||||
"sys_pll1_40m", "sys_pll3_out", "clk_ext2",
|
||||
"sys_pll1_80m", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mn_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
|
||||
"sys_pll1_40m", "sys_pll3_out", "clk_ext2",
|
||||
"sys_pll1_80m", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mn_wdog_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_160m",
|
||||
"vpu_pll_out", "sys_pll2_125m", "sys_pll3_out",
|
||||
"sys_pll1_80m", "sys_pll2_166m", };
|
||||
|
||||
static const char * const imx8mn_wrclk_sels[] = {"osc_24m", "sys_pll1_40m", "vpu_pll_out",
|
||||
"sys_pll3_out", "sys_pll2_200m", "sys_pll1_266m",
|
||||
"sys_pll2_500m", "sys_pll1_100m", };
|
||||
|
||||
static const char * const imx8mn_dsi_core_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m",
|
||||
"sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
|
||||
"audio_pll2_out", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mn_dsi_phy_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_100m",
|
||||
"sys_pll1_800m", "sys_pll2_1000m", "clk_ext2",
|
||||
"audio_pll2_out", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mn_dsi_dbi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_100m",
|
||||
"sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
|
||||
"audio_pll2_out", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mn_usdhc3_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
|
||||
"sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
|
||||
"audio_pll2_out", "sys_pll1_100m", };
|
||||
|
||||
static const char * const imx8mn_camera_pixel_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m",
|
||||
"sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
|
||||
"audio_pll2_out", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mn_csi1_phy_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m",
|
||||
"sys_pll1_800m", "sys_pll2_1000m", "clk_ext2",
|
||||
"audio_pll2_out", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mn_csi2_phy_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m",
|
||||
"sys_pll1_800m", "sys_pll2_1000m", "clk_ext2",
|
||||
"audio_pll2_out", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mn_csi2_esc_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_80m",
|
||||
"sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
|
||||
"clk_ext3", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_ecspi3_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
|
||||
"sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
|
||||
"sys_pll2_250m", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_pdm_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out",
|
||||
"sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
|
||||
"clk_ext3", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", };
|
||||
|
||||
static const char * const imx8mn_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "osc_27m",
|
||||
"sys_pll1_200m", "audio_pll2_out", "vpu_pll",
|
||||
"sys_pll1_80m", };
|
||||
static const char * const imx8mn_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_400m",
|
||||
"sys_pll2_166m", "sys_pll3_out", "audio_pll1_out",
|
||||
"video_pll1_out", "osc_32k", };
|
||||
|
||||
static struct clk *clks[IMX8MN_CLK_END];
|
||||
static struct clk_onecell_data clk_data;
|
||||
|
||||
static struct clk ** const uart_clks[] = {
|
||||
&clks[IMX8MN_CLK_UART1_ROOT],
|
||||
&clks[IMX8MN_CLK_UART2_ROOT],
|
||||
&clks[IMX8MN_CLK_UART3_ROOT],
|
||||
&clks[IMX8MN_CLK_UART4_ROOT],
|
||||
NULL
|
||||
};
|
||||
|
||||
static int imx8mn_clocks_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np = dev->of_node;
|
||||
void __iomem *base;
|
||||
int ret;
|
||||
|
||||
clks[IMX8MN_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
|
||||
clks[IMX8MN_CLK_24M] = of_clk_get_by_name(np, "osc_24m");
|
||||
clks[IMX8MN_CLK_32K] = of_clk_get_by_name(np, "osc_32k");
|
||||
clks[IMX8MN_CLK_EXT1] = of_clk_get_by_name(np, "clk_ext1");
|
||||
clks[IMX8MN_CLK_EXT2] = of_clk_get_by_name(np, "clk_ext2");
|
||||
clks[IMX8MN_CLK_EXT3] = of_clk_get_by_name(np, "clk_ext3");
|
||||
clks[IMX8MN_CLK_EXT4] = of_clk_get_by_name(np, "clk_ext4");
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx8mn-anatop");
|
||||
base = of_iomap(np, 0);
|
||||
if (WARN_ON(!base)) {
|
||||
ret = -ENOMEM;
|
||||
goto unregister_clks;
|
||||
}
|
||||
|
||||
clks[IMX8MN_AUDIO_PLL1_REF_SEL] = imx_clk_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
clks[IMX8MN_AUDIO_PLL2_REF_SEL] = imx_clk_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
clks[IMX8MN_VIDEO_PLL1_REF_SEL] = imx_clk_mux("video_pll1_ref_sel", base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
clks[IMX8MN_DRAM_PLL_REF_SEL] = imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
clks[IMX8MN_GPU_PLL_REF_SEL] = imx_clk_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
clks[IMX8MN_VPU_PLL_REF_SEL] = imx_clk_mux("vpu_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
clks[IMX8MN_ARM_PLL_REF_SEL] = imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
clks[IMX8MN_SYS_PLL1_REF_SEL] = imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
clks[IMX8MN_SYS_PLL2_REF_SEL] = imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
clks[IMX8MN_SYS_PLL3_REF_SEL] = imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
|
||||
clks[IMX8MN_AUDIO_PLL1] = imx_clk_pll14xx("audio_pll1", "audio_pll1_ref_sel", base, &imx8mn_audio_pll);
|
||||
clks[IMX8MN_AUDIO_PLL2] = imx_clk_pll14xx("audio_pll2", "audio_pll2_ref_sel", base + 0x14, &imx8mn_audio_pll);
|
||||
clks[IMX8MN_VIDEO_PLL1] = imx_clk_pll14xx("video_pll1", "video_pll1_ref_sel", base + 0x28, &imx8mn_video_pll);
|
||||
clks[IMX8MN_DRAM_PLL] = imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx8mn_dram_pll);
|
||||
clks[IMX8MN_GPU_PLL] = imx_clk_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64, &imx8mn_gpu_pll);
|
||||
clks[IMX8MN_VPU_PLL] = imx_clk_pll14xx("vpu_pll", "vpu_pll_ref_sel", base + 0x74, &imx8mn_vpu_pll);
|
||||
clks[IMX8MN_ARM_PLL] = imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, &imx8mn_arm_pll);
|
||||
clks[IMX8MN_SYS_PLL1] = imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel", base + 0x94, &imx8mn_sys_pll);
|
||||
clks[IMX8MN_SYS_PLL2] = imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel", base + 0x104, &imx8mn_sys_pll);
|
||||
clks[IMX8MN_SYS_PLL3] = imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114, &imx8mn_sys_pll);
|
||||
|
||||
/* PLL bypass out */
|
||||
clks[IMX8MN_AUDIO_PLL1_BYPASS] = imx_clk_mux_flags("audio_pll1_bypass", base, 16, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MN_AUDIO_PLL2_BYPASS] = imx_clk_mux_flags("audio_pll2_bypass", base + 0x14, 16, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MN_VIDEO_PLL1_BYPASS] = imx_clk_mux_flags("video_pll1_bypass", base + 0x28, 16, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MN_DRAM_PLL_BYPASS] = imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 16, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MN_GPU_PLL_BYPASS] = imx_clk_mux_flags("gpu_pll_bypass", base + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MN_VPU_PLL_BYPASS] = imx_clk_mux_flags("vpu_pll_bypass", base + 0x74, 28, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MN_ARM_PLL_BYPASS] = imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 28, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MN_SYS_PLL1_BYPASS] = imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 28, 1, sys_pll1_bypass_sels, ARRAY_SIZE(sys_pll1_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MN_SYS_PLL2_BYPASS] = imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 28, 1, sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MN_SYS_PLL3_BYPASS] = imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 28, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
|
||||
/* PLL out gate */
|
||||
clks[IMX8MN_AUDIO_PLL1_OUT] = imx_clk_gate("audio_pll1_out", "audio_pll1_bypass", base, 13);
|
||||
clks[IMX8MN_AUDIO_PLL2_OUT] = imx_clk_gate("audio_pll2_out", "audio_pll2_bypass", base + 0x14, 13);
|
||||
clks[IMX8MN_VIDEO_PLL1_OUT] = imx_clk_gate("video_pll1_out", "video_pll1_bypass", base + 0x28, 13);
|
||||
clks[IMX8MN_DRAM_PLL_OUT] = imx_clk_gate("dram_pll_out", "dram_pll_bypass", base + 0x50, 13);
|
||||
clks[IMX8MN_GPU_PLL_OUT] = imx_clk_gate("gpu_pll_out", "gpu_pll_bypass", base + 0x64, 11);
|
||||
clks[IMX8MN_VPU_PLL_OUT] = imx_clk_gate("vpu_pll_out", "vpu_pll_bypass", base + 0x74, 11);
|
||||
clks[IMX8MN_ARM_PLL_OUT] = imx_clk_gate("arm_pll_out", "arm_pll_bypass", base + 0x84, 11);
|
||||
clks[IMX8MN_SYS_PLL1_OUT] = imx_clk_gate("sys_pll1_out", "sys_pll1_bypass", base + 0x94, 11);
|
||||
clks[IMX8MN_SYS_PLL2_OUT] = imx_clk_gate("sys_pll2_out", "sys_pll2_bypass", base + 0x104, 11);
|
||||
clks[IMX8MN_SYS_PLL3_OUT] = imx_clk_gate("sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11);
|
||||
|
||||
/* SYS PLL fixed output */
|
||||
clks[IMX8MN_SYS_PLL1_40M] = imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20);
|
||||
clks[IMX8MN_SYS_PLL1_80M] = imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10);
|
||||
clks[IMX8MN_SYS_PLL1_100M] = imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8);
|
||||
clks[IMX8MN_SYS_PLL1_133M] = imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6);
|
||||
clks[IMX8MN_SYS_PLL1_160M] = imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5);
|
||||
clks[IMX8MN_SYS_PLL1_200M] = imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4);
|
||||
clks[IMX8MN_SYS_PLL1_266M] = imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3);
|
||||
clks[IMX8MN_SYS_PLL1_400M] = imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2);
|
||||
clks[IMX8MN_SYS_PLL1_800M] = imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1);
|
||||
|
||||
clks[IMX8MN_SYS_PLL2_50M] = imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20);
|
||||
clks[IMX8MN_SYS_PLL2_100M] = imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10);
|
||||
clks[IMX8MN_SYS_PLL2_125M] = imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8);
|
||||
clks[IMX8MN_SYS_PLL2_166M] = imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6);
|
||||
clks[IMX8MN_SYS_PLL2_200M] = imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5);
|
||||
clks[IMX8MN_SYS_PLL2_250M] = imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4);
|
||||
clks[IMX8MN_SYS_PLL2_333M] = imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3);
|
||||
clks[IMX8MN_SYS_PLL2_500M] = imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2);
|
||||
clks[IMX8MN_SYS_PLL2_1000M] = imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
|
||||
|
||||
np = dev->of_node;
|
||||
base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (WARN_ON(IS_ERR(base))) {
|
||||
ret = PTR_ERR(base);
|
||||
goto unregister_clks;
|
||||
}
|
||||
|
||||
/* CORE */
|
||||
clks[IMX8MN_CLK_A53_SRC] = imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3, imx8mn_a53_sels, ARRAY_SIZE(imx8mn_a53_sels));
|
||||
clks[IMX8MN_CLK_GPU_CORE_SRC] = imx_clk_mux2("gpu_core_src", base + 0x8180, 24, 3, imx8mn_gpu_core_sels, ARRAY_SIZE(imx8mn_gpu_core_sels));
|
||||
clks[IMX8MN_CLK_GPU_SHADER_SRC] = imx_clk_mux2("gpu_shader_src", base + 0x8200, 24, 3, imx8mn_gpu_shader_sels, ARRAY_SIZE(imx8mn_gpu_shader_sels));
|
||||
clks[IMX8MN_CLK_A53_CG] = imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28);
|
||||
clks[IMX8MN_CLK_GPU_CORE_CG] = imx_clk_gate3("gpu_core_cg", "gpu_core_src", base + 0x8180, 28);
|
||||
clks[IMX8MN_CLK_GPU_SHADER_CG] = imx_clk_gate3("gpu_shader_cg", "gpu_shader_src", base + 0x8200, 28);
|
||||
|
||||
clks[IMX8MN_CLK_A53_DIV] = imx_clk_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3);
|
||||
clks[IMX8MN_CLK_GPU_CORE_DIV] = imx_clk_divider2("gpu_core_div", "gpu_core_cg", base + 0x8180, 0, 3);
|
||||
clks[IMX8MN_CLK_GPU_SHADER_DIV] = imx_clk_divider2("gpu_shader_div", "gpu_shader_cg", base + 0x8200, 0, 3);
|
||||
|
||||
/* BUS */
|
||||
clks[IMX8MN_CLK_MAIN_AXI] = imx8m_clk_composite_critical("main_axi", imx8mn_main_axi_sels, base + 0x8800);
|
||||
clks[IMX8MN_CLK_ENET_AXI] = imx8m_clk_composite("enet_axi", imx8mn_enet_axi_sels, base + 0x8880);
|
||||
clks[IMX8MN_CLK_NAND_USDHC_BUS] = imx8m_clk_composite("nand_usdhc_bus", imx8mn_nand_usdhc_sels, base + 0x8900);
|
||||
clks[IMX8MN_CLK_DISP_AXI] = imx8m_clk_composite("disp_axi", imx8mn_disp_axi_sels, base + 0x8a00);
|
||||
clks[IMX8MN_CLK_DISP_APB] = imx8m_clk_composite("disp_apb", imx8mn_disp_apb_sels, base + 0x8a80);
|
||||
clks[IMX8MN_CLK_USB_BUS] = imx8m_clk_composite("usb_bus", imx8mn_usb_bus_sels, base + 0x8b80);
|
||||
clks[IMX8MN_CLK_GPU_AXI] = imx8m_clk_composite("gpu_axi", imx8mn_gpu_axi_sels, base + 0x8c00);
|
||||
clks[IMX8MN_CLK_GPU_AHB] = imx8m_clk_composite("gpu_ahb", imx8mn_gpu_ahb_sels, base + 0x8c80);
|
||||
clks[IMX8MN_CLK_NOC] = imx8m_clk_composite_critical("noc", imx8mn_noc_sels, base + 0x8d00);
|
||||
|
||||
clks[IMX8MN_CLK_AHB] = imx8m_clk_composite_critical("ahb", imx8mn_ahb_sels, base + 0x9000);
|
||||
clks[IMX8MN_CLK_AUDIO_AHB] = imx8m_clk_composite("audio_ahb", imx8mn_audio_ahb_sels, base + 0x9100);
|
||||
clks[IMX8MN_CLK_IPG_ROOT] = imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1);
|
||||
clks[IMX8MN_CLK_IPG_AUDIO_ROOT] = imx_clk_divider2("ipg_audio_root", "audio_ahb", base + 0x9180, 0, 1);
|
||||
clks[IMX8MN_CLK_DRAM_CORE] = imx_clk_mux2_flags("dram_core_clk", base + 0x9800, 24, 1, imx8mn_dram_core_sels, ARRAY_SIZE(imx8mn_dram_core_sels), CLK_IS_CRITICAL);
|
||||
clks[IMX8MN_CLK_DRAM_ALT] = imx8m_clk_composite("dram_alt", imx8mn_dram_alt_sels, base + 0xa000);
|
||||
clks[IMX8MN_CLK_DRAM_APB] = imx8m_clk_composite_critical("dram_apb", imx8mn_dram_apb_sels, base + 0xa080);
|
||||
clks[IMX8MN_CLK_DISP_PIXEL] = imx8m_clk_composite("disp_pixel", imx8mn_disp_pixel_sels, base + 0xa500);
|
||||
clks[IMX8MN_CLK_SAI2] = imx8m_clk_composite("sai2", imx8mn_sai2_sels, base + 0xa600);
|
||||
clks[IMX8MN_CLK_SAI3] = imx8m_clk_composite("sai3", imx8mn_sai3_sels, base + 0xa680);
|
||||
clks[IMX8MN_CLK_SAI5] = imx8m_clk_composite("sai5", imx8mn_sai5_sels, base + 0xa780);
|
||||
clks[IMX8MN_CLK_SAI6] = imx8m_clk_composite("sai6", imx8mn_sai6_sels, base + 0xa800);
|
||||
clks[IMX8MN_CLK_SPDIF1] = imx8m_clk_composite("spdif1", imx8mn_spdif1_sels, base + 0xa880);
|
||||
clks[IMX8MN_CLK_ENET_REF] = imx8m_clk_composite("enet_ref", imx8mn_enet_ref_sels, base + 0xa980);
|
||||
clks[IMX8MN_CLK_ENET_TIMER] = imx8m_clk_composite("enet_timer", imx8mn_enet_timer_sels, base + 0xaa00);
|
||||
clks[IMX8MN_CLK_ENET_PHY_REF] = imx8m_clk_composite("enet_phy", imx8mn_enet_phy_sels, base + 0xaa80);
|
||||
clks[IMX8MN_CLK_NAND] = imx8m_clk_composite("nand", imx8mn_nand_sels, base + 0xab00);
|
||||
clks[IMX8MN_CLK_QSPI] = imx8m_clk_composite("qspi", imx8mn_qspi_sels, base + 0xab80);
|
||||
clks[IMX8MN_CLK_USDHC1] = imx8m_clk_composite("usdhc1", imx8mn_usdhc1_sels, base + 0xac00);
|
||||
clks[IMX8MN_CLK_USDHC2] = imx8m_clk_composite("usdhc2", imx8mn_usdhc2_sels, base + 0xac80);
|
||||
clks[IMX8MN_CLK_I2C1] = imx8m_clk_composite("i2c1", imx8mn_i2c1_sels, base + 0xad00);
|
||||
clks[IMX8MN_CLK_I2C2] = imx8m_clk_composite("i2c2", imx8mn_i2c2_sels, base + 0xad80);
|
||||
clks[IMX8MN_CLK_I2C3] = imx8m_clk_composite("i2c3", imx8mn_i2c3_sels, base + 0xae00);
|
||||
clks[IMX8MN_CLK_I2C4] = imx8m_clk_composite("i2c4", imx8mn_i2c4_sels, base + 0xae80);
|
||||
clks[IMX8MN_CLK_UART1] = imx8m_clk_composite("uart1", imx8mn_uart1_sels, base + 0xaf00);
|
||||
clks[IMX8MN_CLK_UART2] = imx8m_clk_composite("uart2", imx8mn_uart2_sels, base + 0xaf80);
|
||||
clks[IMX8MN_CLK_UART3] = imx8m_clk_composite("uart3", imx8mn_uart3_sels, base + 0xb000);
|
||||
clks[IMX8MN_CLK_UART4] = imx8m_clk_composite("uart4", imx8mn_uart4_sels, base + 0xb080);
|
||||
clks[IMX8MN_CLK_USB_CORE_REF] = imx8m_clk_composite("usb_core_ref", imx8mn_usb_core_sels, base + 0xb100);
|
||||
clks[IMX8MN_CLK_USB_PHY_REF] = imx8m_clk_composite("usb_phy_ref", imx8mn_usb_phy_sels, base + 0xb180);
|
||||
clks[IMX8MN_CLK_GIC] = imx8m_clk_composite_critical("gic", imx8mn_gic_sels, base + 0xb200);
|
||||
clks[IMX8MN_CLK_ECSPI1] = imx8m_clk_composite("ecspi1", imx8mn_ecspi1_sels, base + 0xb280);
|
||||
clks[IMX8MN_CLK_ECSPI2] = imx8m_clk_composite("ecspi2", imx8mn_ecspi2_sels, base + 0xb300);
|
||||
clks[IMX8MN_CLK_PWM1] = imx8m_clk_composite("pwm1", imx8mn_pwm1_sels, base + 0xb380);
|
||||
clks[IMX8MN_CLK_PWM2] = imx8m_clk_composite("pwm2", imx8mn_pwm2_sels, base + 0xb400);
|
||||
clks[IMX8MN_CLK_PWM3] = imx8m_clk_composite("pwm3", imx8mn_pwm3_sels, base + 0xb480);
|
||||
clks[IMX8MN_CLK_PWM4] = imx8m_clk_composite("pwm4", imx8mn_pwm4_sels, base + 0xb500);
|
||||
clks[IMX8MN_CLK_WDOG] = imx8m_clk_composite("wdog", imx8mn_wdog_sels, base + 0xb900);
|
||||
clks[IMX8MN_CLK_WRCLK] = imx8m_clk_composite("wrclk", imx8mn_wrclk_sels, base + 0xb980);
|
||||
clks[IMX8MN_CLK_CLKO1] = imx8m_clk_composite("clko1", imx8mn_clko1_sels, base + 0xba00);
|
||||
clks[IMX8MN_CLK_CLKO2] = imx8m_clk_composite("clko2", imx8mn_clko2_sels, base + 0xba80);
|
||||
clks[IMX8MN_CLK_DSI_CORE] = imx8m_clk_composite("dsi_core", imx8mn_dsi_core_sels, base + 0xbb00);
|
||||
clks[IMX8MN_CLK_DSI_PHY_REF] = imx8m_clk_composite("dsi_phy_ref", imx8mn_dsi_phy_sels, base + 0xbb80);
|
||||
clks[IMX8MN_CLK_DSI_DBI] = imx8m_clk_composite("dsi_dbi", imx8mn_dsi_dbi_sels, base + 0xbc00);
|
||||
clks[IMX8MN_CLK_USDHC3] = imx8m_clk_composite("usdhc3", imx8mn_usdhc3_sels, base + 0xbc80);
|
||||
clks[IMX8MN_CLK_CAMERA_PIXEL] = imx8m_clk_composite("camera_pixel", imx8mn_camera_pixel_sels, base + 0xbd00);
|
||||
clks[IMX8MN_CLK_CSI1_PHY_REF] = imx8m_clk_composite("csi1_phy_ref", imx8mn_csi1_phy_sels, base + 0xbd80);
|
||||
clks[IMX8MN_CLK_CSI2_PHY_REF] = imx8m_clk_composite("csi2_phy_ref", imx8mn_csi2_phy_sels, base + 0xbf00);
|
||||
clks[IMX8MN_CLK_CSI2_ESC] = imx8m_clk_composite("csi2_esc", imx8mn_csi2_esc_sels, base + 0xbf80);
|
||||
clks[IMX8MN_CLK_ECSPI3] = imx8m_clk_composite("ecspi3", imx8mn_ecspi3_sels, base + 0xc180);
|
||||
clks[IMX8MN_CLK_PDM] = imx8m_clk_composite("pdm", imx8mn_pdm_sels, base + 0xc200);
|
||||
clks[IMX8MN_CLK_SAI7] = imx8m_clk_composite("sai7", imx8mn_sai7_sels, base + 0xc300);
|
||||
|
||||
clks[IMX8MN_CLK_ECSPI1_ROOT] = imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0);
|
||||
clks[IMX8MN_CLK_ECSPI2_ROOT] = imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0);
|
||||
clks[IMX8MN_CLK_ECSPI3_ROOT] = imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0);
|
||||
clks[IMX8MN_CLK_ENET1_ROOT] = imx_clk_gate4("enet1_root_clk", "enet_axi", base + 0x40a0, 0);
|
||||
clks[IMX8MN_CLK_GPIO1_ROOT] = imx_clk_gate4("gpio1_root_clk", "ipg_root", base + 0x40b0, 0);
|
||||
clks[IMX8MN_CLK_GPIO2_ROOT] = imx_clk_gate4("gpio2_root_clk", "ipg_root", base + 0x40c0, 0);
|
||||
clks[IMX8MN_CLK_GPIO3_ROOT] = imx_clk_gate4("gpio3_root_clk", "ipg_root", base + 0x40d0, 0);
|
||||
clks[IMX8MN_CLK_GPIO4_ROOT] = imx_clk_gate4("gpio4_root_clk", "ipg_root", base + 0x40e0, 0);
|
||||
clks[IMX8MN_CLK_GPIO5_ROOT] = imx_clk_gate4("gpio5_root_clk", "ipg_root", base + 0x40f0, 0);
|
||||
clks[IMX8MN_CLK_I2C1_ROOT] = imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0);
|
||||
clks[IMX8MN_CLK_I2C2_ROOT] = imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0);
|
||||
clks[IMX8MN_CLK_I2C3_ROOT] = imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0);
|
||||
clks[IMX8MN_CLK_I2C4_ROOT] = imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0);
|
||||
clks[IMX8MN_CLK_MU_ROOT] = imx_clk_gate4("mu_root_clk", "ipg_root", base + 0x4210, 0);
|
||||
clks[IMX8MN_CLK_OCOTP_ROOT] = imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0);
|
||||
clks[IMX8MN_CLK_PWM1_ROOT] = imx_clk_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0);
|
||||
clks[IMX8MN_CLK_PWM2_ROOT] = imx_clk_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0);
|
||||
clks[IMX8MN_CLK_PWM3_ROOT] = imx_clk_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0);
|
||||
clks[IMX8MN_CLK_PWM4_ROOT] = imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0);
|
||||
clks[IMX8MN_CLK_QSPI_ROOT] = imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0);
|
||||
clks[IMX8MN_CLK_NAND_ROOT] = imx_clk_gate2_shared2("nand_root_clk", "nand", base + 0x4300, 0, &share_count_nand);
|
||||
clks[IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK] = imx_clk_gate2_shared2("nand_usdhc_rawnand_clk", "nand_usdhc_bus", base + 0x4300, 0, &share_count_nand);
|
||||
clks[IMX8MN_CLK_SAI2_ROOT] = imx_clk_gate2_shared2("sai2_root_clk", "sai2", base + 0x4340, 0, &share_count_sai2);
|
||||
clks[IMX8MN_CLK_SAI2_IPG] = imx_clk_gate2_shared2("sai2_ipg_clk", "ipg_audio_root", base + 0x4340, 0, &share_count_sai2);
|
||||
clks[IMX8MN_CLK_SAI3_ROOT] = imx_clk_gate2_shared2("sai3_root_clk", "sai3", base + 0x4350, 0, &share_count_sai3);
|
||||
clks[IMX8MN_CLK_SAI3_IPG] = imx_clk_gate2_shared2("sai3_ipg_clk", "ipg_audio_root", base + 0x4350, 0, &share_count_sai3);
|
||||
clks[IMX8MN_CLK_SAI5_ROOT] = imx_clk_gate2_shared2("sai5_root_clk", "sai5", base + 0x4370, 0, &share_count_sai5);
|
||||
clks[IMX8MN_CLK_SAI5_IPG] = imx_clk_gate2_shared2("sai5_ipg_clk", "ipg_audio_root", base + 0x4370, 0, &share_count_sai5);
|
||||
clks[IMX8MN_CLK_SAI6_ROOT] = imx_clk_gate2_shared2("sai6_root_clk", "sai6", base + 0x4380, 0, &share_count_sai6);
|
||||
clks[IMX8MN_CLK_SAI6_IPG] = imx_clk_gate2_shared2("sai6_ipg_clk", "ipg_audio_root", base + 0x4380, 0, &share_count_sai6);
|
||||
clks[IMX8MN_CLK_UART1_ROOT] = imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0);
|
||||
clks[IMX8MN_CLK_UART2_ROOT] = imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0);
|
||||
clks[IMX8MN_CLK_UART3_ROOT] = imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0);
|
||||
clks[IMX8MN_CLK_UART4_ROOT] = imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0);
|
||||
clks[IMX8MN_CLK_USB1_CTRL_ROOT] = imx_clk_gate4("usb1_ctrl_root_clk", "usb_core_ref", base + 0x44d0, 0);
|
||||
clks[IMX8MN_CLK_GPU_CORE_ROOT] = imx_clk_gate4("gpu_core_root_clk", "gpu_core_div", base + 0x44f0, 0);
|
||||
clks[IMX8MN_CLK_USDHC1_ROOT] = imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0);
|
||||
clks[IMX8MN_CLK_USDHC2_ROOT] = imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0);
|
||||
clks[IMX8MN_CLK_WDOG1_ROOT] = imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0);
|
||||
clks[IMX8MN_CLK_WDOG2_ROOT] = imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0);
|
||||
clks[IMX8MN_CLK_WDOG3_ROOT] = imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0);
|
||||
clks[IMX8MN_CLK_GPU_BUS_ROOT] = imx_clk_gate4("gpu_root_clk", "gpu_axi", base + 0x4570, 0);
|
||||
clks[IMX8MN_CLK_ASRC_ROOT] = imx_clk_gate4("asrc_root_clk", "audio_ahb", base + 0x4580, 0);
|
||||
clks[IMX8MN_CLK_PDM_ROOT] = imx_clk_gate2_shared2("pdm_root_clk", "pdm", base + 0x45b0, 0, &share_count_pdm);
|
||||
clks[IMX8MN_CLK_PDM_IPG] = imx_clk_gate2_shared2("pdm_ipg_clk", "ipg_audio_root", base + 0x45b0, 0, &share_count_pdm);
|
||||
clks[IMX8MN_CLK_DISP_AXI_ROOT] = imx_clk_gate2_shared2("disp_axi_root_clk", "disp_axi", base + 0x45d0, 0, &share_count_disp);
|
||||
clks[IMX8MN_CLK_DISP_APB_ROOT] = imx_clk_gate2_shared2("disp_apb_root_clk", "disp_apb", base + 0x45d0, 0, &share_count_disp);
|
||||
clks[IMX8MN_CLK_CAMERA_PIXEL_ROOT] = imx_clk_gate2_shared2("camera_pixel_clk", "camera_pixel", base + 0x45d0, 0, &share_count_disp);
|
||||
clks[IMX8MN_CLK_DISP_PIXEL_ROOT] = imx_clk_gate2_shared2("disp_pixel_clk", "disp_pixel", base + 0x45d0, 0, &share_count_disp);
|
||||
clks[IMX8MN_CLK_USDHC3_ROOT] = imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0);
|
||||
clks[IMX8MN_CLK_TMU_ROOT] = imx_clk_gate4("tmu_root_clk", "ipg_root", base + 0x4620, 0);
|
||||
clks[IMX8MN_CLK_SDMA1_ROOT] = imx_clk_gate4("sdma1_clk", "ipg_root", base + 0x43a0, 0);
|
||||
clks[IMX8MN_CLK_SDMA2_ROOT] = imx_clk_gate4("sdma2_clk", "ipg_audio_root", base + 0x43b0, 0);
|
||||
clks[IMX8MN_CLK_SDMA3_ROOT] = imx_clk_gate4("sdma3_clk", "ipg_audio_root", base + 0x45f0, 0);
|
||||
clks[IMX8MN_CLK_SAI7_ROOT] = imx_clk_gate2_shared2("sai7_root_clk", "sai7", base + 0x4650, 0, &share_count_sai7);
|
||||
|
||||
clks[IMX8MN_CLK_DRAM_ALT_ROOT] = imx_clk_fixed_factor("dram_alt_root", "dram_alt", 1, 4);
|
||||
|
||||
clks[IMX8MN_CLK_ARM] = imx_clk_cpu("arm", "arm_a53_div",
|
||||
clks[IMX8MN_CLK_A53_DIV],
|
||||
clks[IMX8MN_CLK_A53_SRC],
|
||||
clks[IMX8MN_ARM_PLL_OUT],
|
||||
clks[IMX8MN_CLK_24M]);
|
||||
|
||||
imx_check_clocks(clks, ARRAY_SIZE(clks));
|
||||
|
||||
clk_data.clks = clks;
|
||||
clk_data.clk_num = ARRAY_SIZE(clks);
|
||||
ret = of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "failed to register clks for i.MX8MN\n");
|
||||
goto unregister_clks;
|
||||
}
|
||||
|
||||
imx_register_uart_clocks(uart_clks);
|
||||
|
||||
return 0;
|
||||
|
||||
unregister_clks:
|
||||
imx_unregister_clocks(clks, ARRAY_SIZE(clks));
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct of_device_id imx8mn_clk_of_match[] = {
|
||||
{ .compatible = "fsl,imx8mn-ccm" },
|
||||
{ /* Sentinel */ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, imx8mn_clk_of_match);
|
||||
|
||||
static struct platform_driver imx8mn_clk_driver = {
|
||||
.probe = imx8mn_clocks_probe,
|
||||
.driver = {
|
||||
.name = "imx8mn-ccm",
|
||||
.of_match_table = of_match_ptr(imx8mn_clk_of_match),
|
||||
},
|
||||
};
|
||||
module_platform_driver(imx8mn_clk_driver);
|
||||
|
|
@ -41,34 +41,34 @@ static const char * const dram_pll_out_sels[] = {"dram_pll1_ref_sel", };
|
|||
|
||||
/* CCM ROOT */
|
||||
static const char * const imx8mq_a53_sels[] = {"osc_25m", "arm_pll_out", "sys2_pll_500m", "sys2_pll_1000m",
|
||||
"sys1_pll_800m", "sys1_pll_400m", "audio_pll1_out", "sys3_pll2_out", };
|
||||
"sys1_pll_800m", "sys1_pll_400m", "audio_pll1_out", "sys3_pll_out", };
|
||||
|
||||
static const char * const imx8mq_arm_m4_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_250m", "sys1_pll_266m",
|
||||
"sys1_pll_800m", "audio_pll1_out", "video_pll1_out", "sys3_pll2_out", };
|
||||
"sys1_pll_800m", "audio_pll1_out", "video_pll1_out", "sys3_pll_out", };
|
||||
|
||||
static const char * const imx8mq_vpu_sels[] = {"osc_25m", "arm_pll_out", "sys2_pll_500m", "sys2_pll_1000m",
|
||||
"sys1_pll_800m", "sys1_pll_400m", "audio_pll1_out", "vpu_pll_out", };
|
||||
|
||||
static const char * const imx8mq_gpu_core_sels[] = {"osc_25m", "gpu_pll_out", "sys1_pll_800m", "sys3_pll2_out",
|
||||
static const char * const imx8mq_gpu_core_sels[] = {"osc_25m", "gpu_pll_out", "sys1_pll_800m", "sys3_pll_out",
|
||||
"sys2_pll_1000m", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mq_gpu_shader_sels[] = {"osc_25m", "gpu_pll_out", "sys1_pll_800m", "sys3_pll2_out",
|
||||
static const char * const imx8mq_gpu_shader_sels[] = {"osc_25m", "gpu_pll_out", "sys1_pll_800m", "sys3_pll_out",
|
||||
"sys2_pll_1000m", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mq_main_axi_sels[] = {"osc_25m", "sys2_pll_333m", "sys1_pll_800m", "sys2_pll_250m",
|
||||
"sys2_pll_1000m", "audio_pll1_out", "video_pll1_out", "sys1_pll_100m",};
|
||||
|
||||
static const char * const imx8mq_enet_axi_sels[] = {"osc_25m", "sys1_pll_266m", "sys1_pll_800m", "sys2_pll_250m",
|
||||
"sys2_pll_200m", "audio_pll1_out", "video_pll1_out", "sys3_pll2_out", };
|
||||
"sys2_pll_200m", "audio_pll1_out", "video_pll1_out", "sys3_pll_out", };
|
||||
|
||||
static const char * const imx8mq_nand_usdhc_sels[] = {"osc_25m", "sys1_pll_266m", "sys1_pll_800m", "sys2_pll_200m",
|
||||
"sys1_pll_133m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll1_out", };
|
||||
"sys1_pll_133m", "sys3_pll_out", "sys2_pll_250m", "audio_pll1_out", };
|
||||
|
||||
static const char * const imx8mq_vpu_bus_sels[] = {"osc_25m", "sys1_pll_800m", "vpu_pll_out", "audio_pll2_out", "sys3_pll2_out", "sys2_pll_1000m", "sys2_pll_200m", "sys1_pll_100m", };
|
||||
static const char * const imx8mq_vpu_bus_sels[] = {"osc_25m", "sys1_pll_800m", "vpu_pll_out", "audio_pll2_out", "sys3_pll_out", "sys2_pll_1000m", "sys2_pll_200m", "sys1_pll_100m", };
|
||||
|
||||
static const char * const imx8mq_disp_axi_sels[] = {"osc_25m", "sys2_pll_125m", "sys1_pll_800m", "sys3_pll2_out", "sys1_pll_400m", "audio_pll2_out", "clk_ext1", "clk_ext4", };
|
||||
static const char * const imx8mq_disp_axi_sels[] = {"osc_25m", "sys2_pll_125m", "sys1_pll_800m", "sys3_pll_out", "sys1_pll_400m", "audio_pll2_out", "clk_ext1", "clk_ext4", };
|
||||
|
||||
static const char * const imx8mq_disp_apb_sels[] = {"osc_25m", "sys2_pll_125m", "sys1_pll_800m", "sys3_pll2_out",
|
||||
static const char * const imx8mq_disp_apb_sels[] = {"osc_25m", "sys2_pll_125m", "sys1_pll_800m", "sys3_pll_out",
|
||||
"sys1_pll_40m", "audio_pll2_out", "clk_ext1", "clk_ext3", };
|
||||
|
||||
static const char * const imx8mq_disp_rtrm_sels[] = {"osc_25m", "sys1_pll_800m", "sys2_pll_200m", "sys1_pll_400m",
|
||||
|
|
@ -77,53 +77,53 @@ static const char * const imx8mq_disp_rtrm_sels[] = {"osc_25m", "sys1_pll_800m",
|
|||
static const char * const imx8mq_usb_bus_sels[] = {"osc_25m", "sys2_pll_500m", "sys1_pll_800m", "sys2_pll_100m",
|
||||
"sys2_pll_200m", "clk_ext2", "clk_ext4", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mq_gpu_axi_sels[] = {"osc_25m", "sys1_pll_800m", "gpu_pll_out", "sys3_pll2_out", "sys2_pll_1000m",
|
||||
static const char * const imx8mq_gpu_axi_sels[] = {"osc_25m", "sys1_pll_800m", "gpu_pll_out", "sys3_pll_out", "sys2_pll_1000m",
|
||||
"audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mq_gpu_ahb_sels[] = {"osc_25m", "sys1_pll_800m", "gpu_pll_out", "sys3_pll2_out", "sys2_pll_1000m",
|
||||
static const char * const imx8mq_gpu_ahb_sels[] = {"osc_25m", "sys1_pll_800m", "gpu_pll_out", "sys3_pll_out", "sys2_pll_1000m",
|
||||
"audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mq_noc_sels[] = {"osc_25m", "sys1_pll_800m", "sys3_pll2_out", "sys2_pll_1000m", "sys2_pll_500m",
|
||||
static const char * const imx8mq_noc_sels[] = {"osc_25m", "sys1_pll_800m", "sys3_pll_out", "sys2_pll_1000m", "sys2_pll_500m",
|
||||
"audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mq_noc_apb_sels[] = {"osc_25m", "sys1_pll_400m", "sys3_pll2_out", "sys2_pll_333m", "sys2_pll_200m",
|
||||
static const char * const imx8mq_noc_apb_sels[] = {"osc_25m", "sys1_pll_400m", "sys3_pll_out", "sys2_pll_333m", "sys2_pll_200m",
|
||||
"sys1_pll_800m", "audio_pll1_out", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mq_ahb_sels[] = {"osc_25m", "sys1_pll_133m", "sys1_pll_800m", "sys1_pll_400m",
|
||||
"sys2_pll_125m", "sys3_pll2_out", "audio_pll1_out", "video_pll1_out", };
|
||||
"sys2_pll_125m", "sys3_pll_out", "audio_pll1_out", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mq_audio_ahb_sels[] = {"osc_25m", "sys2_pll_500m", "sys1_pll_800m", "sys2_pll_1000m",
|
||||
"sys2_pll_166m", "sys3_pll2_out", "audio_pll1_out", "video_pll1_out", };
|
||||
"sys2_pll_166m", "sys3_pll_out", "audio_pll1_out", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mq_dsi_ahb_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m",
|
||||
"sys2_pll_1000m", "sys3_pll2_out", "clk_ext3", "audio_pll2_out"};
|
||||
"sys2_pll_1000m", "sys3_pll_out", "clk_ext3", "audio_pll2_out"};
|
||||
|
||||
static const char * const imx8mq_dram_alt_sels[] = {"osc_25m", "sys1_pll_800m", "sys1_pll_100m", "sys2_pll_500m",
|
||||
"sys2_pll_250m", "sys1_pll_400m", "audio_pll1_out", "sys1_pll_266m", };
|
||||
|
||||
static const char * const imx8mq_dram_apb_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys1_pll_160m",
|
||||
"sys1_pll_800m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll2_out", };
|
||||
"sys1_pll_800m", "sys3_pll_out", "sys2_pll_250m", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mq_vpu_g1_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_100m", "sys2_pll_125m", "sys3_pll2_out", "audio_pll1_out", };
|
||||
static const char * const imx8mq_vpu_g1_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_100m", "sys2_pll_125m", "sys3_pll_out", "audio_pll1_out", };
|
||||
|
||||
static const char * const imx8mq_vpu_g2_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_100m", "sys2_pll_125m", "sys3_pll2_out", "audio_pll1_out", };
|
||||
static const char * const imx8mq_vpu_g2_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_100m", "sys2_pll_125m", "sys3_pll_out", "audio_pll1_out", };
|
||||
|
||||
static const char * const imx8mq_disp_dtrc_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_160m", "sys2_pll_100m", "sys3_pll2_out", "audio_pll2_out", };
|
||||
static const char * const imx8mq_disp_dtrc_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_160m", "sys2_pll_100m", "sys3_pll_out", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mq_disp_dc8000_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_160m", "sys2_pll_100m", "sys3_pll2_out", "audio_pll2_out", };
|
||||
static const char * const imx8mq_disp_dc8000_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_160m", "sys2_pll_100m", "sys3_pll_out", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mq_pcie1_ctrl_sels[] = {"osc_25m", "sys2_pll_250m", "sys2_pll_200m", "sys1_pll_266m",
|
||||
"sys1_pll_800m", "sys2_pll_500m", "sys2_pll_250m", "sys3_pll2_out", };
|
||||
"sys1_pll_800m", "sys2_pll_500m", "sys2_pll_250m", "sys3_pll_out", };
|
||||
|
||||
static const char * const imx8mq_pcie1_phy_sels[] = {"osc_25m", "sys2_pll_100m", "sys2_pll_500m", "clk_ext1", "clk_ext2",
|
||||
"clk_ext3", "clk_ext4", };
|
||||
|
||||
static const char * const imx8mq_pcie1_aux_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_500m", "sys3_pll2_out",
|
||||
static const char * const imx8mq_pcie1_aux_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_500m", "sys3_pll_out",
|
||||
"sys2_pll_100m", "sys1_pll_80m", "sys1_pll_160m", "sys1_pll_200m", };
|
||||
|
||||
static const char * const imx8mq_dc_pixel_sels[] = {"osc_25m", "video_pll1_out", "audio_pll2_out", "audio_pll1_out", "sys1_pll_800m", "sys2_pll_1000m", "sys3_pll2_out", "clk_ext4", };
|
||||
static const char * const imx8mq_dc_pixel_sels[] = {"osc_25m", "video_pll1_out", "audio_pll2_out", "audio_pll1_out", "sys1_pll_800m", "sys2_pll_1000m", "sys3_pll_out", "clk_ext4", };
|
||||
|
||||
static const char * const imx8mq_lcdif_pixel_sels[] = {"osc_25m", "video_pll1_out", "audio_pll2_out", "audio_pll1_out", "sys1_pll_800m", "sys2_pll_1000m", "sys3_pll2_out", "clk_ext4", };
|
||||
static const char * const imx8mq_lcdif_pixel_sels[] = {"osc_25m", "video_pll1_out", "audio_pll2_out", "audio_pll1_out", "sys1_pll_800m", "sys2_pll_1000m", "sys3_pll_out", "clk_ext4", };
|
||||
|
||||
static const char * const imx8mq_sai1_sels[] = {"osc_25m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext1", "clk_ext2", };
|
||||
|
||||
|
|
@ -151,40 +151,40 @@ static const char * const imx8mq_enet_phy_sels[] = {"osc_25m", "sys2_pll_50m", "
|
|||
"audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mq_nand_sels[] = {"osc_25m", "sys2_pll_500m", "audio_pll1_out", "sys1_pll_400m",
|
||||
"audio_pll2_out", "sys3_pll2_out", "sys2_pll_250m", "video_pll1_out", };
|
||||
"audio_pll2_out", "sys3_pll_out", "sys2_pll_250m", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mq_qspi_sels[] = {"osc_25m", "sys1_pll_400m", "sys1_pll_800m", "sys2_pll_500m",
|
||||
"audio_pll2_out", "sys1_pll_266m", "sys3_pll2_out", "sys1_pll_100m", };
|
||||
"audio_pll2_out", "sys1_pll_266m", "sys3_pll_out", "sys1_pll_100m", };
|
||||
|
||||
static const char * const imx8mq_usdhc1_sels[] = {"osc_25m", "sys1_pll_400m", "sys1_pll_800m", "sys2_pll_500m",
|
||||
"audio_pll2_out", "sys1_pll_266m", "sys3_pll2_out", "sys1_pll_100m", };
|
||||
"audio_pll2_out", "sys1_pll_266m", "sys3_pll_out", "sys1_pll_100m", };
|
||||
|
||||
static const char * const imx8mq_usdhc2_sels[] = {"osc_25m", "sys1_pll_400m", "sys1_pll_800m", "sys2_pll_500m",
|
||||
"audio_pll2_out", "sys1_pll_266m", "sys3_pll2_out", "sys1_pll_100m", };
|
||||
"audio_pll2_out", "sys1_pll_266m", "sys3_pll_out", "sys1_pll_100m", };
|
||||
|
||||
static const char * const imx8mq_i2c1_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll2_out", "audio_pll1_out",
|
||||
static const char * const imx8mq_i2c1_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll_out", "audio_pll1_out",
|
||||
"video_pll1_out", "audio_pll2_out", "sys1_pll_133m", };
|
||||
|
||||
static const char * const imx8mq_i2c2_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll2_out", "audio_pll1_out",
|
||||
static const char * const imx8mq_i2c2_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll_out", "audio_pll1_out",
|
||||
"video_pll1_out", "audio_pll2_out", "sys1_pll_133m", };
|
||||
|
||||
static const char * const imx8mq_i2c3_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll2_out", "audio_pll1_out",
|
||||
static const char * const imx8mq_i2c3_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll_out", "audio_pll1_out",
|
||||
"video_pll1_out", "audio_pll2_out", "sys1_pll_133m", };
|
||||
|
||||
static const char * const imx8mq_i2c4_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll2_out", "audio_pll1_out",
|
||||
static const char * const imx8mq_i2c4_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll_out", "audio_pll1_out",
|
||||
"video_pll1_out", "audio_pll2_out", "sys1_pll_133m", };
|
||||
|
||||
static const char * const imx8mq_uart1_sels[] = {"osc_25m", "sys1_pll_80m", "sys2_pll_200m", "sys2_pll_100m",
|
||||
"sys3_pll2_out", "clk_ext2", "clk_ext4", "audio_pll2_out", };
|
||||
"sys3_pll_out", "clk_ext2", "clk_ext4", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mq_uart2_sels[] = {"osc_25m", "sys1_pll_80m", "sys2_pll_200m", "sys2_pll_100m",
|
||||
"sys3_pll2_out", "clk_ext2", "clk_ext3", "audio_pll2_out", };
|
||||
"sys3_pll_out", "clk_ext2", "clk_ext3", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mq_uart3_sels[] = {"osc_25m", "sys1_pll_80m", "sys2_pll_200m", "sys2_pll_100m",
|
||||
"sys3_pll2_out", "clk_ext2", "clk_ext4", "audio_pll2_out", };
|
||||
"sys3_pll_out", "clk_ext2", "clk_ext4", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mq_uart4_sels[] = {"osc_25m", "sys1_pll_80m", "sys2_pll_200m", "sys2_pll_100m",
|
||||
"sys3_pll2_out", "clk_ext2", "clk_ext3", "audio_pll2_out", };
|
||||
"sys3_pll_out", "clk_ext2", "clk_ext3", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mq_usb_core_sels[] = {"osc_25m", "sys1_pll_100m", "sys1_pll_40m", "sys2_pll_100m",
|
||||
"sys2_pll_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", };
|
||||
|
|
@ -196,79 +196,79 @@ static const char * const imx8mq_gic_sels[] = {"osc_25m", "sys2_pll_200m", "sys1
|
|||
"sys2_pll_200m", "clk_ext2", "clk_ext3", "audio_pll2_out" };
|
||||
|
||||
static const char * const imx8mq_ecspi1_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys1_pll_160m",
|
||||
"sys1_pll_800m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll2_out", };
|
||||
"sys1_pll_800m", "sys3_pll_out", "sys2_pll_250m", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mq_ecspi2_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys1_pll_160m",
|
||||
"sys1_pll_800m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll2_out", };
|
||||
"sys1_pll_800m", "sys3_pll_out", "sys2_pll_250m", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mq_pwm1_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_160m", "sys1_pll_40m",
|
||||
"sys3_pll2_out", "clk_ext1", "sys1_pll_80m", "video_pll1_out", };
|
||||
"sys3_pll_out", "clk_ext1", "sys1_pll_80m", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mq_pwm2_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_160m", "sys1_pll_40m",
|
||||
"sys3_pll2_out", "clk_ext1", "sys1_pll_80m", "video_pll1_out", };
|
||||
"sys3_pll_out", "clk_ext1", "sys1_pll_80m", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mq_pwm3_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_160m", "sys1_pll_40m",
|
||||
"sys3_pll2_out", "clk_ext2", "sys1_pll_80m", "video_pll1_out", };
|
||||
"sys3_pll_out", "clk_ext2", "sys1_pll_80m", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mq_pwm4_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_160m", "sys1_pll_40m",
|
||||
"sys3_pll2_out", "clk_ext2", "sys1_pll_80m", "video_pll1_out", };
|
||||
"sys3_pll_out", "clk_ext2", "sys1_pll_80m", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mq_gpt1_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_400m", "sys1_pll_40m",
|
||||
"sys1_pll_80m", "audio_pll1_out", "clk_ext1", };
|
||||
|
||||
static const char * const imx8mq_wdog_sels[] = {"osc_25m", "sys1_pll_133m", "sys1_pll_160m", "vpu_pll_out",
|
||||
"sys2_pll_125m", "sys3_pll2_out", "sys1_pll_80m", "sys2_pll_166m", };
|
||||
"sys2_pll_125m", "sys3_pll_out", "sys1_pll_80m", "sys2_pll_166m", };
|
||||
|
||||
static const char * const imx8mq_wrclk_sels[] = {"osc_25m", "sys1_pll_40m", "vpu_pll_out", "sys3_pll2_out", "sys2_pll_200m",
|
||||
static const char * const imx8mq_wrclk_sels[] = {"osc_25m", "sys1_pll_40m", "vpu_pll_out", "sys3_pll_out", "sys2_pll_200m",
|
||||
"sys1_pll_266m", "sys2_pll_500m", "sys1_pll_100m", };
|
||||
|
||||
static const char * const imx8mq_dsi_core_sels[] = {"osc_25m", "sys1_pll_266m", "sys2_pll_250m", "sys1_pll_800m",
|
||||
"sys2_pll_1000m", "sys3_pll2_out", "audio_pll2_out", "video_pll1_out", };
|
||||
"sys2_pll_1000m", "sys3_pll_out", "audio_pll2_out", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mq_dsi_phy_sels[] = {"osc_25m", "sys2_pll_125m", "sys2_pll_100m", "sys1_pll_800m",
|
||||
"sys2_pll_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mq_dsi_dbi_sels[] = {"osc_25m", "sys1_pll_266m", "sys2_pll_100m", "sys1_pll_800m",
|
||||
"sys2_pll_1000m", "sys3_pll2_out", "audio_pll2_out", "video_pll1_out", };
|
||||
"sys2_pll_1000m", "sys3_pll_out", "audio_pll2_out", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mq_dsi_esc_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m",
|
||||
"sys2_pll_1000m", "sys3_pll2_out", "clk_ext3", "audio_pll2_out", };
|
||||
"sys2_pll_1000m", "sys3_pll_out", "clk_ext3", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mq_csi1_core_sels[] = {"osc_25m", "sys1_pll_266m", "sys2_pll_250m", "sys1_pll_800m",
|
||||
"sys2_pll_1000m", "sys3_pll2_out", "audio_pll2_out", "video_pll1_out", };
|
||||
"sys2_pll_1000m", "sys3_pll_out", "audio_pll2_out", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mq_csi1_phy_sels[] = {"osc_25m", "sys2_pll_125m", "sys2_pll_100m", "sys1_pll_800m",
|
||||
"sys2_pll_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mq_csi1_esc_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m",
|
||||
"sys2_pll_1000m", "sys3_pll2_out", "clk_ext3", "audio_pll2_out", };
|
||||
"sys2_pll_1000m", "sys3_pll_out", "clk_ext3", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mq_csi2_core_sels[] = {"osc_25m", "sys1_pll_266m", "sys2_pll_250m", "sys1_pll_800m",
|
||||
"sys2_pll_1000m", "sys3_pll2_out", "audio_pll2_out", "video_pll1_out", };
|
||||
"sys2_pll_1000m", "sys3_pll_out", "audio_pll2_out", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mq_csi2_phy_sels[] = {"osc_25m", "sys2_pll_125m", "sys2_pll_100m", "sys1_pll_800m",
|
||||
"sys2_pll_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mq_csi2_esc_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m",
|
||||
"sys2_pll_1000m", "sys3_pll2_out", "clk_ext3", "audio_pll2_out", };
|
||||
"sys2_pll_1000m", "sys3_pll_out", "clk_ext3", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mq_pcie2_ctrl_sels[] = {"osc_25m", "sys2_pll_250m", "sys2_pll_200m", "sys1_pll_266m",
|
||||
"sys1_pll_800m", "sys2_pll_500m", "sys2_pll_333m", "sys3_pll2_out", };
|
||||
"sys1_pll_800m", "sys2_pll_500m", "sys2_pll_333m", "sys3_pll_out", };
|
||||
|
||||
static const char * const imx8mq_pcie2_phy_sels[] = {"osc_25m", "sys2_pll_100m", "sys2_pll_500m", "clk_ext1",
|
||||
"clk_ext2", "clk_ext3", "clk_ext4", "sys1_pll_400m", };
|
||||
|
||||
static const char * const imx8mq_pcie2_aux_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_50m", "sys3_pll2_out",
|
||||
static const char * const imx8mq_pcie2_aux_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_50m", "sys3_pll_out",
|
||||
"sys2_pll_100m", "sys1_pll_80m", "sys1_pll_160m", "sys1_pll_200m", };
|
||||
|
||||
static const char * const imx8mq_ecspi3_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys1_pll_160m",
|
||||
"sys1_pll_800m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll2_out", };
|
||||
"sys1_pll_800m", "sys3_pll_out", "sys2_pll_250m", "audio_pll2_out", };
|
||||
static const char * const imx8mq_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", };
|
||||
|
||||
static const char * const imx8mq_clko1_sels[] = {"osc_25m", "sys1_pll_800m", "osc_27m", "sys1_pll_200m",
|
||||
"audio_pll2_out", "sys2_pll_500m", "vpu_pll_out", "sys1_pll_80m", };
|
||||
static const char * const imx8mq_clko2_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_400m", "sys2_pll_166m",
|
||||
"sys3_pll2_out", "audio_pll1_out", "video_pll1_out", "ckil", };
|
||||
"sys3_pll_out", "audio_pll1_out", "video_pll1_out", "ckil", };
|
||||
|
||||
static struct clk_onecell_data clk_data;
|
||||
|
||||
|
|
@ -406,7 +406,8 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
|
|||
clks[IMX8MQ_CLK_NOC_APB] = imx8m_clk_composite_critical("noc_apb", imx8mq_noc_apb_sels, base + 0x8d80);
|
||||
|
||||
/* AHB */
|
||||
clks[IMX8MQ_CLK_AHB] = imx8m_clk_composite("ahb", imx8mq_ahb_sels, base + 0x9000);
|
||||
/* AHB clock is used by the AHB bus therefore marked as critical */
|
||||
clks[IMX8MQ_CLK_AHB] = imx8m_clk_composite_critical("ahb", imx8mq_ahb_sels, base + 0x9000);
|
||||
clks[IMX8MQ_CLK_AUDIO_AHB] = imx8m_clk_composite("audio_ahb", imx8mq_audio_ahb_sels, base + 0x9100);
|
||||
|
||||
/* IPG */
|
||||
|
|
@ -523,8 +524,8 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
|
|||
clks[IMX8MQ_CLK_UART2_ROOT] = imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0);
|
||||
clks[IMX8MQ_CLK_UART3_ROOT] = imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0);
|
||||
clks[IMX8MQ_CLK_UART4_ROOT] = imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0);
|
||||
clks[IMX8MQ_CLK_USB1_CTRL_ROOT] = imx_clk_gate4("usb1_ctrl_root_clk", "usb_core_ref", base + 0x44d0, 0);
|
||||
clks[IMX8MQ_CLK_USB2_CTRL_ROOT] = imx_clk_gate4("usb2_ctrl_root_clk", "usb_core_ref", base + 0x44e0, 0);
|
||||
clks[IMX8MQ_CLK_USB1_CTRL_ROOT] = imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0);
|
||||
clks[IMX8MQ_CLK_USB2_CTRL_ROOT] = imx_clk_gate4("usb2_ctrl_root_clk", "usb_bus", base + 0x44e0, 0);
|
||||
clks[IMX8MQ_CLK_USB1_PHY_ROOT] = imx_clk_gate4("usb1_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0);
|
||||
clks[IMX8MQ_CLK_USB2_PHY_ROOT] = imx_clk_gate4("usb2_phy_root_clk", "usb_phy_ref", base + 0x4500, 0);
|
||||
clks[IMX8MQ_CLK_USDHC1_ROOT] = imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0);
|
||||
|
|
@ -539,7 +540,7 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
|
|||
clks[IMX8MQ_CLK_DISP_AXI_ROOT] = imx_clk_gate2_shared2("disp_axi_root_clk", "disp_axi", base + 0x45d0, 0, &share_count_dcss);
|
||||
clks[IMX8MQ_CLK_DISP_APB_ROOT] = imx_clk_gate2_shared2("disp_apb_root_clk", "disp_apb", base + 0x45d0, 0, &share_count_dcss);
|
||||
clks[IMX8MQ_CLK_DISP_RTRM_ROOT] = imx_clk_gate2_shared2("disp_rtrm_root_clk", "disp_rtrm", base + 0x45d0, 0, &share_count_dcss);
|
||||
clks[IMX8MQ_CLK_TMU_ROOT] = imx_clk_gate4_flags("tmu_root_clk", "ipg_root", base + 0x4620, 0, CLK_IS_CRITICAL);
|
||||
clks[IMX8MQ_CLK_TMU_ROOT] = imx_clk_gate4("tmu_root_clk", "ipg_root", base + 0x4620, 0);
|
||||
clks[IMX8MQ_CLK_VPU_DEC_ROOT] = imx_clk_gate2_flags("vpu_dec_root_clk", "vpu_bus", base + 0x4630, 0, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE);
|
||||
clks[IMX8MQ_CLK_CSI1_ROOT] = imx_clk_gate4("csi1_root_clk", "csi1_core", base + 0x4650, 0);
|
||||
clks[IMX8MQ_CLK_CSI2_ROOT] = imx_clk_gate4("csi2_root_clk", "csi2_core", base + 0x4660, 0);
|
||||
|
|
@ -561,10 +562,18 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
|
|||
clk_data.clk_num = ARRAY_SIZE(clks);
|
||||
|
||||
err = of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
WARN_ON(err);
|
||||
if (err < 0) {
|
||||
dev_err(dev, "failed to register clks for i.MX8MQ\n");
|
||||
goto unregister_clks;
|
||||
}
|
||||
|
||||
imx_register_uart_clocks(uart_clks);
|
||||
|
||||
return 0;
|
||||
|
||||
unregister_clks:
|
||||
imx_unregister_clocks(clks, ARRAY_SIZE(clks));
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -72,6 +72,11 @@ static const struct imx8qxp_lpcg_data imx8qxp_lpcg_adma[] = {
|
|||
{ IMX_ADMA_LPCG_I2C2_CLK, "i2c2_lpcg_clk", "i2c2_clk", 0, ADMA_LPI2C_2_LPCG, 0, 0, },
|
||||
{ IMX_ADMA_LPCG_I2C3_IPG_CLK, "i2c3_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPI2C_3_LPCG, 16, 0, },
|
||||
{ IMX_ADMA_LPCG_I2C3_CLK, "i2c3_lpcg_clk", "i2c3_clk", 0, ADMA_LPI2C_3_LPCG, 0, 0, },
|
||||
|
||||
{ IMX_ADMA_LPCG_DSP_CORE_CLK, "dsp_lpcg_core_clk", "dma_ipg_clk_root", 0, ADMA_HIFI_LPCG, 28, 0, },
|
||||
{ IMX_ADMA_LPCG_DSP_IPG_CLK, "dsp_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_HIFI_LPCG, 20, 0, },
|
||||
{ IMX_ADMA_LPCG_DSP_ADB_CLK, "dsp_lpcg_adb_clk", "dma_ipg_clk_root", 0, ADMA_HIFI_LPCG, 16, 0, },
|
||||
{ IMX_ADMA_LPCG_OCRAM_IPG_CLK, "ocram_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_OCRAM_LPCG, 16, 0, },
|
||||
};
|
||||
|
||||
static const struct imx8qxp_ss_lpcg imx8qxp_ss_adma = {
|
||||
|
|
|
|||
|
|
@ -191,6 +191,10 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate,
|
|||
tmp &= ~RST_MASK;
|
||||
writel_relaxed(tmp, pll->base);
|
||||
|
||||
/* Enable BYPASS */
|
||||
tmp |= BYPASS_MASK;
|
||||
writel(tmp, pll->base);
|
||||
|
||||
div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
|
||||
(rate->sdiv << SDIV_SHIFT);
|
||||
writel_relaxed(div_val, pll->base + 0x4);
|
||||
|
|
@ -250,6 +254,10 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate,
|
|||
tmp &= ~RST_MASK;
|
||||
writel_relaxed(tmp, pll->base);
|
||||
|
||||
/* Enable BYPASS */
|
||||
tmp |= BYPASS_MASK;
|
||||
writel_relaxed(tmp, pll->base);
|
||||
|
||||
div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
|
||||
(rate->sdiv << SDIV_SHIFT);
|
||||
writel_relaxed(div_val, pll->base + 0x4);
|
||||
|
|
@ -283,16 +291,28 @@ static int clk_pll14xx_prepare(struct clk_hw *hw)
|
|||
{
|
||||
struct clk_pll14xx *pll = to_clk_pll14xx(hw);
|
||||
u32 val;
|
||||
int ret;
|
||||
|
||||
/*
|
||||
* RESETB = 1 from 0, PLL starts its normal
|
||||
* operation after lock time
|
||||
*/
|
||||
val = readl_relaxed(pll->base + GNRL_CTL);
|
||||
if (val & RST_MASK)
|
||||
return 0;
|
||||
val |= BYPASS_MASK;
|
||||
writel_relaxed(val, pll->base + GNRL_CTL);
|
||||
val |= RST_MASK;
|
||||
writel_relaxed(val, pll->base + GNRL_CTL);
|
||||
|
||||
return clk_pll14xx_wait_lock(pll);
|
||||
ret = clk_pll14xx_wait_lock(pll);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
val &= ~BYPASS_MASK;
|
||||
writel_relaxed(val, pll->base + GNRL_CTL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int clk_pll14xx_is_prepared(struct clk_hw *hw)
|
||||
|
|
@ -348,6 +368,7 @@ struct clk *imx_clk_pll14xx(const char *name, const char *parent_name,
|
|||
struct clk_pll14xx *pll;
|
||||
struct clk *clk;
|
||||
struct clk_init_data init;
|
||||
u32 val;
|
||||
|
||||
pll = kzalloc(sizeof(*pll), GFP_KERNEL);
|
||||
if (!pll)
|
||||
|
|
@ -379,6 +400,10 @@ struct clk *imx_clk_pll14xx(const char *name, const char *parent_name,
|
|||
pll->rate_table = pll_clk->rate_table;
|
||||
pll->rate_count = pll_clk->rate_count;
|
||||
|
||||
val = readl_relaxed(pll->base + GNRL_CTL);
|
||||
val &= ~BYPASS_MASK;
|
||||
writel_relaxed(val, pll->base + GNRL_CTL);
|
||||
|
||||
clk = clk_register(NULL, &pll->hw);
|
||||
if (IS_ERR(clk)) {
|
||||
pr_err("%s: failed to register pll %s %lu\n",
|
||||
|
|
|
|||
|
|
@ -14,6 +14,14 @@
|
|||
|
||||
DEFINE_SPINLOCK(imx_ccm_lock);
|
||||
|
||||
void imx_unregister_clocks(struct clk *clks[], unsigned int count)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < count; i++)
|
||||
clk_unregister(clks[i]);
|
||||
}
|
||||
|
||||
void __init imx_mmdc_mask_handshake(void __iomem *ccm_base,
|
||||
unsigned int chn)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -10,8 +10,8 @@ extern spinlock_t imx_ccm_lock;
|
|||
void imx_check_clocks(struct clk *clks[], unsigned int count);
|
||||
void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count);
|
||||
void imx_register_uart_clocks(struct clk ** const clks[]);
|
||||
void imx_register_uart_clocks_hws(struct clk_hw ** const hws[]);
|
||||
void imx_mmdc_mask_handshake(void __iomem *ccm_base, unsigned int chn);
|
||||
void imx_unregister_clocks(struct clk *clks[], unsigned int count);
|
||||
|
||||
extern void imx_cscmr1_fixup(u32 *val);
|
||||
|
||||
|
|
@ -50,12 +50,6 @@ struct imx_pll14xx_clk {
|
|||
int flags;
|
||||
};
|
||||
|
||||
#define imx_clk_busy_divider(name, parent_name, reg, shift, width, busy_reg, busy_shift) \
|
||||
imx_clk_hw_busy_divider(name, parent_name, reg, shift, width, busy_reg, busy_shift)->clk
|
||||
|
||||
#define imx_clk_busy_mux(name, reg, shift, width, busy_reg, busy_shift, parent_names, num_parents) \
|
||||
imx_clk_hw_busy_mux(name, reg, shift, width, busy_reg, busy_shift, parent_names, num_parents)->clk
|
||||
|
||||
#define imx_clk_cpu(name, parent_name, div, mux, pll, step) \
|
||||
imx_clk_hw_cpu(name, parent_name, div, mux, pll, step)->clk
|
||||
|
||||
|
|
@ -73,15 +67,6 @@ struct imx_pll14xx_clk {
|
|||
#define imx_clk_gate_exclusive(name, parent, reg, shift, exclusive_mask) \
|
||||
imx_clk_hw_gate_exclusive(name, parent, reg, shift, exclusive_mask)->clk
|
||||
|
||||
#define imx_clk_fixup_divider(name, parent, reg, shift, width, fixup) \
|
||||
imx_clk_hw_fixup_divider(name, parent, reg, shift, width, fixup)->clk
|
||||
|
||||
#define imx_clk_fixup_mux(name, reg, shift, width, parents, num_parents, fixup) \
|
||||
imx_clk_hw_fixup_mux(name, reg, shift, width, parents, num_parents, fixup)->clk
|
||||
|
||||
#define imx_clk_mux_ldb(name, reg, shift, width, parents, num_parents) \
|
||||
imx_clk_hw_mux_ldb(name, reg, shift, width, parents, num_parents)->clk
|
||||
|
||||
#define imx_clk_fixed_factor(name, parent, mult, div) \
|
||||
imx_clk_hw_fixed_factor(name, parent, mult, div)->clk
|
||||
|
||||
|
|
@ -91,21 +76,12 @@ struct imx_pll14xx_clk {
|
|||
#define imx_clk_gate_dis(name, parent, reg, shift) \
|
||||
imx_clk_hw_gate_dis(name, parent, reg, shift)->clk
|
||||
|
||||
#define imx_clk_gate_dis_flags(name, parent, reg, shift, flags) \
|
||||
imx_clk_hw_gate_dis_flags(name, parent, reg, shift, flags)->clk
|
||||
|
||||
#define imx_clk_gate_flags(name, parent, reg, shift, flags) \
|
||||
imx_clk_hw_gate_flags(name, parent, reg, shift, flags)->clk
|
||||
|
||||
#define imx_clk_gate2(name, parent, reg, shift) \
|
||||
imx_clk_hw_gate2(name, parent, reg, shift)->clk
|
||||
|
||||
#define imx_clk_gate2_flags(name, parent, reg, shift, flags) \
|
||||
imx_clk_hw_gate2_flags(name, parent, reg, shift, flags)->clk
|
||||
|
||||
#define imx_clk_gate2_shared(name, parent, reg, shift, share_count) \
|
||||
imx_clk_hw_gate2_shared(name, parent, reg, shift, share_count)->clk
|
||||
|
||||
#define imx_clk_gate2_shared2(name, parent, reg, shift, share_count) \
|
||||
imx_clk_hw_gate2_shared2(name, parent, reg, shift, share_count)->clk
|
||||
|
||||
|
|
@ -153,6 +129,23 @@ enum imx_pllv3_type {
|
|||
struct clk_hw *imx_clk_hw_pllv3(enum imx_pllv3_type type, const char *name,
|
||||
const char *parent_name, void __iomem *base, u32 div_mask);
|
||||
|
||||
#define PLL_1416X_RATE(_rate, _m, _p, _s) \
|
||||
{ \
|
||||
.rate = (_rate), \
|
||||
.mdiv = (_m), \
|
||||
.pdiv = (_p), \
|
||||
.sdiv = (_s), \
|
||||
}
|
||||
|
||||
#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
|
||||
{ \
|
||||
.rate = (_rate), \
|
||||
.mdiv = (_m), \
|
||||
.pdiv = (_p), \
|
||||
.sdiv = (_s), \
|
||||
.kdiv = (_k), \
|
||||
}
|
||||
|
||||
struct clk_hw *imx_clk_pllv4(const char *name, const char *parent_name,
|
||||
void __iomem *base);
|
||||
|
||||
|
|
|
|||
|
|
@ -1053,15 +1053,18 @@ static int axg_audio_clkc_probe(struct platform_device *pdev)
|
|||
|
||||
/* Take care to skip the registered input clocks */
|
||||
for (i = AUD_CLKID_DDR_ARB; i < data->hw_onecell_data->num; i++) {
|
||||
const char *name;
|
||||
|
||||
hw = data->hw_onecell_data->hws[i];
|
||||
/* array might be sparse */
|
||||
if (!hw)
|
||||
continue;
|
||||
|
||||
name = hw->init->name;
|
||||
|
||||
ret = devm_clk_hw_register(dev, hw);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to register clock %s\n",
|
||||
hw->init->name);
|
||||
dev_err(dev, "failed to register clock %s\n", name);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1105,8 +1105,6 @@ static int clk_rcg2_enable_dfs(const struct clk_rcg_dfs_data *data,
|
|||
|
||||
rcg->freq_tbl = NULL;
|
||||
|
||||
pr_debug("DFS registered for clk %s\n", init->name);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -1117,12 +1115,8 @@ int qcom_cc_register_rcg_dfs(struct regmap *regmap,
|
|||
|
||||
for (i = 0; i < len; i++) {
|
||||
ret = clk_rcg2_enable_dfs(&rcgs[i], regmap);
|
||||
if (ret) {
|
||||
const char *name = rcgs[i].init->name;
|
||||
|
||||
pr_err("DFS register failed for clk %s\n", name);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -429,6 +429,7 @@ static int clk_rpmh_probe(struct platform_device *pdev)
|
|||
hw_clks = desc->clks;
|
||||
|
||||
for (i = 0; i < desc->num_clks; i++) {
|
||||
const char *name = hw_clks[i]->init->name;
|
||||
u32 res_addr;
|
||||
size_t aux_data_len;
|
||||
const struct bcm_db *data;
|
||||
|
|
@ -459,8 +460,7 @@ static int clk_rpmh_probe(struct platform_device *pdev)
|
|||
|
||||
ret = devm_clk_hw_register(&pdev->dev, hw_clks[i]);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "failed to register %s\n",
|
||||
hw_clks[i]->init->name);
|
||||
dev_err(&pdev->dev, "failed to register %s\n", name);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -297,9 +297,10 @@ static u8 dmn_clk_get_parent(struct clk_hw *hw)
|
|||
{
|
||||
struct clk_dmn *clk = to_dmnclk(hw);
|
||||
u32 cfg = clkc_readl(clk->regofs);
|
||||
const char *name = clk_hw_get_name(hw);
|
||||
|
||||
/* parent of io domain can only be pll3 */
|
||||
if (strcmp(hw->init->name, "io") == 0)
|
||||
if (strcmp(name, "io") == 0)
|
||||
return 4;
|
||||
|
||||
WARN_ON((cfg & (BIT(3) - 1)) > 4);
|
||||
|
|
@ -311,9 +312,10 @@ static int dmn_clk_set_parent(struct clk_hw *hw, u8 parent)
|
|||
{
|
||||
struct clk_dmn *clk = to_dmnclk(hw);
|
||||
u32 cfg = clkc_readl(clk->regofs);
|
||||
const char *name = clk_hw_get_name(hw);
|
||||
|
||||
/* parent of io domain can only be pll3 */
|
||||
if (strcmp(hw->init->name, "io") == 0)
|
||||
if (strcmp(name, "io") == 0)
|
||||
return -EINVAL;
|
||||
|
||||
cfg &= ~(BIT(3) - 1);
|
||||
|
|
@ -353,7 +355,8 @@ static long dmn_clk_round_rate(struct clk_hw *hw, unsigned long rate,
|
|||
{
|
||||
unsigned long fin;
|
||||
unsigned ratio, wait, hold;
|
||||
unsigned bits = (strcmp(hw->init->name, "mem") == 0) ? 3 : 4;
|
||||
const char *name = clk_hw_get_name(hw);
|
||||
unsigned bits = (strcmp(name, "mem") == 0) ? 3 : 4;
|
||||
|
||||
fin = *parent_rate;
|
||||
ratio = fin / rate;
|
||||
|
|
@ -375,7 +378,8 @@ static int dmn_clk_set_rate(struct clk_hw *hw, unsigned long rate,
|
|||
struct clk_dmn *clk = to_dmnclk(hw);
|
||||
unsigned long fin;
|
||||
unsigned ratio, wait, hold, reg;
|
||||
unsigned bits = (strcmp(hw->init->name, "mem") == 0) ? 3 : 4;
|
||||
const char *name = clk_hw_get_name(hw);
|
||||
unsigned bits = (strcmp(name, "mem") == 0) ? 3 : 4;
|
||||
|
||||
fin = parent_rate;
|
||||
ratio = fin / rate;
|
||||
|
|
|
|||
|
|
@ -30,22 +30,23 @@ static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
|
|||
{
|
||||
u32 l4_src;
|
||||
u32 perpll_src;
|
||||
const char *name = clk_hw_get_name(hwclk);
|
||||
|
||||
if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) {
|
||||
if (streq(name, SOCFPGA_L4_MP_CLK)) {
|
||||
l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
|
||||
return l4_src &= 0x1;
|
||||
}
|
||||
if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) {
|
||||
if (streq(name, SOCFPGA_L4_SP_CLK)) {
|
||||
l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
|
||||
return !!(l4_src & 2);
|
||||
}
|
||||
|
||||
perpll_src = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
|
||||
if (streq(hwclk->init->name, SOCFPGA_MMC_CLK))
|
||||
if (streq(name, SOCFPGA_MMC_CLK))
|
||||
return perpll_src &= 0x3;
|
||||
if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) ||
|
||||
streq(hwclk->init->name, SOCFPGA_NAND_X_CLK))
|
||||
return (perpll_src >> 2) & 3;
|
||||
if (streq(name, SOCFPGA_NAND_CLK) ||
|
||||
streq(name, SOCFPGA_NAND_X_CLK))
|
||||
return (perpll_src >> 2) & 3;
|
||||
|
||||
/* QSPI clock */
|
||||
return (perpll_src >> 4) & 3;
|
||||
|
|
@ -55,24 +56,25 @@ static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
|
|||
static int socfpga_clk_set_parent(struct clk_hw *hwclk, u8 parent)
|
||||
{
|
||||
u32 src_reg;
|
||||
const char *name = clk_hw_get_name(hwclk);
|
||||
|
||||
if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) {
|
||||
if (streq(name, SOCFPGA_L4_MP_CLK)) {
|
||||
src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
|
||||
src_reg &= ~0x1;
|
||||
src_reg |= parent;
|
||||
writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
|
||||
} else if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) {
|
||||
} else if (streq(name, SOCFPGA_L4_SP_CLK)) {
|
||||
src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
|
||||
src_reg &= ~0x2;
|
||||
src_reg |= (parent << 1);
|
||||
writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
|
||||
} else {
|
||||
src_reg = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
|
||||
if (streq(hwclk->init->name, SOCFPGA_MMC_CLK)) {
|
||||
if (streq(name, SOCFPGA_MMC_CLK)) {
|
||||
src_reg &= ~0x3;
|
||||
src_reg |= parent;
|
||||
} else if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) ||
|
||||
streq(hwclk->init->name, SOCFPGA_NAND_X_CLK)) {
|
||||
} else if (streq(name, SOCFPGA_NAND_CLK) ||
|
||||
streq(name, SOCFPGA_NAND_X_CLK)) {
|
||||
src_reg &= ~0xC;
|
||||
src_reg |= (parent << 2);
|
||||
} else {/* QSPI clock */
|
||||
|
|
|
|||
|
|
@ -40,11 +40,12 @@ static u8 clk_periclk_get_parent(struct clk_hw *hwclk)
|
|||
{
|
||||
struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(hwclk);
|
||||
u32 clk_src;
|
||||
const char *name = clk_hw_get_name(hwclk);
|
||||
|
||||
clk_src = readl(socfpgaclk->hw.reg);
|
||||
if (streq(hwclk->init->name, SOCFPGA_MPU_FREE_CLK) ||
|
||||
streq(hwclk->init->name, SOCFPGA_NOC_FREE_CLK) ||
|
||||
streq(hwclk->init->name, SOCFPGA_SDMMC_FREE_CLK))
|
||||
if (streq(name, SOCFPGA_MPU_FREE_CLK) ||
|
||||
streq(name, SOCFPGA_NOC_FREE_CLK) ||
|
||||
streq(name, SOCFPGA_SDMMC_FREE_CLK))
|
||||
return (clk_src >> CLK_MGR_FREE_SHIFT) &
|
||||
CLK_MGR_FREE_MASK;
|
||||
else
|
||||
|
|
|
|||
|
|
@ -76,16 +76,17 @@ int sprd_clk_probe(struct device *dev, struct clk_hw_onecell_data *clkhw)
|
|||
struct clk_hw *hw;
|
||||
|
||||
for (i = 0; i < clkhw->num; i++) {
|
||||
const char *name;
|
||||
|
||||
hw = clkhw->hws[i];
|
||||
|
||||
if (!hw)
|
||||
continue;
|
||||
|
||||
name = hw->init->name;
|
||||
ret = devm_clk_hw_register(dev, hw);
|
||||
if (ret) {
|
||||
dev_err(dev, "Couldn't register clock %d - %s\n",
|
||||
i, hw->init->name);
|
||||
i, name);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -505,7 +505,7 @@ static struct ccu_div i2s3_clk = {
|
|||
.hw.init = CLK_HW_INIT_PARENTS("i2s3",
|
||||
audio_parents,
|
||||
&ccu_div_ops,
|
||||
0),
|
||||
CLK_SET_RATE_PARENT),
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -518,7 +518,7 @@ static struct ccu_div i2s0_clk = {
|
|||
.hw.init = CLK_HW_INIT_PARENTS("i2s0",
|
||||
audio_parents,
|
||||
&ccu_div_ops,
|
||||
0),
|
||||
CLK_SET_RATE_PARENT),
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -531,7 +531,7 @@ static struct ccu_div i2s1_clk = {
|
|||
.hw.init = CLK_HW_INIT_PARENTS("i2s1",
|
||||
audio_parents,
|
||||
&ccu_div_ops,
|
||||
0),
|
||||
CLK_SET_RATE_PARENT),
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -544,7 +544,7 @@ static struct ccu_div i2s2_clk = {
|
|||
.hw.init = CLK_HW_INIT_PARENTS("i2s2",
|
||||
audio_parents,
|
||||
&ccu_div_ops,
|
||||
0),
|
||||
CLK_SET_RATE_PARENT),
|
||||
},
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -77,7 +77,7 @@ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
|
|||
BIT(28), /* lock */
|
||||
0);
|
||||
|
||||
static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr",
|
||||
static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
|
||||
"osc24M", 0x020,
|
||||
8, 5, /* N */
|
||||
4, 2, /* K */
|
||||
|
|
@ -116,6 +116,14 @@ static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph1_clk, "pll-periph1",
|
|||
2, /* post-div */
|
||||
0);
|
||||
|
||||
static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1",
|
||||
"osc24M", 0x04c,
|
||||
8, 7, /* N */
|
||||
0, 2, /* M */
|
||||
BIT(31), /* gate */
|
||||
BIT(28), /* lock */
|
||||
0);
|
||||
|
||||
static const char * const cpu_parents[] = { "osc32k", "osc24M",
|
||||
"pll-cpu", "pll-cpu" };
|
||||
static SUNXI_CCU_MUX(cpu_clk, "cpu", cpu_parents,
|
||||
|
|
@ -227,6 +235,8 @@ static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1",
|
|||
0x068, BIT(0), 0);
|
||||
static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1",
|
||||
0x068, BIT(5), 0);
|
||||
static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",
|
||||
0x068, BIT(12), 0);
|
||||
|
||||
static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
|
||||
0x06c, BIT(0), 0);
|
||||
|
|
@ -298,12 +308,18 @@ static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
|
|||
BIT(31), /* gate */
|
||||
0);
|
||||
|
||||
static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
|
||||
"pll-audio-2x", "pll-audio" };
|
||||
static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,
|
||||
0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
|
||||
|
||||
static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
|
||||
0x0cc, BIT(8), 0);
|
||||
static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc24M",
|
||||
0x0cc, BIT(16), 0);
|
||||
|
||||
static const char * const dram_parents[] = { "pll-ddr", "pll-periph0-2x" };
|
||||
static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1",
|
||||
"pll-periph0-2x" };
|
||||
static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents,
|
||||
0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL);
|
||||
|
||||
|
|
@ -363,10 +379,11 @@ static struct ccu_common *sun8i_v3s_ccu_clks[] = {
|
|||
&pll_audio_base_clk.common,
|
||||
&pll_video_clk.common,
|
||||
&pll_ve_clk.common,
|
||||
&pll_ddr_clk.common,
|
||||
&pll_ddr0_clk.common,
|
||||
&pll_periph0_clk.common,
|
||||
&pll_isp_clk.common,
|
||||
&pll_periph1_clk.common,
|
||||
&pll_ddr1_clk.common,
|
||||
&cpu_clk.common,
|
||||
&axi_clk.common,
|
||||
&ahb1_clk.common,
|
||||
|
|
@ -433,6 +450,80 @@ static const struct clk_hw *clk_parent_pll_audio[] = {
|
|||
&pll_audio_base_clk.common.hw
|
||||
};
|
||||
|
||||
static struct ccu_common *sun8i_v3_ccu_clks[] = {
|
||||
&pll_cpu_clk.common,
|
||||
&pll_audio_base_clk.common,
|
||||
&pll_video_clk.common,
|
||||
&pll_ve_clk.common,
|
||||
&pll_ddr0_clk.common,
|
||||
&pll_periph0_clk.common,
|
||||
&pll_isp_clk.common,
|
||||
&pll_periph1_clk.common,
|
||||
&pll_ddr1_clk.common,
|
||||
&cpu_clk.common,
|
||||
&axi_clk.common,
|
||||
&ahb1_clk.common,
|
||||
&apb1_clk.common,
|
||||
&apb2_clk.common,
|
||||
&ahb2_clk.common,
|
||||
&bus_ce_clk.common,
|
||||
&bus_dma_clk.common,
|
||||
&bus_mmc0_clk.common,
|
||||
&bus_mmc1_clk.common,
|
||||
&bus_mmc2_clk.common,
|
||||
&bus_dram_clk.common,
|
||||
&bus_emac_clk.common,
|
||||
&bus_hstimer_clk.common,
|
||||
&bus_spi0_clk.common,
|
||||
&bus_otg_clk.common,
|
||||
&bus_ehci0_clk.common,
|
||||
&bus_ohci0_clk.common,
|
||||
&bus_ve_clk.common,
|
||||
&bus_tcon0_clk.common,
|
||||
&bus_csi_clk.common,
|
||||
&bus_de_clk.common,
|
||||
&bus_codec_clk.common,
|
||||
&bus_pio_clk.common,
|
||||
&bus_i2s0_clk.common,
|
||||
&bus_i2c0_clk.common,
|
||||
&bus_i2c1_clk.common,
|
||||
&bus_uart0_clk.common,
|
||||
&bus_uart1_clk.common,
|
||||
&bus_uart2_clk.common,
|
||||
&bus_ephy_clk.common,
|
||||
&bus_dbg_clk.common,
|
||||
&mmc0_clk.common,
|
||||
&mmc0_sample_clk.common,
|
||||
&mmc0_output_clk.common,
|
||||
&mmc1_clk.common,
|
||||
&mmc1_sample_clk.common,
|
||||
&mmc1_output_clk.common,
|
||||
&mmc2_clk.common,
|
||||
&mmc2_sample_clk.common,
|
||||
&mmc2_output_clk.common,
|
||||
&ce_clk.common,
|
||||
&spi0_clk.common,
|
||||
&i2s0_clk.common,
|
||||
&usb_phy0_clk.common,
|
||||
&usb_ohci0_clk.common,
|
||||
&dram_clk.common,
|
||||
&dram_ve_clk.common,
|
||||
&dram_csi_clk.common,
|
||||
&dram_ohci_clk.common,
|
||||
&dram_ehci_clk.common,
|
||||
&de_clk.common,
|
||||
&tcon_clk.common,
|
||||
&csi_misc_clk.common,
|
||||
&csi0_mclk_clk.common,
|
||||
&csi1_sclk_clk.common,
|
||||
&csi1_mclk_clk.common,
|
||||
&ve_clk.common,
|
||||
&ac_dig_clk.common,
|
||||
&avs_clk.common,
|
||||
&mbus_clk.common,
|
||||
&mipi_csi_clk.common,
|
||||
};
|
||||
|
||||
/* We hardcode the divider to 4 for now */
|
||||
static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
|
||||
clk_parent_pll_audio,
|
||||
|
|
@ -460,11 +551,12 @@ static struct clk_hw_onecell_data sun8i_v3s_hw_clks = {
|
|||
[CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
|
||||
[CLK_PLL_VIDEO] = &pll_video_clk.common.hw,
|
||||
[CLK_PLL_VE] = &pll_ve_clk.common.hw,
|
||||
[CLK_PLL_DDR] = &pll_ddr_clk.common.hw,
|
||||
[CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw,
|
||||
[CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw,
|
||||
[CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw,
|
||||
[CLK_PLL_ISP] = &pll_isp_clk.common.hw,
|
||||
[CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw,
|
||||
[CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw,
|
||||
[CLK_CPU] = &cpu_clk.common.hw,
|
||||
[CLK_AXI] = &axi_clk.common.hw,
|
||||
[CLK_AHB1] = &ahb1_clk.common.hw,
|
||||
|
|
@ -502,6 +594,9 @@ static struct clk_hw_onecell_data sun8i_v3s_hw_clks = {
|
|||
[CLK_MMC1] = &mmc1_clk.common.hw,
|
||||
[CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw,
|
||||
[CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,
|
||||
[CLK_MMC2] = &mmc2_clk.common.hw,
|
||||
[CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw,
|
||||
[CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw,
|
||||
[CLK_CE] = &ce_clk.common.hw,
|
||||
[CLK_SPI0] = &spi0_clk.common.hw,
|
||||
[CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
|
||||
|
|
@ -526,6 +621,88 @@ static struct clk_hw_onecell_data sun8i_v3s_hw_clks = {
|
|||
.num = CLK_NUMBER,
|
||||
};
|
||||
|
||||
static struct clk_hw_onecell_data sun8i_v3_hw_clks = {
|
||||
.hws = {
|
||||
[CLK_PLL_CPU] = &pll_cpu_clk.common.hw,
|
||||
[CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
|
||||
[CLK_PLL_AUDIO] = &pll_audio_clk.hw,
|
||||
[CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
|
||||
[CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
|
||||
[CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
|
||||
[CLK_PLL_VIDEO] = &pll_video_clk.common.hw,
|
||||
[CLK_PLL_VE] = &pll_ve_clk.common.hw,
|
||||
[CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw,
|
||||
[CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw,
|
||||
[CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw,
|
||||
[CLK_PLL_ISP] = &pll_isp_clk.common.hw,
|
||||
[CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw,
|
||||
[CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw,
|
||||
[CLK_CPU] = &cpu_clk.common.hw,
|
||||
[CLK_AXI] = &axi_clk.common.hw,
|
||||
[CLK_AHB1] = &ahb1_clk.common.hw,
|
||||
[CLK_APB1] = &apb1_clk.common.hw,
|
||||
[CLK_APB2] = &apb2_clk.common.hw,
|
||||
[CLK_AHB2] = &ahb2_clk.common.hw,
|
||||
[CLK_BUS_CE] = &bus_ce_clk.common.hw,
|
||||
[CLK_BUS_DMA] = &bus_dma_clk.common.hw,
|
||||
[CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
|
||||
[CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
|
||||
[CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
|
||||
[CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
|
||||
[CLK_BUS_EMAC] = &bus_emac_clk.common.hw,
|
||||
[CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
|
||||
[CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
|
||||
[CLK_BUS_OTG] = &bus_otg_clk.common.hw,
|
||||
[CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,
|
||||
[CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,
|
||||
[CLK_BUS_VE] = &bus_ve_clk.common.hw,
|
||||
[CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw,
|
||||
[CLK_BUS_CSI] = &bus_csi_clk.common.hw,
|
||||
[CLK_BUS_DE] = &bus_de_clk.common.hw,
|
||||
[CLK_BUS_CODEC] = &bus_codec_clk.common.hw,
|
||||
[CLK_BUS_PIO] = &bus_pio_clk.common.hw,
|
||||
[CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
|
||||
[CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
|
||||
[CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
|
||||
[CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
|
||||
[CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
|
||||
[CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
|
||||
[CLK_BUS_EPHY] = &bus_ephy_clk.common.hw,
|
||||
[CLK_BUS_DBG] = &bus_dbg_clk.common.hw,
|
||||
[CLK_MMC0] = &mmc0_clk.common.hw,
|
||||
[CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw,
|
||||
[CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw,
|
||||
[CLK_MMC1] = &mmc1_clk.common.hw,
|
||||
[CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw,
|
||||
[CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,
|
||||
[CLK_MMC2] = &mmc2_clk.common.hw,
|
||||
[CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw,
|
||||
[CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw,
|
||||
[CLK_CE] = &ce_clk.common.hw,
|
||||
[CLK_SPI0] = &spi0_clk.common.hw,
|
||||
[CLK_I2S0] = &i2s0_clk.common.hw,
|
||||
[CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
|
||||
[CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
|
||||
[CLK_DRAM] = &dram_clk.common.hw,
|
||||
[CLK_DRAM_VE] = &dram_ve_clk.common.hw,
|
||||
[CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
|
||||
[CLK_DRAM_EHCI] = &dram_ehci_clk.common.hw,
|
||||
[CLK_DRAM_OHCI] = &dram_ohci_clk.common.hw,
|
||||
[CLK_DE] = &de_clk.common.hw,
|
||||
[CLK_TCON0] = &tcon_clk.common.hw,
|
||||
[CLK_CSI_MISC] = &csi_misc_clk.common.hw,
|
||||
[CLK_CSI0_MCLK] = &csi0_mclk_clk.common.hw,
|
||||
[CLK_CSI1_SCLK] = &csi1_sclk_clk.common.hw,
|
||||
[CLK_CSI1_MCLK] = &csi1_mclk_clk.common.hw,
|
||||
[CLK_VE] = &ve_clk.common.hw,
|
||||
[CLK_AC_DIG] = &ac_dig_clk.common.hw,
|
||||
[CLK_AVS] = &avs_clk.common.hw,
|
||||
[CLK_MBUS] = &mbus_clk.common.hw,
|
||||
[CLK_MIPI_CSI] = &mipi_csi_clk.common.hw,
|
||||
},
|
||||
.num = CLK_NUMBER,
|
||||
};
|
||||
|
||||
static struct ccu_reset_map sun8i_v3s_ccu_resets[] = {
|
||||
[RST_USB_PHY0] = { 0x0cc, BIT(0) },
|
||||
|
||||
|
|
@ -561,6 +738,42 @@ static struct ccu_reset_map sun8i_v3s_ccu_resets[] = {
|
|||
[RST_BUS_UART2] = { 0x2d8, BIT(18) },
|
||||
};
|
||||
|
||||
static struct ccu_reset_map sun8i_v3_ccu_resets[] = {
|
||||
[RST_USB_PHY0] = { 0x0cc, BIT(0) },
|
||||
|
||||
[RST_MBUS] = { 0x0fc, BIT(31) },
|
||||
|
||||
[RST_BUS_CE] = { 0x2c0, BIT(5) },
|
||||
[RST_BUS_DMA] = { 0x2c0, BIT(6) },
|
||||
[RST_BUS_MMC0] = { 0x2c0, BIT(8) },
|
||||
[RST_BUS_MMC1] = { 0x2c0, BIT(9) },
|
||||
[RST_BUS_MMC2] = { 0x2c0, BIT(10) },
|
||||
[RST_BUS_DRAM] = { 0x2c0, BIT(14) },
|
||||
[RST_BUS_EMAC] = { 0x2c0, BIT(17) },
|
||||
[RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
|
||||
[RST_BUS_SPI0] = { 0x2c0, BIT(20) },
|
||||
[RST_BUS_OTG] = { 0x2c0, BIT(24) },
|
||||
[RST_BUS_EHCI0] = { 0x2c0, BIT(26) },
|
||||
[RST_BUS_OHCI0] = { 0x2c0, BIT(29) },
|
||||
|
||||
[RST_BUS_VE] = { 0x2c4, BIT(0) },
|
||||
[RST_BUS_TCON0] = { 0x2c4, BIT(4) },
|
||||
[RST_BUS_CSI] = { 0x2c4, BIT(8) },
|
||||
[RST_BUS_DE] = { 0x2c4, BIT(12) },
|
||||
[RST_BUS_DBG] = { 0x2c4, BIT(31) },
|
||||
|
||||
[RST_BUS_EPHY] = { 0x2c8, BIT(2) },
|
||||
|
||||
[RST_BUS_CODEC] = { 0x2d0, BIT(0) },
|
||||
[RST_BUS_I2S0] = { 0x2d0, BIT(12) },
|
||||
|
||||
[RST_BUS_I2C0] = { 0x2d8, BIT(0) },
|
||||
[RST_BUS_I2C1] = { 0x2d8, BIT(1) },
|
||||
[RST_BUS_UART0] = { 0x2d8, BIT(16) },
|
||||
[RST_BUS_UART1] = { 0x2d8, BIT(17) },
|
||||
[RST_BUS_UART2] = { 0x2d8, BIT(18) },
|
||||
};
|
||||
|
||||
static const struct sunxi_ccu_desc sun8i_v3s_ccu_desc = {
|
||||
.ccu_clks = sun8i_v3s_ccu_clks,
|
||||
.num_ccu_clks = ARRAY_SIZE(sun8i_v3s_ccu_clks),
|
||||
|
|
@ -571,7 +784,18 @@ static const struct sunxi_ccu_desc sun8i_v3s_ccu_desc = {
|
|||
.num_resets = ARRAY_SIZE(sun8i_v3s_ccu_resets),
|
||||
};
|
||||
|
||||
static void __init sun8i_v3s_ccu_setup(struct device_node *node)
|
||||
static const struct sunxi_ccu_desc sun8i_v3_ccu_desc = {
|
||||
.ccu_clks = sun8i_v3_ccu_clks,
|
||||
.num_ccu_clks = ARRAY_SIZE(sun8i_v3_ccu_clks),
|
||||
|
||||
.hw_clks = &sun8i_v3_hw_clks,
|
||||
|
||||
.resets = sun8i_v3_ccu_resets,
|
||||
.num_resets = ARRAY_SIZE(sun8i_v3_ccu_resets),
|
||||
};
|
||||
|
||||
static void __init sun8i_v3_v3s_ccu_init(struct device_node *node,
|
||||
const struct sunxi_ccu_desc *ccu_desc)
|
||||
{
|
||||
void __iomem *reg;
|
||||
u32 val;
|
||||
|
|
@ -587,7 +811,21 @@ static void __init sun8i_v3s_ccu_setup(struct device_node *node)
|
|||
val &= ~GENMASK(19, 16);
|
||||
writel(val | (3 << 16), reg + SUN8I_V3S_PLL_AUDIO_REG);
|
||||
|
||||
sunxi_ccu_probe(node, reg, &sun8i_v3s_ccu_desc);
|
||||
sunxi_ccu_probe(node, reg, ccu_desc);
|
||||
}
|
||||
|
||||
static void __init sun8i_v3s_ccu_setup(struct device_node *node)
|
||||
{
|
||||
sun8i_v3_v3s_ccu_init(node, &sun8i_v3s_ccu_desc);
|
||||
}
|
||||
|
||||
static void __init sun8i_v3_ccu_setup(struct device_node *node)
|
||||
{
|
||||
sun8i_v3_v3s_ccu_init(node, &sun8i_v3_ccu_desc);
|
||||
}
|
||||
|
||||
CLK_OF_DECLARE(sun8i_v3s_ccu, "allwinner,sun8i-v3s-ccu",
|
||||
sun8i_v3s_ccu_setup);
|
||||
|
||||
CLK_OF_DECLARE(sun8i_v3_ccu, "allwinner,sun8i-v3-ccu",
|
||||
sun8i_v3_ccu_setup);
|
||||
|
|
|
|||
|
|
@ -20,7 +20,7 @@
|
|||
#define CLK_PLL_AUDIO_8X 5
|
||||
#define CLK_PLL_VIDEO 6
|
||||
#define CLK_PLL_VE 7
|
||||
#define CLK_PLL_DDR 8
|
||||
#define CLK_PLL_DDR0 8
|
||||
#define CLK_PLL_PERIPH0 9
|
||||
#define CLK_PLL_PERIPH0_2X 10
|
||||
#define CLK_PLL_ISP 11
|
||||
|
|
@ -49,6 +49,8 @@
|
|||
|
||||
/* And the GPU module clock is exported */
|
||||
|
||||
#define CLK_NUMBER (CLK_MIPI_CSI + 1)
|
||||
#define CLK_PLL_DDR1 74
|
||||
|
||||
#define CLK_NUMBER (CLK_I2S0 + 1)
|
||||
|
||||
#endif /* _CCU_SUN8I_H3_H_ */
|
||||
|
|
|
|||
|
|
@ -97,14 +97,15 @@ int sunxi_ccu_probe(struct device_node *node, void __iomem *reg,
|
|||
|
||||
for (i = 0; i < desc->hw_clks->num ; i++) {
|
||||
struct clk_hw *hw = desc->hw_clks->hws[i];
|
||||
const char *name;
|
||||
|
||||
if (!hw)
|
||||
continue;
|
||||
|
||||
name = hw->init->name;
|
||||
ret = of_clk_hw_register(node, hw);
|
||||
if (ret) {
|
||||
pr_err("Couldn't register clock %d - %s\n",
|
||||
i, clk_hw_get_name(hw));
|
||||
pr_err("Couldn't register clock %d - %s\n", i, name);
|
||||
goto err_clk_unreg;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -140,6 +140,7 @@ static void __init omap_clk_register_apll(void *user,
|
|||
struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw);
|
||||
struct dpll_data *ad = clk_hw->dpll_data;
|
||||
struct clk *clk;
|
||||
const struct clk_init_data *init = clk_hw->hw.init;
|
||||
|
||||
clk = of_clk_get(node, 0);
|
||||
if (IS_ERR(clk)) {
|
||||
|
|
@ -168,15 +169,15 @@ static void __init omap_clk_register_apll(void *user,
|
|||
clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, node->name);
|
||||
if (!IS_ERR(clk)) {
|
||||
of_clk_add_provider(node, of_clk_src_simple_get, clk);
|
||||
kfree(clk_hw->hw.init->parent_names);
|
||||
kfree(clk_hw->hw.init);
|
||||
kfree(init->parent_names);
|
||||
kfree(init);
|
||||
return;
|
||||
}
|
||||
|
||||
cleanup:
|
||||
kfree(clk_hw->dpll_data);
|
||||
kfree(clk_hw->hw.init->parent_names);
|
||||
kfree(clk_hw->hw.init);
|
||||
kfree(init->parent_names);
|
||||
kfree(init);
|
||||
kfree(clk_hw);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -165,6 +165,7 @@ static void __init _register_dpll(void *user,
|
|||
struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw);
|
||||
struct dpll_data *dd = clk_hw->dpll_data;
|
||||
struct clk *clk;
|
||||
const struct clk_init_data *init = hw->init;
|
||||
|
||||
clk = of_clk_get(node, 0);
|
||||
if (IS_ERR(clk)) {
|
||||
|
|
@ -196,15 +197,15 @@ static void __init _register_dpll(void *user,
|
|||
|
||||
if (!IS_ERR(clk)) {
|
||||
of_clk_add_provider(node, of_clk_src_simple_get, clk);
|
||||
kfree(clk_hw->hw.init->parent_names);
|
||||
kfree(clk_hw->hw.init);
|
||||
kfree(init->parent_names);
|
||||
kfree(init);
|
||||
return;
|
||||
}
|
||||
|
||||
cleanup:
|
||||
kfree(clk_hw->dpll_data);
|
||||
kfree(clk_hw->hw.init->parent_names);
|
||||
kfree(clk_hw->hw.init);
|
||||
kfree(init->parent_names);
|
||||
kfree(init);
|
||||
kfree(clk_hw);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -564,6 +564,7 @@ static int __init top_clocks_init(struct device_node *np)
|
|||
{
|
||||
void __iomem *reg_base;
|
||||
int i, ret;
|
||||
const char *name;
|
||||
|
||||
reg_base = of_iomap(np, 0);
|
||||
if (!reg_base) {
|
||||
|
|
@ -573,11 +574,10 @@ static int __init top_clocks_init(struct device_node *np)
|
|||
|
||||
for (i = 0; i < ARRAY_SIZE(zx296718_pll_clk); i++) {
|
||||
zx296718_pll_clk[i].reg_base += (uintptr_t)reg_base;
|
||||
name = zx296718_pll_clk[i].hw.init->name;
|
||||
ret = clk_hw_register(NULL, &zx296718_pll_clk[i].hw);
|
||||
if (ret) {
|
||||
pr_warn("top clk %s init error!\n",
|
||||
zx296718_pll_clk[i].hw.init->name);
|
||||
}
|
||||
if (ret)
|
||||
pr_warn("top clk %s init error!\n", name);
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(top_ffactor_clk); i++) {
|
||||
|
|
@ -585,11 +585,10 @@ static int __init top_clocks_init(struct device_node *np)
|
|||
top_hw_onecell_data.hws[top_ffactor_clk[i].id] =
|
||||
&top_ffactor_clk[i].factor.hw;
|
||||
|
||||
name = top_ffactor_clk[i].factor.hw.init->name;
|
||||
ret = clk_hw_register(NULL, &top_ffactor_clk[i].factor.hw);
|
||||
if (ret) {
|
||||
pr_warn("top clk %s init error!\n",
|
||||
top_ffactor_clk[i].factor.hw.init->name);
|
||||
}
|
||||
if (ret)
|
||||
pr_warn("top clk %s init error!\n", name);
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(top_mux_clk); i++) {
|
||||
|
|
@ -598,11 +597,10 @@ static int __init top_clocks_init(struct device_node *np)
|
|||
&top_mux_clk[i].mux.hw;
|
||||
|
||||
top_mux_clk[i].mux.reg += (uintptr_t)reg_base;
|
||||
name = top_mux_clk[i].mux.hw.init->name;
|
||||
ret = clk_hw_register(NULL, &top_mux_clk[i].mux.hw);
|
||||
if (ret) {
|
||||
pr_warn("top clk %s init error!\n",
|
||||
top_mux_clk[i].mux.hw.init->name);
|
||||
}
|
||||
if (ret)
|
||||
pr_warn("top clk %s init error!\n", name);
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(top_gate_clk); i++) {
|
||||
|
|
@ -611,11 +609,10 @@ static int __init top_clocks_init(struct device_node *np)
|
|||
&top_gate_clk[i].gate.hw;
|
||||
|
||||
top_gate_clk[i].gate.reg += (uintptr_t)reg_base;
|
||||
name = top_gate_clk[i].gate.hw.init->name;
|
||||
ret = clk_hw_register(NULL, &top_gate_clk[i].gate.hw);
|
||||
if (ret) {
|
||||
pr_warn("top clk %s init error!\n",
|
||||
top_gate_clk[i].gate.hw.init->name);
|
||||
}
|
||||
if (ret)
|
||||
pr_warn("top clk %s init error!\n", name);
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(top_div_clk); i++) {
|
||||
|
|
@ -624,11 +621,10 @@ static int __init top_clocks_init(struct device_node *np)
|
|||
&top_div_clk[i].div.hw;
|
||||
|
||||
top_div_clk[i].div.reg += (uintptr_t)reg_base;
|
||||
name = top_div_clk[i].div.hw.init->name;
|
||||
ret = clk_hw_register(NULL, &top_div_clk[i].div.hw);
|
||||
if (ret) {
|
||||
pr_warn("top clk %s init error!\n",
|
||||
top_div_clk[i].div.hw.init->name);
|
||||
}
|
||||
if (ret)
|
||||
pr_warn("top clk %s init error!\n", name);
|
||||
}
|
||||
|
||||
ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
|
||||
|
|
@ -754,6 +750,7 @@ static int __init lsp0_clocks_init(struct device_node *np)
|
|||
{
|
||||
void __iomem *reg_base;
|
||||
int i, ret;
|
||||
const char *name;
|
||||
|
||||
reg_base = of_iomap(np, 0);
|
||||
if (!reg_base) {
|
||||
|
|
@ -767,11 +764,10 @@ static int __init lsp0_clocks_init(struct device_node *np)
|
|||
&lsp0_mux_clk[i].mux.hw;
|
||||
|
||||
lsp0_mux_clk[i].mux.reg += (uintptr_t)reg_base;
|
||||
name = lsp0_mux_clk[i].mux.hw.init->name;
|
||||
ret = clk_hw_register(NULL, &lsp0_mux_clk[i].mux.hw);
|
||||
if (ret) {
|
||||
pr_warn("lsp0 clk %s init error!\n",
|
||||
lsp0_mux_clk[i].mux.hw.init->name);
|
||||
}
|
||||
if (ret)
|
||||
pr_warn("lsp0 clk %s init error!\n", name);
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(lsp0_gate_clk); i++) {
|
||||
|
|
@ -780,11 +776,10 @@ static int __init lsp0_clocks_init(struct device_node *np)
|
|||
&lsp0_gate_clk[i].gate.hw;
|
||||
|
||||
lsp0_gate_clk[i].gate.reg += (uintptr_t)reg_base;
|
||||
name = lsp0_gate_clk[i].gate.hw.init->name;
|
||||
ret = clk_hw_register(NULL, &lsp0_gate_clk[i].gate.hw);
|
||||
if (ret) {
|
||||
pr_warn("lsp0 clk %s init error!\n",
|
||||
lsp0_gate_clk[i].gate.hw.init->name);
|
||||
}
|
||||
if (ret)
|
||||
pr_warn("lsp0 clk %s init error!\n", name);
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(lsp0_div_clk); i++) {
|
||||
|
|
@ -793,11 +788,10 @@ static int __init lsp0_clocks_init(struct device_node *np)
|
|||
&lsp0_div_clk[i].div.hw;
|
||||
|
||||
lsp0_div_clk[i].div.reg += (uintptr_t)reg_base;
|
||||
name = lsp0_div_clk[i].div.hw.init->name;
|
||||
ret = clk_hw_register(NULL, &lsp0_div_clk[i].div.hw);
|
||||
if (ret) {
|
||||
pr_warn("lsp0 clk %s init error!\n",
|
||||
lsp0_div_clk[i].div.hw.init->name);
|
||||
}
|
||||
if (ret)
|
||||
pr_warn("lsp0 clk %s init error!\n", name);
|
||||
}
|
||||
|
||||
ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
|
||||
|
|
@ -862,6 +856,7 @@ static int __init lsp1_clocks_init(struct device_node *np)
|
|||
{
|
||||
void __iomem *reg_base;
|
||||
int i, ret;
|
||||
const char *name;
|
||||
|
||||
reg_base = of_iomap(np, 0);
|
||||
if (!reg_base) {
|
||||
|
|
@ -875,11 +870,10 @@ static int __init lsp1_clocks_init(struct device_node *np)
|
|||
&lsp0_mux_clk[i].mux.hw;
|
||||
|
||||
lsp1_mux_clk[i].mux.reg += (uintptr_t)reg_base;
|
||||
name = lsp1_mux_clk[i].mux.hw.init->name;
|
||||
ret = clk_hw_register(NULL, &lsp1_mux_clk[i].mux.hw);
|
||||
if (ret) {
|
||||
pr_warn("lsp1 clk %s init error!\n",
|
||||
lsp1_mux_clk[i].mux.hw.init->name);
|
||||
}
|
||||
if (ret)
|
||||
pr_warn("lsp1 clk %s init error!\n", name);
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(lsp1_gate_clk); i++) {
|
||||
|
|
@ -888,11 +882,10 @@ static int __init lsp1_clocks_init(struct device_node *np)
|
|||
&lsp1_gate_clk[i].gate.hw;
|
||||
|
||||
lsp1_gate_clk[i].gate.reg += (uintptr_t)reg_base;
|
||||
name = lsp1_gate_clk[i].gate.hw.init->name;
|
||||
ret = clk_hw_register(NULL, &lsp1_gate_clk[i].gate.hw);
|
||||
if (ret) {
|
||||
pr_warn("lsp1 clk %s init error!\n",
|
||||
lsp1_gate_clk[i].gate.hw.init->name);
|
||||
}
|
||||
if (ret)
|
||||
pr_warn("lsp1 clk %s init error!\n", name);
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(lsp1_div_clk); i++) {
|
||||
|
|
@ -901,11 +894,10 @@ static int __init lsp1_clocks_init(struct device_node *np)
|
|||
&lsp1_div_clk[i].div.hw;
|
||||
|
||||
lsp1_div_clk[i].div.reg += (uintptr_t)reg_base;
|
||||
name = lsp1_div_clk[i].div.hw.init->name;
|
||||
ret = clk_hw_register(NULL, &lsp1_div_clk[i].div.hw);
|
||||
if (ret) {
|
||||
pr_warn("lsp1 clk %s init error!\n",
|
||||
lsp1_div_clk[i].div.hw.init->name);
|
||||
}
|
||||
if (ret)
|
||||
pr_warn("lsp1 clk %s init error!\n", name);
|
||||
}
|
||||
|
||||
ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
|
||||
|
|
@ -979,6 +971,7 @@ static int __init audio_clocks_init(struct device_node *np)
|
|||
{
|
||||
void __iomem *reg_base;
|
||||
int i, ret;
|
||||
const char *name;
|
||||
|
||||
reg_base = of_iomap(np, 0);
|
||||
if (!reg_base) {
|
||||
|
|
@ -992,11 +985,10 @@ static int __init audio_clocks_init(struct device_node *np)
|
|||
&audio_mux_clk[i].mux.hw;
|
||||
|
||||
audio_mux_clk[i].mux.reg += (uintptr_t)reg_base;
|
||||
name = audio_mux_clk[i].mux.hw.init->name;
|
||||
ret = clk_hw_register(NULL, &audio_mux_clk[i].mux.hw);
|
||||
if (ret) {
|
||||
pr_warn("audio clk %s init error!\n",
|
||||
audio_mux_clk[i].mux.hw.init->name);
|
||||
}
|
||||
if (ret)
|
||||
pr_warn("audio clk %s init error!\n", name);
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(audio_adiv_clk); i++) {
|
||||
|
|
@ -1005,11 +997,10 @@ static int __init audio_clocks_init(struct device_node *np)
|
|||
&audio_adiv_clk[i].hw;
|
||||
|
||||
audio_adiv_clk[i].reg_base += (uintptr_t)reg_base;
|
||||
name = audio_adiv_clk[i].hw.init->name;
|
||||
ret = clk_hw_register(NULL, &audio_adiv_clk[i].hw);
|
||||
if (ret) {
|
||||
pr_warn("audio clk %s init error!\n",
|
||||
audio_adiv_clk[i].hw.init->name);
|
||||
}
|
||||
if (ret)
|
||||
pr_warn("audio clk %s init error!\n", name);
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(audio_div_clk); i++) {
|
||||
|
|
@ -1018,11 +1009,10 @@ static int __init audio_clocks_init(struct device_node *np)
|
|||
&audio_div_clk[i].div.hw;
|
||||
|
||||
audio_div_clk[i].div.reg += (uintptr_t)reg_base;
|
||||
name = audio_div_clk[i].div.hw.init->name;
|
||||
ret = clk_hw_register(NULL, &audio_div_clk[i].div.hw);
|
||||
if (ret) {
|
||||
pr_warn("audio clk %s init error!\n",
|
||||
audio_div_clk[i].div.hw.init->name);
|
||||
}
|
||||
if (ret)
|
||||
pr_warn("audio clk %s init error!\n", name);
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(audio_gate_clk); i++) {
|
||||
|
|
@ -1031,11 +1021,10 @@ static int __init audio_clocks_init(struct device_node *np)
|
|||
&audio_gate_clk[i].gate.hw;
|
||||
|
||||
audio_gate_clk[i].gate.reg += (uintptr_t)reg_base;
|
||||
name = audio_gate_clk[i].gate.hw.init->name;
|
||||
ret = clk_hw_register(NULL, &audio_gate_clk[i].gate.hw);
|
||||
if (ret) {
|
||||
pr_warn("audio clk %s init error!\n",
|
||||
audio_gate_clk[i].gate.hw.init->name);
|
||||
}
|
||||
if (ret)
|
||||
pr_warn("audio clk %s init error!\n", name);
|
||||
}
|
||||
|
||||
ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
|
||||
|
|
|
|||
|
|
@ -335,6 +335,7 @@ static int serdes_am654_clk_mux_set_parent(struct clk_hw *hw, u8 index)
|
|||
{
|
||||
struct serdes_am654_clk_mux *mux = to_serdes_am654_clk_mux(hw);
|
||||
struct regmap *regmap = mux->regmap;
|
||||
const char *name = clk_hw_get_name(hw);
|
||||
unsigned int reg = mux->reg;
|
||||
int clk_id = mux->clk_id;
|
||||
int parents[SERDES_NUM_CLOCKS];
|
||||
|
|
@ -374,8 +375,7 @@ static int serdes_am654_clk_mux_set_parent(struct clk_hw *hw, u8 index)
|
|||
* This can never happen, unless we missed
|
||||
* a valid combination in serdes_am654_mux_table.
|
||||
*/
|
||||
WARN(1, "Failed to find the parent of %s clock\n",
|
||||
hw->init->name);
|
||||
WARN(1, "Failed to find the parent of %s clock\n", name);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -279,7 +279,7 @@ static void __init sun6i_rtc_clk_init(struct device_node *node,
|
|||
|
||||
of_property_read_string_index(node, "clock-output-names", 1,
|
||||
&clkout_name);
|
||||
rtc->ext_losc = clk_register_gate(NULL, clkout_name, rtc->hw.init->name,
|
||||
rtc->ext_losc = clk_register_gate(NULL, clkout_name, init.name,
|
||||
0, rtc->base + SUN6I_LOSC_OUT_GATING,
|
||||
SUN6I_LOSC_OUT_GATING_EN_OFFSET, 0,
|
||||
&rtc->lock);
|
||||
|
|
|
|||
|
|
@ -283,7 +283,11 @@
|
|||
#define IMX_ADMA_LPCG_PWM_IPG_CLK 38
|
||||
#define IMX_ADMA_LPCG_LCD_PIX_CLK 39
|
||||
#define IMX_ADMA_LPCG_LCD_APB_CLK 40
|
||||
#define IMX_ADMA_LPCG_DSP_ADB_CLK 41
|
||||
#define IMX_ADMA_LPCG_DSP_IPG_CLK 42
|
||||
#define IMX_ADMA_LPCG_DSP_CORE_CLK 43
|
||||
#define IMX_ADMA_LPCG_OCRAM_IPG_CLK 44
|
||||
|
||||
#define IMX_ADMA_LPCG_CLK_END 41
|
||||
#define IMX_ADMA_LPCG_CLK_END 45
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_IMX_H */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,216 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright 2018-2019 NXP
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_IMX8MN_H
|
||||
#define __DT_BINDINGS_CLOCK_IMX8MN_H
|
||||
|
||||
#define IMX8MN_CLK_DUMMY 0
|
||||
#define IMX8MN_CLK_32K 1
|
||||
#define IMX8MN_CLK_24M 2
|
||||
#define IMX8MN_OSC_HDMI_CLK 3
|
||||
#define IMX8MN_CLK_EXT1 4
|
||||
#define IMX8MN_CLK_EXT2 5
|
||||
#define IMX8MN_CLK_EXT3 6
|
||||
#define IMX8MN_CLK_EXT4 7
|
||||
#define IMX8MN_AUDIO_PLL1_REF_SEL 8
|
||||
#define IMX8MN_AUDIO_PLL2_REF_SEL 9
|
||||
#define IMX8MN_VIDEO_PLL1_REF_SEL 10
|
||||
#define IMX8MN_DRAM_PLL_REF_SEL 11
|
||||
#define IMX8MN_GPU_PLL_REF_SEL 12
|
||||
#define IMX8MN_VPU_PLL_REF_SEL 13
|
||||
#define IMX8MN_ARM_PLL_REF_SEL 14
|
||||
#define IMX8MN_SYS_PLL1_REF_SEL 15
|
||||
#define IMX8MN_SYS_PLL2_REF_SEL 16
|
||||
#define IMX8MN_SYS_PLL3_REF_SEL 17
|
||||
#define IMX8MN_AUDIO_PLL1 18
|
||||
#define IMX8MN_AUDIO_PLL2 19
|
||||
#define IMX8MN_VIDEO_PLL1 20
|
||||
#define IMX8MN_DRAM_PLL 21
|
||||
#define IMX8MN_GPU_PLL 22
|
||||
#define IMX8MN_VPU_PLL 23
|
||||
#define IMX8MN_ARM_PLL 24
|
||||
#define IMX8MN_SYS_PLL1 25
|
||||
#define IMX8MN_SYS_PLL2 26
|
||||
#define IMX8MN_SYS_PLL3 27
|
||||
#define IMX8MN_AUDIO_PLL1_BYPASS 28
|
||||
#define IMX8MN_AUDIO_PLL2_BYPASS 29
|
||||
#define IMX8MN_VIDEO_PLL1_BYPASS 30
|
||||
#define IMX8MN_DRAM_PLL_BYPASS 31
|
||||
#define IMX8MN_GPU_PLL_BYPASS 32
|
||||
#define IMX8MN_VPU_PLL_BYPASS 33
|
||||
#define IMX8MN_ARM_PLL_BYPASS 34
|
||||
#define IMX8MN_SYS_PLL1_BYPASS 35
|
||||
#define IMX8MN_SYS_PLL2_BYPASS 36
|
||||
#define IMX8MN_SYS_PLL3_BYPASS 37
|
||||
#define IMX8MN_AUDIO_PLL1_OUT 38
|
||||
#define IMX8MN_AUDIO_PLL2_OUT 39
|
||||
#define IMX8MN_VIDEO_PLL1_OUT 40
|
||||
#define IMX8MN_DRAM_PLL_OUT 41
|
||||
#define IMX8MN_GPU_PLL_OUT 42
|
||||
#define IMX8MN_VPU_PLL_OUT 43
|
||||
#define IMX8MN_ARM_PLL_OUT 44
|
||||
#define IMX8MN_SYS_PLL1_OUT 45
|
||||
#define IMX8MN_SYS_PLL2_OUT 46
|
||||
#define IMX8MN_SYS_PLL3_OUT 47
|
||||
#define IMX8MN_SYS_PLL1_40M 48
|
||||
#define IMX8MN_SYS_PLL1_80M 49
|
||||
#define IMX8MN_SYS_PLL1_100M 50
|
||||
#define IMX8MN_SYS_PLL1_133M 51
|
||||
#define IMX8MN_SYS_PLL1_160M 52
|
||||
#define IMX8MN_SYS_PLL1_200M 53
|
||||
#define IMX8MN_SYS_PLL1_266M 54
|
||||
#define IMX8MN_SYS_PLL1_400M 55
|
||||
#define IMX8MN_SYS_PLL1_800M 56
|
||||
#define IMX8MN_SYS_PLL2_50M 57
|
||||
#define IMX8MN_SYS_PLL2_100M 58
|
||||
#define IMX8MN_SYS_PLL2_125M 59
|
||||
#define IMX8MN_SYS_PLL2_166M 60
|
||||
#define IMX8MN_SYS_PLL2_200M 61
|
||||
#define IMX8MN_SYS_PLL2_250M 62
|
||||
#define IMX8MN_SYS_PLL2_333M 63
|
||||
#define IMX8MN_SYS_PLL2_500M 64
|
||||
#define IMX8MN_SYS_PLL2_1000M 65
|
||||
|
||||
/* CORE CLOCK ROOT */
|
||||
#define IMX8MN_CLK_A53_SRC 66
|
||||
#define IMX8MN_CLK_GPU_CORE_SRC 67
|
||||
#define IMX8MN_CLK_GPU_SHADER_SRC 68
|
||||
#define IMX8MN_CLK_A53_CG 69
|
||||
#define IMX8MN_CLK_GPU_CORE_CG 70
|
||||
#define IMX8MN_CLK_GPU_SHADER_CG 71
|
||||
#define IMX8MN_CLK_A53_DIV 72
|
||||
#define IMX8MN_CLK_GPU_CORE_DIV 73
|
||||
#define IMX8MN_CLK_GPU_SHADER_DIV 74
|
||||
|
||||
/* BUS CLOCK ROOT */
|
||||
#define IMX8MN_CLK_MAIN_AXI 75
|
||||
#define IMX8MN_CLK_ENET_AXI 76
|
||||
#define IMX8MN_CLK_NAND_USDHC_BUS 77
|
||||
#define IMX8MN_CLK_DISP_AXI 78
|
||||
#define IMX8MN_CLK_DISP_APB 79
|
||||
#define IMX8MN_CLK_USB_BUS 80
|
||||
#define IMX8MN_CLK_GPU_AXI 81
|
||||
#define IMX8MN_CLK_GPU_AHB 82
|
||||
#define IMX8MN_CLK_NOC 83
|
||||
#define IMX8MN_CLK_AHB 84
|
||||
#define IMX8MN_CLK_AUDIO_AHB 85
|
||||
|
||||
/* IPG CLOCK ROOT */
|
||||
#define IMX8MN_CLK_IPG_ROOT 86
|
||||
#define IMX8MN_CLK_IPG_AUDIO_ROOT 87
|
||||
|
||||
/* IP */
|
||||
#define IMX8MN_CLK_DRAM_CORE 88
|
||||
#define IMX8MN_CLK_DRAM_ALT 89
|
||||
#define IMX8MN_CLK_DRAM_APB 90
|
||||
#define IMX8MN_CLK_DRAM_ALT_ROOT 91
|
||||
#define IMX8MN_CLK_DISP_PIXEL 92
|
||||
#define IMX8MN_CLK_SAI2 93
|
||||
#define IMX8MN_CLK_SAI3 94
|
||||
#define IMX8MN_CLK_SAI5 95
|
||||
#define IMX8MN_CLK_SAI6 96
|
||||
#define IMX8MN_CLK_SPDIF1 97
|
||||
#define IMX8MN_CLK_ENET_REF 98
|
||||
#define IMX8MN_CLK_ENET_TIMER 99
|
||||
#define IMX8MN_CLK_ENET_PHY_REF 100
|
||||
#define IMX8MN_CLK_NAND 101
|
||||
#define IMX8MN_CLK_QSPI 102
|
||||
#define IMX8MN_CLK_USDHC1 103
|
||||
#define IMX8MN_CLK_USDHC2 104
|
||||
#define IMX8MN_CLK_I2C1 105
|
||||
#define IMX8MN_CLK_I2C2 106
|
||||
#define IMX8MN_CLK_I2C3 107
|
||||
#define IMX8MN_CLK_I2C4 118
|
||||
#define IMX8MN_CLK_UART1 119
|
||||
#define IMX8MN_CLK_UART2 110
|
||||
#define IMX8MN_CLK_UART3 111
|
||||
#define IMX8MN_CLK_UART4 112
|
||||
#define IMX8MN_CLK_USB_CORE_REF 113
|
||||
#define IMX8MN_CLK_USB_PHY_REF 114
|
||||
#define IMX8MN_CLK_ECSPI1 115
|
||||
#define IMX8MN_CLK_ECSPI2 116
|
||||
#define IMX8MN_CLK_PWM1 117
|
||||
#define IMX8MN_CLK_PWM2 118
|
||||
#define IMX8MN_CLK_PWM3 119
|
||||
#define IMX8MN_CLK_PWM4 120
|
||||
#define IMX8MN_CLK_WDOG 121
|
||||
#define IMX8MN_CLK_WRCLK 122
|
||||
#define IMX8MN_CLK_CLKO1 123
|
||||
#define IMX8MN_CLK_CLKO2 124
|
||||
#define IMX8MN_CLK_DSI_CORE 125
|
||||
#define IMX8MN_CLK_DSI_PHY_REF 126
|
||||
#define IMX8MN_CLK_DSI_DBI 127
|
||||
#define IMX8MN_CLK_USDHC3 128
|
||||
#define IMX8MN_CLK_CAMERA_PIXEL 129
|
||||
#define IMX8MN_CLK_CSI1_PHY_REF 130
|
||||
#define IMX8MN_CLK_CSI2_PHY_REF 131
|
||||
#define IMX8MN_CLK_CSI2_ESC 132
|
||||
#define IMX8MN_CLK_ECSPI3 133
|
||||
#define IMX8MN_CLK_PDM 134
|
||||
#define IMX8MN_CLK_SAI7 135
|
||||
|
||||
#define IMX8MN_CLK_ECSPI1_ROOT 136
|
||||
#define IMX8MN_CLK_ECSPI2_ROOT 137
|
||||
#define IMX8MN_CLK_ECSPI3_ROOT 138
|
||||
#define IMX8MN_CLK_ENET1_ROOT 139
|
||||
#define IMX8MN_CLK_GPIO1_ROOT 140
|
||||
#define IMX8MN_CLK_GPIO2_ROOT 141
|
||||
#define IMX8MN_CLK_GPIO3_ROOT 142
|
||||
#define IMX8MN_CLK_GPIO4_ROOT 143
|
||||
#define IMX8MN_CLK_GPIO5_ROOT 144
|
||||
#define IMX8MN_CLK_I2C1_ROOT 145
|
||||
#define IMX8MN_CLK_I2C2_ROOT 146
|
||||
#define IMX8MN_CLK_I2C3_ROOT 147
|
||||
#define IMX8MN_CLK_I2C4_ROOT 148
|
||||
#define IMX8MN_CLK_MU_ROOT 149
|
||||
#define IMX8MN_CLK_OCOTP_ROOT 150
|
||||
#define IMX8MN_CLK_PWM1_ROOT 151
|
||||
#define IMX8MN_CLK_PWM2_ROOT 152
|
||||
#define IMX8MN_CLK_PWM3_ROOT 153
|
||||
#define IMX8MN_CLK_PWM4_ROOT 154
|
||||
#define IMX8MN_CLK_QSPI_ROOT 155
|
||||
#define IMX8MN_CLK_NAND_ROOT 156
|
||||
#define IMX8MN_CLK_SAI2_ROOT 157
|
||||
#define IMX8MN_CLK_SAI2_IPG 158
|
||||
#define IMX8MN_CLK_SAI3_ROOT 159
|
||||
#define IMX8MN_CLK_SAI3_IPG 160
|
||||
#define IMX8MN_CLK_SAI5_ROOT 161
|
||||
#define IMX8MN_CLK_SAI5_IPG 162
|
||||
#define IMX8MN_CLK_SAI6_ROOT 163
|
||||
#define IMX8MN_CLK_SAI6_IPG 164
|
||||
#define IMX8MN_CLK_SAI7_ROOT 165
|
||||
#define IMX8MN_CLK_SAI7_IPG 166
|
||||
#define IMX8MN_CLK_SDMA1_ROOT 167
|
||||
#define IMX8MN_CLK_SDMA2_ROOT 168
|
||||
#define IMX8MN_CLK_UART1_ROOT 169
|
||||
#define IMX8MN_CLK_UART2_ROOT 170
|
||||
#define IMX8MN_CLK_UART3_ROOT 171
|
||||
#define IMX8MN_CLK_UART4_ROOT 172
|
||||
#define IMX8MN_CLK_USB1_CTRL_ROOT 173
|
||||
#define IMX8MN_CLK_USDHC1_ROOT 174
|
||||
#define IMX8MN_CLK_USDHC2_ROOT 175
|
||||
#define IMX8MN_CLK_WDOG1_ROOT 176
|
||||
#define IMX8MN_CLK_WDOG2_ROOT 177
|
||||
#define IMX8MN_CLK_WDOG3_ROOT 178
|
||||
#define IMX8MN_CLK_GPU_BUS_ROOT 179
|
||||
#define IMX8MN_CLK_ASRC_ROOT 180
|
||||
#define IMX8MN_CLK_GPU3D_ROOT 181
|
||||
#define IMX8MN_CLK_PDM_ROOT 182
|
||||
#define IMX8MN_CLK_PDM_IPG 183
|
||||
#define IMX8MN_CLK_DISP_AXI_ROOT 184
|
||||
#define IMX8MN_CLK_DISP_APB_ROOT 185
|
||||
#define IMX8MN_CLK_DISP_PIXEL_ROOT 186
|
||||
#define IMX8MN_CLK_CAMERA_PIXEL_ROOT 187
|
||||
#define IMX8MN_CLK_USDHC3_ROOT 188
|
||||
#define IMX8MN_CLK_SDMA3_ROOT 189
|
||||
#define IMX8MN_CLK_TMU_ROOT 190
|
||||
#define IMX8MN_CLK_ARM 191
|
||||
#define IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK 192
|
||||
#define IMX8MN_CLK_GPU_CORE_ROOT 193
|
||||
#define IMX8MN_CLK_GIC 194
|
||||
|
||||
#define IMX8MN_CLK_END 195
|
||||
|
||||
#endif
|
||||
|
|
@ -104,4 +104,8 @@
|
|||
|
||||
#define CLK_MIPI_CSI 73
|
||||
|
||||
/* Clocks not available on V3s */
|
||||
#define CLK_BUS_I2S0 75
|
||||
#define CLK_I2S0 76
|
||||
|
||||
#endif /* _DT_BINDINGS_CLK_SUN8I_V3S_H_ */
|
||||
|
|
|
|||
|
|
@ -75,4 +75,7 @@
|
|||
#define RST_BUS_UART1 50
|
||||
#define RST_BUS_UART2 51
|
||||
|
||||
/* Reset lines not available on V3s */
|
||||
#define RST_BUS_I2S0 52
|
||||
|
||||
#endif /* _DT_BINDINGS_RST_SUN8I_H3_H_ */
|
||||
|
|
|
|||
|
|
@ -299,7 +299,8 @@ struct clk_init_data {
|
|||
* into the clk API
|
||||
*
|
||||
* @init: pointer to struct clk_init_data that contains the init data shared
|
||||
* with the common clock framework.
|
||||
* with the common clock framework. This pointer will be set to NULL once
|
||||
* a clk_register() variant is called on this clk_hw pointer.
|
||||
*/
|
||||
struct clk_hw {
|
||||
struct clk_core *core;
|
||||
|
|
|
|||
|
|
@ -4,6 +4,9 @@
|
|||
* Sylwester Nawrocki <s.nawrocki@samsung.com>
|
||||
*/
|
||||
|
||||
#ifndef __CLK_CONF_H
|
||||
#define __CLK_CONF_H
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
struct device_node;
|
||||
|
|
@ -17,3 +20,5 @@ static inline int of_clk_set_defaults(struct device_node *node,
|
|||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CLK_CONF_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue