From 9e0665fc3f11c5e7bc122faff7c91035025b8038 Mon Sep 17 00:00:00 2001
From: Jacky Bai <ping.bai@nxp.com>
Date: Fri, 25 Sep 2020 10:43:13 +0800
Subject: [PATCH] MLK-24914 irqchip: gpcv2: Revert "MLK-23354 irqchip: gpcv2:
 Add wait mode workaround on imx8mp"

This reverts commit 3d65a3518149d33e289b5417d7a4a175b4ef0737.

The i.MX8MP A0 silicon will not be supported, so revert the SW workaround
for A0 to provide more robust & clean code support for i.MX8MP.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Tested-by: Jian Li <jian.li@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8mp-evk-root.dts |  2 --
 arch/arm64/boot/dts/freescale/imx8mp.dtsi         | 13 ++-----------
 drivers/irqchip/irq-imx-gpcv2.c                   |  5 +----
 3 files changed, 3 insertions(+), 17 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-root.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-root.dts
index c445708de5a7..c4fca332f75a 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk-root.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-root.dts
@@ -19,8 +19,6 @@
 	/delete-property/ compatible;
 };
 
-/delete-node/ &gpc;
-
 &clk {
 	init-on-array = <IMX8MP_CLK_USDHC3_ROOT
 			 IMX8MP_CLK_NAND_USDHC_BUS
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index dba1a3561473..e38100718342 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -15,7 +15,7 @@
 
 / {
 	compatible = "fsl,imx8mp";
-	interrupt-parent = <&gpc>;
+	interrupt-parent = <&gic>;
 	#address-cells = <2>;
 	#size-cells = <2>;
 
@@ -728,15 +728,6 @@
 				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 				#reset-cells = <1>;
 			};
-
-			gpc: gpc@303a0000 {
-				compatible = "fsl,imx8mp-gpc";
-				reg = <0x303a0000 0x10000>;
-				interrupt-parent = <&gic>;
-				interrupt-controller;
-				broken-wake-request-signals;
-				#interrupt-cells = <3>;
-			};
 		};
 
 		aips2: bus@30400000 {
@@ -1596,6 +1587,7 @@
 				reg = <0x32fc2000 0x1000>;
 				interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 				interrupt-controller;
+				interrupt-parent = <&gic>;
 				#interrupt-cells = <1>;
 				fsl,channel = <1>;
 				fsl,num-irqs = <64>;
@@ -2443,5 +2435,4 @@
 			};
 		};
 	};
-
 };
diff --git a/drivers/irqchip/irq-imx-gpcv2.c b/drivers/irqchip/irq-imx-gpcv2.c
index 16edb2f35a1e..988c08cad87d 100644
--- a/drivers/irqchip/irq-imx-gpcv2.c
+++ b/drivers/irqchip/irq-imx-gpcv2.c
@@ -332,7 +332,6 @@ static const struct irq_domain_ops gpcv2_irqchip_data_domain_ops = {
 static const struct of_device_id gpcv2_of_match[] = {
 	{ .compatible = "fsl,imx7d-gpc",  .data = (const void *) 2 },
 	{ .compatible = "fsl,imx8mq-gpc", .data = (const void *) 4 },
-	{ .compatible = "fsl,imx8mp-gpc", .data = (const void *) 4 },
 	{ /* END */ }
 };
 
@@ -388,8 +387,7 @@ static int __init imx_gpcv2_irqchip_init(struct device_node *node,
 	}
 	irq_set_default_host(domain);
 
-	if (of_machine_is_compatible("fsl,imx8mq") ||
-	    of_machine_is_compatible("fsl,imx8mp")) {
+	if (of_machine_is_compatible("fsl,imx8mq")) {
 		/* sw workaround for IPI can't wakeup CORE
 		ERRATA(ERR011171) on i.MX8MQ */
 		err11171 = true;
@@ -437,4 +435,3 @@ static int __init imx_gpcv2_irqchip_init(struct device_node *node,
 
 IRQCHIP_DECLARE(imx_gpcv2_imx7d, "fsl,imx7d-gpc", imx_gpcv2_irqchip_init);
 IRQCHIP_DECLARE(imx_gpcv2_imx8mq, "fsl,imx8mq-gpc", imx_gpcv2_irqchip_init);
-IRQCHIP_DECLARE(imx_gpcv2_imx8mp, "fsl,imx8mp-gpc", imx_gpcv2_irqchip_init);