MLK-23421: mailbox: imx: add SECO MU support
i.MX8/8X SECO firmware IPC is an implementation of passing messages.
But current imx-mailbox driver only support one word message,
i.MX8/8X linux side firmware has to request four TX, four RX and a
TXDB to support IPC to SECO firmware. This is low efficent and
more interrupts triggered compared with one TX and one RX.
To make SECO MU work,
- parse the size of msg.
- Only enable TR0/RR0 interrupt for transmit/receive message.
- For TX/RX, only support one TX channel and one RX channel
- For RX, support receive msg of any size, linited by hardcoded value of 30.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
(cherry picked from commit 297f4cf6e1)
This commit is contained in:
Franck LENORMAND
Silvano di Ninno
parent
4cc99e389c
commit
972fba7b94
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@ -4,6 +4,7 @@
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*/
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#include <linux/clk.h>
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#include <linux/firmware/imx/ipc.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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@ -36,6 +37,11 @@ enum imx_mu_chan_type {
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IMX_MU_TYPE_RXDB, /* Rx doorbell */
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};
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struct imx_sc_rpc_msg_max {
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struct imx_sc_rpc_msg hdr;
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u32 data[30];
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};
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struct imx_mu_con_priv {
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unsigned int idx;
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char irq_desc[IMX_MU_CHAN_NAME_SIZE];
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@ -64,8 +70,10 @@ struct imx_mu_priv {
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};
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struct imx_mu_dcfg {
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int (*tx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data);
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int (*tx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp,
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void *data);
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int (*rx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp);
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int (*rxdb)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp);
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void (*init)(struct imx_mu_priv *priv);
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u32 xTR[4]; /* Transmit Registers */
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u32 xRR[4]; /* Receive Registers */
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@ -88,6 +96,57 @@ static u32 imx_mu_read(struct imx_mu_priv *priv, u32 offs)
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return ioread32(priv->base + offs);
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}
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static int imx_mu_tx_waiting_write(struct imx_mu_priv *priv, u32 idx, u32 val)
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{
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u32 timeout = 500;
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u32 status;
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u32 can_write;
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dev_dbg(priv->dev, "Trying to write %.8x to idx %d\n", val, idx);
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do {
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status = imx_mu_read(priv, priv->dcfg->xSR);
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can_write = status & IMX_MU_xSR_TEn(idx % 4);
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timeout--;
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} while (!can_write && timeout > 0);
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if (timeout == 0) {
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dev_err(priv->dev, "timeout trying to write %.8x at %d(%.8x)\n",
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val, idx, status);
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return -ETIME;
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}
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imx_mu_write(priv, val, priv->dcfg->xTR[idx % 4]);
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return 0;
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}
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static int imx_mu_rx_waiting_read(struct imx_mu_priv *priv, u32 idx, u32 *val)
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{
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u32 timeout = 500;
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u32 status;
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u32 can_read;
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dev_dbg(priv->dev, "Trying to read from idx %d\n", idx);
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do {
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status = imx_mu_read(priv, priv->dcfg->xSR);
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can_read = status & IMX_MU_xSR_RFn(idx % 4);
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timeout--;
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} while (!can_read && timeout > 0);
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if (timeout == 0) {
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dev_err(priv->dev, "timeout trying to read idx %d (%.8x)\n",
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idx, status);
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return -ETIME;
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}
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*val = imx_mu_read(priv, priv->dcfg->xRR[idx % 4]);
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dev_dbg(priv->dev, "Read %.8x\n", *val);
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return 0;
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}
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static u32 imx_mu_xcr_rmw(struct imx_mu_priv *priv, u32 set, u32 clr)
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{
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unsigned long flags;
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@ -119,7 +178,9 @@ static int imx_mu_generic_tx(struct imx_mu_priv *priv,
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tasklet_schedule(&cp->txdb_tasklet);
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break;
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default:
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dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);
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dev_warn_ratelimited(priv->dev,
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"Send data on wrong channel type: %d\n",
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cp->type);
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return -EINVAL;
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}
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@ -137,6 +198,124 @@ static int imx_mu_generic_rx(struct imx_mu_priv *priv,
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return 0;
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}
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static int imx_mu_generic_rxdb(struct imx_mu_priv *priv,
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struct imx_mu_con_priv *cp)
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{
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imx_mu_write(priv, IMX_MU_xSR_GIPn(cp->idx), priv->dcfg->xSR);
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mbox_chan_received_data(cp->chan, NULL);
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return 0;
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}
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static int imx_mu_seco_tx(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp,
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void *data)
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{
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struct imx_sc_rpc_msg_max *msg = data;
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u32 *arg = data;
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u32 byte_size;
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int err;
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int i;
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dev_dbg(priv->dev, "Sending message\n");
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switch (cp->type) {
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case IMX_MU_TYPE_TXDB:
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byte_size = msg->hdr.size * sizeof(u32);
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if (byte_size > sizeof(*msg)) {
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/*
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* The real message size can be different to
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* struct imx_sc_rpc_msg_max size
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*/
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dev_err(priv->dev,
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"Exceed max msg size (%li) on TX, got: %i\n",
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sizeof(*msg), byte_size);
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return -EINVAL;
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}
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print_hex_dump_debug("from client ", DUMP_PREFIX_OFFSET, 4, 4,
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data, byte_size, false);
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/* Send first word */
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dev_dbg(priv->dev, "Sending header\n");
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imx_mu_write(priv, *arg++, priv->dcfg->xTR[0]);
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/* Send signaling */
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dev_dbg(priv->dev, "Sending signaling\n");
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imx_mu_xcr_rmw(priv, IMX_MU_xCR_GIRn(cp->idx), 0);
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/* Send words to fill the mailbox */
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for (i = 1; i < 4 && i < msg->hdr.size; i++) {
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dev_dbg(priv->dev, "Sending word %d\n", i);
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imx_mu_write(priv, *arg++, priv->dcfg->xTR[i % 4]);
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}
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/* Send rest of message waiting for remote read */
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for (; i < msg->hdr.size; i++) {
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dev_dbg(priv->dev, "Sending word %d\n", i);
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err = imx_mu_tx_waiting_write(priv, i, *arg++);
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if (err) {
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dev_err(priv->dev, "Timeout tx %d\n", i);
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return err;
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}
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}
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/* Simulate hack for mbox framework */
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tasklet_schedule(&cp->txdb_tasklet);
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break;
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default:
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dev_warn_ratelimited(priv->dev,
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"Send data on wrong channel type: %d\n",
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cp->type);
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return -EINVAL;
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}
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return 0;
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}
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static int imx_mu_seco_rxdb(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp)
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{
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struct imx_sc_rpc_msg_max msg;
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u32 *data = (u32 *)&msg;
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u32 byte_size;
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int err;
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int i;
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dev_dbg(priv->dev, "Receiving message\n");
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/* Read header */
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dev_dbg(priv->dev, "Receiving header\n");
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*data++ = imx_mu_read(priv, priv->dcfg->xRR[0]);
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byte_size = msg.hdr.size * sizeof(u32);
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if (byte_size > sizeof(msg)) {
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dev_err(priv->dev, "Exceed max msg size (%li) on RX, got: %i\n",
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sizeof(msg), byte_size);
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return -EINVAL;
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}
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/* Read message waiting they are written */
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for (i = 1; i < msg.hdr.size; i++) {
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dev_dbg(priv->dev, "Receiving word %d\n", i);
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err = imx_mu_rx_waiting_read(priv, i, data++);
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if (err) {
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dev_err(priv->dev, "Timeout rx %d\n", i);
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return err;
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}
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}
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/* Clear GIP */
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imx_mu_write(priv, IMX_MU_xSR_GIPn(cp->idx), priv->dcfg->xSR);
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print_hex_dump_debug("to client ", DUMP_PREFIX_OFFSET, 4, 4,
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&msg, byte_size, false);
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/* send data to client */
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dev_dbg(priv->dev, "Sending message to client\n");
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mbox_chan_received_data(cp->chan, (void *)&msg);
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return 0;
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}
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static void imx_mu_txdb_tasklet(unsigned long data)
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{
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struct imx_mu_con_priv *cp = (struct imx_mu_con_priv *)data;
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@ -154,6 +333,8 @@ static irqreturn_t imx_mu_isr(int irq, void *p)
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ctrl = imx_mu_read(priv, priv->dcfg->xCR);
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val = imx_mu_read(priv, priv->dcfg->xSR);
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dev_dbg(priv->dev, "isr: status: %.8x ctrl: %.8x\n", val, ctrl);
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switch (cp->type) {
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case IMX_MU_TYPE_TX:
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val &= IMX_MU_xSR_TEn(cp->idx) &
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@ -180,8 +361,7 @@ static irqreturn_t imx_mu_isr(int irq, void *p)
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} else if (val == IMX_MU_xSR_RFn(cp->idx)) {
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priv->dcfg->rx(priv, cp);
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} else if (val == IMX_MU_xSR_GIPn(cp->idx)) {
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imx_mu_write(priv, IMX_MU_xSR_GIPn(cp->idx), priv->dcfg->xSR);
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mbox_chan_received_data(chan, NULL);
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priv->dcfg->rxdb(priv, cp);
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} else {
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dev_warn_ratelimited(priv->dev, "Not handled interrupt\n");
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return IRQ_NONE;
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@ -272,7 +452,8 @@ static struct mbox_chan * imx_mu_xlate(struct mbox_controller *mbox,
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u32 type, idx, chan;
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if (sp->args_count != 2) {
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dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count);
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dev_err(mbox->dev, "Invalid argument count %d\n",
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sp->args_count);
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return ERR_PTR(-EINVAL);
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}
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@ -281,13 +462,37 @@ static struct mbox_chan * imx_mu_xlate(struct mbox_controller *mbox,
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chan = type * 4 + idx;
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if (chan >= mbox->num_chans) {
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dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx);
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dev_err(mbox->dev,
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"Not supported chan number: %d. (type: %d, idx: %d)\n",
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chan, type, idx);
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return ERR_PTR(-EINVAL);
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}
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return &mbox->chans[chan];
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}
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static struct mbox_chan * imx_mu_seco_xlate(struct mbox_controller *mbox,
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const struct of_phandle_args *sp)
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{
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u32 type;
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if (sp->args_count < 1) {
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dev_err(mbox->dev, "Invalid argument count %d\n",
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sp->args_count);
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return ERR_PTR(-EINVAL);
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}
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type = sp->args[0]; /* channel type */
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/* Only supports TXDB and RXDB */
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if (type == IMX_MU_TYPE_TX || type == IMX_MU_TYPE_RX) {
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dev_err(mbox->dev, "Invalid type: %d\n", type);
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return ERR_PTR(-EINVAL);
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}
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return imx_mu_xlate(mbox, sp);
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}
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static void imx_mu_init_generic(struct imx_mu_priv *priv)
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{
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unsigned int i;
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@ -313,6 +518,12 @@ static void imx_mu_init_generic(struct imx_mu_priv *priv)
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imx_mu_write(priv, 0, priv->dcfg->xCR);
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}
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static void imx_mu_seco_init(struct imx_mu_priv *priv)
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{
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imx_mu_init_generic(priv);
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priv->mbox.of_xlate = imx_mu_seco_xlate;
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}
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static int imx_mu_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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@ -405,6 +616,7 @@ static const struct dev_pm_ops imx_mu_pm_ops = {
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static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = {
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.tx = imx_mu_generic_tx,
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.rx = imx_mu_generic_rx,
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.rxdb = imx_mu_generic_rxdb,
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.init = imx_mu_init_generic,
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.xTR = {0x0, 0x4, 0x8, 0xc},
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.xRR = {0x10, 0x14, 0x18, 0x1c},
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@ -415,6 +627,7 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = {
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static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = {
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.tx = imx_mu_generic_tx,
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.rx = imx_mu_generic_rx,
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.rxdb = imx_mu_generic_rxdb,
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.init = imx_mu_init_generic,
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.xTR = {0x20, 0x24, 0x28, 0x2c},
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.xRR = {0x40, 0x44, 0x48, 0x4c},
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@ -422,9 +635,20 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = {
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.xCR = 0x64,
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};
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static const struct imx_mu_dcfg imx_mu_cfg_imx8_seco = {
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.tx = imx_mu_seco_tx,
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.rxdb = imx_mu_seco_rxdb,
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.init = imx_mu_seco_init,
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.xTR = {0x0, 0x4, 0x8, 0xc},
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.xRR = {0x10, 0x14, 0x18, 0x1c},
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.xSR = 0x20,
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.xCR = 0x24,
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};
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static const struct of_device_id imx_mu_dt_ids[] = {
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{ .compatible = "fsl,imx7ulp-mu", .data = &imx_mu_cfg_imx7ulp },
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{ .compatible = "fsl,imx6sx-mu", .data = &imx_mu_cfg_imx6sx },
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{ .compatible = "fsl,imx8-mu-seco", .data = &imx_mu_cfg_imx8_seco },
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{ },
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};
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MODULE_DEVICE_TABLE(of, imx_mu_dt_ids);
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