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Merge branch 'omap-for-v3.8/pm' into omap-for-v3.8/clock

This commit is contained in:
Tony Lindgren 2012-11-13 13:25:38 -08:00
parent c9d501e5cb 46bf4a5622
commit 89ab216b33
648 changed files with 8602 additions and 5226 deletions
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4
Documentation/00-INDEX
View File

@ -210,6 +210,8 @@ local_ops.txt
- semantics and behavior of local atomic operations.
lockdep-design.txt
- documentation on the runtime locking correctness validator.
lockup-watchdogs.txt
- info on soft and hard lockup detectors (aka nmi_watchdog).
logo.gif
- full colour GIF image of Linux logo (penguin - Tux).
logo.txt
@ -240,8 +242,6 @@ netlabel/
- directory with information on the NetLabel subsystem.
networking/
- directory with info on various aspects of networking with Linux.
nmi_watchdog.txt
- info on NMI watchdog for SMP systems.
nommu-mmap.txt
- documentation about no-mmu memory mapping support.
numastat.txt

2
Documentation/devicetree/bindings/arm/atmel-at91.txt
View File

@ -8,7 +8,7 @@ PIT Timer required properties:
shared across all System Controller members.
TC/TCLIB Timer required properties:
- compatible: Should be "atmel,<chip>-pit".
- compatible: Should be "atmel,<chip>-tcb".
<chip> can be "at91rm9200" or "at91sam9x5"
- reg: Should contain registers location and length
- interrupts: Should contain all interrupts for the TC block

19
Documentation/devicetree/bindings/input/touchscreen/egalax-ts.txt Normal file
View File

@ -0,0 +1,19 @@
* EETI eGalax Multiple Touch Controller
Required properties:
- compatible: must be "eeti,egalax_ts"
- reg: i2c slave address
- interrupt-parent: the phandle for the interrupt controller
- interrupts: touch controller interrupt
- wakeup-gpios: the gpio pin to be used for waking up the controller
as well as uased as irq pin
Example:
egalax_ts@04 {
compatible = "eeti,egalax_ts";
reg = <0x04>;
interrupt-parent = <&gpio1>;
interrupts = <9 2>;
wakeup-gpios = <&gpio1 9 0>;
};

2
Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt
View File

@ -93,7 +93,7 @@ Valid values for pin and group names are:
With some exceptions, these support nvidia,high-speed-mode,
nvidia,schmitt, nvidia,low-power-mode, nvidia,pull-down-strength,
nvidia,pull-up-strength, nvidia,slew_rate-rising, nvidia,slew_rate-falling.
nvidia,pull-up-strength, nvidia,slew-rate-rising, nvidia,slew-rate-falling.
drive_ao1, drive_ao2, drive_at1, drive_at2, drive_cdev1, drive_cdev2,
drive_csus, drive_dap1, drive_dap2, drive_dap3, drive_dap4, drive_dbg,

2
Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt
View File

@ -83,7 +83,7 @@ Valid values for pin and group names are:
drive groups:
These all support nvidia,pull-down-strength, nvidia,pull-up-strength,
nvidia,slew_rate-rising, nvidia,slew_rate-falling. Most but not all
nvidia,slew-rate-rising, nvidia,slew-rate-falling. Most but not all
support nvidia,high-speed-mode, nvidia,schmitt, nvidia,low-power-mode.
ao1, ao2, at1, at2, at3, at4, at5, cdev1, cdev2, cec, crt, csus, dap1,

24
Documentation/firmware_class/README
View File

@ -18,32 +18,40 @@
High level behavior (mixed):
============================
kernel(driver): calls request_firmware(&fw_entry, $FIRMWARE, device)
1), kernel(driver):
- calls request_firmware(&fw_entry, $FIRMWARE, device)
- kernel searchs the fimware image with name $FIRMWARE directly
in the below search path of root filesystem:
"/lib/firmware/updates/" UTS_RELEASE,
"/lib/firmware/updates",
"/lib/firmware/" UTS_RELEASE,
"/lib/firmware"
- If found, goto 7), else goto 2)
userspace:
2), userspace:
- /sys/class/firmware/xxx/{loading,data} appear.
- hotplug gets called with a firmware identifier in $FIRMWARE
and the usual hotplug environment.
- hotplug: echo 1 > /sys/class/firmware/xxx/loading
kernel: Discard any previous partial load.
3), kernel: Discard any previous partial load.
userspace:
4), userspace:
- hotplug: cat appropriate_firmware_image > \
/sys/class/firmware/xxx/data
kernel: grows a buffer in PAGE_SIZE increments to hold the image as it
5), kernel: grows a buffer in PAGE_SIZE increments to hold the image as it
comes in.
userspace:
6), userspace:
- hotplug: echo 0 > /sys/class/firmware/xxx/loading
kernel: request_firmware() returns and the driver has the firmware
7), kernel: request_firmware() returns and the driver has the firmware
image in fw_entry->{data,size}. If something went wrong
request_firmware() returns non-zero and fw_entry is set to
NULL.
kernel(driver): Driver code calls release_firmware(fw_entry) releasing
8), kernel(driver): Driver code calls release_firmware(fw_entry) releasing
the firmware image and any related resource.
High level behavior (driver code):

2
Documentation/hwmon/fam15h_power
View File

@ -10,7 +10,7 @@ Supported chips:
BIOS and Kernel Developer's Guide (BKDG) For AMD Family 15h Processors
(not yet published)
Author: Andreas Herrmann <andreas.herrmann3@amd.com>
Author: Andreas Herrmann <herrmann.der.user@googlemail.com>
Description
-----------

39
Documentation/zh_CN/IRQ.txt Normal file
View File

@ -0,0 +1,39 @@
Chinese translated version of Documentation/IRQ.txt
If you have any comment or update to the content, please contact the
original document maintainer directly. However, if you have a problem
communicating in English you can also ask the Chinese maintainer for
help. Contact the Chinese maintainer if this translation is outdated
or if there is a problem with the translation.
Maintainer: Eric W. Biederman <ebiederman@xmission.com>
Chinese maintainer: Fu Wei <tekkamanninja@gmail.com>
---------------------------------------------------------------------
Documentation/IRQ.txt 的中文翻译
如果想评论或更新本文的内容，请直接联系原文档的维护者。如果你使用英文
交流有困难的话，也可以向中文版维护者求助。如果本翻译更新不及时或者翻
译存在问题，请联系中文版维护者。
英文版维护者： Eric W. Biederman <ebiederman@xmission.com>
中文版维护者： 傅炜 Fu Wei <tekkamanninja@gmail.com>
中文版翻译者： 傅炜 Fu Wei <tekkamanninja@gmail.com>
中文版校译者： 傅炜 Fu Wei <tekkamanninja@gmail.com>
以下为正文
---------------------------------------------------------------------
何为 IRQ?
一个 IRQ 是来自某个设备的一个中断请求。目前，它们可以来自一个硬件引脚，
或来自一个数据包。多个设备可能连接到同个硬件引脚，从而共享一个 IRQ。
一个 IRQ 编号是用于告知硬件中断源的内核标识。通常情况下，这是一个
全局 irq_desc 数组的索引，但是除了在 linux/interrupt.h 中的实现，
具体的细节是体系结构特定的。
一个 IRQ 编号是设备上某个可能的中断源的枚举。通常情况下，枚举的编号是
该引脚在系统内中断控制器的所有输入引脚中的编号。对于 ISA 总线中的情况，
枚举的是在两个 i8259 中断控制器中 16 个输入引脚。
架构可以对 IRQ 编号指定额外的含义，在硬件涉及任何手工配置的情况下，
是被提倡的。ISA 的 IRQ 是一个分配这类额外含义的典型例子。

156
Documentation/zh_CN/arm64/booting.txt Normal file
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@ -0,0 +1,156 @@
Chinese translated version of Documentation/arm64/booting.txt
If you have any comment or update to the content, please contact the
original document maintainer directly. However, if you have a problem
communicating in English you can also ask the Chinese maintainer for
help. Contact the Chinese maintainer if this translation is outdated
or if there is a problem with the translation.
Maintainer: Will Deacon <will.deacon@arm.com>
Chinese maintainer: Fu Wei <tekkamanninja@gmail.com>
---------------------------------------------------------------------
Documentation/arm64/booting.txt 的中文翻译
如果想评论或更新本文的内容，请直接联系原文档的维护者。如果你使用英文
交流有困难的话，也可以向中文版维护者求助。如果本翻译更新不及时或者翻
译存在问题，请联系中文版维护者。
英文版维护者： Will Deacon <will.deacon@arm.com>
中文版维护者： 傅炜 Fu Wei <tekkamanninja@gmail.com>
中文版翻译者： 傅炜 Fu Wei <tekkamanninja@gmail.com>
中文版校译者： 傅炜 Fu Wei <tekkamanninja@gmail.com>
以下为正文
---------------------------------------------------------------------
启动 AArch64 Linux
==================
作者: Will Deacon <will.deacon@arm.com>
日期: 2012 年 09 月 07 日
本文档基于 Russell King 的 ARM 启动文档，且适用于所有公开发布的
AArch64 Linux 内核代码。
AArch64 异常模型由多个异常级别（EL0 - EL3）组成，对于 EL0 和 EL1
异常级有对应的安全和非安全模式。EL2 是系统管理级，且仅存在于
非安全模式下。EL3 是最高特权级，且仅存在于安全模式下。
基于本文档的目的，我们将简单地使用‘引导装载程序’（‘boot loader’）
这个术语来定义在将控制权交给 Linux 内核前 CPU 上执行的所有软件。
这可能包含安全监控和系统管理代码，或者它可能只是一些用于准备最小启动
环境的指令。
基本上，引导装载程序（至少）应实现以下操作：
1、设置和初始化 RAM
2、设置设备树数据
3、解压内核映像
4、调用内核映像
1、设置和初始化 RAM
-----------------
必要性: 强制
引导装载程序应该找到并初始化系统中所有内核用于保持系统变量数据的 RAM。
这个操作的执行是设备依赖的。（它可能使用内部算法来自动定位和计算所有
RAM，或可能使用对这个设备已知的 RAM 信息，还可能使用任何引导装载程序
设计者想到的匹配方法。）
2、设置设备树数据
---------------
必要性: 强制
设备树数据块（dtb）大小必须不大于 2 MB，且位于从内核映像起始算起第一个
512MB 内的 2MB 边界上。这使得内核可以通过初始页表中的单个节描述符来
映射此数据块。
3、解压内核映像
-------------
必要性: 可选
AArch64 内核当前没有提供自解压代码，因此如果使用了压缩内核映像文件
（比如 Image.gz），则需要通过引导装载程序（使用 gzip 等）来进行解压。
若引导装载程序没有实现这个需求，就要使用非压缩内核映像文件。
4、调用内核映像
-------------
必要性: 强制
已解压的内核映像包含一个 32 字节的头，内容如下：
u32 magic = 0x14000008; /* 跳转到 stext, 小端 */
u32 res0 = 0; /* 保留 */
u64 text_offset; /* 映像装载偏移 */
u64 res1 = 0; /* 保留 */
u64 res2 = 0; /* 保留 */
映像必须位于系统 RAM 起始处的特定偏移（当前是 0x80000）。系统 RAM
的起始地址必须是以 2MB 对齐的。
在跳转入内核前，必须符合以下状态：
- 停止所有 DMA 设备，这样内存数据就不会因为虚假网络包或磁盘数据而
被破坏。这可能可以节省你许多的调试时间。
- 主 CPU 通用寄存器设置
x0 = 系统 RAM 中设备树数据块（dtb）的物理地址。
x1 = 0 (保留，将来可能使用)
x2 = 0 (保留，将来可能使用)
x3 = 0 (保留，将来可能使用)
- CPU 模式
所有形式的中断必须在 PSTATE.DAIF 中被屏蔽（Debug、SError、IRQ
和 FIQ）。
CPU 必须处于 EL2（推荐，可访问虚拟化扩展）或非安全 EL1 模式下。
- 高速缓存、MMU
MMU 必须关闭。
指令缓存开启或关闭都可以。
数据缓存必须关闭且无效。
外部高速缓存（如果存在）必须配置并禁用。
- 架构计时器
CNTFRQ 必须设定为计时器的频率。
如果在 EL1 模式下进入内核，则 CNTHCTL_EL2 中的 EL1PCTEN (bit 0)
必须置位。
- 一致性
通过内核启动的所有 CPU 在内核入口地址上必须处于相同的一致性域中。
这可能要根据具体实现来定义初始化过程，以使能每个CPU上对维护操作的
接收。
- 系统寄存器
在进入内核映像的异常级中，所有构架中可写的系统寄存器必须通过软件
在一个更高的异常级别下初始化，以防止在 未知 状态下运行。
引导装载程序必须在每个 CPU 处于以下状态时跳入内核入口：
- 主 CPU 必须直接跳入内核映像的第一条指令。通过此 CPU 传递的设备树
数据块必须在每个 CPU 节点中包含以下内容：
1、‘enable-method’属性。目前，此字段支持的值仅为字符串“spin-table”。
2、‘cpu-release-addr’标识一个 64-bit、初始化为零的内存位置。
引导装载程序必须生成这些设备树属性，并在跳入内核入口之前将其插入
数据块。
- 任何辅助 CPU 必须在内存保留区（通过设备树中的 /memreserve/ 域传递
给内核）中自旋于内核之外，轮询它们的 cpu-release-addr 位置（必须
包含在保留区中）。可通过插入 wfe 指令来降低忙循环开销，而主 CPU 将
发出 sev 指令。当对 cpu-release-addr 所指位置的读取操作返回非零值
时，CPU 必须直接跳入此值所指向的地址。
- 辅助 CPU 通用寄存器设置
x0 = 0 (保留，将来可能使用)
x1 = 0 (保留，将来可能使用)
x2 = 0 (保留，将来可能使用)
x3 = 0 (保留，将来可能使用)

93
Documentation/zh_CN/arm64/memory.txt Normal file
View File

@ -0,0 +1,93 @@
Chinese translated version of Documentation/arm64/memory.txt
If you have any comment or update to the content, please contact the
original document maintainer directly. However, if you have a problem
communicating in English you can also ask the Chinese maintainer for
help. Contact the Chinese maintainer if this translation is outdated
or if there is a problem with the translation.
Maintainer: Catalin Marinas <catalin.marinas@arm.com>
Chinese maintainer: Fu Wei <tekkamanninja@gmail.com>
---------------------------------------------------------------------
Documentation/arm64/memory.txt 的中文翻译
如果想评论或更新本文的内容，请直接联系原文档的维护者。如果你使用英文
交流有困难的话，也可以向中文版维护者求助。如果本翻译更新不及时或者翻
译存在问题，请联系中文版维护者。
英文版维护者： Catalin Marinas <catalin.marinas@arm.com>
中文版维护者： 傅炜 Fu Wei <tekkamanninja@gmail.com>
中文版翻译者： 傅炜 Fu Wei <tekkamanninja@gmail.com>
中文版校译者： 傅炜 Fu Wei <tekkamanninja@gmail.com>
以下为正文
---------------------------------------------------------------------
Linux 在 AArch64 中的内存布局
===========================
作者: Catalin Marinas <catalin.marinas@arm.com>
日期: 2012 年 02 月 20 日
本文档描述 AArch64 Linux 内核所使用的虚拟内存布局。此构架可以实现
页大小为 4KB 的 4 级转换表和页大小为 64KB 的 3 级转换表。
AArch64 Linux 使用页大小为 4KB 的 3 级转换表配置，对于用户和内核
都有 39-bit (512GB) 的虚拟地址空间。对于页大小为 64KB的配置，仅
使用 2 级转换表，但内存布局相同。
用户地址空间的 63:39 位为 0，而内核地址空间的相应位为 1。TTBRx 的
选择由虚拟地址的 63 位给出。swapper_pg_dir 仅包含内核（全局）映射，
而用户 pgd 仅包含用户（非全局）映射。swapper_pgd_dir 地址被写入
TTBR1 中，且从不写入 TTBR0。
AArch64 Linux 内存布局：
起始地址 结束地址 大小 用途
-----------------------------------------------------------------------
0000000000000000 0000007fffffffff 512GB 用户空间
ffffff8000000000 ffffffbbfffcffff ~240GB vmalloc
ffffffbbfffd0000 ffffffbcfffdffff 64KB [防护页]
ffffffbbfffe0000 ffffffbcfffeffff 64KB PCI I/O 空间
ffffffbbffff0000 ffffffbcffffffff 64KB [防护页]
ffffffbc00000000 ffffffbdffffffff 8GB vmemmap
ffffffbe00000000 ffffffbffbffffff ~8GB [防护页，未来用于 vmmemap]
ffffffbffc000000 ffffffbfffffffff 64MB 模块
ffffffc000000000 ffffffffffffffff 256GB 内存空间
4KB 页大小的转换表查找：
+--------+--------+--------+--------+--------+--------+--------+--------+
|63 56|55 48|47 40|39 32|31 24|23 16|15 8|7 0|
+--------+--------+--------+--------+--------+--------+--------+--------+
| | | | | |
| | | | | v
| | | | | [11:0] 页内偏移
| | | | +-> [20:12] L3 索引
| | | +-----------> [29:21] L2 索引
| | +---------------------> [38:30] L1 索引
| +-------------------------------> [47:39] L0 索引 (未使用)
+-------------------------------------------------> [63] TTBR0/1
64KB 页大小的转换表查找：
+--------+--------+--------+--------+--------+--------+--------+--------+
|63 56|55 48|47 40|39 32|31 24|23 16|15 8|7 0|
+--------+--------+--------+--------+--------+--------+--------+--------+
| | | | |
| | | | v
| | | | [15:0] 页内偏移
| | | +----------> [28:16] L3 索引
| | +--------------------------> [41:29] L2 索引 (仅使用 38:29 )
| +-------------------------------> [47:42] L1 索引 (未使用)
+-------------------------------------------------> [63] TTBR0/1

21
MAINTAINERS
View File

@ -503,7 +503,7 @@ F: include/linux/altera_uart.h
F: include/linux/altera_jtaguart.h
AMD FAM15H PROCESSOR POWER MONITORING DRIVER
M: Andreas Herrmann <andreas.herrmann3@amd.com>
M: Andreas Herrmann <herrmann.der.user@googlemail.com>
L: lm-sensors@lm-sensors.org
S: Maintained
F: Documentation/hwmon/fam15h_power
@ -637,6 +637,13 @@ W: http://www.arm.linux.org.uk/
S: Maintained
F: arch/arm/
ARM SUB-ARCHITECTURES
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: MAINTAINED
F: arch/arm/mach-*/
F: arch/arm/plat-*/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git
ARM PRIMECELL AACI PL041 DRIVER
M: Russell King <linux@arm.linux.org.uk>
S: Maintained
@ -2500,6 +2507,7 @@ M: Joonyoung Shim <jy0922.shim@samsung.com>
M: Seung-Woo Kim <sw0312.kim@samsung.com>
M: Kyungmin Park <kyungmin.park@samsung.com>
L: dri-devel@lists.freedesktop.org
T: git git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos.git
S: Supported
F: drivers/gpu/drm/exynos
F: include/drm/exynos*
@ -2802,6 +2810,7 @@ F: sound/usb/misc/ua101.c
EXTENSIBLE FIRMWARE INTERFACE (EFI)
M: Matt Fleming <matt.fleming@intel.com>
L: linux-efi@vger.kernel.org
T: git git://git.kernel.org/pub/scm/linux/kernel/git/mfleming/efi.git
S: Maintained
F: Documentation/x86/efi-stub.txt
F: arch/ia64/kernel/efi.c
@ -5061,7 +5070,13 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git
S: Odd Fixes
F: drivers/net/
F: include/linux/if_*
F: include/linux/*device.h
F: include/linux/netdevice.h
F: include/linux/arcdevice.h
F: include/linux/etherdevice.h
F: include/linux/fcdevice.h
F: include/linux/fddidevice.h
F: include/linux/hippidevice.h
F: include/linux/inetdevice.h
NETXEN (1/10) GbE SUPPORT
M: Sony Chacko <sony.chacko@qlogic.com>
@ -5633,7 +5648,7 @@ S: Maintained
F: drivers/pinctrl/spear/
PKTCDVD DRIVER
M: Peter Osterlund <petero2@telia.com>
M: Jiri Kosina <jkosina@suse.cz>
S: Maintained
F: drivers/block/pktcdvd.c
F: include/linux/pktcdvd.h

2
Makefile
View File

@ -1,7 +1,7 @@
VERSION = 3
PATCHLEVEL = 7
SUBLEVEL = 0
EXTRAVERSION = -rc2
EXTRAVERSION = -rc4
NAME = Terrified Chipmunk
# *DOCUMENTATION*

80
arch/alpha/include/asm/thread_info.h
View File

@ -7,6 +7,7 @@
#include <asm/processor.h>
#include <asm/types.h>
#include <asm/hwrpb.h>
#include <asm/sysinfo.h>
#endif
#ifndef __ASSEMBLY__
@ -21,6 +22,7 @@ struct thread_info {
mm_segment_t addr_limit; /* thread address space */
unsigned cpu; /* current CPU */
int preempt_count; /* 0 => preemptable, <0 => BUG */
unsigned int status; /* thread-synchronous flags */
int bpt_nsaved;
unsigned long bpt_addr[2]; /* breakpoint handling */
@ -63,8 +65,6 @@ register struct thread_info *__current_thread_info __asm__("$8");
* - these are process state flags and used from assembly
* - pending work-to-be-done flags come first and must be assigned to be
* within bits 0 to 7 to fit in and immediate operand.
* - ALPHA_UAC_SHIFT below must be kept consistent with the unaligned
* control flags.
*
* TIF_SYSCALL_TRACE is known to be 0 via blbs.
*/
@ -72,18 +72,12 @@ register struct thread_info *__current_thread_info __asm__("$8");
#define TIF_NOTIFY_RESUME 1 /* callback before returning to user */
#define TIF_SIGPENDING 2 /* signal pending */
#define TIF_NEED_RESCHED 3 /* rescheduling necessary */
#define TIF_POLLING_NRFLAG 8 /* poll_idle is polling NEED_RESCHED */
#define TIF_DIE_IF_KERNEL 9 /* dik recursion lock */
#define TIF_UAC_NOPRINT 10 /* ! Preserve sequence of following */
#define TIF_UAC_NOFIX 11 /* ! flags as they match */
#define TIF_UAC_SIGBUS 12 /* ! userspace part of 'osf_sysinfo' */
#define TIF_MEMDIE 13 /* is terminating due to OOM killer */
#define TIF_RESTORE_SIGMASK 14 /* restore signal mask in do_signal */
#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
#define _TIF_SIGPENDING (1<<TIF_SIGPENDING)
#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG)
#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME)
/* Work to do on interrupt/exception return. */
@ -94,29 +88,63 @@ register struct thread_info *__current_thread_info __asm__("$8");
#define _TIF_ALLWORK_MASK (_TIF_WORK_MASK \
| _TIF_SYSCALL_TRACE)
#define ALPHA_UAC_SHIFT TIF_UAC_NOPRINT
#define ALPHA_UAC_MASK (1 << TIF_UAC_NOPRINT | 1 << TIF_UAC_NOFIX | \
1 << TIF_UAC_SIGBUS)
#define TS_UAC_NOPRINT 0x0001 /* ! Preserve the following three */
#define TS_UAC_NOFIX 0x0002 /* ! flags as they match */
#define TS_UAC_SIGBUS 0x0004 /* ! userspace part of 'osf_sysinfo' */
#define TS_RESTORE_SIGMASK 0x0008 /* restore signal mask in do_signal() */
#define TS_POLLING 0x0010 /* idle task polling need_resched,
skip sending interrupt */
#define SET_UNALIGN_CTL(task,value) ({ \
task_thread_info(task)->flags = ((task_thread_info(task)->flags & \
~ALPHA_UAC_MASK) \
| (((value) << ALPHA_UAC_SHIFT) & (1<<TIF_UAC_NOPRINT))\
| (((value) << (ALPHA_UAC_SHIFT + 1)) & (1<<TIF_UAC_SIGBUS)) \
| (((value) << (ALPHA_UAC_SHIFT - 1)) & (1<<TIF_UAC_NOFIX)));\
#define tsk_is_polling(t) (task_thread_info(t)->status & TS_POLLING)
#ifndef __ASSEMBLY__
#define HAVE_SET_RESTORE_SIGMASK 1
static inline void set_restore_sigmask(void)
{
struct thread_info *ti = current_thread_info();
ti->status |= TS_RESTORE_SIGMASK;
WARN_ON(!test_bit(TIF_SIGPENDING, (unsigned long *)&ti->flags));
}
static inline void clear_restore_sigmask(void)
{
current_thread_info()->status &= ~TS_RESTORE_SIGMASK;
}
static inline bool test_restore_sigmask(void)
{
return current_thread_info()->status & TS_RESTORE_SIGMASK;
}
static inline bool test_and_clear_restore_sigmask(void)
{
struct thread_info *ti = current_thread_info();
if (!(ti->status & TS_RESTORE_SIGMASK))
return false;
ti->status &= ~TS_RESTORE_SIGMASK;
return true;
}
#endif
#define SET_UNALIGN_CTL(task,value) ({ \
__u32 status = task_thread_info(task)->status & ~UAC_BITMASK; \
if (value & PR_UNALIGN_NOPRINT) \
status |= TS_UAC_NOPRINT; \
if (value & PR_UNALIGN_SIGBUS) \
status |= TS_UAC_SIGBUS; \
if (value & 4) /* alpha-specific */ \
status |= TS_UAC_NOFIX; \
task_thread_info(task)->status = status; \
0; })
#define GET_UNALIGN_CTL(task,value) ({ \
put_user((task_thread_info(task)->flags & (1 << TIF_UAC_NOPRINT))\
>> ALPHA_UAC_SHIFT \
| (task_thread_info(task)->flags & (1 << TIF_UAC_SIGBUS))\
>> (ALPHA_UAC_SHIFT + 1) \
| (task_thread_info(task)->flags & (1 << TIF_UAC_NOFIX))\
>> (ALPHA_UAC_SHIFT - 1), \
(int __user *)(value)); \
__u32 status = task_thread_info(task)->status & ~UAC_BITMASK; \
__u32 res = 0; \
if (status & TS_UAC_NOPRINT) \
res |= PR_UNALIGN_NOPRINT; \
if (status & TS_UAC_SIGBUS) \
res |= PR_UNALIGN_SIGBUS; \
if (status & TS_UAC_NOFIX) \
res |= 4; \
put_user(res, (int __user *)(value)); \
})
#define tsk_is_polling(t) test_tsk_thread_flag(t, TIF_POLLING_NRFLAG)
#endif /* __KERNEL__ */
#endif /* _ALPHA_THREAD_INFO_H */

25
arch/alpha/kernel/osf_sys.c
View File

@ -793,8 +793,7 @@ SYSCALL_DEFINE5(osf_getsysinfo, unsigned long, op, void __user *, buffer,
case GSI_UACPROC:
if (nbytes < sizeof(unsigned int))
return -EINVAL;
w = (current_thread_info()->flags >> ALPHA_UAC_SHIFT) &
UAC_BITMASK;
w = current_thread_info()->status & UAC_BITMASK;
if (put_user(w, (unsigned int __user *)buffer))
return -EFAULT;
return 1;
@ -904,24 +903,20 @@ SYSCALL_DEFINE5(osf_setsysinfo, unsigned long, op, void __user *, buffer,
break;
case SSI_NVPAIRS: {
unsigned long v, w, i;
unsigned int old, new;
unsigned __user *p = buffer;
unsigned i;
for (i = 0; i < nbytes; ++i) {
for (i = 0, p = buffer; i < nbytes; ++i, p += 2) {
unsigned v, w, status;
if (get_user(v, 2*i + (unsigned int __user *)buffer))
return -EFAULT;
if (get_user(w, 2*i + 1 + (unsigned int __user *)buffer))
if (get_user(v, p) || get_user(w, p + 1))
return -EFAULT;
switch (v) {
case SSIN_UACPROC:
again:
old = current_thread_info()->flags;
new = old & ~(UAC_BITMASK << ALPHA_UAC_SHIFT);
new = new | (w & UAC_BITMASK) << ALPHA_UAC_SHIFT;
if (cmpxchg(&current_thread_info()->flags,
old, new) != old)
goto again;
w &= UAC_BITMASK;
status = current_thread_info()->status;
status = (status & ~UAC_BITMASK) | w;
current_thread_info()->status = status;
break;
default:

2
arch/alpha/kernel/process.c
View File

@ -49,7 +49,7 @@ EXPORT_SYMBOL(pm_power_off);
void
cpu_idle(void)
{
set_thread_flag(TIF_POLLING_NRFLAG);
current_thread_info()->status |= TS_POLLING;
while (1) {
/* FIXME -- EV6 and LCA45 know how to power down

6
arch/alpha/kernel/traps.c
View File

@ -780,17 +780,17 @@ do_entUnaUser(void __user * va, unsigned long opcode,
/* Check the UAC bits to decide what the user wants us to do
with the unaliged access. */
if (!test_thread_flag (TIF_UAC_NOPRINT)) {
if (!(current_thread_info()->status & TS_UAC_NOPRINT)) {
if (__ratelimit(&ratelimit)) {
printk("%s(%d): unaligned trap at %016lx: %p %lx %ld\n",
current->comm, task_pid_nr(current),
regs->pc - 4, va, opcode, reg);
}
}
if (test_thread_flag (TIF_UAC_SIGBUS))
if ((current_thread_info()->status & TS_UAC_SIGBUS))
goto give_sigbus;
/* Not sure why you'd want to use this, but... */
if (test_thread_flag (TIF_UAC_NOFIX))
if ((current_thread_info()->status & TS_UAC_NOFIX))
return;
/* Don't bother reading ds in the access check since we already

9
arch/arm/Kconfig
View File

@ -1603,8 +1603,8 @@ config NR_CPUS
default "4"
config HOTPLUG_CPU
bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
depends on SMP && HOTPLUG && EXPERIMENTAL
bool "Support for hot-pluggable CPUs"
depends on SMP && HOTPLUG
help
Say Y here to experiment with turning CPUs off and on. CPUs
can be controlled through /sys/devices/system/cpu.
@ -1645,8 +1645,8 @@ config HZ
default 100
config THUMB2_KERNEL
bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
bool "Compile the kernel in Thumb-2 mode"
depends on CPU_V7 && !CPU_V6 && !CPU_V6K
select AEABI
select ARM_ASM_UNIFIED
select ARM_UNWIND
@ -1850,6 +1850,7 @@ config XEN_DOM0
config XEN
bool "Xen guest support on ARM (EXPERIMENTAL)"
depends on EXPERIMENTAL && ARM && OF
depends on CPU_V7 && !CPU_V6
help
Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.

13
arch/arm/Makefile
View File

@ -21,8 +21,6 @@ endif
OBJCOPYFLAGS :=-O binary -R .comment -S
GZFLAGS :=-9
#KBUILD_CFLAGS +=-pipe
# Explicitly specifiy 32-bit ARM ISA since toolchain default can be -mthumb:
KBUILD_CFLAGS +=$(call cc-option,-marm,)
# Never generate .eh_frame
KBUILD_CFLAGS += $(call cc-option,-fno-dwarf2-cfi-asm)
@ -105,17 +103,20 @@ endif
ifeq ($(CONFIG_THUMB2_KERNEL),y)
AFLAGS_AUTOIT :=$(call as-option,-Wa$(comma)-mimplicit-it=always,-Wa$(comma)-mauto-it)
AFLAGS_NOWARN :=$(call as-option,-Wa$(comma)-mno-warn-deprecated,-Wa$(comma)-W)
CFLAGS_THUMB2 :=-mthumb $(AFLAGS_AUTOIT) $(AFLAGS_NOWARN)
AFLAGS_THUMB2 :=$(CFLAGS_THUMB2) -Wa$(comma)-mthumb
CFLAGS_ISA :=-mthumb $(AFLAGS_AUTOIT) $(AFLAGS_NOWARN)
AFLAGS_ISA :=$(CFLAGS_ISA) -Wa$(comma)-mthumb
# Work around buggy relocation from gas if requested:
ifeq ($(CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11),y)
CFLAGS_MODULE +=-fno-optimize-sibling-calls
endif
else
CFLAGS_ISA :=$(call cc-option,-marm,)
AFLAGS_ISA :=$(CFLAGS_ISA)
endif
# Need -Uarm for gcc < 3.x
KBUILD_CFLAGS +=$(CFLAGS_ABI) $(CFLAGS_THUMB2) $(arch-y) $(tune-y) $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -msoft-float -Uarm
KBUILD_AFLAGS +=$(CFLAGS_ABI) $(AFLAGS_THUMB2) $(arch-y) $(tune-y) -include asm/unified.h -msoft-float
KBUILD_CFLAGS +=$(CFLAGS_ABI) $(CFLAGS_ISA) $(arch-y) $(tune-y) $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -msoft-float -Uarm
KBUILD_AFLAGS +=$(CFLAGS_ABI) $(AFLAGS_ISA) $(arch-y) $(tune-y) -include asm/unified.h -msoft-float
CHECKFLAGS += -D__arm__

10
arch/arm/boot/Makefile
View File

@ -33,7 +33,7 @@ ifeq ($(CONFIG_XIP_KERNEL),y)
$(obj)/xipImage: vmlinux FORCE
$(call if_changed,objcopy)
@echo ' Kernel: $@ is ready (physical address: $(CONFIG_XIP_PHYS_ADDR))'
$(kecho) ' Kernel: $@ is ready (physical address: $(CONFIG_XIP_PHYS_ADDR))'
$(obj)/Image $(obj)/zImage: FORCE
@echo 'Kernel configured for XIP (CONFIG_XIP_KERNEL=y)'
@ -48,14 +48,14 @@ $(obj)/xipImage: FORCE
$(obj)/Image: vmlinux FORCE
$(call if_changed,objcopy)
@echo ' Kernel: $@ is ready'
$(kecho) ' Kernel: $@ is ready'
$(obj)/compressed/vmlinux: $(obj)/Image FORCE
$(Q)$(MAKE) $(build)=$(obj)/compressed $@
$(obj)/zImage: $(obj)/compressed/vmlinux FORCE
$(call if_changed,objcopy)
@echo ' Kernel: $@ is ready'
$(kecho) ' Kernel: $@ is ready'
endif
@ -90,7 +90,7 @@ fi
$(obj)/uImage: $(obj)/zImage FORCE
@$(check_for_multiple_loadaddr)
$(call if_changed,uimage)
@echo ' Image $@ is ready'
$(kecho) ' Image $@ is ready'
$(obj)/bootp/bootp: $(obj)/zImage initrd FORCE
$(Q)$(MAKE) $(build)=$(obj)/bootp $@
@ -98,7 +98,7 @@ $(obj)/bootp/bootp: $(obj)/zImage initrd FORCE
$(obj)/bootpImage: $(obj)/bootp/bootp FORCE
$(call if_changed,objcopy)
@echo ' Kernel: $@ is ready'
$(kecho) ' Kernel: $@ is ready'
PHONY += initrd FORCE
initrd:

4
arch/arm/boot/dts/at91sam9g20ek_common.dtsi
View File

@ -126,14 +126,14 @@
#size-cells = <0>;
btn3 {
label = "Buttin 3";
label = "Button 3";
gpios = <&pioA 30 1>;
linux,code = <0x103>;
gpio-key,wakeup;
};
btn4 {
label = "Buttin 4";
label = "Button 4";
gpios = <&pioA 31 1>;
linux,code = <0x104>;
gpio-key,wakeup;

17
arch/arm/boot/dts/dbx5x0.dtsi
View File

@ -483,6 +483,8 @@
compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
reg = <0x80004000 0x1000>;
interrupts = <0 21 0x4>;
arm,primecell-periphid = <0x180024>;
#address-cells = <1>;
#size-cells = <0>;
v-i2c-supply = <&db8500_vape_reg>;
@ -494,6 +496,8 @@
compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
reg = <0x80122000 0x1000>;
interrupts = <0 22 0x4>;
arm,primecell-periphid = <0x180024>;
#address-cells = <1>;
#size-cells = <0>;
v-i2c-supply = <&db8500_vape_reg>;
@ -505,6 +509,8 @@
compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
reg = <0x80128000 0x1000>;
interrupts = <0 55 0x4>;
arm,primecell-periphid = <0x180024>;
#address-cells = <1>;
#size-cells = <0>;
v-i2c-supply = <&db8500_vape_reg>;
@ -516,6 +522,8 @@
compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
reg = <0x80110000 0x1000>;
interrupts = <0 12 0x4>;
arm,primecell-periphid = <0x180024>;
#address-cells = <1>;
#size-cells = <0>;
v-i2c-supply = <&db8500_vape_reg>;
@ -527,6 +535,8 @@
compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
reg = <0x8012a000 0x1000>;
interrupts = <0 51 0x4>;
arm,primecell-periphid = <0x180024>;
#address-cells = <1>;
#size-cells = <0>;
v-i2c-supply = <&db8500_vape_reg>;
@ -573,33 +583,38 @@
interrupts = <0 60 0x4>;
status = "disabled";
};
sdi@80118000 {
compatible = "arm,pl18x", "arm,primecell";
reg = <0x80118000 0x1000>;
interrupts = <0 50 0x4>;
status = "disabled";
};
sdi@80005000 {
compatible = "arm,pl18x", "arm,primecell";
reg = <0x80005000 0x1000>;
interrupts = <0 41 0x4>;
status = "disabled";
};
sdi@80119000 {
compatible = "arm,pl18x", "arm,primecell";
reg = <0x80119000 0x1000>;
interrupts = <0 59 0x4>;
status = "disabled";
};
sdi@80114000 {
compatible = "arm,pl18x", "arm,primecell";
reg = <0x80114000 0x1000>;
interrupts = <0 99 0x4>;
status = "disabled";
};
sdi@80008000 {
compatible = "arm,pl18x", "arm,primecell";
reg = <0x80114000 0x1000>;
reg = <0x80008000 0x1000>;
interrupts = <0 100 0x4>;
status = "disabled";
};

6
arch/arm/boot/dts/exynos4210-trats.dts
View File

@ -20,8 +20,10 @@
compatible = "samsung,trats", "samsung,exynos4210";
memory {
reg = <0x40000000 0x20000000
0x60000000 0x20000000>;
reg = <0x40000000 0x10000000
0x50000000 0x10000000
0x60000000 0x10000000
0x70000000 0x10000000>;
};
chosen {

1
arch/arm/boot/dts/imx23.dtsi
View File

@ -69,6 +69,7 @@
interrupts = <13>, <56>;
interrupt-names = "gpmi-dma", "bch";
clocks = <&clks 34>;
clock-names = "gpmi_io";
fsl,gpmi-dma-channel = <4>;
status = "disabled";
};

1
arch/arm/boot/dts/imx28.dtsi
View File

@ -85,6 +85,7 @@
interrupts = <88>, <41>;
interrupt-names = "gpmi-dma", "bch";
clocks = <&clks 50>;
clock-names = "gpmi_io";
fsl,gpmi-dma-channel = <4>;
status = "disabled";
};

4
arch/arm/boot/dts/omap3.dtsi
View File

@ -257,7 +257,7 @@
interrupt-names = "common", "tx", "rx", "sidetone";
interrupt-parent = <&intc>;
ti,buffer-size = <1280>;
ti,hwmods = "mcbsp2";
ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
};
mcbsp3: mcbsp@49024000 {
@ -272,7 +272,7 @@
interrupt-names = "common", "tx", "rx", "sidetone";
interrupt-parent = <&intc>;
ti,buffer-size = <128>;
ti,hwmods = "mcbsp3";
ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
};
mcbsp4: mcbsp@49026000 {

2
arch/arm/configs/imx_v6_v7_defconfig
View File

@ -139,6 +139,7 @@ CONFIG_I2C_IMX=y
CONFIG_SPI=y
CONFIG_SPI_IMX=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_MC9S08DZ60=y
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
CONFIG_IMX2_WDT=y
@ -155,6 +156,7 @@ CONFIG_SOC_CAMERA=y
CONFIG_SOC_CAMERA_OV2640=y
CONFIG_VIDEO_MX3=y
CONFIG_FB=y
CONFIG_LCD_PLATFORM=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_LCD_CLASS_DEVICE=y
CONFIG_LCD_L4F00242T03=y

10
arch/arm/configs/mvebu_defconfig
View File

@ -1,6 +1,6 @@
CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
CONFIG_NO_HZ=y
CONFIG_IRQ_DOMAIN_DEBUG=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
@ -9,10 +9,12 @@ CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_ARCH_MVEBU=y
CONFIG_MACH_ARMADA_370_XP=y
CONFIG_MACH_ARMADA_370=y
CONFIG_MACH_ARMADA_XP=y
# CONFIG_CACHE_L2X0 is not set
CONFIG_AEABI=y
CONFIG_HIGHMEM=y
CONFIG_USE_OF=y
# CONFIG_COMPACTION is not set
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_ARM_APPENDED_DTB=y
@ -23,6 +25,8 @@ CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_SYSFS=y
# CONFIG_USB_SUPPORT is not set
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y
# CONFIG_EXT3_FS_XATTR is not set

1
arch/arm/configs/versatile_defconfig
View File

@ -1,3 +1,4 @@
CONFIG_ARCH_VERSATILE=y
CONFIG_EXPERIMENTAL=y
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_SYSVIPC=y

2
arch/arm/include/asm/flat.h
View File

@ -8,7 +8,7 @@
#define flat_argvp_envp_on_stack() 1
#define flat_old_ram_flag(flags) (flags)
#define flat_reloc_valid(reloc, size) ((reloc) <= (size))
#define flat_get_addr_from_rp(rp, relval, flags, persistent) get_unaligned(rp)
#define flat_get_addr_from_rp(rp, relval, flags, persistent) ((void)persistent,get_unaligned(rp))
#define flat_put_addr_at_rp(rp, val, relval) put_unaligned(val,rp)
#define flat_get_relocate_addr(rel) (rel)
#define flat_set_persistent(relval, p) 0

4
arch/arm/include/asm/uaccess.h
View File

@ -200,8 +200,8 @@ extern int __put_user_8(void *, unsigned long long);
#define USER_DS KERNEL_DS
#define segment_eq(a,b) (1)
#define __addr_ok(addr) (1)
#define __range_ok(addr,size) (0)
#define __addr_ok(addr) ((void)(addr),1)
#define __range_ok(addr,size) ((void)(addr),0)
#define get_fs() (KERNEL_DS)
static inline void set_fs(mm_segment_t fs)

12
arch/arm/include/asm/xen/interface.h
View File

@ -29,16 +29,22 @@
#ifndef __ASSEMBLY__
/* Explicitly size integers that represent pfns in the interface with
* Xen so that we can have one ABI that works for 32 and 64 bit guests. */
* Xen so that we can have one ABI that works for 32 and 64 bit guests.
* Note that this means that the xen_pfn_t type may be capable of
* representing pfn's which the guest cannot represent in its own pfn
* type. However since pfn space is controlled by the guest this is
* fine since it simply wouldn't be able to create any sure pfns in
* the first place.
*/
typedef uint64_t xen_pfn_t;
#define PRI_xen_pfn "llx"
typedef uint64_t xen_ulong_t;
#define PRI_xen_ulong "llx"
/* Guest handles for primitive C types. */
__DEFINE_GUEST_HANDLE(uchar, unsigned char);
__DEFINE_GUEST_HANDLE(uint, unsigned int);
__DEFINE_GUEST_HANDLE(ulong, unsigned long);
DEFINE_GUEST_HANDLE(char);
DEFINE_GUEST_HANDLE(int);
DEFINE_GUEST_HANDLE(long);
DEFINE_GUEST_HANDLE(void);
DEFINE_GUEST_HANDLE(uint64_t);
DEFINE_GUEST_HANDLE(uint32_t);

13
arch/arm/include/asm/xen/page.h
View File

@ -10,7 +10,7 @@
#include <xen/interface/grant_table.h>
#define pfn_to_mfn(pfn) (pfn)
#define phys_to_machine_mapping_valid (1)
#define phys_to_machine_mapping_valid(pfn) (1)
#define mfn_to_pfn(mfn) (mfn)
#define mfn_to_virt(m) (__va(mfn_to_pfn(m) << PAGE_SHIFT))
@ -30,6 +30,8 @@ typedef struct xpaddr {
#define XMADDR(x) ((xmaddr_t) { .maddr = (x) })
#define XPADDR(x) ((xpaddr_t) { .paddr = (x) })
#define INVALID_P2M_ENTRY (~0UL)
static inline xmaddr_t phys_to_machine(xpaddr_t phys)
{
unsigned offset = phys.paddr & ~PAGE_MASK;
@ -74,9 +76,14 @@ static inline int m2p_remove_override(struct page *page, bool clear_pte)
return 0;
}
static inline bool __set_phys_to_machine(unsigned long pfn, unsigned long mfn)
{
BUG_ON(pfn != mfn && mfn != INVALID_P2M_ENTRY);
return true;
}
static inline bool set_phys_to_machine(unsigned long pfn, unsigned long mfn)
{
BUG();
return false;
return __set_phys_to_machine(pfn, mfn);
}
#endif /* _ASM_ARM_XEN_PAGE_H */

27
arch/arm/include/debug/8250_32.S Normal file
View File

@ -0,0 +1,27 @@
/*
* Copyright (c) 2011 Picochip Ltd., Jamie Iles
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Derived from arch/arm/mach-davinci/include/mach/debug-macro.S to use 32-bit
* accesses to the 8250.
*/
#include <linux/serial_reg.h>
.macro senduart,rd,rx
str \rd, [\rx, #UART_TX << UART_SHIFT]
.endm
.macro busyuart,rd,rx
1002: ldr \rd, [\rx, #UART_LSR << UART_SHIFT]
and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
teq \rd, #UART_LSR_TEMT | UART_LSR_THRE
bne 1002b
.endm
/* The UART's don't have any flow control IO's wired up. */
.macro waituart,rd,rx
.endm

18
arch/arm/include/debug/picoxcell.S
View File

@ -5,10 +5,7 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Derived from arch/arm/mach-davinci/include/mach/debug-macro.S to use 32-bit
* accesses to the 8250.
*/
#include <linux/serial_reg.h>
#define UART_SHIFT 2
#define PICOXCELL_UART1_BASE 0x80230000
@ -19,17 +16,4 @@
ldr \rp, =PICOXCELL_UART1_BASE
.endm
.macro senduart,rd,rx
str \rd, [\rx, #UART_TX << UART_SHIFT]
.endm
.macro busyuart,rd,rx
1002: ldr \rd, [\rx, #UART_LSR << UART_SHIFT]
and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
teq \rd, #UART_LSR_TEMT | UART_LSR_THRE
bne 1002b
.endm
/* The UART's don't have any flow control IO's wired up. */
.macro waituart,rd,rx
.endm
#include "8250_32.S"

5
arch/arm/include/debug/socfpga.S
View File

@ -7,6 +7,9 @@
* published by the Free Software Foundation.
*/
#define UART_SHIFT 2
#define DEBUG_LL_UART_OFFSET 0x00002000
.macro addruart, rp, rv, tmp
mov \rp, #DEBUG_LL_UART_OFFSET
orr \rp, \rp, #0x00c00000
@ -14,3 +17,5 @@
orr \rp, \rp, #0xff000000 @ physical base
.endm
#include "8250_32.S"

2
arch/arm/kernel/irq.c
View File

@ -34,6 +34,7 @@
#include <linux/list.h>
#include <linux/kallsyms.h>
#include <linux/proc_fs.h>
#include <linux/export.h>
#include <asm/exception.h>
#include <asm/mach/arch.h>
@ -109,6 +110,7 @@ void set_irq_flags(unsigned int irq, unsigned int iflags)
/* Order is clear bits in "clr" then set bits in "set" */
irq_modify_status(irq, clr, set & ~clr);
}
EXPORT_SYMBOL_GPL(set_irq_flags);
void __init init_IRQ(void)
{

4
arch/arm/kernel/kprobes-test-arm.c
View File

@ -366,7 +366,9 @@ void kprobe_arm_test_cases(void)
TEST_UNSUPPORTED(".word 0xe04f0392 @ umaal r0, pc, r2, r3")
TEST_UNSUPPORTED(".word 0xe0500090 @ undef")
TEST_UNSUPPORTED(".word 0xe05fff9f @ undef")
#endif
#if __LINUX_ARM_ARCH__ >= 7
TEST_RRR( "mls r0, r",1, VAL1,", r",2, VAL2,", r",3, VAL3,"")
TEST_RRR( "mlshi r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
TEST_RR( "mls lr, r",1, VAL2,", r",2, VAL3,", r13")
@ -456,6 +458,8 @@ void kprobe_arm_test_cases(void)
TEST_UNSUPPORTED(".word 0xe1700090") /* Unallocated space */
#if __LINUX_ARM_ARCH__ >= 6
TEST_UNSUPPORTED("ldrex r2, [sp]")
#endif
#if (__LINUX_ARM_ARCH__ >= 7) || defined(CONFIG_CPU_32v6K)
TEST_UNSUPPORTED("strexd r0, r2, r3, [sp]")
TEST_UNSUPPORTED("ldrexd r2, r3, [sp]")
TEST_UNSUPPORTED("strexb r0, r2, [sp]")

7
arch/arm/kernel/machine_kexec.c
View File

@ -45,10 +45,9 @@ int machine_kexec_prepare(struct kimage *image)
for (i = 0; i < image->nr_segments; i++) {
current_segment = &image->segment[i];
err = memblock_is_region_memory(current_segment->mem,
current_segment->memsz);
if (err)
return - EINVAL;
if (!memblock_is_region_memory(current_segment->mem,
current_segment->memsz))
return -EINVAL;
err = get_user(header, (__be32*)current_segment->buf);
if (err)

4
arch/arm/kernel/perf_event.c
View File

@ -96,6 +96,10 @@ armpmu_event_set_period(struct perf_event *event,
s64 period = hwc->sample_period;
int ret = 0;
/* The period may have been changed by PERF_EVENT_IOC_PERIOD */
if (unlikely(period != hwc->last_period))
left = period - (hwc->last_period - left);
if (unlikely(left <= -period)) {
left = period;
local64_set(&hwc->period_left, left);

14
arch/arm/kernel/smp.c
View File

@ -294,18 +294,24 @@ static void percpu_timer_setup(void);
asmlinkage void __cpuinit secondary_start_kernel(void)
{
struct mm_struct *mm = &init_mm;
unsigned int cpu = smp_processor_id();
unsigned int cpu;
/*
* The identity mapping is uncached (strongly ordered), so
* switch away from it before attempting any exclusive accesses.
*/
cpu_switch_mm(mm->pgd, mm);
enter_lazy_tlb(mm, current);
local_flush_tlb_all();
/*
* All kernel threads share the same mm context; grab a
* reference and switch to it.
*/
cpu = smp_processor_id();
atomic_inc(&mm->mm_count);
current->active_mm = mm;
cpumask_set_cpu(cpu, mm_cpumask(mm));
cpu_switch_mm(mm->pgd, mm);
enter_lazy_tlb(mm, current);
local_flush_tlb_all();
printk("CPU%u: Booted secondary processor\n", cpu);

4
arch/arm/kernel/smp_twd.c
View File

@ -42,10 +42,10 @@ static void twd_set_mode(enum clock_event_mode mode,
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
/* timer load already set up */
ctrl = TWD_TIMER_CONTROL_ENABLE | TWD_TIMER_CONTROL_IT_ENABLE
| TWD_TIMER_CONTROL_PERIODIC;
__raw_writel(twd_timer_rate / HZ, twd_base + TWD_TIMER_LOAD);
__raw_writel(DIV_ROUND_CLOSEST(twd_timer_rate, HZ),
twd_base + TWD_TIMER_LOAD);
break;
case CLOCK_EVT_MODE_ONESHOT:
/* period set, and timer enabled in 'next_event' hook */

1
arch/arm/lib/delay.c
View File

@ -45,6 +45,7 @@ int read_current_timer(unsigned long *timer_val)
*timer_val = delay_timer->read_current_timer();
return 0;
}
EXPORT_SYMBOL_GPL(read_current_timer);
static void __timer_delay(unsigned long cycles)
{

10
arch/arm/mach-at91/Kconfig
View File

@ -21,19 +21,13 @@ config SOC_AT91SAM9
bool
select CPU_ARM926T
select GENERIC_CLOCKEVENTS
select MULTI_IRQ_HANDLER
select SPARSE_IRQ
menu "Atmel AT91 System-on-Chip"
comment "Atmel AT91 Processor"
config SOC_AT91SAM9
bool
select AT91_SAM9_SMC
select AT91_SAM9_TIME
select CPU_ARM926T
select MULTI_IRQ_HANDLER
select SPARSE_IRQ
config SOC_AT91RM9200
bool "AT91RM9200"
select CPU_ARM920T

2
arch/arm/mach-at91/at91rm9200.c
View File

@ -187,7 +187,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk),
CLKDEV_CON_DEV_ID(NULL, "i2c-at91rm9200", &twi_clk),
CLKDEV_CON_DEV_ID(NULL, "i2c-at91rm9200.0", &twi_clk),
/* fake hclk clock */
CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
CLKDEV_CON_ID("pioA", &pioA_clk),

4
arch/arm/mach-at91/at91rm9200_devices.c
View File

@ -479,7 +479,7 @@ static struct i2c_gpio_platform_data pdata = {
static struct platform_device at91rm9200_twi_device = {
.name = "i2c-gpio",
.id = -1,
.id = 0,
.dev.platform_data = &pdata,
};
@ -512,7 +512,7 @@ static struct resource twi_resources[] = {
static struct platform_device at91rm9200_twi_device = {
.name = "i2c-at91rm9200",
.id = -1,
.id = 0,
.resource = twi_resources,
.num_resources = ARRAY_SIZE(twi_resources),
};

4
arch/arm/mach-at91/at91sam9260.c
View File

@ -211,8 +211,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc_clk),
CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9260", &twi_clk),
CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20", &twi_clk),
CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9260.0", &twi_clk),
CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi_clk),
/* more usart lookup table for DT entries */
CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk),

4
arch/arm/mach-at91/at91sam9260_devices.c
View File

@ -389,7 +389,7 @@ static struct i2c_gpio_platform_data pdata = {
static struct platform_device at91sam9260_twi_device = {
.name = "i2c-gpio",
.id = -1,
.id = 0,
.dev.platform_data = &pdata,
};
@ -421,7 +421,7 @@ static struct resource twi_resources[] = {
};
static struct platform_device at91sam9260_twi_device = {
.id = -1,
.id = 0,
.resource = twi_resources,
.num_resources = ARRAY_SIZE(twi_resources),
};

4
arch/arm/mach-at91/at91sam9261.c
View File

@ -178,8 +178,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk),
CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &hck0),
CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9261", &twi_clk),
CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10", &twi_clk),
CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9261.0", &twi_clk),
CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.0", &twi_clk),
CLKDEV_CON_ID("pioA", &pioA_clk),
CLKDEV_CON_ID("pioB", &pioB_clk),
CLKDEV_CON_ID("pioC", &pioC_clk),

4
arch/arm/mach-at91/at91sam9261_devices.c
View File

@ -285,7 +285,7 @@ static struct i2c_gpio_platform_data pdata = {
static struct platform_device at91sam9261_twi_device = {
.name = "i2c-gpio",
.id = -1,
.id = 0,
.dev.platform_data = &pdata,
};
@ -317,7 +317,7 @@ static struct resource twi_resources[] = {
};
static struct platform_device at91sam9261_twi_device = {
.id = -1,
.id = 0,
.resource = twi_resources,
.num_resources = ARRAY_SIZE(twi_resources),
};

2
arch/arm/mach-at91/at91sam9263.c
View File

@ -193,7 +193,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9260", &twi_clk),
CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9260.0", &twi_clk),
/* fake hclk clock */
CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
CLKDEV_CON_ID("pioA", &pioA_clk),

4
arch/arm/mach-at91/at91sam9263_devices.c
View File

@ -567,7 +567,7 @@ static struct i2c_gpio_platform_data pdata = {
static struct platform_device at91sam9263_twi_device = {
.name = "i2c-gpio",
.id = -1,
.id = 0,
.dev.platform_data = &pdata,
};
@ -600,7 +600,7 @@ static struct resource twi_resources[] = {
static struct platform_device at91sam9263_twi_device = {
.name = "i2c-at91sam9260",
.id = -1,
.id = 0,
.resource = twi_resources,
.num_resources = ARRAY_SIZE(twi_resources),
};

4
arch/arm/mach-at91/at91sam9rl_devices.c
View File

@ -314,7 +314,7 @@ static struct i2c_gpio_platform_data pdata = {
static struct platform_device at91sam9rl_twi_device = {
.name = "i2c-gpio",
.id = -1,
.id = 0,
.dev.platform_data = &pdata,
};
@ -347,7 +347,7 @@ static struct resource twi_resources[] = {
static struct platform_device at91sam9rl_twi_device = {
.name = "i2c-at91sam9g20",
.id = -1,
.id = 0,
.resource = twi_resources,
.num_resources = ARRAY_SIZE(twi_resources),
};

2
arch/arm/mach-at91/at91x40.c
View File

@ -88,6 +88,6 @@ void __init at91x40_init_interrupts(unsigned int priority[NR_AIC_IRQS])
if (!priority)
priority = at91x40_default_irq_priority;
at91_aic_init(priority);
at91_aic_init(priority, at91_extern_irq);
}

2
arch/arm/mach-at91/board-neocore926.c
View File

@ -129,7 +129,7 @@ static struct spi_board_info neocore926_spi_devices[] = {
.max_speed_hz = 125000 * 16,
.bus_num = 0,
.platform_data = &ads_info,
.irq = AT91SAM9263_ID_IRQ1,
.irq = NR_IRQS_LEGACY + AT91SAM9263_ID_IRQ1,
},
#endif
};

2
arch/arm/mach-at91/board-sam9261ek.c
View File

@ -309,7 +309,7 @@ static struct spi_board_info ek_spi_devices[] = {
.max_speed_hz = 125000 * 26, /* (max sample rate @ 3V) * (cmd + data + overhead) */
.bus_num = 0,
.platform_data = &ads_info,
.irq = AT91SAM9261_ID_IRQ0,
.irq = NR_IRQS_LEGACY + AT91SAM9261_ID_IRQ0,
.controller_data = (void *) AT91_PIN_PA28, /* CS pin */
},
#endif

2
arch/arm/mach-at91/board-sam9263ek.c
View File

@ -132,7 +132,7 @@ static struct spi_board_info ek_spi_devices[] = {
.max_speed_hz = 125000 * 26, /* (max sample rate @ 3V) * (cmd + data + overhead) */
.bus_num = 0,
.platform_data = &ads_info,
.irq = AT91SAM9263_ID_IRQ1,
.irq = NR_IRQS_LEGACY + AT91SAM9263_ID_IRQ1,
},
#endif
};

3
arch/arm/mach-at91/generic.h
View File

@ -26,7 +26,8 @@ extern void __init at91_dt_initialize(void);
extern void __init at91_init_irq_default(void);
extern void __init at91_init_interrupts(unsigned int priority[]);
extern void __init at91x40_init_interrupts(unsigned int priority[]);
extern void __init at91_aic_init(unsigned int priority[]);
extern void __init at91_aic_init(unsigned int priority[],
unsigned int ext_irq_mask);
extern int __init at91_aic_of_init(struct device_node *node,
struct device_node *parent);
extern int __init at91_aic5_of_init(struct device_node *node,

9
arch/arm/mach-at91/irq.c
View File

@ -502,14 +502,19 @@ int __init at91_aic5_of_init(struct device_node *node,
/*
* Initialize the AIC interrupt controller.
*/
void __init at91_aic_init(unsigned int *priority)
void __init at91_aic_init(unsigned int *priority, unsigned int ext_irq_mask)
{
unsigned int i;
int irq_base;
if (at91_aic_pm_init())
at91_extern_irq = kzalloc(BITS_TO_LONGS(n_irqs)
* sizeof(*at91_extern_irq), GFP_KERNEL);
if (at91_aic_pm_init() || at91_extern_irq == NULL)
panic("Unable to allocate bit maps\n");
*at91_extern_irq = ext_irq_mask;
at91_aic_base = ioremap(AT91_AIC, 512);
if (!at91_aic_base)
panic("Unable to ioremap AIC registers\n");

4
arch/arm/mach-at91/setup.c
View File

@ -47,7 +47,7 @@ void __init at91_init_irq_default(void)
void __init at91_init_interrupts(unsigned int *priority)
{
/* Initialize the AIC interrupt controller */
at91_aic_init(priority);
at91_aic_init(priority, at91_extern_irq);
/* Enable GPIO interrupts */
at91_gpio_irq_setup();
@ -151,7 +151,7 @@ static void __init soc_detect(u32 dbgu_base)
}
/* at91sam9g10 */
if ((cidr & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
if ((socid & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
at91_soc_initdata.type = AT91_SOC_SAM9G10;
at91_boot_soc = at91sam9261_soc;
}

5
arch/arm/mach-exynos/common.c
View File

@ -47,6 +47,7 @@
#include <plat/fimc-core.h>
#include <plat/iic-core.h>
#include <plat/tv-core.h>
#include <plat/spi-core.h>
#include <plat/regs-serial.h>
#include "common.h"
@ -346,6 +347,8 @@ static void __init exynos4_map_io(void)
s5p_fb_setname(0, "exynos4-fb");
s5p_hdmi_setname("exynos4-hdmi");
s3c64xx_spi_setname("exynos4210-spi");
}
static void __init exynos5_map_io(void)
@ -366,6 +369,8 @@ static void __init exynos5_map_io(void)
s3c_i2c0_setname("s3c2440-i2c");
s3c_i2c1_setname("s3c2440-i2c");
s3c_i2c2_setname("s3c2440-i2c");
s3c64xx_spi_setname("exynos4210-spi");
}
static void __init exynos4_init_clocks(int xtal)

1
arch/arm/mach-exynos/mach-exynos4-dt.c
View File

@ -99,6 +99,7 @@ static char const *exynos4_dt_compat[] __initdata = {
DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)")
/* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */
.smp = smp_ops(exynos_smp_ops),
.init_irq = exynos4_init_irq,
.map_io = exynos4_dt_map_io,
.handle_irq = gic_handle_irq,

2
arch/arm/mach-imx/clk-busy.c
View File

@ -108,7 +108,7 @@ struct clk *imx_clk_busy_divider(const char *name, const char *parent_name,
busy->div.hw.init = &init;
clk = clk_register(NULL, &busy->div.hw);
if (!clk)
if (IS_ERR(clk))
kfree(busy);
return clk;

4
arch/arm/mach-imx/clk-imx25.c
View File

@ -127,8 +127,8 @@ int __init mx25_clocks_init(void)
clk[esdhc2_ipg_per] = imx_clk_gate("esdhc2_ipg_per", "per4", ccm(CCM_CGCR0), 4);
clk[gpt_ipg_per] = imx_clk_gate("gpt_ipg_per", "per5", ccm(CCM_CGCR0), 5);
clk[i2c_ipg_per] = imx_clk_gate("i2c_ipg_per", "per6", ccm(CCM_CGCR0), 6);
clk[lcdc_ipg_per] = imx_clk_gate("lcdc_ipg_per", "per8", ccm(CCM_CGCR0), 7);
clk[nfc_ipg_per] = imx_clk_gate("nfc_ipg_per", "ipg_per", ccm(CCM_CGCR0), 8);
clk[lcdc_ipg_per] = imx_clk_gate("lcdc_ipg_per", "per7", ccm(CCM_CGCR0), 7);
clk[nfc_ipg_per] = imx_clk_gate("nfc_ipg_per", "per8", ccm(CCM_CGCR0), 8);
clk[ssi1_ipg_per] = imx_clk_gate("ssi1_ipg_per", "per13", ccm(CCM_CGCR0), 13);
clk[ssi2_ipg_per] = imx_clk_gate("ssi2_ipg_per", "per14", ccm(CCM_CGCR0), 14);
clk[uart_ipg_per] = imx_clk_gate("uart_ipg_per", "per15", ccm(CCM_CGCR0), 15);

4
arch/arm/mach-imx/clk-imx27.c
View File

@ -109,7 +109,7 @@ int __init mx27_clocks_init(unsigned long fref)
clk[per3_div] = imx_clk_divider("per3_div", "mpll_main2", CCM_PCDR1, 16, 6);
clk[per4_div] = imx_clk_divider("per4_div", "mpll_main2", CCM_PCDR1, 24, 6);
clk[vpu_sel] = imx_clk_mux("vpu_sel", CCM_CSCR, 21, 1, vpu_sel_clks, ARRAY_SIZE(vpu_sel_clks));
clk[vpu_div] = imx_clk_divider("vpu_div", "vpu_sel", CCM_PCDR0, 10, 3);
clk[vpu_div] = imx_clk_divider("vpu_div", "vpu_sel", CCM_PCDR0, 10, 6);
clk[usb_div] = imx_clk_divider("usb_div", "spll", CCM_CSCR, 28, 3);
clk[cpu_sel] = imx_clk_mux("cpu_sel", CCM_CSCR, 15, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks));
clk[clko_sel] = imx_clk_mux("clko_sel", CCM_CCSR, 0, 5, clko_sel_clks, ARRAY_SIZE(clko_sel_clks));
@ -121,7 +121,7 @@ int __init mx27_clocks_init(unsigned long fref)
clk[ssi1_sel] = imx_clk_mux("ssi1_sel", CCM_CSCR, 22, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
clk[ssi2_sel] = imx_clk_mux("ssi2_sel", CCM_CSCR, 23, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
clk[ssi1_div] = imx_clk_divider("ssi1_div", "ssi1_sel", CCM_PCDR0, 16, 6);
clk[ssi2_div] = imx_clk_divider("ssi2_div", "ssi2_sel", CCM_PCDR0, 26, 3);
clk[ssi2_div] = imx_clk_divider("ssi2_div", "ssi2_sel", CCM_PCDR0, 26, 6);
clk[clko_en] = imx_clk_gate("clko_en", "clko_div", CCM_PCCR0, 0);
clk[ssi2_ipg_gate] = imx_clk_gate("ssi2_ipg_gate", "ipg", CCM_PCCR0, 0);
clk[ssi1_ipg_gate] = imx_clk_gate("ssi1_ipg_gate", "ipg", CCM_PCCR0, 1);

5
arch/arm/mach-imx/mm-imx3.c
View File

@ -108,9 +108,8 @@ void __init imx3_init_l2x0(void)
}
l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096);
if (IS_ERR(l2x0_base)) {
printk(KERN_ERR "remapping L2 cache area failed with %ld\n",
PTR_ERR(l2x0_base));
if (!l2x0_base) {
printk(KERN_ERR "remapping L2 cache area failed\n");
return;
}

1
arch/arm/mach-omap2/Kconfig
View File

@ -11,7 +11,6 @@ config ARCH_OMAP2PLUS_TYPICAL
select I2C_OMAP
select MENELAUS if ARCH_OMAP2
select NEON if ARCH_OMAP3 || ARCH_OMAP4 || SOC_OMAP5
select PINCTRL
select PM_RUNTIME
select REGULATOR
select SERIAL_OMAP

22
arch/arm/mach-omap2/board-omap3beagle.c
View File

@ -24,6 +24,7 @@
#include <linux/input.h>
#include <linux/gpio_keys.h>
#include <linux/opp.h>
#include <linux/cpu.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
@ -447,27 +448,31 @@ static struct omap_board_mux board_mux[] __initdata = {
};
#endif
static void __init beagle_opp_init(void)
static int __init beagle_opp_init(void)
{
int r = 0;
/* Initialize the omap3 opp table */
if (omap3_opp_init()) {
if (!machine_is_omap3_beagle())
return 0;
/* Initialize the omap3 opp table if not already created. */
r = omap3_opp_init();
if (IS_ERR_VALUE(r) && (r != -EEXIST)) {
pr_err("%s: opp default init failed\n", __func__);
return;
return r;
}
/* Custom OPP enabled for all xM versions */
if (cpu_is_omap3630()) {
struct device *mpu_dev, *iva_dev;
mpu_dev = omap_device_get_by_hwmod_name("mpu");
mpu_dev = get_cpu_device(0);
iva_dev = omap_device_get_by_hwmod_name("iva");
if (IS_ERR(mpu_dev) || IS_ERR(iva_dev)) {
pr_err("%s: Aiee.. no mpu/dsp devices? %p %p\n",
__func__, mpu_dev, iva_dev);
return;
return -ENODEV;
}
/* Enable MPU 1GHz and lower opps */
r = opp_enable(mpu_dev, 800000000);
@ -487,8 +492,9 @@ static void __init beagle_opp_init(void)
opp_disable(iva_dev, 660000000);
}
}
return;
return 0;
}
device_initcall(beagle_opp_init);
static void __init omap3_beagle_init(void)
{
@ -526,8 +532,6 @@ static void __init omap3_beagle_init(void)
/* Ensure SDRC pins are mux'd for self-refresh */
omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
beagle_opp_init();
}
MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")

14
arch/arm/mach-omap2/clock33xx_data.c
View File

@ -547,16 +547,16 @@ static struct clk mcasp1_fck = {
.recalc = &followparent_recalc,
};
static struct clk smartreflex0_fck = {
.name = "smartreflex0_fck",
static struct clk smartreflex_mpu_fck = {
.name = "smartreflex_mpu_fck",
.clkdm_name = "l4_wkup_clkdm",
.parent = &sys_clkin_ck,
.ops = &clkops_null,
.recalc = &followparent_recalc,
};
static struct clk smartreflex1_fck = {
.name = "smartreflex1_fck",
static struct clk smartreflex_core_fck = {
.name = "smartreflex_core_fck",
.clkdm_name = "l4_wkup_clkdm",
.parent = &sys_clkin_ck,
.ops = &clkops_null,
@ -1038,8 +1038,8 @@ static struct omap_clk am33xx_clks[] = {
CLK(NULL, "mcasp1_fck", &mcasp1_fck, CK_AM33XX),
CLK("NULL", "mmc2_fck", &mmc2_fck, CK_AM33XX),
CLK(NULL, "mmu_fck", &mmu_fck, CK_AM33XX),
CLK(NULL, "smartreflex0_fck", &smartreflex0_fck, CK_AM33XX),
CLK(NULL, "smartreflex1_fck", &smartreflex1_fck, CK_AM33XX),
CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_AM33XX),
CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_AM33XX),
CLK(NULL, "timer1_fck", &timer1_fck, CK_AM33XX),
CLK(NULL, "timer2_fck", &timer2_fck, CK_AM33XX),
CLK(NULL, "timer3_fck", &timer3_fck, CK_AM33XX),
@ -1072,6 +1072,8 @@ static struct omap_clk am33xx_clks[] = {
CLK(NULL, "gfx_fck_div_ck", &gfx_fck_div_ck, CK_AM33XX),
CLK(NULL, "sysclkout_pre_ck", &sysclkout_pre_ck, CK_AM33XX),
CLK(NULL, "clkout2_ck", &clkout2_ck, CK_AM33XX),
CLK(NULL, "timer_32k_ck", &clkdiv32k_ick, CK_AM33XX),
CLK(NULL, "timer_sys_ck", &sys_clkin_ck, CK_AM33XX),
};
int __init am33xx_clk_init(void)

12
arch/arm/mach-omap2/clock3xxx_data.c
View File

@ -3048,8 +3048,8 @@ static struct clk traceclk_fck = {
/* SR clocks */
/* SmartReflex fclk (VDD1) */
static struct clk sr1_fck = {
.name = "sr1_fck",
static struct clk smartreflex_mpu_iva_fck = {
.name = "smartreflex_mpu_iva_fck",
.ops = &clkops_omap2_dflt_wait,
.parent = &sys_ck,
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
@ -3059,8 +3059,8 @@ static struct clk sr1_fck = {
};
/* SmartReflex fclk (VDD2) */
static struct clk sr2_fck = {
.name = "sr2_fck",
static struct clk smartreflex_core_fck = {
.name = "smartreflex_core_fck",
.ops = &clkops_omap2_dflt_wait,
.parent = &sys_ck,
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
@ -3476,8 +3476,8 @@ static struct omap_clk omap3xxx_clks[] = {
CLK(NULL, "atclk_fck", &atclk_fck, CK_3XXX),
CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_3XXX),
CLK(NULL, "traceclk_fck", &traceclk_fck, CK_3XXX),
CLK(NULL, "sr1_fck", &sr1_fck, CK_34XX | CK_36XX),
CLK(NULL, "sr2_fck", &sr2_fck, CK_34XX | CK_36XX),
CLK(NULL, "smartreflex_mpu_iva_fck", &smartreflex_mpu_iva_fck, CK_34XX | CK_36XX),
CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_34XX | CK_36XX),
CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_34XX | CK_36XX),
CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_3XXX),
CLK(NULL, "gpt12_fck", &gpt12_fck, CK_3XXX),

6
arch/arm/mach-omap2/clock44xx_data.c
View File

@ -3224,9 +3224,9 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0, CK_443X),
CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk, CK_443X),
CLK(NULL, "slimbus2_fck", &slimbus2_fck, CK_443X),
CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_443X),
CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X),
CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_443X),
CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_443X),
CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X),
CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_443X),
CLK(NULL, "timer1_fck", &timer1_fck, CK_443X),
CLK(NULL, "timer10_fck", &timer10_fck, CK_443X),
CLK(NULL, "timer11_fck", &timer11_fck, CK_443X),

1
arch/arm/mach-omap2/control.h
View File

@ -201,6 +201,7 @@
#define OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO 0x249
#define OMAP44XX_CONTROL_FUSE_CORE_OPP50 0x254
#define OMAP44XX_CONTROL_FUSE_CORE_OPP100 0x257
#define OMAP44XX_CONTROL_FUSE_CORE_OPP100OV 0x25A
/* AM35XX only CONTROL_GENERAL register offsets */
#define AM35XX_CONTROL_MSUSPENDMUX_6 (OMAP2_CONTROL_GENERAL + 0x0038)

8
arch/arm/mach-omap2/mux34xx.c
View File

@ -614,16 +614,16 @@ static struct omap_mux __initdata omap3_muxmodes[] = {
"sys_off_mode", NULL, NULL, NULL,
"gpio_9", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(UART1_CTS, 150,
"uart1_cts", NULL, NULL, NULL,
"uart1_cts", "ssi1_rdy_tx", NULL, NULL,
"gpio_150", "hsusb3_tll_clk", NULL, "safe_mode"),
_OMAP3_MUXENTRY(UART1_RTS, 149,
"uart1_rts", NULL, NULL, NULL,
"uart1_rts", "ssi1_flag_tx", NULL, NULL,
"gpio_149", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(UART1_RX, 151,
"uart1_rx", NULL, "mcbsp1_clkr", "mcspi4_clk",
"uart1_rx", "ss1_wake_tx", "mcbsp1_clkr", "mcspi4_clk",
"gpio_151", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(UART1_TX, 148,
"uart1_tx", NULL, NULL, NULL,
"uart1_tx", "ssi1_dat_tx", NULL, NULL,
"gpio_148", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(UART2_CTS, 144,
"uart2_cts", "mcbsp3_dx", "gpt9_pwm_evt", NULL,

8
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
View File

@ -1410,7 +1410,7 @@ static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
static struct omap_hwmod omap34xx_sr1_hwmod = {
.name = "smartreflex_mpu_iva",
.class = &omap34xx_smartreflex_hwmod_class,
.main_clk = "sr1_fck",
.main_clk = "smartreflex_mpu_iva_fck",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
@ -1428,7 +1428,7 @@ static struct omap_hwmod omap34xx_sr1_hwmod = {
static struct omap_hwmod omap36xx_sr1_hwmod = {
.name = "smartreflex_mpu_iva",
.class = &omap36xx_smartreflex_hwmod_class,
.main_clk = "sr1_fck",
.main_clk = "smartreflex_mpu_iva_fck",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
@ -1455,7 +1455,7 @@ static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
static struct omap_hwmod omap34xx_sr2_hwmod = {
.name = "smartreflex_core",
.class = &omap34xx_smartreflex_hwmod_class,
.main_clk = "sr2_fck",
.main_clk = "smartreflex_core_fck",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
@ -1473,7 +1473,7 @@ static struct omap_hwmod omap34xx_sr2_hwmod = {
static struct omap_hwmod omap36xx_sr2_hwmod = {
.name = "smartreflex_core",
.class = &omap36xx_smartreflex_hwmod_class,
.main_clk = "sr2_fck",
.main_clk = "smartreflex_core_fck",
.prcm = {
.omap2 = {
.prcm_reg_id = 1,

9
arch/arm/mach-omap2/omap_opp_data.h
View File

@ -89,8 +89,11 @@ extern struct omap_volt_data omap34xx_vddcore_volt_data[];
extern struct omap_volt_data omap36xx_vddmpu_volt_data[];
extern struct omap_volt_data omap36xx_vddcore_volt_data[];
extern struct omap_volt_data omap44xx_vdd_mpu_volt_data[];
extern struct omap_volt_data omap44xx_vdd_iva_volt_data[];
extern struct omap_volt_data omap44xx_vdd_core_volt_data[];
extern struct omap_volt_data omap443x_vdd_mpu_volt_data[];
extern struct omap_volt_data omap443x_vdd_iva_volt_data[];
extern struct omap_volt_data omap443x_vdd_core_volt_data[];
extern struct omap_volt_data omap446x_vdd_mpu_volt_data[];
extern struct omap_volt_data omap446x_vdd_iva_volt_data[];
extern struct omap_volt_data omap446x_vdd_core_volt_data[];
#endif /* __ARCH_ARM_MACH_OMAP2_OMAP_OPP_DATA_H */

73
arch/arm/mach-omap2/omap_twl.c
View File

@ -31,16 +31,6 @@
#define OMAP3_VP_VSTEPMAX_VSTEPMAX 0x04
#define OMAP3_VP_VLIMITTO_TIMEOUT_US 200
#define OMAP3430_VP1_VLIMITTO_VDDMIN 0x14
#define OMAP3430_VP1_VLIMITTO_VDDMAX 0x42
#define OMAP3430_VP2_VLIMITTO_VDDMIN 0x18
#define OMAP3430_VP2_VLIMITTO_VDDMAX 0x2c
#define OMAP3630_VP1_VLIMITTO_VDDMIN 0x18
#define OMAP3630_VP1_VLIMITTO_VDDMAX 0x3c
#define OMAP3630_VP2_VLIMITTO_VDDMIN 0x18
#define OMAP3630_VP2_VLIMITTO_VDDMAX 0x30
#define OMAP4_SRI2C_SLAVE_ADDR 0x12
#define OMAP4_VDD_MPU_SR_VOLT_REG 0x55
#define OMAP4_VDD_MPU_SR_CMD_REG 0x56
@ -54,13 +44,6 @@
#define OMAP4_VP_VSTEPMAX_VSTEPMAX 0x04
#define OMAP4_VP_VLIMITTO_TIMEOUT_US 200
#define OMAP4_VP_MPU_VLIMITTO_VDDMIN 0xA
#define OMAP4_VP_MPU_VLIMITTO_VDDMAX 0x39
#define OMAP4_VP_IVA_VLIMITTO_VDDMIN 0xA
#define OMAP4_VP_IVA_VLIMITTO_VDDMAX 0x2D
#define OMAP4_VP_CORE_VLIMITTO_VDDMIN 0xA
#define OMAP4_VP_CORE_VLIMITTO_VDDMAX 0x28
static bool is_offset_valid;
static u8 smps_offset;
/*
@ -159,16 +142,11 @@ static u8 twl6030_uv_to_vsel(unsigned long uv)
static struct omap_voltdm_pmic omap3_mpu_pmic = {
.slew_rate = 4000,
.step_size = 12500,
.on_volt = 1200000,
.onlp_volt = 1000000,
.ret_volt = 975000,
.off_volt = 600000,
.volt_setup_time = 0xfff,
.vp_erroroffset = OMAP3_VP_CONFIG_ERROROFFSET,
.vp_vstepmin = OMAP3_VP_VSTEPMIN_VSTEPMIN,
.vp_vstepmax = OMAP3_VP_VSTEPMAX_VSTEPMAX,
.vp_vddmin = OMAP3430_VP1_VLIMITTO_VDDMIN,
.vp_vddmax = OMAP3430_VP1_VLIMITTO_VDDMAX,
.vddmin = 600000,
.vddmax = 1450000,
.vp_timeout_us = OMAP3_VP_VLIMITTO_TIMEOUT_US,
.i2c_slave_addr = OMAP3_SRI2C_SLAVE_ADDR,
.volt_reg_addr = OMAP3_VDD_MPU_SR_CONTROL_REG,
@ -180,16 +158,11 @@ static struct omap_voltdm_pmic omap3_mpu_pmic = {
static struct omap_voltdm_pmic omap3_core_pmic = {
.slew_rate = 4000,
.step_size = 12500,
.on_volt = 1200000,
.onlp_volt = 1000000,
.ret_volt = 975000,
.off_volt = 600000,
.volt_setup_time = 0xfff,
.vp_erroroffset = OMAP3_VP_CONFIG_ERROROFFSET,
.vp_vstepmin = OMAP3_VP_VSTEPMIN_VSTEPMIN,
.vp_vstepmax = OMAP3_VP_VSTEPMAX_VSTEPMAX,
.vp_vddmin = OMAP3430_VP2_VLIMITTO_VDDMIN,
.vp_vddmax = OMAP3430_VP2_VLIMITTO_VDDMAX,
.vddmin = 600000,
.vddmax = 1450000,
.vp_timeout_us = OMAP3_VP_VLIMITTO_TIMEOUT_US,
.i2c_slave_addr = OMAP3_SRI2C_SLAVE_ADDR,
.volt_reg_addr = OMAP3_VDD_CORE_SR_CONTROL_REG,
@ -201,21 +174,17 @@ static struct omap_voltdm_pmic omap3_core_pmic = {
static struct omap_voltdm_pmic omap4_mpu_pmic = {
.slew_rate = 4000,
.step_size = 12660,
.on_volt = 1375000,
.onlp_volt = 1375000,
.ret_volt = 830000,
.off_volt = 0,
.volt_setup_time = 0,
.vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET,
.vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN,
.vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX,
.vp_vddmin = OMAP4_VP_MPU_VLIMITTO_VDDMIN,
.vp_vddmax = OMAP4_VP_MPU_VLIMITTO_VDDMAX,
.vddmin = 0,
.vddmax = 2100000,
.vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
.i2c_slave_addr = OMAP4_SRI2C_SLAVE_ADDR,
.volt_reg_addr = OMAP4_VDD_MPU_SR_VOLT_REG,
.cmd_reg_addr = OMAP4_VDD_MPU_SR_CMD_REG,
.i2c_high_speed = true,
.i2c_pad_load = 3,
.vsel_to_uv = twl6030_vsel_to_uv,
.uv_to_vsel = twl6030_uv_to_vsel,
};
@ -223,21 +192,17 @@ static struct omap_voltdm_pmic omap4_mpu_pmic = {
static struct omap_voltdm_pmic omap4_iva_pmic = {
.slew_rate = 4000,
.step_size = 12660,
.on_volt = 1188000,
.onlp_volt = 1188000,
.ret_volt = 830000,
.off_volt = 0,
.volt_setup_time = 0,
.vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET,
.vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN,
.vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX,
.vp_vddmin = OMAP4_VP_IVA_VLIMITTO_VDDMIN,
.vp_vddmax = OMAP4_VP_IVA_VLIMITTO_VDDMAX,
.vddmin = 0,
.vddmax = 2100000,
.vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
.i2c_slave_addr = OMAP4_SRI2C_SLAVE_ADDR,
.volt_reg_addr = OMAP4_VDD_IVA_SR_VOLT_REG,
.cmd_reg_addr = OMAP4_VDD_IVA_SR_CMD_REG,
.i2c_high_speed = true,
.i2c_pad_load = 3,
.vsel_to_uv = twl6030_vsel_to_uv,
.uv_to_vsel = twl6030_uv_to_vsel,
};
@ -245,20 +210,17 @@ static struct omap_voltdm_pmic omap4_iva_pmic = {
static struct omap_voltdm_pmic omap4_core_pmic = {
.slew_rate = 4000,
.step_size = 12660,
.on_volt = 1200000,
.onlp_volt = 1200000,
.ret_volt = 830000,
.off_volt = 0,
.volt_setup_time = 0,
.vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET,
.vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN,
.vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX,
.vp_vddmin = OMAP4_VP_CORE_VLIMITTO_VDDMIN,
.vp_vddmax = OMAP4_VP_CORE_VLIMITTO_VDDMAX,
.vddmin = 0,
.vddmax = 2100000,
.vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
.i2c_slave_addr = OMAP4_SRI2C_SLAVE_ADDR,
.volt_reg_addr = OMAP4_VDD_CORE_SR_VOLT_REG,
.cmd_reg_addr = OMAP4_VDD_CORE_SR_CMD_REG,
.i2c_high_speed = true,
.i2c_pad_load = 3,
.vsel_to_uv = twl6030_vsel_to_uv,
.uv_to_vsel = twl6030_uv_to_vsel,
};
@ -289,13 +251,6 @@ int __init omap3_twl_init(void)
if (!cpu_is_omap34xx())
return -ENODEV;
if (cpu_is_omap3630()) {
omap3_mpu_pmic.vp_vddmin = OMAP3630_VP1_VLIMITTO_VDDMIN;
omap3_mpu_pmic.vp_vddmax = OMAP3630_VP1_VLIMITTO_VDDMAX;
omap3_core_pmic.vp_vddmin = OMAP3630_VP2_VLIMITTO_VDDMIN;
omap3_core_pmic.vp_vddmax = OMAP3630_VP2_VLIMITTO_VDDMAX;
}
/*
* The smartreflex bit on twl4030 specifies if the setting of voltage
* is done over the I2C_SR path. Since this setting is independent of

98
arch/arm/mach-omap2/opp4xxx_data.c
View File

@ -1,7 +1,7 @@
/*
* OMAP4 OPP table definitions.
*
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2010-2012 Texas Instruments Incorporated - http://www.ti.com/
* Nishanth Menon
* Kevin Hilman
* Thara Gopinath
@ -35,7 +35,7 @@
#define OMAP4430_VDD_MPU_OPPTURBO_UV 1313000
#define OMAP4430_VDD_MPU_OPPNITRO_UV 1375000
struct omap_volt_data omap44xx_vdd_mpu_volt_data[] = {
struct omap_volt_data omap443x_vdd_mpu_volt_data[] = {
VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP50_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP50, 0xf4, 0x0c),
VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP100_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP100, 0xf9, 0x16),
VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPTURBO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO, 0xfa, 0x23),
@ -47,7 +47,7 @@ struct omap_volt_data omap44xx_vdd_mpu_volt_data[] = {
#define OMAP4430_VDD_IVA_OPP100_UV 1188000
#define OMAP4430_VDD_IVA_OPPTURBO_UV 1300000
struct omap_volt_data omap44xx_vdd_iva_volt_data[] = {
struct omap_volt_data omap443x_vdd_iva_volt_data[] = {
VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPP50_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP50, 0xf4, 0x0c),
VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPP100_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP100, 0xf9, 0x16),
VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPPTURBO_UV, OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO, 0xfa, 0x23),
@ -57,14 +57,14 @@ struct omap_volt_data omap44xx_vdd_iva_volt_data[] = {
#define OMAP4430_VDD_CORE_OPP50_UV 1025000
#define OMAP4430_VDD_CORE_OPP100_UV 1200000
struct omap_volt_data omap44xx_vdd_core_volt_data[] = {
struct omap_volt_data omap443x_vdd_core_volt_data[] = {
VOLT_DATA_DEFINE(OMAP4430_VDD_CORE_OPP50_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP50, 0xf4, 0x0c),
VOLT_DATA_DEFINE(OMAP4430_VDD_CORE_OPP100_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP100, 0xf9, 0x16),
VOLT_DATA_DEFINE(0, 0, 0, 0),
};
static struct omap_opp_def __initdata omap44xx_opp_def_list[] = {
static struct omap_opp_def __initdata omap443x_opp_def_list[] = {
/* MPU OPP1 - OPP50 */
OPP_INITIALIZER("mpu", true, 300000000, OMAP4430_VDD_MPU_OPP50_UV),
/* MPU OPP2 - OPP100 */
@ -86,6 +86,82 @@ static struct omap_opp_def __initdata omap44xx_opp_def_list[] = {
/* TODO: add DSP, aess, fdif, gpu */
};
#define OMAP4460_VDD_MPU_OPP50_UV 1025000
#define OMAP4460_VDD_MPU_OPP100_UV 1200000
#define OMAP4460_VDD_MPU_OPPTURBO_UV 1313000
#define OMAP4460_VDD_MPU_OPPNITRO_UV 1375000
struct omap_volt_data omap446x_vdd_mpu_volt_data[] = {
VOLT_DATA_DEFINE(OMAP4460_VDD_MPU_OPP50_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP50, 0xf4, 0x0c),
VOLT_DATA_DEFINE(OMAP4460_VDD_MPU_OPP100_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP100, 0xf9, 0x16),
VOLT_DATA_DEFINE(OMAP4460_VDD_MPU_OPPTURBO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO, 0xfa, 0x23),
VOLT_DATA_DEFINE(OMAP4460_VDD_MPU_OPPNITRO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO, 0xfa, 0x27),
VOLT_DATA_DEFINE(0, 0, 0, 0),
};
#define OMAP4460_VDD_IVA_OPP50_UV 1025000
#define OMAP4460_VDD_IVA_OPP100_UV 1200000
#define OMAP4460_VDD_IVA_OPPTURBO_UV 1313000
#define OMAP4460_VDD_IVA_OPPNITRO_UV 1375000
struct omap_volt_data omap446x_vdd_iva_volt_data[] = {
VOLT_DATA_DEFINE(OMAP4460_VDD_IVA_OPP50_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP50, 0xf4, 0x0c),
VOLT_DATA_DEFINE(OMAP4460_VDD_IVA_OPP100_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP100, 0xf9, 0x16),
VOLT_DATA_DEFINE(OMAP4460_VDD_IVA_OPPTURBO_UV, OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO, 0xfa, 0x23),
VOLT_DATA_DEFINE(OMAP4460_VDD_IVA_OPPNITRO_UV, OMAP44XX_CONTROL_FUSE_IVA_OPPNITRO, 0xfa, 0x23),
VOLT_DATA_DEFINE(0, 0, 0, 0),
};
#define OMAP4460_VDD_CORE_OPP50_UV 1025000
#define OMAP4460_VDD_CORE_OPP100_UV 1200000
#define OMAP4460_VDD_CORE_OPP100_OV_UV 1250000
struct omap_volt_data omap446x_vdd_core_volt_data[] = {
VOLT_DATA_DEFINE(OMAP4460_VDD_CORE_OPP50_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP50, 0xf4, 0x0c),
VOLT_DATA_DEFINE(OMAP4460_VDD_CORE_OPP100_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP100, 0xf9, 0x16),
VOLT_DATA_DEFINE(OMAP4460_VDD_CORE_OPP100_OV_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP100OV, 0xf9, 0x16),
VOLT_DATA_DEFINE(0, 0, 0, 0),
};
static struct omap_opp_def __initdata omap446x_opp_def_list[] = {
/* MPU OPP1 - OPP50 */
OPP_INITIALIZER("mpu", true, 350000000, OMAP4460_VDD_MPU_OPP50_UV),
/* MPU OPP2 - OPP100 */
OPP_INITIALIZER("mpu", true, 700000000, OMAP4460_VDD_MPU_OPP100_UV),
/* MPU OPP3 - OPP-Turbo */
OPP_INITIALIZER("mpu", true, 920000000, OMAP4460_VDD_MPU_OPPTURBO_UV),
/*
* MPU OPP4 - OPP-Nitro + Disabled as the reference schematics
* recommends TPS623631 - confirm and enable the opp in board file
* XXX: May be we should enable these based on mpu capability and
* Exception board files disable it...
*/
OPP_INITIALIZER("mpu", false, 1200000000, OMAP4460_VDD_MPU_OPPNITRO_UV),
/* MPU OPP4 - OPP-Nitro SpeedBin */
OPP_INITIALIZER("mpu", false, 1500000000, OMAP4460_VDD_MPU_OPPNITRO_UV),
/* L3 OPP1 - OPP50 */
OPP_INITIALIZER("l3_main_1", true, 100000000, OMAP4460_VDD_CORE_OPP50_UV),
/* L3 OPP2 - OPP100 */
OPP_INITIALIZER("l3_main_1", true, 200000000, OMAP4460_VDD_CORE_OPP100_UV),
/* IVA OPP1 - OPP50 */
OPP_INITIALIZER("iva", true, 133000000, OMAP4460_VDD_IVA_OPP50_UV),
/* IVA OPP2 - OPP100 */
OPP_INITIALIZER("iva", true, 266100000, OMAP4460_VDD_IVA_OPP100_UV),
/*
* IVA OPP3 - OPP-Turbo + Disabled as the reference schematics
* recommends Phoenix VCORE2 which can supply only 600mA - so the ones
* above this OPP frequency, even though OMAP is capable, should be
* enabled by board file which is sure of the chip power capability
*/
OPP_INITIALIZER("iva", false, 332000000, OMAP4460_VDD_IVA_OPPTURBO_UV),
/* IVA OPP4 - OPP-Nitro */
OPP_INITIALIZER("iva", false, 430000000, OMAP4460_VDD_IVA_OPPNITRO_UV),
/* IVA OPP5 - OPP-Nitro SpeedBin*/
OPP_INITIALIZER("iva", false, 500000000, OMAP4460_VDD_IVA_OPPNITRO_UV),
/* TODO: add DSP, aess, fdif, gpu */
};
/**
* omap4_opp_init() - initialize omap4 opp table
*/
@ -93,12 +169,12 @@ int __init omap4_opp_init(void)
{
int r = -ENODEV;
if (!cpu_is_omap443x())
return r;
r = omap_init_opp_table(omap44xx_opp_def_list,
ARRAY_SIZE(omap44xx_opp_def_list));
if (cpu_is_omap443x())
r = omap_init_opp_table(omap443x_opp_def_list,
ARRAY_SIZE(omap443x_opp_def_list));
else if (cpu_is_omap446x())
r = omap_init_opp_table(omap446x_opp_def_list,
ARRAY_SIZE(omap446x_opp_def_list));
return r;
}
device_initcall(omap4_opp_init);

30
arch/arm/mach-omap2/pm.c
View File

@ -40,6 +40,36 @@ static struct omap_device_pm_latency *pm_lats;
*/
int (*omap_pm_suspend)(void);
/**
* struct omap2_oscillator - Describe the board main oscillator latencies
* @startup_time: oscillator startup latency
* @shutdown_time: oscillator shutdown latency
*/
struct omap2_oscillator {
u32 startup_time;
u32 shutdown_time;
};
static struct omap2_oscillator oscillator = {
.startup_time = ULONG_MAX,
.shutdown_time = ULONG_MAX,
};
void omap_pm_setup_oscillator(u32 tstart, u32 tshut)
{
oscillator.startup_time = tstart;
oscillator.shutdown_time = tshut;
}
void omap_pm_get_oscillator(u32 *tstart, u32 *tshut)
{
if (!tstart || !tshut)
return;
*tstart = oscillator.startup_time;
*tshut = oscillator.shutdown_time;
}
static int __init _init_omap_device(char *name)
{
struct omap_hwmod *oh;

11
arch/arm/mach-omap2/pm.h
View File

@ -91,6 +91,7 @@ extern void omap3_save_scratchpad_contents(void);
#define PM_RTA_ERRATUM_i608 (1 << 0)
#define PM_SDRC_WAKEUP_ERRATUM_i583 (1 << 1)
#define PM_PER_MEMORIES_ERRATUM_i582 (1 << 2)
#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
extern u16 pm34xx_errata;
@ -128,4 +129,14 @@ static inline int omap4_twl_init(void)
}
#endif
#ifdef CONFIG_PM
extern void omap_pm_setup_oscillator(u32 tstart, u32 tshut);
extern void omap_pm_get_oscillator(u32 *tstart, u32 *tshut);
extern void omap_pm_setup_sr_i2c_pcb_length(u32 mm);
#else
static inline void omap_pm_setup_oscillator(u32 tstart, u32 tshut) { }
static inline void omap_pm_get_oscillator(u32 *tstart, u32 *tshut) { }
static inline void omap_pm_setup_sr_i2c_pcb_length(u32 mm) { }
#endif
#endif

30
arch/arm/mach-omap2/pm34xx.c
View File

@ -651,14 +651,17 @@ static void __init pm_errata_configure(void)
/* Enable the l2 cache toggling in sleep logic */
enable_omap3630_toggle_l2_on_restore();
if (omap_rev() < OMAP3630_REV_ES1_2)
pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583;
pm34xx_errata |= (PM_SDRC_WAKEUP_ERRATUM_i583 |
PM_PER_MEMORIES_ERRATUM_i582);
} else if (cpu_is_omap34xx()) {
pm34xx_errata |= PM_PER_MEMORIES_ERRATUM_i582;
}
}
int __init omap3_pm_init(void)
{
struct power_state *pwrst, *tmp;
struct clockdomain *neon_clkdm, *mpu_clkdm;
struct clockdomain *neon_clkdm, *mpu_clkdm, *per_clkdm, *wkup_clkdm;
int ret;
if (!omap3_has_io_chain_ctrl())
@ -710,6 +713,8 @@ int __init omap3_pm_init(void)
neon_clkdm = clkdm_lookup("neon_clkdm");
mpu_clkdm = clkdm_lookup("mpu_clkdm");
per_clkdm = clkdm_lookup("per_clkdm");
wkup_clkdm = clkdm_lookup("wkup_clkdm");
#ifdef CONFIG_SUSPEND
omap_pm_suspend = omap3_pm_suspend;
@ -726,6 +731,27 @@ int __init omap3_pm_init(void)
if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
omap3630_ctrl_disable_rta();
/*
* The UART3/4 FIFO and the sidetone memory in McBSP2/3 are
* not correctly reset when the PER powerdomain comes back
* from OFF or OSWR when the CORE powerdomain is kept active.
* See OMAP36xx Erratum i582 "PER Domain reset issue after
* Domain-OFF/OSWR Wakeup". This wakeup dependency is not a
* complete workaround. The kernel must also prevent the PER
* powerdomain from going to OSWR/OFF while the CORE
* powerdomain is not going to OSWR/OFF. And if PER last
* power state was off while CORE last power state was ON, the
* UART3/4 and McBSP2/3 SIDETONE devices need to run a
* self-test using their loopback tests; if that fails, those
* devices are unusable until the PER/CORE can complete a transition
* from ON to OSWR/OFF and then back to ON.
*
* XXX Technically this workaround is only needed if off-mode
* or OSWR is enabled.
*/
if (IS_PM34XX_ERRATUM(PM_PER_MEMORIES_ERRATUM_i582))
clkdm_add_wkdep(per_clkdm, wkup_clkdm);
clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
omap3_secure_ram_storage =

5
arch/arm/mach-omap2/serial.c
View File

@ -330,6 +330,11 @@ void __init omap_serial_init_port(struct omap_board_data *bdata,
oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
if (console_uart_id == bdata->id) {
omap_device_enable(pdev);
pm_runtime_set_active(&pdev->dev);
}
oh->dev_attr = uart;
if (((cpu_is_omap34xx() || cpu_is_omap44xx()) && bdata->pads)

13
arch/arm/mach-omap2/sr_device.c
View File

@ -121,6 +121,19 @@ static int __init sr_dev_init(struct omap_hwmod *oh, void *user)
sr_data->senn_mod = 0x1;
sr_data->senp_mod = 0x1;
if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
sr_data->err_weight = OMAP3430_SR_ERRWEIGHT;
sr_data->err_maxlimit = OMAP3430_SR_ERRMAXLIMIT;
sr_data->accum_data = OMAP3430_SR_ACCUMDATA;
if (!(strcmp(sr_data->name, "smartreflex_mpu"))) {
sr_data->senn_avgweight = OMAP3430_SR1_SENNAVGWEIGHT;
sr_data->senp_avgweight = OMAP3430_SR1_SENPAVGWEIGHT;
} else {
sr_data->senn_avgweight = OMAP3430_SR2_SENNAVGWEIGHT;
sr_data->senp_avgweight = OMAP3430_SR2_SENPAVGWEIGHT;
}
}
sr_data->voltdm = voltdm_lookup(sr_dev_attr->sensor_voltdm_name);
if (!sr_data->voltdm) {
pr_err("%s: Unable to get voltage domain pointer for VDD %s\n",

465
arch/arm/mach-omap2/vc.c
View File

@ -11,13 +11,20 @@
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/bug.h>
#include <linux/io.h>
#include <asm/div64.h>
#include "iomap.h"
#include "soc.h"
#include "voltage.h"
#include "vc.h"
#include "prm-regbits-34xx.h"
#include "prm-regbits-44xx.h"
#include "prm44xx.h"
#include "pm.h"
#include "scrm44xx.h"
#include "control.h"
/**
* struct omap_vc_channel_cfg - describe the cfg_channel bitfield
@ -63,6 +70,9 @@ static struct omap_vc_channel_cfg vc_mutant_channel_cfg = {
};
static struct omap_vc_channel_cfg *vc_cfg_bits;
/* Default I2C trace length on pcb, 6.3cm. Used for capacitance calculations. */
static u32 sr_i2c_pcb_length = 63;
#define CFG_CHANNEL_MASK 0x1f
/**
@ -135,6 +145,8 @@ int omap_vc_pre_scale(struct voltagedomain *voltdm,
vc_cmdval |= (*target_vsel << vc->common->cmd_on_shift);
voltdm->write(vc_cmdval, vc->cmdval_reg);
voltdm->vc_param->on = target_volt;
omap_vp_update_errorgain(voltdm, target_volt);
return 0;
@ -202,46 +214,389 @@ int omap_vc_bypass_scale(struct voltagedomain *voltdm,
return 0;
}
static void __init omap3_vfsm_init(struct voltagedomain *voltdm)
/* Convert microsecond value to number of 32kHz clock cycles */
static inline u32 omap_usec_to_32k(u32 usec)
{
return DIV_ROUND_UP_ULL(32768ULL * (u64)usec, 1000000ULL);
}
/* Set oscillator setup time for omap3 */
static void omap3_set_clksetup(u32 usec, struct voltagedomain *voltdm)
{
voltdm->write(omap_usec_to_32k(usec), OMAP3_PRM_CLKSETUP_OFFSET);
}
/**
* omap3_set_i2c_timings - sets i2c sleep timings for a channel
* @voltdm: channel to configure
* @off_mode: select whether retention or off mode values used
*
* Calculates and sets up voltage controller to use I2C based
* voltage scaling for sleep modes. This can be used for either off mode
* or retention. Off mode has additionally an option to use sys_off_mode
* pad, which uses a global signal to program the whole power IC to
* off-mode.
*/
static void omap3_set_i2c_timings(struct voltagedomain *voltdm, bool off_mode)
{
unsigned long voltsetup1;
u32 tgt_volt;
/*
* Voltage Manager FSM parameters init
* XXX This data should be passed in from the board file
* Oscillator is shut down only if we are using sys_off_mode pad,
* thus we set a minimal setup time here
*/
voltdm->write(OMAP3_CLKSETUP, OMAP3_PRM_CLKSETUP_OFFSET);
voltdm->write(OMAP3_VOLTOFFSET, OMAP3_PRM_VOLTOFFSET_OFFSET);
voltdm->write(OMAP3_VOLTSETUP2, OMAP3_PRM_VOLTSETUP2_OFFSET);
omap3_set_clksetup(1, voltdm);
if (off_mode)
tgt_volt = voltdm->vc_param->off;
else
tgt_volt = voltdm->vc_param->ret;
voltsetup1 = (voltdm->vc_param->on - tgt_volt) /
voltdm->pmic->slew_rate;
voltsetup1 = voltsetup1 * voltdm->sys_clk.rate / 8 / 1000000 + 1;
voltdm->rmw(voltdm->vfsm->voltsetup_mask,
voltsetup1 << __ffs(voltdm->vfsm->voltsetup_mask),
voltdm->vfsm->voltsetup_reg);
/*
* pmic is not controlling the voltage scaling during retention,
* thus set voltsetup2 to 0
*/
voltdm->write(0, OMAP3_PRM_VOLTSETUP2_OFFSET);
}
/**
* omap3_set_off_timings - sets off-mode timings for a channel
* @voltdm: channel to configure
*
* Calculates and sets up off-mode timings for a channel. Off-mode
* can use either I2C based voltage scaling, or alternatively
* sys_off_mode pad can be used to send a global command to power IC.
* This function first checks which mode is being used, and calls
* omap3_set_i2c_timings() if the system is using I2C control mode.
* sys_off_mode has the additional benefit that voltages can be
* scaled to zero volt level with TWL4030 / TWL5030, I2C can only
* scale to 600mV.
*/
static void omap3_set_off_timings(struct voltagedomain *voltdm)
{
unsigned long clksetup;
unsigned long voltsetup2;
unsigned long voltsetup2_old;
u32 val;
u32 tstart, tshut;
/* check if sys_off_mode is used to control off-mode voltages */
val = voltdm->read(OMAP3_PRM_VOLTCTRL_OFFSET);
if (!(val & OMAP3430_SEL_OFF_MASK)) {
/* No, omap is controlling them over I2C */
omap3_set_i2c_timings(voltdm, true);
return;
}
omap_pm_get_oscillator(&tstart, &tshut);
omap3_set_clksetup(tstart, voltdm);
clksetup = voltdm->read(OMAP3_PRM_CLKSETUP_OFFSET);
/* voltsetup 2 in us */
voltsetup2 = voltdm->vc_param->on / voltdm->pmic->slew_rate;
/* convert to 32k clk cycles */
voltsetup2 = DIV_ROUND_UP(voltsetup2 * 32768, 1000000);
voltsetup2_old = voltdm->read(OMAP3_PRM_VOLTSETUP2_OFFSET);
/*
* Update voltsetup2 if higher than current value (needed because
* we have multiple channels with different ramp times), also
* update voltoffset always to value recommended by TRM
*/
if (voltsetup2 > voltsetup2_old) {
voltdm->write(voltsetup2, OMAP3_PRM_VOLTSETUP2_OFFSET);
voltdm->write(clksetup - voltsetup2,
OMAP3_PRM_VOLTOFFSET_OFFSET);
} else
voltdm->write(clksetup - voltsetup2_old,
OMAP3_PRM_VOLTOFFSET_OFFSET);
/*
* omap is not controlling voltage scaling during off-mode,
* thus set voltsetup1 to 0
*/
voltdm->rmw(voltdm->vfsm->voltsetup_mask, 0,
voltdm->vfsm->voltsetup_reg);
/* voltoffset must be clksetup minus voltsetup2 according to TRM */
voltdm->write(clksetup - voltsetup2, OMAP3_PRM_VOLTOFFSET_OFFSET);
}
static void __init omap3_vc_init_channel(struct voltagedomain *voltdm)
{
static bool is_initialized;
if (is_initialized)
return;
omap3_vfsm_init(voltdm);
is_initialized = true;
omap3_set_off_timings(voltdm);
}
/**
* omap4_calc_volt_ramp - calculates voltage ramping delays on omap4
* @voltdm: channel to calculate values for
* @voltage_diff: voltage difference in microvolts
*
* Calculates voltage ramp prescaler + counter values for a voltage
* difference on omap4. Returns a field value suitable for writing to
* VOLTSETUP register for a channel in following format:
* bits[8:9] prescaler ... bits[0:5] counter. See OMAP4 TRM for reference.
*/
static u32 omap4_calc_volt_ramp(struct voltagedomain *voltdm, u32 voltage_diff)
{
u32 prescaler;
u32 cycles;
u32 time;
time = voltage_diff / voltdm->pmic->slew_rate;
cycles = voltdm->sys_clk.rate / 1000 * time / 1000;
cycles /= 64;
prescaler = 0;
/* shift to next prescaler until no overflow */
/* scale for div 256 = 64 * 4 */
if (cycles > 63) {
cycles /= 4;
prescaler++;
}
/* scale for div 512 = 256 * 2 */
if (cycles > 63) {
cycles /= 2;
prescaler++;
}
/* scale for div 2048 = 512 * 4 */
if (cycles > 63) {
cycles /= 4;
prescaler++;
}
/* check for overflow => invalid ramp time */
if (cycles > 63) {
pr_warn("%s: invalid setuptime for vdd_%s\n", __func__,
voltdm->name);
return 0;
}
cycles++;
return (prescaler << OMAP4430_RAMP_UP_PRESCAL_SHIFT) |
(cycles << OMAP4430_RAMP_UP_COUNT_SHIFT);
}
/**
* omap4_usec_to_val_scrm - convert microsecond value to SCRM module bitfield
* @usec: microseconds
* @shift: number of bits to shift left
* @mask: bitfield mask
*
* Converts microsecond value to OMAP4 SCRM bitfield. Bitfield is
* shifted to requested position, and checked agains the mask value.
* If larger, forced to the max value of the field (i.e. the mask itself.)
* Returns the SCRM bitfield value.
*/
static u32 omap4_usec_to_val_scrm(u32 usec, int shift, u32 mask)
{
u32 val;
val = omap_usec_to_32k(usec) << shift;
/* Check for overflow, if yes, force to max value */
if (val > mask)
val = mask;
return val;
}
/**
* omap4_set_timings - set voltage ramp timings for a channel
* @voltdm: channel to configure
* @off_mode: whether off-mode values are used
*
* Calculates and sets the voltage ramp up / down values for a channel.
*/
static void omap4_set_timings(struct voltagedomain *voltdm, bool off_mode)
{
u32 val;
u32 ramp;
int offset;
u32 tstart, tshut;
if (off_mode) {
ramp = omap4_calc_volt_ramp(voltdm,
voltdm->vc_param->on - voltdm->vc_param->off);
offset = voltdm->vfsm->voltsetup_off_reg;
} else {
ramp = omap4_calc_volt_ramp(voltdm,
voltdm->vc_param->on - voltdm->vc_param->ret);
offset = voltdm->vfsm->voltsetup_reg;
}
if (!ramp)
return;
val = voltdm->read(offset);
val |= ramp << OMAP4430_RAMP_DOWN_COUNT_SHIFT;
val |= ramp << OMAP4430_RAMP_UP_COUNT_SHIFT;
voltdm->write(val, offset);
omap_pm_get_oscillator(&tstart, &tshut);
val = omap4_usec_to_val_scrm(tstart, OMAP4_SETUPTIME_SHIFT,
OMAP4_SETUPTIME_MASK);
val |= omap4_usec_to_val_scrm(tshut, OMAP4_DOWNTIME_SHIFT,
OMAP4_DOWNTIME_MASK);
__raw_writel(val, OMAP4_SCRM_CLKSETUPTIME);
}
/* OMAP4 specific voltage init functions */
static void __init omap4_vc_init_channel(struct voltagedomain *voltdm)
{
static bool is_initialized;
u32 vc_val;
if (is_initialized)
return;
/* XXX These are magic numbers and do not belong! */
vc_val = (0x60 << OMAP4430_SCLL_SHIFT | 0x26 << OMAP4430_SCLH_SHIFT);
voltdm->write(vc_val, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET);
is_initialized = true;
omap4_set_timings(voltdm, true);
omap4_set_timings(voltdm, false);
}
struct i2c_init_data {
u8 loadbits;
u8 load;
u8 hsscll_38_4;
u8 hsscll_26;
u8 hsscll_19_2;
u8 hsscll_16_8;
u8 hsscll_12;
};
static const __initdata struct i2c_init_data omap4_i2c_timing_data[] = {
{
.load = 50,
.loadbits = 0x3,
.hsscll_38_4 = 13,
.hsscll_26 = 11,
.hsscll_19_2 = 9,
.hsscll_16_8 = 9,
.hsscll_12 = 8,
},
{
.load = 25,
.loadbits = 0x2,
.hsscll_38_4 = 13,
.hsscll_26 = 11,
.hsscll_19_2 = 9,
.hsscll_16_8 = 9,
.hsscll_12 = 8,
},
{
.load = 12,
.loadbits = 0x1,
.hsscll_38_4 = 11,
.hsscll_26 = 10,
.hsscll_19_2 = 9,
.hsscll_16_8 = 9,
.hsscll_12 = 8,
},
{
.load = 0,
.loadbits = 0x0,
.hsscll_38_4 = 12,
.hsscll_26 = 10,
.hsscll_19_2 = 9,
.hsscll_16_8 = 8,
.hsscll_12 = 8,
},
};
/**
* omap4_vc_i2c_timing_init - sets up board I2C timing parameters
* @voltdm: voltagedomain pointer to get data from
*
* Use PMIC + board supplied settings for calculating the total I2C
* channel capacitance and set the timing parameters based on this.
* Pre-calculated values are provided in data tables, as it is not
* too straightforward to calculate these runtime.
*/
static void __init omap4_vc_i2c_timing_init(struct voltagedomain *voltdm)
{
u32 capacitance;
u32 val;
u16 hsscll;
const struct i2c_init_data *i2c_data;
if (!voltdm->pmic->i2c_high_speed) {
pr_warn("%s: only high speed supported!\n", __func__);
return;
}
/* PCB trace capacitance, 0.125pF / mm => mm / 8 */
capacitance = DIV_ROUND_UP(sr_i2c_pcb_length, 8);
/* OMAP pad capacitance */
capacitance += 4;
/* PMIC pad capacitance */
capacitance += voltdm->pmic->i2c_pad_load;
/* Search for capacitance match in the table */
i2c_data = omap4_i2c_timing_data;
while (i2c_data->load > capacitance)
i2c_data++;
/* Select proper values based on sysclk frequency */
switch (voltdm->sys_clk.rate) {
case 38400000:
hsscll = i2c_data->hsscll_38_4;
break;
case 26000000:
hsscll = i2c_data->hsscll_26;
break;
case 19200000:
hsscll = i2c_data->hsscll_19_2;
break;
case 16800000:
hsscll = i2c_data->hsscll_16_8;
break;
case 12000000:
hsscll = i2c_data->hsscll_12;
break;
default:
pr_warn("%s: unsupported sysclk rate: %d!\n", __func__,
voltdm->sys_clk.rate);
return;
}
/* Loadbits define pull setup for the I2C channels */
val = i2c_data->loadbits << 25 | i2c_data->loadbits << 29;
/* Write to SYSCTRL_PADCONF_WKUP_CTRL_I2C_2 to setup I2C pull */
__raw_writel(val, OMAP2_L4_IO_ADDRESS(OMAP4_CTRL_MODULE_PAD_WKUP +
OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2));
/* HSSCLH can always be zero */
val = hsscll << OMAP4430_HSSCLL_SHIFT;
val |= (0x28 << OMAP4430_SCLL_SHIFT | 0x2c << OMAP4430_SCLH_SHIFT);
/* Write setup times to I2C config register */
voltdm->write(val, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET);
}
/**
* omap_vc_i2c_init - initialize I2C interface to PMIC
* @voltdm: voltage domain containing VC data
@ -281,9 +636,49 @@ static void __init omap_vc_i2c_init(struct voltagedomain *voltdm)
mcode << __ffs(vc->common->i2c_mcode_mask),
vc->common->i2c_cfg_reg);
if (cpu_is_omap44xx())
omap4_vc_i2c_timing_init(voltdm);
initialized = true;
}
/**
* omap_vc_calc_vsel - calculate vsel value for a channel
* @voltdm: channel to calculate value for
* @uvolt: microvolt value to convert to vsel
*
* Converts a microvolt value to vsel value for the used PMIC.
* This checks whether the microvolt value is out of bounds, and
* adjusts the value accordingly. If unsupported value detected,
* warning is thrown.
*/
static u8 omap_vc_calc_vsel(struct voltagedomain *voltdm, u32 uvolt)
{
if (voltdm->pmic->vddmin > uvolt)
uvolt = voltdm->pmic->vddmin;
if (voltdm->pmic->vddmax < uvolt) {
WARN(1, "%s: voltage not supported by pmic: %u vs max %u\n",
__func__, uvolt, voltdm->pmic->vddmax);
/* Lets try maximum value anyway */
uvolt = voltdm->pmic->vddmax;
}
return voltdm->pmic->uv_to_vsel(uvolt);
}
/**
* omap_pm_setup_sr_i2c_pcb_length - set length of SR I2C traces on PCB
* @mm: length of the PCB trace in millimetres
*
* Sets the PCB trace length for the I2C channel. By default uses 63mm.
* This is needed for properly calculating the capacitance value for
* the PCB trace, and for setting the SR I2C channel timing parameters.
*/
void __init omap_pm_setup_sr_i2c_pcb_length(u32 mm)
{
sr_i2c_pcb_length = mm;
}
void __init omap_vc_init_channel(struct voltagedomain *voltdm)
{
struct omap_vc_channel *vc = voltdm->vc;
@ -311,7 +706,6 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm)
vc->i2c_slave_addr = voltdm->pmic->i2c_slave_addr;
vc->volt_reg_addr = voltdm->pmic->volt_reg_addr;
vc->cmd_reg_addr = voltdm->pmic->cmd_reg_addr;
vc->setup_time = voltdm->pmic->volt_setup_time;
/* Configure the i2c slave address for this VC */
voltdm->rmw(vc->smps_sa_mask,
@ -331,14 +725,18 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm)
voltdm->rmw(vc->smps_cmdra_mask,
vc->cmd_reg_addr << __ffs(vc->smps_cmdra_mask),
vc->smps_cmdra_reg);
vc->cfg_channel |= vc_cfg_bits->rac | vc_cfg_bits->racen;
vc->cfg_channel |= vc_cfg_bits->rac;
}
if (vc->cmd_reg_addr == vc->volt_reg_addr)
vc->cfg_channel |= vc_cfg_bits->racen;
/* Set up the on, inactive, retention and off voltage */
on_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->on_volt);
onlp_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->onlp_volt);
ret_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->ret_volt);
off_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->off_volt);
on_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->on);
onlp_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->onlp);
ret_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->ret);
off_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->off);
val = ((on_vsel << vc->common->cmd_on_shift) |
(onlp_vsel << vc->common->cmd_onlp_shift) |
(ret_vsel << vc->common->cmd_ret_shift) |
@ -349,11 +747,6 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm)
/* Channel configuration */
omap_vc_config_channel(voltdm);
/* Configure the setup times */
voltdm->rmw(voltdm->vfsm->voltsetup_mask,
vc->setup_time << __ffs(voltdm->vfsm->voltsetup_mask),
voltdm->vfsm->voltsetup_reg);
omap_vc_i2c_init(voltdm);
if (cpu_is_omap34xx())

8
arch/arm/mach-omap2/vc.h
View File

@ -86,7 +86,6 @@ struct omap_vc_channel {
u16 i2c_slave_addr;
u16 volt_reg_addr;
u16 cmd_reg_addr;
u16 setup_time;
u8 cfg_channel;
bool i2c_high_speed;
@ -111,6 +110,13 @@ extern struct omap_vc_channel omap4_vc_mpu;
extern struct omap_vc_channel omap4_vc_iva;
extern struct omap_vc_channel omap4_vc_core;
extern struct omap_vc_param omap3_mpu_vc_data;
extern struct omap_vc_param omap3_core_vc_data;
extern struct omap_vc_param omap4_mpu_vc_data;
extern struct omap_vc_param omap4_iva_vc_data;
extern struct omap_vc_param omap4_core_vc_data;
void omap_vc_init_channel(struct voltagedomain *voltdm);
int omap_vc_pre_scale(struct voltagedomain *voltdm,
unsigned long target_volt,

22
arch/arm/mach-omap2/vc3xxx_data.c
View File

@ -71,3 +71,25 @@ struct omap_vc_channel omap3_vc_core = {
.smps_cmdra_mask = OMAP3430_CMDRA1_MASK,
.cfg_channel_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT,
};
/*
* Voltage levels for different operating modes: on, sleep, retention and off
*/
#define OMAP3_ON_VOLTAGE_UV 1200000
#define OMAP3_ONLP_VOLTAGE_UV 1000000
#define OMAP3_RET_VOLTAGE_UV 975000
#define OMAP3_OFF_VOLTAGE_UV 600000
struct omap_vc_param omap3_mpu_vc_data = {
.on = OMAP3_ON_VOLTAGE_UV,
.onlp = OMAP3_ONLP_VOLTAGE_UV,
.ret = OMAP3_RET_VOLTAGE_UV,
.off = OMAP3_OFF_VOLTAGE_UV,
};
struct omap_vc_param omap3_core_vc_data = {
.on = OMAP3_ON_VOLTAGE_UV,
.onlp = OMAP3_ONLP_VOLTAGE_UV,
.ret = OMAP3_RET_VOLTAGE_UV,
.off = OMAP3_OFF_VOLTAGE_UV,
};

28
arch/arm/mach-omap2/vc44xx_data.c
View File

@ -87,3 +87,31 @@ struct omap_vc_channel omap4_vc_core = {
.cfg_channel_sa_shift = OMAP4430_SA_VDD_CORE_L_SHIFT,
};
/*
* Voltage levels for different operating modes: on, sleep, retention and off
*/
#define OMAP4_ON_VOLTAGE_UV 1375000
#define OMAP4_ONLP_VOLTAGE_UV 1375000
#define OMAP4_RET_VOLTAGE_UV 837500
#define OMAP4_OFF_VOLTAGE_UV 0
struct omap_vc_param omap4_mpu_vc_data = {
.on = OMAP4_ON_VOLTAGE_UV,
.onlp = OMAP4_ONLP_VOLTAGE_UV,
.ret = OMAP4_RET_VOLTAGE_UV,
.off = OMAP4_OFF_VOLTAGE_UV,
};
struct omap_vc_param omap4_iva_vc_data = {
.on = OMAP4_ON_VOLTAGE_UV,
.onlp = OMAP4_ONLP_VOLTAGE_UV,
.ret = OMAP4_RET_VOLTAGE_UV,
.off = OMAP4_OFF_VOLTAGE_UV,
};
struct omap_vc_param omap4_core_vc_data = {
.on = OMAP4_ON_VOLTAGE_UV,
.onlp = OMAP4_ONLP_VOLTAGE_UV,
.ret = OMAP4_RET_VOLTAGE_UV,
.off = OMAP4_OFF_VOLTAGE_UV,
};

44
arch/arm/mach-omap2/voltage.h
View File

@ -40,12 +40,14 @@ struct powerdomain;
* data
* @voltsetup_mask: SETUP_TIME* bitmask in the PRM_VOLTSETUP* register
* @voltsetup_reg: register offset of PRM_VOLTSETUP from PRM base
* @voltsetup_off_reg: register offset of PRM_VOLTSETUP_OFF from PRM base
*
* XXX What about VOLTOFFSET/VOLTCTRL?
*/
struct omap_vfsm_instance {
u32 voltsetup_mask;
u8 voltsetup_reg;
u8 voltsetup_off_reg;
};
/**
@ -74,6 +76,8 @@ struct voltagedomain {
const struct omap_vfsm_instance *vfsm;
struct omap_vp_instance *vp;
struct omap_voltdm_pmic *pmic;
struct omap_vp_param *vp_param;
struct omap_vc_param *vc_param;
/* VC/VP register access functions: SoC specific */
u32 (*read) (u8 offset);
@ -92,6 +96,24 @@ struct voltagedomain {
struct omap_volt_data *volt_data;
};
/* Min and max voltages from OMAP perspective */
#define OMAP3430_VP1_VLIMITTO_VDDMIN 850000
#define OMAP3430_VP1_VLIMITTO_VDDMAX 1425000
#define OMAP3430_VP2_VLIMITTO_VDDMIN 900000
#define OMAP3430_VP2_VLIMITTO_VDDMAX 1150000
#define OMAP3630_VP1_VLIMITTO_VDDMIN 900000
#define OMAP3630_VP1_VLIMITTO_VDDMAX 1350000
#define OMAP3630_VP2_VLIMITTO_VDDMIN 900000
#define OMAP3630_VP2_VLIMITTO_VDDMAX 1200000
#define OMAP4_VP_MPU_VLIMITTO_VDDMIN 830000
#define OMAP4_VP_MPU_VLIMITTO_VDDMAX 1410000
#define OMAP4_VP_IVA_VLIMITTO_VDDMIN 830000
#define OMAP4_VP_IVA_VLIMITTO_VDDMAX 1260000
#define OMAP4_VP_CORE_VLIMITTO_VDDMIN 830000
#define OMAP4_VP_CORE_VLIMITTO_VDDMAX 1200000
/**
* struct omap_voltdm_pmic - PMIC specific data required by voltage driver.
* @slew_rate: PMIC slew rate (in uv/us)
@ -107,26 +129,34 @@ struct voltagedomain {
struct omap_voltdm_pmic {
int slew_rate;
int step_size;
u32 on_volt;
u32 onlp_volt;
u32 ret_volt;
u32 off_volt;
u16 volt_setup_time;
u16 i2c_slave_addr;
u16 volt_reg_addr;
u16 cmd_reg_addr;
u8 vp_erroroffset;
u8 vp_vstepmin;
u8 vp_vstepmax;
u8 vp_vddmin;
u8 vp_vddmax;
u32 vddmin;
u32 vddmax;
u8 vp_timeout_us;
bool i2c_high_speed;
u32 i2c_pad_load;
u8 i2c_mcode;
unsigned long (*vsel_to_uv) (const u8 vsel);
u8 (*uv_to_vsel) (unsigned long uV);
};
struct omap_vp_param {
u32 vddmax;
u32 vddmin;
};
struct omap_vc_param {
u32 on;
u32 onlp;
u32 ret;
u32 off;
};
void omap_voltage_get_volttable(struct voltagedomain *voltdm,
struct omap_volt_data **volt_data);
struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm,

5
arch/arm/mach-omap2/voltagedomains3xxx_data.c
View File

@ -117,6 +117,11 @@ void __init omap3xxx_voltagedomains_init(void)
}
#endif
omap3_voltdm_mpu.vp_param = &omap3_mpu_vp_data;
omap3_voltdm_core.vp_param = &omap3_core_vp_data;
omap3_voltdm_mpu.vc_param = &omap3_mpu_vc_data;
omap3_voltdm_core.vc_param = &omap3_core_vc_data;
if (soc_is_am35xx())
voltdms = voltagedomains_am35xx;
else

25
arch/arm/mach-omap2/voltagedomains44xx_data.c
View File

@ -22,7 +22,7 @@
#include <linux/init.h>
#include "common.h"
#include "soc.h"
#include "prm-regbits-44xx.h"
#include "prm44xx.h"
#include "prcm44xx.h"
@ -34,14 +34,17 @@
static const struct omap_vfsm_instance omap4_vdd_mpu_vfsm = {
.voltsetup_reg = OMAP4_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET,
.voltsetup_off_reg = OMAP4_PRM_VOLTSETUP_MPU_OFF_OFFSET,
};
static const struct omap_vfsm_instance omap4_vdd_iva_vfsm = {
.voltsetup_reg = OMAP4_PRM_VOLTSETUP_IVA_RET_SLEEP_OFFSET,
.voltsetup_off_reg = OMAP4_PRM_VOLTSETUP_IVA_OFF_OFFSET,
};
static const struct omap_vfsm_instance omap4_vdd_core_vfsm = {
.voltsetup_reg = OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET,
.voltsetup_off_reg = OMAP4_PRM_VOLTSETUP_CORE_OFF_OFFSET,
};
static struct voltagedomain omap4_voltdm_mpu = {
@ -101,11 +104,25 @@ void __init omap44xx_voltagedomains_init(void)
* for the currently-running IC
*/
#ifdef CONFIG_PM_OPP
omap4_voltdm_mpu.volt_data = omap44xx_vdd_mpu_volt_data;
omap4_voltdm_iva.volt_data = omap44xx_vdd_iva_volt_data;
omap4_voltdm_core.volt_data = omap44xx_vdd_core_volt_data;
if (cpu_is_omap443x()) {
omap4_voltdm_mpu.volt_data = omap443x_vdd_mpu_volt_data;
omap4_voltdm_iva.volt_data = omap443x_vdd_iva_volt_data;
omap4_voltdm_core.volt_data = omap443x_vdd_core_volt_data;
} else if (cpu_is_omap446x()) {
omap4_voltdm_mpu.volt_data = omap446x_vdd_mpu_volt_data;
omap4_voltdm_iva.volt_data = omap446x_vdd_iva_volt_data;
omap4_voltdm_core.volt_data = omap446x_vdd_core_volt_data;
}
#endif
omap4_voltdm_mpu.vp_param = &omap4_mpu_vp_data;
omap4_voltdm_iva.vp_param = &omap4_iva_vp_data;
omap4_voltdm_core.vp_param = &omap4_core_vp_data;
omap4_voltdm_mpu.vc_param = &omap4_mpu_vc_data;
omap4_voltdm_iva.vc_param = &omap4_iva_vc_data;
omap4_voltdm_core.vc_param = &omap4_core_vc_data;
for (i = 0; voltdm = voltagedomains_omap4[i], voltdm; i++)
voltdm->sys_clk.name = sys_clk_name;

19
arch/arm/mach-omap2/vp.c
View File

@ -58,8 +58,10 @@ void __init omap_vp_init(struct voltagedomain *voltdm)
sys_clk_rate = voltdm->sys_clk.rate / 1000;
timeout = (sys_clk_rate * voltdm->pmic->vp_timeout_us) / 1000;
vddmin = voltdm->pmic->vp_vddmin;
vddmax = voltdm->pmic->vp_vddmax;
vddmin = max(voltdm->vp_param->vddmin, voltdm->pmic->vddmin);
vddmax = min(voltdm->vp_param->vddmax, voltdm->pmic->vddmax);
vddmin = voltdm->pmic->uv_to_vsel(vddmin);
vddmax = voltdm->pmic->uv_to_vsel(vddmax);
waittime = DIV_ROUND_UP(voltdm->pmic->step_size * sys_clk_rate,
1000 * voltdm->pmic->slew_rate);
@ -138,7 +140,7 @@ int omap_vp_forceupdate_scale(struct voltagedomain *voltdm,
udelay(1);
}
if (timeout >= VP_TRANXDONE_TIMEOUT) {
pr_warn("%s: vdd_%s TRANXDONE timeout exceeded. Voltage change aborted",
pr_warn("%s: vdd_%s TRANXDONE timeout exceeded. Voltage change aborted\n",
__func__, voltdm->name);
return -ETIMEDOUT;
}
@ -197,7 +199,7 @@ void omap_vp_enable(struct voltagedomain *voltdm)
u32 vpconfig, volt;
if (!voltdm || IS_ERR(voltdm)) {
pr_warning("%s: VDD specified does not exist!\n", __func__);
pr_warn("%s: VDD specified does not exist!\n", __func__);
return;
}
@ -214,8 +216,8 @@ void omap_vp_enable(struct voltagedomain *voltdm)
volt = voltdm_get_voltage(voltdm);
if (!volt) {
pr_warning("%s: unable to find current voltage for %s\n",
__func__, voltdm->name);
pr_warn("%s: unable to find current voltage for %s\n",
__func__, voltdm->name);
return;
}
@ -242,7 +244,7 @@ void omap_vp_disable(struct voltagedomain *voltdm)
int timeout;
if (!voltdm || IS_ERR(voltdm)) {
pr_warning("%s: VDD specified does not exist!\n", __func__);
pr_warn("%s: VDD specified does not exist!\n", __func__);
return;
}
@ -272,8 +274,7 @@ void omap_vp_disable(struct voltagedomain *voltdm)
VP_IDLE_TIMEOUT, timeout);
if (timeout >= VP_IDLE_TIMEOUT)
pr_warning("%s: vdd_%s idle timedout\n",
__func__, voltdm->name);
pr_warn("%s: vdd_%s idle timedout\n", __func__, voltdm->name);
vp->enabled = false;

7
arch/arm/mach-omap2/vp.h
View File

@ -117,6 +117,13 @@ extern struct omap_vp_instance omap4_vp_mpu;
extern struct omap_vp_instance omap4_vp_iva;
extern struct omap_vp_instance omap4_vp_core;
extern struct omap_vp_param omap3_mpu_vp_data;
extern struct omap_vp_param omap3_core_vp_data;
extern struct omap_vp_param omap4_mpu_vp_data;
extern struct omap_vp_param omap4_iva_vp_data;
extern struct omap_vp_param omap4_core_vp_data;
void omap_vp_init(struct voltagedomain *voltdm);
void omap_vp_enable(struct voltagedomain *voltdm);
void omap_vp_disable(struct voltagedomain *voltdm);

10
arch/arm/mach-omap2/vp3xxx_data.c
View File

@ -77,3 +77,13 @@ struct omap_vp_instance omap3_vp_core = {
.vstatus = OMAP3_PRM_VP2_STATUS_OFFSET,
.voltage = OMAP3_PRM_VP2_VOLTAGE_OFFSET,
};
struct omap_vp_param omap3_mpu_vp_data = {
.vddmin = OMAP3430_VP1_VLIMITTO_VDDMIN,
.vddmax = OMAP3430_VP1_VLIMITTO_VDDMAX,
};
struct omap_vp_param omap3_core_vp_data = {
.vddmin = OMAP3430_VP2_VLIMITTO_VDDMIN,
.vddmax = OMAP3430_VP2_VLIMITTO_VDDMAX,
};

15
arch/arm/mach-omap2/vp44xx_data.c
View File

@ -87,3 +87,18 @@ struct omap_vp_instance omap4_vp_core = {
.vstatus = OMAP4_PRM_VP_CORE_STATUS_OFFSET,
.voltage = OMAP4_PRM_VP_CORE_VOLTAGE_OFFSET,
};
struct omap_vp_param omap4_mpu_vp_data = {
.vddmin = OMAP4_VP_MPU_VLIMITTO_VDDMIN,
.vddmax = OMAP4_VP_MPU_VLIMITTO_VDDMAX,
};
struct omap_vp_param omap4_iva_vp_data = {
.vddmin = OMAP4_VP_IVA_VLIMITTO_VDDMIN,
.vddmax = OMAP4_VP_IVA_VLIMITTO_VDDMAX,
};
struct omap_vp_param omap4_core_vp_data = {
.vddmin = OMAP4_VP_CORE_VLIMITTO_VDDMIN,
.vddmax = OMAP4_VP_CORE_VLIMITTO_VDDMAX,
};

2
arch/arm/mach-s3c24xx/s3c2416.c
View File

@ -61,6 +61,7 @@
#include <plat/nand-core.h>
#include <plat/adc-core.h>
#include <plat/rtc-core.h>
#include <plat/spi-core.h>
static struct map_desc s3c2416_iodesc[] __initdata = {
IODESC_ENT(WATCHDOG),
@ -132,6 +133,7 @@ void __init s3c2416_map_io(void)
/* initialize device information early */
s3c2416_default_sdhci0();
s3c2416_default_sdhci1();
s3c64xx_spi_setname("s3c2443-spi");
iotable_init(s3c2416_iodesc, ARRAY_SIZE(s3c2416_iodesc));
}

4
arch/arm/mach-s3c24xx/s3c2443.c
View File

@ -43,6 +43,7 @@
#include <plat/nand-core.h>
#include <plat/adc-core.h>
#include <plat/rtc-core.h>
#include <plat/spi-core.h>
static struct map_desc s3c2443_iodesc[] __initdata = {
IODESC_ENT(WATCHDOG),
@ -100,6 +101,9 @@ void __init s3c2443_map_io(void)
s3c24xx_gpiocfg_default.set_pull = s3c2443_gpio_setpull;
s3c24xx_gpiocfg_default.get_pull = s3c2443_gpio_getpull;
/* initialize device information early */
s3c64xx_spi_setname("s3c2443-spi");
iotable_init(s3c2443_iodesc, ARRAY_SIZE(s3c2443_iodesc));
}

3
arch/arm/mach-s5p64x0/common.c
View File

@ -44,6 +44,7 @@
#include <plat/sdhci.h>
#include <plat/adc-core.h>
#include <plat/fb-core.h>
#include <plat/spi-core.h>
#include <plat/gpio-cfg.h>
#include <plat/regs-irqtype.h>
#include <plat/regs-serial.h>
@ -179,6 +180,7 @@ void __init s5p6440_map_io(void)
/* initialize any device information early */
s3c_adc_setname("s3c64xx-adc");
s3c_fb_setname("s5p64x0-fb");
s3c64xx_spi_setname("s5p64x0-spi");
s5p64x0_default_sdhci0();
s5p64x0_default_sdhci1();
@ -193,6 +195,7 @@ void __init s5p6450_map_io(void)
/* initialize any device information early */
s3c_adc_setname("s3c64xx-adc");
s3c_fb_setname("s5p64x0-fb");
s3c64xx_spi_setname("s5p64x0-spi");
s5p64x0_default_sdhci0();
s5p64x0_default_sdhci1();

3
arch/arm/mach-s5pc100/common.c
View File

@ -45,6 +45,7 @@
#include <plat/fb-core.h>
#include <plat/iic-core.h>
#include <plat/onenand-core.h>
#include <plat/spi-core.h>
#include <plat/regs-serial.h>
#include <plat/watchdog-reset.h>
@ -165,6 +166,8 @@ void __init s5pc100_map_io(void)
s3c_onenand_setname("s5pc100-onenand");
s3c_fb_setname("s5pc100-fb");
s3c_cfcon_setname("s5pc100-pata");
s3c64xx_spi_setname("s5pc100-spi");
}
void __init s5pc100_init_clocks(int xtal)

3
arch/arm/mach-s5pv210/common.c
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@ -43,6 +43,7 @@
#include <plat/iic-core.h>
#include <plat/keypad-core.h>
#include <plat/tv-core.h>
#include <plat/spi-core.h>
#include <plat/regs-serial.h>
#include "common.h"
@ -196,6 +197,8 @@ void __init s5pv210_map_io(void)
/* setup TV devices */
s5p_hdmi_setname("s5pv210-hdmi");
s3c64xx_spi_setname("s5pv210-spi");
}
void __init s5pv210_init_clocks(int xtal)

2
arch/arm/mach-shmobile/setup-r8a7779.c
View File

@ -247,7 +247,7 @@ void __init r8a7779_add_standard_devices(void)
{
#ifdef CONFIG_CACHE_L2X0
/* Early BRESP enable, Shared attribute override enable, 64K*16way */
l2x0_init((void __iomem __force *)(0xf0100000), 0x40470000, 0x82000fff);
l2x0_init(IOMEM(0xf0100000), 0x40470000, 0x82000fff);
#endif
r8a7779_pm_init();

0
arch/arm/mach-spear13xx/include/mach/spear1310_misc_regs.h
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0
arch/arm/mach-spear13xx/include/mach/spear1340_misc_regs.h
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