video: fbdev: mxc: add HX8363 mipi panel driver support
Add driver support for Truly HX8363 mipi panel. Signed-off-by: Fancy Fang <chen.fang@nxp.com>
This commit is contained in:
Fancy Fang
Dong Aisheng
parent
d89f676e5e
commit
8508b3b54f
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@ -46,3 +46,8 @@ config FB_MXC_ADV7535
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depends on FB_MXC_MIPI_DSI_NORTHWEST
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help
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Driver support for the ADV7535 DSI-to-HDMI module
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config FB_MXC_TRULY_PANEL_TFT3P5581E
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tristate "TRULY Panel TFT3P5581E"
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depends on FB_MXC_DISP_FRAMEWORK
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depends on FB_MXC_MIPI_DSI_NORTHWEST
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@ -2,3 +2,4 @@ obj-$(CONFIG_FB_MXC_DISP_FRAMEWORK) += mxc_dispdrv.o
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obj-$(CONFIG_FB_MXC_MIPI_DSI_NORTHWEST) += mipi_dsi_northwest.o
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obj-$(CONFIG_FB_MXC_EDID) += mxc_edid.o
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obj-$(CONFIG_FB_MXC_ADV7535) += adv7535.o
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obj-$(CONFIG_FB_MXC_TRULY_PANEL_TFT3P5581E) += mxcfb_hx8363_wvga.o
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@ -0,0 +1,220 @@
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/platform_device.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/console.h>
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#include <linux/io.h>
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#include <linux/bitops.h>
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#include <linux/spinlock.h>
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#include <linux/mipi_dsi.h>
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#include <linux/mxcfb.h>
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#include <linux/backlight.h>
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#include <video/mipi_display.h>
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#include "mipi_dsi.h"
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#define HX8363_TWO_DATA_LANE (0x2)
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#define HX8363_MAX_DPHY_CLK (800)
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#define HX8363_CMD_GETHXID (0xF4)
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#define HX8363_CMD_GETHXID_LEN (0x4)
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#define HX8363_ID (0x84)
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#define HX8363_ID_MASK (0xFF)
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#define CHECK_RETCODE(ret) \
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do { \
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if (ret < 0) { \
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dev_err(&mipi_dsi->pdev->dev, \
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"%s ERR: ret:%d, line:%d.\n", \
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__func__, ret, __LINE__); \
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return ret; \
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} \
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} while (0)
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static void parse_variadic(int n, u8 *buf, ...)
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{
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int i = 0;
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va_list args;
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if (unlikely(!n)) return;
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va_start(args, buf);
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for (i = 0; i < n; i++)
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buf[i + 1] = (u8)va_arg(args, int);
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va_end(args);
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}
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#define TC358763_DCS_write_1A_nP(n, addr, ...) { \
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int err; \
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\
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buf[0] = addr; \
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parse_variadic(n, buf, ##__VA_ARGS__); \
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\
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if (n >= 2) \
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err = mipi_dsi->mipi_dsi_pkt_write(mipi_dsi, \
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MIPI_DSI_DCS_LONG_WRITE, (u32*)buf, n + 1); \
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else if (n == 1) \
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err = mipi_dsi->mipi_dsi_pkt_write(mipi_dsi, \
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MIPI_DSI_DCS_SHORT_WRITE_PARAM, (u32*)buf, 0); \
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else if (n == 0) \
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{ \
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buf[1] = 0; \
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err = mipi_dsi->mipi_dsi_pkt_write(mipi_dsi, \
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MIPI_DSI_DCS_SHORT_WRITE, (u32*)buf, 0); \
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} \
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CHECK_RETCODE(err); \
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}
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#define TC358763_DCS_write_1A_0P(addr) \
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TC358763_DCS_write_1A_nP(0, addr)
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#define TC358763_DCS_write_1A_1P(addr, ...) \
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TC358763_DCS_write_1A_nP(1, addr, __VA_ARGS__)
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#define TC358763_DCS_write_1A_2P(addr, ...) \
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TC358763_DCS_write_1A_nP(2, addr, __VA_ARGS__)
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#define TC358763_DCS_write_1A_3P(addr, ...) \
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TC358763_DCS_write_1A_nP(3, addr, __VA_ARGS__)
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#define TC358763_DCS_write_1A_5P(addr, ...) \
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TC358763_DCS_write_1A_nP(5, addr, __VA_ARGS__)
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#define TC358763_DCS_write_1A_6P(addr, ...) \
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TC358763_DCS_write_1A_nP(6, addr, __VA_ARGS__)
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#define TC358763_DCS_write_1A_7P(addr, ...) \
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TC358763_DCS_write_1A_nP(7, addr, __VA_ARGS__)
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#define TC358763_DCS_write_1A_12P(addr, ...) \
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TC358763_DCS_write_1A_nP(12, addr, __VA_ARGS__)
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#define TC358763_DCS_write_1A_13P(addr, ...) \
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TC358763_DCS_write_1A_nP(13, addr, __VA_ARGS__)
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#define TC358763_DCS_write_1A_14P(addr, ...) \
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TC358763_DCS_write_1A_nP(14, addr, __VA_ARGS__)
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#define TC358763_DCS_write_1A_19P(addr, ...) \
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TC358763_DCS_write_1A_nP(19, addr, __VA_ARGS__)
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#define TC358763_DCS_write_1A_34P(addr, ...) \
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TC358763_DCS_write_1A_nP(34, addr, __VA_ARGS__)
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#define TC358763_DCS_write_1A_127P(addr, ...) \
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TC358763_DCS_write_1A_nP(127, addr, __VA_ARGS__)
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static int hx8363bl_brightness;
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#define ACTIVE_HIGH_NAME "TRUULY-WVGA-SYNC-HIGH"
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#define ACTIVE_LOW_NAME "TRUULY-WVGA-SYNC-LOW"
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static struct fb_videomode truly_lcd_modedb[] = {
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{
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ACTIVE_HIGH_NAME, 50, 480, 854, 41042,
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40, 60,
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3, 3,
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8, 4,
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0x0,
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FB_VMODE_NONINTERLACED,
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0,
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}, {
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ACTIVE_LOW_NAME, 50, 480, 854, 41042,
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40, 60,
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3, 3,
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8, 4,
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FB_SYNC_OE_LOW_ACT,
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FB_VMODE_NONINTERLACED,
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0,
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},
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};
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static struct mipi_lcd_config lcd_config = {
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.virtual_ch = 0x0,
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.data_lane_num = HX8363_TWO_DATA_LANE,
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.max_phy_clk = HX8363_MAX_DPHY_CLK,
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.dpi_fmt = MIPI_RGB888,
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};
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void mipid_hx8363_get_lcd_videomode(struct fb_videomode **mode, int *size,
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struct mipi_lcd_config **data)
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{
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*mode = &truly_lcd_modedb[0];
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*size = ARRAY_SIZE(truly_lcd_modedb);
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*data = &lcd_config;
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}
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int mipid_hx8363_lcd_setup(struct mipi_dsi_info *mipi_dsi)
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{
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u8 buf[DSI_CMD_BUF_MAXSIZE];
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dev_dbg(&mipi_dsi->pdev->dev, "MIPI DSI LCD HX8363 setup.\n");
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TC358763_DCS_write_1A_3P(0xB9,0xFF,0x83,0x63);/* SET password */
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TC358763_DCS_write_1A_19P(0xB1,0x01,0x00,0x44,0x08,0x01,0x10,0x10,0x36,
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0x3E,0x1A,0x1A,0x40,0x12,0x00,0xE6,0xE6,0xE6,0xE6,0xE6);/* Set Power */
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TC358763_DCS_write_1A_2P(0xB2,0x08,0x03);/* Set DISP */
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TC358763_DCS_write_1A_7P(0xB4,0x02,0x18,0x9C,0x08,0x18,0x04,0x6C);
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TC358763_DCS_write_1A_1P(0xB6,0x00);/* Set VCOM */
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TC358763_DCS_write_1A_1P(0xCC,0x0B);/* Set Panel */
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TC358763_DCS_write_1A_34P(0xE0,0x0E,0x15,0x19,0x30,0x31,0x3F,0x27,0x3C,0x88,0x8F,0xD1,0xD5,0xD7,0x16,0x16,
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0x0C,0x1E,0x0E,0x15,0x19,0x30,0x31,0x3F,0x27,0x3C,0x88,0x8F,
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0xD1,0xD5,0xD7,0x16,0x16,0x0C,0x1E);
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mdelay(5);
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TC358763_DCS_write_1A_1P(0x3A,0x77);/* 24bit */
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TC358763_DCS_write_1A_14P(0xBA,0x11,0x00,0x56,0xC6,0x10,0x89,0xFF,0x0F,0x32,0x6E,0x04,0x07,0x9A,0x92);
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TC358763_DCS_write_1A_0P(0x21);
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TC358763_DCS_write_1A_0P(0x11);
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msleep(10);
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TC358763_DCS_write_1A_0P(0x29);
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msleep(120);
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return 0;
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}
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static int mipid_bl_update_status(struct backlight_device *bl)
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{
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return 0;
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}
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static int mipid_bl_get_brightness(struct backlight_device *bl)
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{
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return hx8363bl_brightness;
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}
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static int mipi_bl_check_fb(struct backlight_device *bl, struct fb_info *fbi)
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{
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return 0;
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}
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static const struct backlight_ops mipid_lcd_bl_ops = {
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.update_status = mipid_bl_update_status,
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.get_brightness = mipid_bl_get_brightness,
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.check_fb = mipi_bl_check_fb,
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};
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@ -0,0 +1,165 @@
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/*
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* Copyright (C) 2011-2015 Freescale Semiconductor, Inc. All Rights Reserved.
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*/
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/*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#ifndef __INCLUDE_MIPI_DSI_H
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#define __INCLUDE_MIPI_DSI_H
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#define MIPI_DSI_VERSION (0x000)
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#define MIPI_DSI_PWR_UP (0x004)
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#define MIPI_DSI_CLKMGR_CFG (0x008)
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#define MIPI_DSI_DPI_CFG (0x00c)
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#define MIPI_DSI_DBI_CFG (0x010)
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#define MIPI_DSI_DBIS_CMDSIZE (0x014)
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#define MIPI_DSI_PCKHDL_CFG (0x018)
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#define MIPI_DSI_VID_MODE_CFG (0x01c)
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#define MIPI_DSI_VID_PKT_CFG (0x020)
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#define MIPI_DSI_CMD_MODE_CFG (0x024)
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#define MIPI_DSI_TMR_LINE_CFG (0x028)
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#define MIPI_DSI_VTIMING_CFG (0x02c)
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#define MIPI_DSI_PHY_TMR_CFG (0x030)
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#define MIPI_DSI_GEN_HDR (0x034)
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#define MIPI_DSI_GEN_PLD_DATA (0x038)
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#define MIPI_DSI_CMD_PKT_STATUS (0x03c)
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#define MIPI_DSI_TO_CNT_CFG (0x040)
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#define MIPI_DSI_ERROR_ST0 (0x044)
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#define MIPI_DSI_ERROR_ST1 (0x048)
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#define MIPI_DSI_ERROR_MSK0 (0x04c)
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#define MIPI_DSI_ERROR_MSK1 (0x050)
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#define MIPI_DSI_PHY_RSTZ (0x054)
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#define MIPI_DSI_PHY_IF_CFG (0x058)
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#define MIPI_DSI_PHY_IF_CTRL (0x05c)
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#define MIPI_DSI_PHY_STATUS (0x060)
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#define MIPI_DSI_PHY_TST_CTRL0 (0x064)
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#define MIPI_DSI_PHY_TST_CTRL1 (0x068)
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#define DSI_PWRUP_RESET (0x0 << 0)
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#define DSI_PWRUP_POWERUP (0x1 << 0)
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#define DSI_DPI_CFG_VID_SHIFT (0)
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#define DSI_DPI_CFG_VID_MASK (0x3)
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#define DSI_DPI_CFG_COLORCODE_SHIFT (2)
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#define DSI_DPI_CFG_COLORCODE_MASK (0x7)
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#define DSI_DPI_CFG_DATAEN_ACT_LOW (0x1 << 5)
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#define DSI_DPI_CFG_DATAEN_ACT_HIGH (0x0 << 5)
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#define DSI_DPI_CFG_VSYNC_ACT_LOW (0x1 << 6)
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#define DSI_DPI_CFG_VSYNC_ACT_HIGH (0x0 << 6)
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#define DSI_DPI_CFG_HSYNC_ACT_LOW (0x1 << 7)
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#define DSI_DPI_CFG_HSYNC_ACT_HIGH (0x0 << 7)
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#define DSI_DPI_CFG_SHUTD_ACT_LOW (0x1 << 8)
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#define DSI_DPI_CFG_SHUTD_ACT_HIGH (0x0 << 8)
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#define DSI_DPI_CFG_COLORMODE_ACT_LOW (0x1 << 9)
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#define DSI_DPI_CFG_COLORMODE_ACT_HIGH (0x0 << 9)
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#define DSI_DPI_CFG_EN18LOOSELY (0x1 << 10)
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#define DSI_PCKHDL_CFG_EN_EOTP_TX (0x1 << 0)
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#define DSI_PCKHDL_CFG_EN_EOTP_RX (0x1 << 1)
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#define DSI_PCKHDL_CFG_EN_BTA (0x1 << 2)
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#define DSI_PCKHDL_CFG_EN_ECC_RX (0x1 << 3)
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#define DSI_PCKHDL_CFG_EN_CRC_RX (0x1 << 4)
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#define DSI_PCKHDL_CFG_GEN_VID_RX_MASK (0x3)
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#define DSI_PCKHDL_CFG_GEN_VID_RX_SHIFT (5)
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#define DSI_VID_MODE_CFG_EN (0x1 << 0)
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#define DSI_VID_MODE_CFG_EN_BURSTMODE (0x3 << 1)
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#define DSI_VID_MODE_CFG_TYPE_MASK (0x3)
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#define DSI_VID_MODE_CFG_TYPE_SHIFT (1)
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#define DSI_VID_MODE_CFG_EN_LP_VSA (0x1 << 3)
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#define DSI_VID_MODE_CFG_EN_LP_VBP (0x1 << 4)
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#define DSI_VID_MODE_CFG_EN_LP_VFP (0x1 << 5)
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#define DSI_VID_MODE_CFG_EN_LP_VACT (0x1 << 6)
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#define DSI_VID_MODE_CFG_EN_LP_HBP (0x1 << 7)
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#define DSI_VID_MODE_CFG_EN_LP_HFP (0x1 << 8)
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#define DSI_VID_MODE_CFG_EN_MULTI_PKT (0x1 << 9)
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#define DSI_VID_MODE_CFG_EN_NULL_PKT (0x1 << 10)
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#define DSI_VID_MODE_CFG_EN_FRAME_ACK (0x1 << 11)
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#define DSI_VID_MODE_CFG_EN_LP_MODE (DSI_VID_MODE_CFG_EN_LP_VSA | \
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DSI_VID_MODE_CFG_EN_LP_VBP | \
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DSI_VID_MODE_CFG_EN_LP_VFP | \
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DSI_VID_MODE_CFG_EN_LP_HFP | \
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DSI_VID_MODE_CFG_EN_LP_HBP | \
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DSI_VID_MODE_CFG_EN_LP_VACT)
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#define DSI_VID_PKT_CFG_VID_PKT_SZ_MASK (0x7ff)
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#define DSI_VID_PKT_CFG_VID_PKT_SZ_SHIFT (0)
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#define DSI_VID_PKT_CFG_NUM_CHUNKS_MASK (0x3ff)
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#define DSI_VID_PKT_CFG_NUM_CHUNKS_SHIFT (11)
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#define DSI_VID_PKT_CFG_NULL_PKT_SZ_MASK (0x3ff)
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#define DSI_VID_PKT_CFG_NULL_PKT_SZ_SHIFT (21)
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#define MIPI_DSI_CMD_MODE_CFG_EN_LOWPOWER (0x1FFF)
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#define MIPI_DSI_CMD_MODE_CFG_EN_CMD_MODE (0x1 << 0)
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#define DSI_TME_LINE_CFG_HSA_TIME_MASK (0x1ff)
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#define DSI_TME_LINE_CFG_HSA_TIME_SHIFT (0)
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#define DSI_TME_LINE_CFG_HBP_TIME_MASK (0x1ff)
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#define DSI_TME_LINE_CFG_HBP_TIME_SHIFT (9)
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#define DSI_TME_LINE_CFG_HLINE_TIME_MASK (0x3fff)
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#define DSI_TME_LINE_CFG_HLINE_TIME_SHIFT (18)
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#define DSI_VTIMING_CFG_VSA_LINES_MASK (0xf)
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#define DSI_VTIMING_CFG_VSA_LINES_SHIFT (0)
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#define DSI_VTIMING_CFG_VBP_LINES_MASK (0x3f)
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#define DSI_VTIMING_CFG_VBP_LINES_SHIFT (4)
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#define DSI_VTIMING_CFG_VFP_LINES_MASK (0x3f)
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#define DSI_VTIMING_CFG_VFP_LINES_SHIFT (10)
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#define DSI_VTIMING_CFG_V_ACT_LINES_MASK (0x7ff)
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#define DSI_VTIMING_CFG_V_ACT_LINES_SHIFT (16)
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#define DSI_PHY_TMR_CFG_BTA_TIME_MASK (0xfff)
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#define DSI_PHY_TMR_CFG_BTA_TIME_SHIFT (0)
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#define DSI_PHY_TMR_CFG_LP2HS_TIME_MASK (0xff)
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#define DSI_PHY_TMR_CFG_LP2HS_TIME_SHIFT (12)
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#define DSI_PHY_TMR_CFG_HS2LP_TIME_MASK (0xff)
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#define DSI_PHY_TMR_CFG_HS2LP_TIME_SHIFT (20)
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#define DSI_PHY_IF_CFG_N_LANES_MASK (0x3)
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#define DSI_PHY_IF_CFG_N_LANES_SHIFT (0)
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#define DSI_PHY_IF_CFG_WAIT_TIME_MASK (0xff)
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#define DSI_PHY_IF_CFG_WAIT_TIME_SHIFT (2)
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#define DSI_PHY_RSTZ_EN_CLK (0x1 << 2)
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#define DSI_PHY_RSTZ_DISABLE_RST (0x1 << 1)
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#define DSI_PHY_RSTZ_DISABLE_SHUTDOWN (0x1 << 0)
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#define DSI_PHY_RSTZ_RST (0x0)
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#define DSI_PHY_STATUS_LOCK (0x1 << 0)
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#define DSI_PHY_STATUS_STOPSTATE_CLK_LANE (0x1 << 2)
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||||
#define DSI_GEN_HDR_TYPE_MASK (0xff)
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#define DSI_GEN_HDR_TYPE_SHIFT (0)
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#define DSI_GEN_HDR_DATA_MASK (0xffff)
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#define DSI_GEN_HDR_DATA_SHIFT (8)
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|
||||
#define DSI_CMD_PKT_STATUS_GEN_CMD_EMPTY (0x1 << 0)
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#define DSI_CMD_PKT_STATUS_GEN_CMD_FULL (0x1 << 1)
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#define DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY (0x1 << 2)
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#define DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL (0x1 << 3)
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||||
#define DSI_CMD_PKT_STATUS_GEN_PLD_R_EMPTY (0x1 << 4)
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#define DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY (0x1 << 6)
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|
||||
#define DSI_ERROR_MSK0_ALL_MASK (0x1fffff)
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||||
#define DSI_ERROR_MSK1_ALL_MASK (0x3ffff)
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||||
|
||||
#define DSI_PHY_IF_CTRL_RESET (0x0)
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||||
#define DSI_PHY_IF_CTRL_TX_REQ_CLK_HS (0x1 << 0)
|
||||
#define DSI_PHY_IF_CTRL_TX_REQ_CLK_ULPS (0x1 << 1)
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||||
#define DSI_PHY_IF_CTRL_TX_EXIT_CLK_ULPS (0x1 << 2)
|
||||
#define DSI_PHY_IF_CTRL_TX_REQ_DATA_ULPS (0x1 << 3)
|
||||
#define DSI_PHY_IF_CTRL_TX_EXIT_DATA_ULPS (0x1 << 4)
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||||
#define DSI_PHY_IF_CTRL_TX_TRIG_MASK (0xF)
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||||
#define DSI_PHY_IF_CTRL_TX_TRIG_SHIFT (5)
|
||||
|
||||
#define DSI_PHY_CLK_INIT_COMMAND (0x44)
|
||||
#define DSI_GEN_PLD_DATA_BUF_SIZE (0x4)
|
||||
#endif
|
||||
Loading…
Reference in New Issue