drm/amd/display: add valid regoffset and NULL pointer check
Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -33,6 +33,7 @@
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#include "dc_link_dp.h"
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#include "dc_link_ddc.h"
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#include "link_hwss.h"
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#include "opp.h"
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#include "link_encoder.h"
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#include "hw_sequencer.h"
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@ -2382,9 +2383,10 @@ void core_link_enable_stream(
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core_dc->hwss.enable_audio_stream(pipe_ctx);
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/* turn off otg test pattern if enable */
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pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
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CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
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COLOR_DEPTH_UNDEFINED);
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if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
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pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
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CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
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COLOR_DEPTH_UNDEFINED);
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core_dc->hwss.enable_stream(pipe_ctx);
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@ -3,6 +3,7 @@
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#include "dc.h"
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#include "dc_link_dp.h"
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#include "dm_helpers.h"
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#include "opp.h"
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#include "inc/core_types.h"
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#include "link_hwss.h"
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@ -2511,8 +2512,8 @@ static void set_crtc_test_pattern(struct dc_link *link,
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pipe_ctx->stream->bit_depth_params = params;
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pipe_ctx->stream_res.opp->funcs->
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opp_program_bit_depth_reduction(pipe_ctx->stream_res.opp, ¶ms);
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pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
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if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
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pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
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controller_test_pattern, color_depth);
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}
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break;
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@ -2524,8 +2525,8 @@ static void set_crtc_test_pattern(struct dc_link *link,
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pipe_ctx->stream->bit_depth_params = params;
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pipe_ctx->stream_res.opp->funcs->
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opp_program_bit_depth_reduction(pipe_ctx->stream_res.opp, ¶ms);
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pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
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if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
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pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
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CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
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color_depth);
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}
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@ -1475,7 +1475,7 @@ static void power_down_controllers(struct dc *dc)
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{
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int i;
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for (i = 0; i < dc->res_pool->pipe_count; i++) {
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for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
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dc->res_pool->timing_generators[i]->funcs->disable_crtc(
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dc->res_pool->timing_generators[i]);
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}
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@ -1515,12 +1515,13 @@ static void disable_vga_and_power_gate_all_controllers(
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struct timing_generator *tg;
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struct dc_context *ctx = dc->ctx;
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for (i = 0; i < dc->res_pool->pipe_count; i++) {
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for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
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tg = dc->res_pool->timing_generators[i];
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if (tg->funcs->disable_vga)
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tg->funcs->disable_vga(tg);
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}
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for (i = 0; i < dc->res_pool->pipe_count; i++) {
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/* Enable CLOCK gating for each pipe BEFORE controller
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* powergating. */
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enable_display_pipe_clock_gating(ctx,
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@ -483,6 +483,11 @@ void hubbub1_update_dchub(
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struct hubbub *hubbub,
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struct dchub_init_data *dh_data)
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{
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if (REG(DCHUBBUB_SDPIF_FB_TOP) == 0) {
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ASSERT(false);
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/*should not come here*/
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return;
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}
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/* TODO: port code from dal2 */
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switch (dh_data->fb_mode) {
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case FRAME_BUFFER_MODE_ZFB_ONLY:
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@ -415,6 +415,8 @@ static void dpp_pg_control(
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if (hws->ctx->dc->debug.disable_dpp_power_gate)
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return;
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if (REG(DOMAIN1_PG_CONFIG) == 0)
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return;
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switch (dpp_inst) {
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case 0: /* DPP0 */
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@ -465,6 +467,8 @@ static void hubp_pg_control(
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if (hws->ctx->dc->debug.disable_hubp_power_gate)
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return;
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if (REG(DOMAIN0_PG_CONFIG) == 0)
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return;
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switch (hubp_inst) {
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case 0: /* DCHUBP0 */
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@ -865,7 +869,8 @@ void hwss1_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)
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return;
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mpc->funcs->remove_mpcc(mpc, mpc_tree_params, mpcc_to_remove);
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opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
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if (opp != NULL)
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opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
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dc->optimized_required = true;
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@ -1343,10 +1348,11 @@ static void dcn10_enable_per_frame_crtc_position_reset(
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DC_SYNC_INFO("Setting up\n");
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for (i = 0; i < group_size; i++)
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grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(
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grouped_pipes[i]->stream_res.tg,
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grouped_pipes[i]->stream->triggered_crtc_reset.event_source->status.primary_otg_inst,
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&grouped_pipes[i]->stream->triggered_crtc_reset);
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if (grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset)
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grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(
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grouped_pipes[i]->stream_res.tg,
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grouped_pipes[i]->stream->triggered_crtc_reset.event_source->status.primary_otg_inst,
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&grouped_pipes[i]->stream->triggered_crtc_reset);
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DC_SYNC_INFO("Waiting for trigger\n");
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@ -2496,8 +2502,14 @@ static void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)
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static void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data)
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{
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if (hws->ctx->dc->res_pool->hubbub != NULL)
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hubbub1_update_dchub(hws->ctx->dc->res_pool->hubbub, dh_data);
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if (hws->ctx->dc->res_pool->hubbub != NULL) {
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struct hubp *hubp = hws->ctx->dc->res_pool->hubps[0];
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if (hubp->funcs->hubp_update_dchub)
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hubp->funcs->hubp_update_dchub(hubp, dh_data);
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else
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hubbub1_update_dchub(hws->ctx->dc->res_pool->hubbub, dh_data);
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}
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}
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static void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
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