drm: brainlcd: set LCDIF clock
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@ -285,6 +285,8 @@ static void brain_enable(struct drm_simple_display_pipe *pipe,
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writel(TIMING_CMD_HOLD(1) | TIMING_CMD_SETUP(1) | TIMING_DATA_HOLD(1) | TIMING_DATA_SETUP(1),
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ili->base + LCDC_TIMING);
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clk_set_rate(ili->clk_lcdif, m->vtotal * m->htotal * 60 * 2);
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/* Initialize LCD */
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/* Decrease the bus width to 8-bit temporarily */
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valid = CTRL1_GET_BYTE_PACKAGING(readl(ili->base + LCDC_CTRL1));
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