MLK-23131-2 soc: imx: busfreq-imx8mq: Correct dram pll clock for rate update
When DRAM PLL clock is changed in TF-A, the DRAM PLL clock rate needs to be updated, previous implementation uses dram_pll_clk which is clock gate and it will NOT trigger clock rate update, need to use PLL type clock which has CLK_GET_RATE_NOCACHE flag set and will trigger clock rate recalculation. Otherwise, when system enters low bus mode, checking clock rate via "cat /sys/kernel/debug/clk/dram_core_clk/clk_rate" will NOT return the latest dram core clk rate. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Robin Gong <yibin.gong@nxp.com>
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@ -61,6 +61,7 @@ static int low_bus_mode_fsp_index;
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static bool bypass_support = true;
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static struct clk *dram_pll_clk;
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static struct clk *dram_pll;
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static struct clk *sys1_pll_800m;
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static struct clk *sys1_pll_400m;
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static struct clk *sys1_pll_100m;
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@ -135,7 +136,7 @@ static void reduce_bus_freq(void)
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* to update the clock tree info in kernel side.
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*/
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clk_set_rate(dram_apb_pre_div, 160000000);
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clk_get_rate(dram_pll_clk);
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clk_get_rate(dram_pll);
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}
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/* change the NOC rate */
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if (of_machine_is_compatible("fsl,imx8mq"))
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@ -180,7 +181,7 @@ static void reduce_bus_freq(void)
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* to update the clock tree info in kernel side.
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*/
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clk_set_rate(dram_apb_pre_div, 160000000);
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clk_get_rate(dram_pll_clk);
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clk_get_rate(dram_pll);
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}
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/* change the NOC rate */
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@ -282,7 +283,7 @@ static int set_high_bus_freq(int high_bus_freq)
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update_bus_freq(HIGH_FREQ_3200MTS);
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clk_set_rate(dram_apb_pre_div, 200000000);
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clk_get_rate(dram_pll_clk);
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clk_get_rate(dram_pll);
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}
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clk_set_rate(noc_div, origin_noc_rate);
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@ -508,6 +509,7 @@ static int imx8mq_init_busfreq_clk(struct platform_device *pdev)
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static int imx8mm_init_busfreq_clk(struct platform_device *pdev)
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{
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dram_pll = devm_clk_get(&pdev->dev, "dram_pll_div");
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dram_pll_clk = devm_clk_get(&pdev->dev, "dram_pll");
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dram_alt_src = devm_clk_get(&pdev->dev, "dram_alt_src");
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dram_alt_root = devm_clk_get(&pdev->dev, "dram_alt_root");
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