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MLK-24957-1 ASoC: fsl_xcvr: sync with upstream version
Sync fsl_xcvr driver with the upstream accepted version. Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
This commit is contained in:
parent
f676b0e9ec
commit
787e6e98a1
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@ -19,7 +19,12 @@
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#define FSL_XCVR_CAPDS_SIZE 256
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struct fsl_xcvr_soc_data {
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const char *fw_name;
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};
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struct fsl_xcvr {
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const struct fsl_xcvr_soc_data *soc_data;
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struct platform_device *pdev;
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struct regmap *regmap;
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struct clk *ipg_clk;
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@ -27,7 +32,6 @@ struct fsl_xcvr {
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struct clk *phy_clk;
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struct clk *spba_clk;
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struct reset_control *reset;
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const char *fw_name;
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u8 streams;
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u32 mode;
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u32 arc_mode;
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@ -51,7 +55,11 @@ static const struct fsl_xcvr_pll_conf {
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{ .mfi = 29, .mfn = 1, .mfd = 6, .fout = 700000000, }, /* 700 MHz */
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};
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static const u32 fsl_xcvr_earc_channels[] = { 1, 2, 8, 16, 32, }; /* one bit 6, 12 ? */
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/*
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* HDMI2.1 spec defines 6- and 12-channels layout for one bit audio
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* stream. Todo: to check how this case can be considered below
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*/
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static const u32 fsl_xcvr_earc_channels[] = { 1, 2, 8, 16, 32, };
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static const struct snd_pcm_hw_constraint_list fsl_xcvr_earc_channels_constr = {
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.count = ARRAY_SIZE(fsl_xcvr_earc_channels),
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.list = fsl_xcvr_earc_channels,
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@ -105,7 +113,7 @@ static int fsl_xcvr_arc_mode_get(struct snd_kcontrol *kcontrol,
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return 0;
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}
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static const int fsl_xcvr_phy_arc_cfg[] = {
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static const u32 fsl_xcvr_phy_arc_cfg[] = {
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FSL_XCVR_PHY_CTRL_ARC_MODE_SE_EN, FSL_XCVR_PHY_CTRL_ARC_MODE_CM_EN,
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};
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@ -226,7 +234,9 @@ static struct snd_kcontrol_new fsl_xcvr_mode_kctl =
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/** phy: true => phy, false => pll */
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static int fsl_xcvr_ai_write(struct fsl_xcvr *xcvr, u8 reg, u32 data, bool phy)
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{
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struct device *dev = &xcvr->pdev->dev;
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u32 val, idx, tidx;
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int ret;
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idx = BIT(phy ? 26 : 24);
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tidx = BIT(phy ? 27 : 25);
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@ -236,11 +246,13 @@ static int fsl_xcvr_ai_write(struct fsl_xcvr *xcvr, u8 reg, u32 data, bool phy)
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regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_WDATA, data);
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regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_TOG, idx);
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do {
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regmap_read(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL, &val);
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} while ((val & idx) != ((val & tidx) >> 1));
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return 0;
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ret = regmap_read_poll_timeout(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL, val,
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(val & idx) == ((val & tidx) >> 1),
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10, 10000);
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if (ret)
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dev_err(dev, "AI timeout: failed to set %s reg 0x%02x=0x%08x\n",
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phy ? "PHY" : "PLL", reg, data);
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return ret;
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}
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static int fsl_xcvr_en_phy_pll(struct fsl_xcvr *xcvr, u32 freq, bool tx)
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@ -608,18 +620,16 @@ static int fsl_xcvr_trigger(struct snd_pcm_substream *substream, int cmd,
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FSL_XCVR_ISR_SET,
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FSL_XCVR_ISR_CMDC_TX_EN);
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if (ret < 0) {
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dev_err(dai->dev,
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"err updating isr %d\n", ret);
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dev_err(dai->dev, "err updating isr %d\n", ret);
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return ret;
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}
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/* fall through */
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fallthrough;
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case FSL_XCVR_MODE_SPDIF:
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ret = regmap_write(xcvr->regmap,
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FSL_XCVR_TX_DPTH_CTRL_SET,
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FSL_XCVR_TX_DPTH_CTRL_STRT_DATA_TX);
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if (ret < 0) {
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dev_err(dai->dev, "Failed to set TX_DPTH_CTRL_STRT_DATA_TX: %d\n", ret);
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dev_err(dai->dev, "Failed to start DATA_TX: %d\n", ret);
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return ret;
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}
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break;
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@ -653,10 +663,10 @@ static int fsl_xcvr_trigger(struct snd_pcm_substream *substream, int cmd,
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FSL_XCVR_TX_DPTH_CTRL_CLR,
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FSL_XCVR_TX_DPTH_CTRL_STRT_DATA_TX);
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if (ret < 0) {
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dev_err(dai->dev, "Failed to clr TX_DPTH_CTRL_STRT_DATA_TX: %d\n", ret);
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dev_err(dai->dev, "Failed to stop DATA_TX: %d\n", ret);
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return ret;
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}
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/* fall through ...*/
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fallthrough;
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case FSL_XCVR_MODE_EARC:
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/* clear ISR_CMDC_TX_EN, W1C */
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ret = regmap_write(xcvr->regmap,
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@ -685,7 +695,7 @@ static int fsl_xcvr_load_firmware(struct fsl_xcvr *xcvr)
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int ret = 0, rem, off, out, page = 0, size = FSL_XCVR_REG_OFFSET;
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u32 mask, val;
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ret = request_firmware(&fw, xcvr->fw_name, dev);
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ret = request_firmware(&fw, xcvr->soc_data->fw_name, dev);
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if (ret) {
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dev_err(dev, "failed to request firmware.\n");
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return ret;
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@ -693,14 +703,18 @@ static int fsl_xcvr_load_firmware(struct fsl_xcvr *xcvr)
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rem = fw->size;
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/* RAM is 20KiB => max 10 pages 2KiB each */
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for (page = 0; page < 10; page++)
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{
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/* RAM is 20KiB = 16KiB code + 4KiB data => max 10 pages 2KiB each */
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if (rem > 16384) {
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dev_err(dev, "FW size %d is bigger than 16KiB.\n", rem);
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return -ENOMEM;
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}
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for (page = 0; page < 10; page++) {
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ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
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FSL_XCVR_EXT_CTRL_PAGE_MASK,
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FSL_XCVR_EXT_CTRL_PAGE(page));
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if (ret < 0) {
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dev_err(dev, "FW: failed to set page %d, err=%d \n",
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dev_err(dev, "FW: failed to set page %d, err=%d\n",
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page, ret);
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goto err_firmware;
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}
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@ -748,7 +762,6 @@ static int fsl_xcvr_load_firmware(struct fsl_xcvr *xcvr)
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/* Store Capabilities Data Structure into Data RAM */
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memcpy_toio(xcvr->ram_addr + FSL_XCVR_CAP_DATA_STR, xcvr->cap_ds,
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FSL_XCVR_CAPDS_SIZE);
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return 0;
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}
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@ -1035,13 +1048,13 @@ static irqreturn_t irq0_isr(int irq, void *devid)
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struct device *dev = &xcvr->pdev->dev;
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struct regmap *regmap = xcvr->regmap;
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void __iomem *reg_ctrl, *reg_buff;
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u32 isr, val, i;
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u32 isr, isr_clr = 0, val, i;
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regmap_read(regmap, FSL_XCVR_EXT_ISR, &isr);
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regmap_write(regmap, FSL_XCVR_EXT_ISR_CLR, isr);
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if (isr & FSL_XCVR_IRQ_NEW_CS) {
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dev_dbg(dev, "Received new CS block\n");
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isr_clr |= FSL_XCVR_IRQ_NEW_CS;
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/* Data RAM is 4KiB, last two pages: 8 and 9. Select page 8. */
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regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
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FSL_XCVR_EXT_CTRL_PAGE_MASK,
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@ -1070,52 +1083,52 @@ static irqreturn_t irq0_isr(int irq, void *devid)
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memset_io(reg_ctrl, 0, sizeof(val));
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}
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}
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if (isr & FSL_XCVR_IRQ_NEW_UD)
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if (isr & FSL_XCVR_IRQ_NEW_UD) {
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dev_dbg(dev, "Received new UD block\n");
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if (isr & FSL_XCVR_IRQ_MUTE)
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isr_clr |= FSL_XCVR_IRQ_NEW_UD;
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}
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if (isr & FSL_XCVR_IRQ_MUTE) {
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dev_dbg(dev, "HW mute bit detected\n");
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if (isr & FSL_XCVR_IRQ_FIFO_UOFL_ERR)
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isr_clr |= FSL_XCVR_IRQ_MUTE;
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}
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if (isr & FSL_XCVR_IRQ_FIFO_UOFL_ERR) {
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dev_dbg(dev, "RX/TX FIFO full/empty\n");
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if (isr & FSL_XCVR_IRQ_ARC_MODE)
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isr_clr |= FSL_XCVR_IRQ_FIFO_UOFL_ERR;
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}
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if (isr & FSL_XCVR_IRQ_ARC_MODE) {
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dev_dbg(dev, "CMDC SM falls out of eARC mode\n");
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if (isr & FSL_XCVR_IRQ_DMA_RD_REQ)
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isr_clr |= FSL_XCVR_IRQ_ARC_MODE;
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}
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if (isr & FSL_XCVR_IRQ_DMA_RD_REQ) {
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dev_dbg(dev, "DMA read request\n");
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if (isr & FSL_XCVR_IRQ_DMA_WR_REQ)
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isr_clr |= FSL_XCVR_IRQ_DMA_RD_REQ;
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}
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if (isr & FSL_XCVR_IRQ_DMA_WR_REQ) {
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dev_dbg(dev, "DMA write request\n");
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isr_clr |= FSL_XCVR_IRQ_DMA_WR_REQ;
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}
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return IRQ_HANDLED;
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if (isr_clr) {
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regmap_write(regmap, FSL_XCVR_EXT_ISR_CLR, isr_clr);
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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}
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static irqreturn_t irq1_isr(int irq, void *devid)
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{
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struct fsl_xcvr *xcvr = (struct fsl_xcvr *)devid;
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struct device *dev = &xcvr->pdev->dev;
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dev_dbg(dev, "irq[1]: %d\n", irq);
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return IRQ_HANDLED;
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}
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static irqreturn_t irq2_isr(int irq, void *devid)
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{
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struct fsl_xcvr *xcvr = (struct fsl_xcvr *)devid;
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struct device *dev = &xcvr->pdev->dev;
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dev_dbg(dev, "irq[2]: %d\n", irq);
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return IRQ_HANDLED;
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}
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static const struct fsl_xcvr_soc_data fsl_xcvr_imx8mp_data = {
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.fw_name = "imx/xcvr/xcvr-imx8mp.bin",
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};
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static const struct of_device_id fsl_xcvr_dt_ids[] = {
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{ .compatible = "fsl,imx8mp-xcvr", },
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{ }
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{ .compatible = "fsl,imx8mp-xcvr", .data = &fsl_xcvr_imx8mp_data },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, fsl_xcvr_dt_ids);
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static int fsl_xcvr_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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const struct of_device_id *of_id;
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struct fsl_xcvr *xcvr;
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struct resource *ram_res, *regs_res, *rx_res, *tx_res;
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@ -1131,6 +1144,8 @@ static int fsl_xcvr_probe(struct platform_device *pdev)
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return -ENOMEM;
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xcvr->pdev = pdev;
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xcvr->soc_data = of_device_get_match_data(&pdev->dev);
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xcvr->ipg_clk = devm_clk_get(dev, "ipg");
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if (IS_ERR(xcvr->ipg_clk)) {
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dev_err(dev, "failed to get ipg clock\n");
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@ -1173,12 +1188,10 @@ static int fsl_xcvr_probe(struct platform_device *pdev)
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return PTR_ERR(xcvr->regmap);
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}
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xcvr->reset = of_reset_control_get(np, NULL);
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ret = of_property_read_string(np, "fsl,xcvr-fw", &xcvr->fw_name);
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if (ret) {
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dev_err(dev, "failed to get fsl,xcvr-fw: %d\n", ret);
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return ret;
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xcvr->reset = devm_reset_control_get_exclusive(dev, NULL);
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if (IS_ERR(xcvr->reset)) {
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dev_err(dev, "failed to get XCVR reset control\n");
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return PTR_ERR(xcvr->reset);
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}
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/* get IRQs */
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@ -1194,30 +1207,6 @@ static int fsl_xcvr_probe(struct platform_device *pdev)
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return ret;
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}
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irq = platform_get_irq(pdev, 1);
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if (irq < 0) {
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dev_err(dev, "no irq[1]: %d\n", irq);
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return irq;
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}
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ret = devm_request_irq(dev, irq, irq1_isr, 0, pdev->name, xcvr);
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if (ret) {
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dev_err(dev, "failed to claim IRQ1: %i\n", ret);
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return ret;
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}
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irq = platform_get_irq(pdev, 2);
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if (irq < 0) {
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dev_err(dev, "no irq[2]: %d\n", irq);
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return irq;
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}
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ret = devm_request_irq(dev, irq, irq2_isr, 0, pdev->name, xcvr);
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if (ret) {
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dev_err(dev, "failed to claim IRQ2: %i\n", ret);
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return ret;
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}
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rx_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rxfifo");
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tx_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "txfifo");
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xcvr->dma_prms_rx.chan_name = "rx";
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@ -1246,8 +1235,7 @@ static int fsl_xcvr_probe(struct platform_device *pdev)
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return ret;
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}
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#ifdef CONFIG_PM
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static int fsl_xcvr_runtime_suspend(struct device *dev)
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static __maybe_unused int fsl_xcvr_runtime_suspend(struct device *dev)
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{
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struct fsl_xcvr *xcvr = dev_get_drvdata(dev);
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int ret;
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@ -1259,6 +1247,10 @@ static int fsl_xcvr_runtime_suspend(struct device *dev)
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if (ret < 0)
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dev_err(dev, "Failed to assert M0+ core: %d\n", ret);
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ret = reset_control_assert(xcvr->reset);
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if (ret < 0)
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dev_err(dev, "Failed to assert M0+ reset: %d\n", ret);
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regcache_cache_only(xcvr->regmap, true);
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clk_disable_unprepare(xcvr->spba_clk);
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@ -1269,7 +1261,7 @@ static int fsl_xcvr_runtime_suspend(struct device *dev)
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return 0;
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}
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static int fsl_xcvr_runtime_resume(struct device *dev)
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static __maybe_unused int fsl_xcvr_runtime_resume(struct device *dev)
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{
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struct fsl_xcvr *xcvr = dev_get_drvdata(dev);
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int ret;
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@ -1283,22 +1275,19 @@ static int fsl_xcvr_runtime_resume(struct device *dev)
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ret = clk_prepare_enable(xcvr->pll_ipg_clk);
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if (ret) {
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dev_err(dev, "failed to start PLL IPG clock.\n");
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return ret;
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goto stop_ipg_clk;
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}
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ret = clk_prepare_enable(xcvr->phy_clk);
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if (ret) {
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dev_err(dev, "failed to start PHY clock: %d\n", ret);
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clk_disable_unprepare(xcvr->ipg_clk);
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return ret;
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goto stop_pll_ipg_clk;
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}
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ret = clk_prepare_enable(xcvr->spba_clk);
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if (ret) {
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dev_err(dev, "failed to start SPBA clock.\n");
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clk_disable_unprepare(xcvr->phy_clk);
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clk_disable_unprepare(xcvr->ipg_clk);
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return ret;
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goto stop_phy_clk;
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}
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regcache_cache_only(xcvr->regmap, false);
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@ -1307,16 +1296,19 @@ static int fsl_xcvr_runtime_resume(struct device *dev)
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if (ret) {
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dev_err(dev, "failed to sync regcache.\n");
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return ret;
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goto stop_spba_clk;
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}
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reset_control_assert(xcvr->reset);
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reset_control_deassert(xcvr->reset);
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ret = reset_control_deassert(xcvr->reset);
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if (ret) {
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dev_err(dev, "failed to deassert M0+ reset.\n");
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goto stop_spba_clk;
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}
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ret = fsl_xcvr_load_firmware(xcvr);
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if (ret) {
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dev_err(dev, "failed to load firmware.\n");
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return ret;
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goto stop_spba_clk;
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}
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/* Release M0+ reset */
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@ -1324,13 +1316,25 @@ static int fsl_xcvr_runtime_resume(struct device *dev)
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FSL_XCVR_EXT_CTRL_CORE_RESET, 0);
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if (ret < 0) {
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dev_err(dev, "M0+ core release failed: %d\n", ret);
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return ret;
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goto stop_spba_clk;
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}
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mdelay(50);
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/* Let M0+ core complete firmware initialization */
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msleep(50);
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return 0;
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|
||||
stop_spba_clk:
|
||||
clk_disable_unprepare(xcvr->spba_clk);
|
||||
stop_phy_clk:
|
||||
clk_disable_unprepare(xcvr->phy_clk);
|
||||
stop_pll_ipg_clk:
|
||||
clk_disable_unprepare(xcvr->pll_ipg_clk);
|
||||
stop_ipg_clk:
|
||||
clk_disable_unprepare(xcvr->ipg_clk);
|
||||
|
||||
return ret;
|
||||
}
|
||||
#endif /* CONFIG_PM*/
|
||||
|
||||
static const struct dev_pm_ops fsl_xcvr_pm_ops = {
|
||||
SET_RUNTIME_PM_OPS(fsl_xcvr_runtime_suspend,
|
||||
|
|
|
@ -132,12 +132,12 @@
|
|||
#define FSL_XCVR_IRQ_UNEXP_PRE_REC BIT(20)
|
||||
#define FSL_XCVR_IRQ_ARC_MODE BIT(21)
|
||||
#define FSL_XCVR_IRQ_CH_UD_OFLOW BIT(22)
|
||||
#define FSL_XCVR_IRQ_EARC_ALL FSL_XCVR_IRQ_NEW_CS | \
|
||||
FSL_XCVR_IRQ_NEW_UD | \
|
||||
FSL_XCVR_IRQ_MUTE | \
|
||||
FSL_XCVR_IRQ_FIFO_UOFL_ERR | \
|
||||
FSL_XCVR_IRQ_HOST_WAKEUP | \
|
||||
FSL_XCVR_IRQ_ARC_MODE
|
||||
#define FSL_XCVR_IRQ_EARC_ALL (FSL_XCVR_IRQ_NEW_CS | \
|
||||
FSL_XCVR_IRQ_NEW_UD | \
|
||||
FSL_XCVR_IRQ_MUTE | \
|
||||
FSL_XCVR_IRQ_FIFO_UOFL_ERR | \
|
||||
FSL_XCVR_IRQ_HOST_WAKEUP | \
|
||||
FSL_XCVR_IRQ_ARC_MODE)
|
||||
|
||||
#define FSL_XCVR_ISR_CMDC_TX_EN BIT(3)
|
||||
#define FSL_XCVR_ISR_HPD_TGL BIT(15)
|
||||
|
|
Loading…
Reference in New Issue
Block a user