Merge remote-tracking branch 'origin/usb/dwc3' into usb/next
* origin/usb/dwc3: (10 commits) usb: dwc3: Add cache type configuration support usb: dwc3: Add chip-specific compatible string MLK-22675 usb: dwc3: host: disable park mode usb: dwc3: Add workaround for host mode VBUS glitch when boot usb: dwc3: Add avoiding vbus glitch happen during xhci reset ...
This commit is contained in:
Dong Aisheng
commit
7866db2c15
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@ -4,7 +4,15 @@ DWC3- USB3 CONTROLLER. Complies to the generic USB binding properties
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as described in 'usb/generic.txt'
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Required properties:
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- compatible: must be "snps,dwc3"
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- compatible: must be "snps,dwc3" and (if applicable) may contain a
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chip-specific compatible string in front of it to allow dwc3 driver be
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able to update cache type configuration accordingly, otherwise
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Layerscape SoC will encounter USB init failure when adding property
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dma-coherent on device tree.
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Example:
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* "fsl,layerscape-dwc3", "snps,dwc3"
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* "snps,dwc3"
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- reg : Address and length of the register set for the device
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- interrupts: Interrupts used by the dwc3 controller.
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- clock-names: should contain "ref", "bus_early", "suspend"
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@ -109,6 +117,10 @@ Optional properties:
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more than one value, which means undefined length INCR burst type
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enabled. The values can be 1, 4, 8, 16, 32, 64, 128 and 256.
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- snps,host-vbus-glitches: Power off all Root Hub ports immediately after
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setting host mode to avoid vbus (negative) glitch happen in later
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xhci reset. And the vbus will back to 5V automatically when reset done.
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- in addition all properties from usb-xhci.txt from the current directory are
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supported as well
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@ -894,6 +894,73 @@ static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
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dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
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}
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static void dwc3_set_power_down_clk_scale(struct dwc3 *dwc)
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{
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u32 reg, scale;
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if (dwc->num_clks == 0)
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return;
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/*
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* The power down scale field specifies how many suspend_clk
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* periods fit into a 16KHz clock period. When performing
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* the division, round up the remainder.
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*/
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scale = DIV_ROUND_UP(clk_get_rate(dwc->clks[2].clk), 16384);
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reg = dwc3_readl(dwc->regs, DWC3_GCTL);
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reg &= ~(DWC3_GCTL_PWRDNSCALE_MASK);
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reg |= DWC3_GCTL_PWRDNSCALE(scale);
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dwc3_writel(dwc->regs, DWC3_GCTL, reg);
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}
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#ifdef CONFIG_OF
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struct dwc3_cache_type {
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u8 transfer_type_datard;
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u8 transfer_type_descrd;
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u8 transfer_type_datawr;
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u8 transfer_type_descwr;
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};
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static const struct dwc3_cache_type layerscape_dwc3_cache_type = {
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.transfer_type_datard = 2,
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.transfer_type_descrd = 2,
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.transfer_type_datawr = 2,
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.transfer_type_descwr = 2,
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};
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/**
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* dwc3_set_cache_type - Configure cache type registers
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* @dwc: Pointer to our controller context structure
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*/
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static void dwc3_set_cache_type(struct dwc3 *dwc)
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{
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u32 tmp, reg;
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const struct dwc3_cache_type *cache_type =
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device_get_match_data(dwc->dev);
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if (cache_type) {
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reg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
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tmp = reg;
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reg &= ~DWC3_GSBUSCFG0_DATARD(~0);
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reg |= DWC3_GSBUSCFG0_DATARD(cache_type->transfer_type_datard);
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reg &= ~DWC3_GSBUSCFG0_DESCRD(~0);
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reg |= DWC3_GSBUSCFG0_DESCRD(cache_type->transfer_type_descrd);
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reg &= ~DWC3_GSBUSCFG0_DATAWR(~0);
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reg |= DWC3_GSBUSCFG0_DATAWR(cache_type->transfer_type_datawr);
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reg &= ~DWC3_GSBUSCFG0_DESCWR(~0);
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reg |= DWC3_GSBUSCFG0_DESCWR(cache_type->transfer_type_descwr);
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if (tmp != reg)
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dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, reg);
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}
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}
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#endif
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/**
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* dwc3_core_init - Low-level initialization of DWC3 Core
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* @dwc: Pointer to our controller context structure
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@ -918,6 +985,8 @@ static int dwc3_core_init(struct dwc3 *dwc)
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dwc->maximum_speed = USB_SPEED_HIGH;
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}
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dwc3_set_power_down_clk_scale(dwc);
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ret = dwc3_phy_setup(dwc);
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if (ret)
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goto err0;
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@ -952,6 +1021,10 @@ static int dwc3_core_init(struct dwc3 *dwc)
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dwc3_set_incr_burst_type(dwc);
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#ifdef CONFIG_OF
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dwc3_set_cache_type(dwc);
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#endif
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usb_phy_set_suspend(dwc->usb2_phy, 0);
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usb_phy_set_suspend(dwc->usb3_phy, 0);
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ret = phy_power_on(dwc->usb2_generic_phy);
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@ -1009,6 +1082,21 @@ static int dwc3_core_init(struct dwc3 *dwc)
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reg |= DWC3_GUCTL_HSTINAUTORETRY;
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dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
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/*
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* Disable Park Mode for super speed:
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* Park mode is used in host mode when only a single async
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* endpoint is active, but which has a known issue cause
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* USB3.0 HC may die when read and write at the same time,
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* considering the advantages of this mode are minimal,
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* this issue only impacts super speed and exist on all IP
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* versions, disable it for SS, Synopsys will release a formal
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* STAR 9001415732, and disable it by default in next IP
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* release.
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*/
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reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
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reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
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dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
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}
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/*
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@ -1236,6 +1324,17 @@ static void dwc3_get_properties(struct dwc3 *dwc)
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dwc->maximum_speed = usb_get_maximum_speed(dev);
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dwc->dr_mode = usb_get_dr_mode(dev);
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if (dwc->dr_mode == USB_DR_MODE_OTG) {
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dwc->otg_caps.otg_rev = 0x0300;
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dwc->otg_caps.hnp_support = true;
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dwc->otg_caps.srp_support = true;
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dwc->otg_caps.adp_support = true;
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/* Update otg capabilities by DT properties */
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of_usb_update_otg_caps(dev->of_node,
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&dwc->otg_caps);
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}
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dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
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dwc->sysdev_is_parent = device_property_read_bool(dev,
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@ -1315,6 +1414,9 @@ static void dwc3_get_properties(struct dwc3 *dwc)
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dwc->dis_metastability_quirk = device_property_read_bool(dev,
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"snps,dis_metastability_quirk");
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dwc->host_vbus_glitches = device_property_read_bool(dev,
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"snps,host-vbus-glitches");
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dwc->lpm_nyet_threshold = lpm_nyet_threshold;
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dwc->tx_de_emphasis = tx_de_emphasis;
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@ -1837,12 +1939,9 @@ static const struct dev_pm_ops dwc3_dev_pm_ops = {
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#ifdef CONFIG_OF
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static const struct of_device_id of_dwc3_match[] = {
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{
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.compatible = "snps,dwc3"
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},
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{
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.compatible = "synopsys,dwc3"
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},
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{ .compatible = "fsl,layerscape-dwc3", .data = &layerscape_dwc3_cache_type, },
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{ .compatible = "snps,dwc3" },
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{ .compatible = "synopsys,dwc3" },
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{ },
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};
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MODULE_DEVICE_TABLE(of, of_dwc3_match);
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@ -25,6 +25,7 @@
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#include <linux/usb/ch9.h>
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#include <linux/usb/gadget.h>
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#include <linux/usb/otg.h>
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#include <linux/usb/role.h>
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#include <linux/ulpi/interface.h>
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#include <linux/phy/phy.h>
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@ -165,6 +166,21 @@
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/* Bit fields */
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/* Global SoC Bus Configuration INCRx Register 0 */
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#ifdef CONFIG_OF
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#define DWC3_GSBUSCFG0_DATARD_SHIFT 28
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#define DWC3_GSBUSCFG0_DATARD(n) (((n) & 0xf) \
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<< DWC3_GSBUSCFG0_DATARD_SHIFT)
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#define DWC3_GSBUSCFG0_DESCRD_SHIFT 24
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#define DWC3_GSBUSCFG0_DESCRD(n) (((n) & 0xf) \
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<< DWC3_GSBUSCFG0_DESCRD_SHIFT)
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#define DWC3_GSBUSCFG0_DATAWR_SHIFT 20
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#define DWC3_GSBUSCFG0_DATAWR(n) (((n) & 0xf) \
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<< DWC3_GSBUSCFG0_DATAWR_SHIFT)
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#define DWC3_GSBUSCFG0_DESCWR_SHIFT 16
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#define DWC3_GSBUSCFG0_DESCWR(n) (((n) & 0xf) \
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<< DWC3_GSBUSCFG0_DESCWR_SHIFT)
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#endif
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#define DWC3_GSBUSCFG0_INCR256BRSTENA (1 << 7) /* INCR256 burst */
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#define DWC3_GSBUSCFG0_INCR128BRSTENA (1 << 6) /* INCR128 burst */
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#define DWC3_GSBUSCFG0_INCR64BRSTENA (1 << 5) /* INCR64 burst */
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@ -223,6 +239,7 @@
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/* Global Configuration Register */
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#define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
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#define DWC3_GCTL_PWRDNSCALE_MASK DWC3_GCTL_PWRDNSCALE(0x1fff)
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#define DWC3_GCTL_U2RSTECN BIT(16)
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#define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6)
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#define DWC3_GCTL_CLK_BUS (0)
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@ -251,6 +268,7 @@
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/* Global User Control 1 Register */
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#define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28)
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#define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24)
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#define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17)
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/* Global Status Register */
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#define DWC3_GSTS_OTG_IP BIT(10)
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@ -941,6 +959,7 @@ struct dwc3_scratchpad_array {
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* @nr_scratch: number of scratch buffers
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* @u1u2: only used on revisions <1.83a for workaround
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* @maximum_speed: maximum speed requested (mainly for testing purposes)
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* @otg_caps: the OTG capabilities from hardware point
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* @revision: revision register contents
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* @version_type: VERSIONTYPE register contents, a sub release of a revision
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* @dr_mode: requested mode of operation
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@ -1029,6 +1048,8 @@ struct dwc3_scratchpad_array {
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* 2 - No de-emphasis
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* 3 - Reserved
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* @dis_metastability_quirk: set to disable metastability quirk.
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* @host_vbus_glitches: set to avoid vbus glitch during
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* xhci reset.
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* @imod_interval: set the interrupt moderation interval in 250ns
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* increments or 0 to disable.
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*/
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@ -1078,6 +1099,7 @@ struct dwc3 {
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void __iomem *regs;
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size_t regs_size;
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struct usb_role_switch *role_switch;
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enum usb_dr_mode dr_mode;
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u32 current_dr_role;
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u32 desired_dr_role;
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@ -1094,6 +1116,7 @@ struct dwc3 {
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u32 nr_scratch;
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u32 u1u2;
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u32 maximum_speed;
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struct usb_otg_caps otg_caps;
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/*
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* All 3.1 IP version constants are greater than the 3.0 IP
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@ -1218,6 +1241,7 @@ struct dwc3 {
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unsigned tx_de_emphasis:2;
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unsigned dis_metastability_quirk:1;
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unsigned host_vbus_glitches:1;
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u16 imod_interval;
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};
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@ -476,6 +476,43 @@ static struct extcon_dev *dwc3_get_extcon(struct dwc3 *dwc)
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return edev;
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}
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static int dwc3_usb_role_switch_set(struct device *dev, enum usb_role role)
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{
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u32 mode;
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switch (role) {
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case USB_ROLE_HOST:
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mode = DWC3_GCTL_PRTCAP_HOST;
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break;
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case USB_ROLE_DEVICE:
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mode = DWC3_GCTL_PRTCAP_DEVICE;
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break;
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default:
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return 0;
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};
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dwc3_set_mode(dev_get_drvdata(dev), mode);
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return 0;
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}
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static enum usb_role dwc3_usb_role_switch_get(struct device *dev)
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{
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struct dwc3 *dwc = dev_get_drvdata(dev);
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unsigned long flags;
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enum usb_role role;
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spin_lock_irqsave(&dwc->lock, flags);
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role = dwc->current_dr_role;
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spin_unlock_irqrestore(&dwc->lock, flags);
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return role;
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}
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|
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static struct usb_role_switch_desc dwc3_role_switch = {
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.set = dwc3_usb_role_switch_set,
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.get = dwc3_usb_role_switch_get,
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};
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int dwc3_drd_init(struct dwc3 *dwc)
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{
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int ret, irq;
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@ -484,7 +521,13 @@ int dwc3_drd_init(struct dwc3 *dwc)
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if (IS_ERR(dwc->edev))
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return PTR_ERR(dwc->edev);
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|
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if (dwc->edev) {
|
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if (device_property_read_bool(dwc->dev, "usb-role-switch")) {
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dwc3_role_switch.fwnode = dev_fwnode(dwc->dev);
|
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dwc->role_switch = usb_role_switch_register(dwc->dev,
|
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&dwc3_role_switch);
|
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if (IS_ERR(dwc->role_switch))
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return PTR_ERR(dwc->role_switch);
|
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} else if (dwc->edev) {
|
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dwc->edev_nb.notifier_call = dwc3_drd_notifier;
|
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ret = extcon_register_notifier(dwc->edev, EXTCON_USB_HOST,
|
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&dwc->edev_nb);
|
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|
|
@ -531,6 +574,9 @@ void dwc3_drd_exit(struct dwc3 *dwc)
|
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{
|
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unsigned long flags;
|
||||
|
||||
if (dwc->role_switch)
|
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usb_role_switch_unregister(dwc->role_switch);
|
||||
|
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if (dwc->edev)
|
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extcon_unregister_notifier(dwc->edev, EXTCON_USB_HOST,
|
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&dwc->edev_nb);
|
||||
|
|
|
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|
|
@ -270,7 +270,7 @@ int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
|
|||
{
|
||||
const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
|
||||
struct dwc3 *dwc = dep->dwc;
|
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u32 timeout = 1000;
|
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u32 timeout = 2000;
|
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u32 saved_config = 0;
|
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u32 reg;
|
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|
||||
|
|
@ -3343,6 +3343,10 @@ int dwc3_gadget_init(struct dwc3 *dwc)
|
|||
dwc->gadget.sg_supported = true;
|
||||
dwc->gadget.name = "dwc3-gadget";
|
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dwc->gadget.lpm_capable = true;
|
||||
dwc->gadget.is_otg = (dwc->dr_mode == USB_DR_MODE_OTG) &&
|
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(dwc->otg_caps.hnp_support ||
|
||||
dwc->otg_caps.srp_support ||
|
||||
dwc->otg_caps.adp_support);
|
||||
|
||||
/*
|
||||
* FIXME We might be setting max_speed to <SUPER, however versions
|
||||
|
|
|
|||
|
|
@ -9,8 +9,49 @@
|
|||
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include "../host/xhci.h"
|
||||
|
||||
#include "core.h"
|
||||
|
||||
|
||||
#define XHCI_HCSPARAMS1 0x4
|
||||
#define XHCI_PORTSC_BASE 0x400
|
||||
|
||||
/*
|
||||
* dwc3_power_off_all_roothub_ports - Power off all Root hub ports
|
||||
* @dwc3: Pointer to our controller context structure
|
||||
*/
|
||||
static void dwc3_power_off_all_roothub_ports(struct dwc3 *dwc)
|
||||
{
|
||||
int i, port_num;
|
||||
u32 reg, op_regs_base, offset;
|
||||
void __iomem *xhci_regs;
|
||||
|
||||
/* xhci regs is not mapped yet, do it temperary here */
|
||||
if (dwc->xhci_resources[0].start) {
|
||||
xhci_regs = ioremap(dwc->xhci_resources[0].start,
|
||||
DWC3_XHCI_REGS_END);
|
||||
if (IS_ERR(xhci_regs)) {
|
||||
dev_err(dwc->dev, "Failed to ioremap xhci_regs\n");
|
||||
return;
|
||||
}
|
||||
|
||||
op_regs_base = HC_LENGTH(readl(xhci_regs));
|
||||
reg = readl(xhci_regs + XHCI_HCSPARAMS1);
|
||||
port_num = HCS_MAX_PORTS(reg);
|
||||
|
||||
for (i = 1; i <= port_num; i++) {
|
||||
offset = op_regs_base + XHCI_PORTSC_BASE + 0x10*(i-1);
|
||||
reg = readl(xhci_regs + offset);
|
||||
reg &= ~PORT_POWER;
|
||||
writel(reg, xhci_regs + offset);
|
||||
}
|
||||
|
||||
iounmap(xhci_regs);
|
||||
} else
|
||||
dev_err(dwc->dev, "xhci base reg invalid\n");
|
||||
}
|
||||
|
||||
static int dwc3_host_get_irq(struct dwc3 *dwc)
|
||||
{
|
||||
struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
|
||||
|
|
@ -50,6 +91,13 @@ int dwc3_host_init(struct dwc3 *dwc)
|
|||
struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
|
||||
int prop_idx = 0;
|
||||
|
||||
/*
|
||||
* We have to power off all Root hub ports immediately after DWC3 set
|
||||
* to host mode to avoid VBUS glitch happen when xhci get reset later.
|
||||
*/
|
||||
if (dwc->host_vbus_glitches)
|
||||
dwc3_power_off_all_roothub_ports(dwc);
|
||||
|
||||
irq = dwc3_host_get_irq(dwc);
|
||||
if (irq < 0)
|
||||
return irq;
|
||||
|
|
|
|||
Loading…
Reference in New Issue