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ARM: dts: qcom-apq8064: disable i2c by default at soc dtsi 

This patch marks all the gsbi i2c node at soc level dtsi, so that kernel
would not assume that its enabled and result in pin conflicts when gsbi
is used for UART or SPI.

Without this patch we see below pin conflict.

apq8064-pinctrl 800000.pinctrl: pin GPIO_20 already requested by
 12450000.serial; cannot claim for 12460000.i2c
apq8064-pinctrl 800000.pinctrl: pin-20 (12460000.i2c) status -22
apq8064-pinctrl 800000.pinctrl: could not request pin 20 (GPIO_20)
 from group gpio20  on device 800000.pinctrl
i2c_qup 12460000.i2c: Error applying setting, reverse things back
i2c_qup: probe of 12460000.i2c failed with error -22

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This commit is contained in:
Srinivas Kandagatla 2018-03-15 14:44:34 +00:00 committed by Andy Gross
parent 60cc43fc88
commit 76a4076511
1 changed files with 4 additions and 0 deletions
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4
arch/arm/boot/dts/qcom-apq8064.dtsi
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@ -461,6 +461,7 @@
clock-names = "core", "iface";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
@ -489,6 +490,7 @@
clock-names = "core", "iface";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
@ -514,6 +516,7 @@
clock-names = "core", "iface";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
@ -538,6 +541,7 @@
clocks = <&gcc GSBI4_QUP_CLK>,
<&gcc GSBI4_H_CLK>;
clock-names = "core", "iface";
status = "disabled";
};
};