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drm/amd/display: separate out wm change request dcn workaround 

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Dmytro Laktyushkin 2018-06-05 13:14:13 -04:00 committed by Alex Deucher
parent 69d6bb171f
commit 7144d3cfff
5 changed files with 13 additions and 5 deletions
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11
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
View File

@ -190,6 +190,12 @@ static uint32_t convert_and_clamp(
}
void hubbub1_wm_change_req_wa(struct hubbub *hubbub)
{
REG_UPDATE_SEQ(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 0, 1);
}
void hubbub1_program_watermarks(
struct hubbub *hubbub,
struct dcn_watermark_set *watermarks,
@ -203,8 +209,6 @@ void hubbub1_program_watermarks(
*/
uint32_t prog_wm_value;
REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 0);
/* Repeat for water mark set A, B, C and D. */
/* clock state A */
@ -459,9 +463,6 @@ void hubbub1_program_watermarks(
watermarks->d.cstate_pstate.pstate_change_ns, prog_wm_value);
}
REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 1);
REG_UPDATE(DCHUBBUB_ARB_SAT_LEVEL,
DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz);
REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND,

2
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
View File

@ -195,6 +195,8 @@ void hubbub1_update_dchub(
bool hubbub1_verify_allow_pstate_change_high(
struct hubbub *hubbub);
void hubbub1_wm_change_req_wa(struct hubbub *hubbub);
void hubbub1_program_watermarks(
struct hubbub *hubbub,
struct dcn_watermark_set *watermarks,

3
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
View File

@ -2305,6 +2305,9 @@ static void dcn10_apply_ctx_for_surface(
hubbub1_program_watermarks(dc->res_pool->hubbub,
&context->bw.dcn.watermarks, ref_clk_mhz, true);
if (dc->hwseq->wa.DEGVIDCN10_254)
hubbub1_wm_change_req_wa(dc->res_pool->hubbub);
if (dc->debug.sanity_checks) {
/* pstate stuck check after watermark update */
dcn10_verify_allow_pstate_change_high(dc);

1
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
View File

@ -743,6 +743,7 @@ static struct dce_hwseq *dcn10_hwseq_create(
hws->masks = &hwseq_mask;
hws->wa.DEGVIDCN10_253 = true;
hws->wa.false_optc_underflow = true;
hws->wa.DEGVIDCN10_254 = true;
}
return hws;
}

1
drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
View File

@ -44,6 +44,7 @@ struct dce_hwseq_wa {
bool blnd_crtc_trigger;
bool DEGVIDCN10_253;
bool false_optc_underflow;
bool DEGVIDCN10_254;
};
struct hwseq_wa_state {