This is the 5.4.87 stable release
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This commit is contained in:
commit
6f99d03764
|
@ -41,6 +41,8 @@ Package
|
|||
Packages contain a number of cores plus shared resources, e.g. DRAM
|
||||
controller, shared caches etc.
|
||||
|
||||
Modern systems may also use the term 'Die' for package.
|
||||
|
||||
AMD nomenclature for package is 'Node'.
|
||||
|
||||
Package-related topology information in the kernel:
|
||||
|
@ -53,11 +55,18 @@ Package-related topology information in the kernel:
|
|||
|
||||
The number of dies in a package. This information is retrieved via CPUID.
|
||||
|
||||
- cpuinfo_x86.cpu_die_id:
|
||||
|
||||
The physical ID of the die. This information is retrieved via CPUID.
|
||||
|
||||
- cpuinfo_x86.phys_proc_id:
|
||||
|
||||
The physical ID of the package. This information is retrieved via CPUID
|
||||
and deduced from the APIC IDs of the cores in the package.
|
||||
|
||||
Modern systems use this value for the socket. There may be multiple
|
||||
packages within a socket. This value may differ from cpu_die_id.
|
||||
|
||||
- cpuinfo_x86.logical_proc_id:
|
||||
|
||||
The logical ID of the package. As we do not trust BIOSes to enumerate the
|
||||
|
|
2
Makefile
2
Makefile
|
@ -1,7 +1,7 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
VERSION = 5
|
||||
PATCHLEVEL = 4
|
||||
SUBLEVEL = 85
|
||||
SUBLEVEL = 87
|
||||
EXTRAVERSION =
|
||||
NAME = Kleptomaniac Octopus
|
||||
|
||||
|
|
16
arch/Kconfig
16
arch/Kconfig
|
@ -131,6 +131,22 @@ config UPROBES
|
|||
managed by the kernel and kept transparent to the probed
|
||||
application. )
|
||||
|
||||
config HAVE_64BIT_ALIGNED_ACCESS
|
||||
def_bool 64BIT && !HAVE_EFFICIENT_UNALIGNED_ACCESS
|
||||
help
|
||||
Some architectures require 64 bit accesses to be 64 bit
|
||||
aligned, which also requires structs containing 64 bit values
|
||||
to be 64 bit aligned too. This includes some 32 bit
|
||||
architectures which can do 64 bit accesses, as well as 64 bit
|
||||
architectures without unaligned access.
|
||||
|
||||
This symbol should be selected by an architecture if 64 bit
|
||||
accesses are required to be 64 bit aligned in this way even
|
||||
though it is not a 64 bit architecture.
|
||||
|
||||
See Documentation/unaligned-memory-access.txt for more
|
||||
information on the topic of unaligned memory accesses.
|
||||
|
||||
config HAVE_EFFICIENT_UNALIGNED_ACCESS
|
||||
bool
|
||||
help
|
||||
|
|
|
@ -266,11 +266,6 @@
|
|||
reg = <0x11000 0x100>;
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
|
||||
reg = <0x11100 0x100>;
|
||||
};
|
||||
|
||||
&mpic {
|
||||
reg = <0x20a00 0x2d0>, <0x21070 0x58>;
|
||||
};
|
||||
|
|
|
@ -81,11 +81,6 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&vuart {
|
||||
// VUART Host Console
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
// Host Console
|
||||
status = "okay";
|
||||
|
|
|
@ -22,9 +22,9 @@
|
|||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
vga_memory: framebuffer@7f000000 {
|
||||
vga_memory: framebuffer@9f000000 {
|
||||
no-map;
|
||||
reg = <0x7f000000 0x01000000>;
|
||||
reg = <0x9f000000 0x01000000>; /* 16M */
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
@ -242,6 +242,11 @@
|
|||
atmel,pins =
|
||||
<AT91_PIOE 9 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>; /* PE9, conflicts with A9 */
|
||||
};
|
||||
pinctrl_usb_default: usb_default {
|
||||
atmel,pins =
|
||||
<AT91_PIOE 3 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
|
||||
AT91_PIOE 4 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
@ -259,6 +264,8 @@
|
|||
&pioE 3 GPIO_ACTIVE_LOW
|
||||
&pioE 4 GPIO_ACTIVE_LOW
|
||||
>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb_default>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
@ -133,6 +133,11 @@
|
|||
atmel,pins =
|
||||
<AT91_PIOE 31 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>;
|
||||
};
|
||||
pinctrl_usb_default: usb_default {
|
||||
atmel,pins =
|
||||
<AT91_PIOE 11 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
|
||||
AT91_PIOE 14 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
|
||||
};
|
||||
pinctrl_key_gpio: key_gpio_0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOE 8 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
|
||||
|
@ -158,6 +163,8 @@
|
|||
&pioE 11 GPIO_ACTIVE_HIGH
|
||||
&pioE 14 GPIO_ACTIVE_HIGH
|
||||
>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb_default>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
@ -278,23 +278,26 @@
|
|||
atmel,adc-use-res = "highres";
|
||||
|
||||
trigger0 {
|
||||
trigger-name = "timer-counter-0";
|
||||
trigger-name = "external-rising";
|
||||
trigger-value = <0x1>;
|
||||
trigger-external;
|
||||
};
|
||||
|
||||
trigger1 {
|
||||
trigger-name = "timer-counter-1";
|
||||
trigger-value = <0x3>;
|
||||
trigger-name = "external-falling";
|
||||
trigger-value = <0x2>;
|
||||
trigger-external;
|
||||
};
|
||||
|
||||
trigger2 {
|
||||
trigger-name = "timer-counter-2";
|
||||
trigger-value = <0x5>;
|
||||
trigger-name = "external-any";
|
||||
trigger-value = <0x3>;
|
||||
trigger-external;
|
||||
};
|
||||
|
||||
trigger3 {
|
||||
trigger-name = "external";
|
||||
trigger-value = <0x13>;
|
||||
trigger-external;
|
||||
trigger-name = "continuous";
|
||||
trigger-value = <0x6>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
@ -327,6 +327,8 @@
|
|||
regulator-name = "vddq_lcd";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
/* Supplies also GPK and GPJ */
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo8_reg: LDO8 {
|
||||
|
@ -637,11 +639,11 @@
|
|||
};
|
||||
|
||||
&usbdrd_dwc3_0 {
|
||||
dr_mode = "host";
|
||||
dr_mode = "peripheral";
|
||||
};
|
||||
|
||||
&usbdrd_dwc3_1 {
|
||||
dr_mode = "peripheral";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&usbdrd3_0 {
|
||||
|
|
|
@ -560,6 +560,34 @@
|
|||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
usb3_1_oc: usb3-1-oc {
|
||||
samsung,pins = "gpk2-4", "gpk2-5";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
usb3_1_vbusctrl: usb3-1-vbusctrl {
|
||||
samsung,pins = "gpk2-6", "gpk2-7";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
|
||||
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
usb3_0_oc: usb3-0-oc {
|
||||
samsung,pins = "gpk3-0", "gpk3-1";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
usb3_0_vbusctrl: usb3-0-vbusctrl {
|
||||
samsung,pins = "gpk3-2", "gpk3-3";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
|
||||
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl_2 {
|
||||
|
|
|
@ -398,6 +398,8 @@
|
|||
&usbdrd3_0 {
|
||||
clocks = <&clock CLK_USBD300>;
|
||||
clock-names = "usbdrd30";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb3_0_oc>, <&usb3_0_vbusctrl>;
|
||||
};
|
||||
|
||||
&usbdrd_phy0 {
|
||||
|
@ -409,6 +411,8 @@
|
|||
&usbdrd3_1 {
|
||||
clocks = <&clock CLK_USBD301>;
|
||||
clock-names = "usbdrd30";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb3_1_oc>, <&usb3_1_vbusctrl>;
|
||||
};
|
||||
|
||||
&usbdrd_dwc3_1 {
|
||||
|
|
|
@ -551,7 +551,7 @@
|
|||
|
||||
pinctrl_i2c3: i2c3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
|
|
@ -166,7 +166,6 @@
|
|||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
|
||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
|
||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
|
||||
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
|
||||
>;
|
||||
};
|
||||
|
||||
|
|
|
@ -219,7 +219,7 @@
|
|||
reg = <0>;
|
||||
|
||||
reset-assert-us = <10000>;
|
||||
reset-deassert-us = <30000>;
|
||||
reset-deassert-us = <80000>;
|
||||
reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>;
|
||||
|
||||
interrupt-parent = <&gpio_intc>;
|
||||
|
|
|
@ -83,7 +83,7 @@
|
|||
reg = <0>;
|
||||
|
||||
reset-assert-us = <10000>;
|
||||
reset-deassert-us = <30000>;
|
||||
reset-deassert-us = <80000>;
|
||||
reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -46,7 +46,7 @@
|
|||
|
||||
button_pins: pinmux_button_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP4_IOPAD(0x11b, PIN_INPUT_PULLUP | MUX_MODE3) /* gpio_113 */
|
||||
OMAP4_IOPAD(0x0fc, PIN_INPUT_PULLUP | MUX_MODE3) /* gpio_113 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -648,6 +648,7 @@
|
|||
clocks = <&pmc PMC_TYPE_PERIPHERAL 51>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
no-memory-wc;
|
||||
ranges = <0 0xf8044000 0x1420>;
|
||||
};
|
||||
|
||||
|
@ -716,7 +717,7 @@
|
|||
|
||||
can0: can@f8054000 {
|
||||
compatible = "bosch,m_can";
|
||||
reg = <0xf8054000 0x4000>, <0x210000 0x4000>;
|
||||
reg = <0xf8054000 0x4000>, <0x210000 0x1c00>;
|
||||
reg-names = "m_can", "message_ram";
|
||||
interrupts = <56 IRQ_TYPE_LEVEL_HIGH 7>,
|
||||
<64 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
|
@ -938,7 +939,7 @@
|
|||
|
||||
can1: can@fc050000 {
|
||||
compatible = "bosch,m_can";
|
||||
reg = <0xfc050000 0x4000>, <0x210000 0x4000>;
|
||||
reg = <0xfc050000 0x4000>, <0x210000 0x3800>;
|
||||
reg-names = "m_can", "message_ram";
|
||||
interrupts = <57 IRQ_TYPE_LEVEL_HIGH 7>,
|
||||
<65 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
|
@ -948,7 +949,7 @@
|
|||
assigned-clocks = <&pmc PMC_TYPE_GCK 57>;
|
||||
assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
|
||||
assigned-clock-rates = <40000000>;
|
||||
bosch,mram-cfg = <0x1100 0 0 64 0 0 32 32>;
|
||||
bosch,mram-cfg = <0x1c00 0 0 64 0 0 32 32>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
|
@ -132,7 +132,7 @@
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac_rgmii_pins>;
|
||||
phy-handle = <&phy1>;
|
||||
phy-mode = "rgmii";
|
||||
phy-mode = "rgmii-id";
|
||||
phy-supply = <®_gmac_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright 2015 Adam Sampson <ats@offog.org>
|
||||
* Copyright 2015-2020 Adam Sampson <ats@offog.org>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
|
@ -115,7 +115,7 @@
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac_rgmii_pins>;
|
||||
phy-handle = <&phy1>;
|
||||
phy-mode = "rgmii";
|
||||
phy-mode = "rgmii-id";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
@ -423,7 +423,7 @@
|
|||
gic: interrupt-controller@1c81000 {
|
||||
compatible = "arm,gic-400";
|
||||
reg = <0x01c81000 0x1000>,
|
||||
<0x01c82000 0x1000>,
|
||||
<0x01c82000 0x2000>,
|
||||
<0x01c84000 0x2000>,
|
||||
<0x01c86000 0x2000>;
|
||||
interrupt-controller;
|
||||
|
|
|
@ -120,7 +120,7 @@
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac_rgmii_pins>;
|
||||
phy-handle = <&phy1>;
|
||||
phy-mode = "rgmii";
|
||||
phy-mode = "rgmii-id";
|
||||
phy-supply = <®_dc1sw>;
|
||||
status = "okay";
|
||||
};
|
||||
|
@ -198,16 +198,16 @@
|
|||
};
|
||||
|
||||
®_dc1sw {
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc-gmac-phy";
|
||||
};
|
||||
|
||||
®_dcdc1 {
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-name = "vcc-3v0";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc-3v3";
|
||||
};
|
||||
|
||||
®_dcdc2 {
|
||||
|
|
|
@ -386,20 +386,32 @@ ENTRY(ce_aes_ctr_encrypt)
|
|||
.Lctrloop4x:
|
||||
subs r4, r4, #4
|
||||
bmi .Lctr1x
|
||||
add r6, r6, #1
|
||||
|
||||
/*
|
||||
* NOTE: the sequence below has been carefully tweaked to avoid
|
||||
* a silicon erratum that exists in Cortex-A57 (#1742098) and
|
||||
* Cortex-A72 (#1655431) cores, where AESE/AESMC instruction pairs
|
||||
* may produce an incorrect result if they take their input from a
|
||||
* register of which a single 32-bit lane has been updated the last
|
||||
* time it was modified. To work around this, the lanes of registers
|
||||
* q0-q3 below are not manipulated individually, and the different
|
||||
* counter values are prepared by successive manipulations of q7.
|
||||
*/
|
||||
add ip, r6, #1
|
||||
vmov q0, q7
|
||||
rev ip, ip
|
||||
add lr, r6, #2
|
||||
vmov s31, ip @ set lane 3 of q1 via q7
|
||||
add ip, r6, #3
|
||||
rev lr, lr
|
||||
vmov q1, q7
|
||||
rev ip, r6
|
||||
add r6, r6, #1
|
||||
vmov s31, lr @ set lane 3 of q2 via q7
|
||||
rev ip, ip
|
||||
vmov q2, q7
|
||||
vmov s7, ip
|
||||
rev ip, r6
|
||||
add r6, r6, #1
|
||||
vmov s31, ip @ set lane 3 of q3 via q7
|
||||
add r6, r6, #4
|
||||
vmov q3, q7
|
||||
vmov s11, ip
|
||||
rev ip, r6
|
||||
add r6, r6, #1
|
||||
vmov s15, ip
|
||||
|
||||
vld1.8 {q4-q5}, [r1]!
|
||||
vld1.8 {q6}, [r1]!
|
||||
vld1.8 {q15}, [r1]!
|
||||
|
|
|
@ -671,12 +671,8 @@ ARM_BE8(rev16 ip, ip)
|
|||
ldrcc r7, [r4], #4 @ use branch for delay slot
|
||||
bcc 1b
|
||||
bx lr
|
||||
#else
|
||||
#ifdef CONFIG_CPU_ENDIAN_BE8
|
||||
moveq r0, #0x00004000 @ set bit 22, mov to mvn instruction
|
||||
#else
|
||||
moveq r0, #0x400000 @ set bit 22, mov to mvn instruction
|
||||
#endif
|
||||
b 2f
|
||||
1: ldr ip, [r7, r3]
|
||||
#ifdef CONFIG_CPU_ENDIAN_BE8
|
||||
|
@ -685,7 +681,7 @@ ARM_BE8(rev16 ip, ip)
|
|||
tst ip, #0x000f0000 @ check the rotation field
|
||||
orrne ip, ip, r6, lsl #24 @ mask in offset bits 31-24
|
||||
biceq ip, ip, #0x00004000 @ clear bit 22
|
||||
orreq ip, ip, r0 @ mask in offset bits 7-0
|
||||
orreq ip, ip, r0, ror #8 @ mask in offset bits 7-0
|
||||
#else
|
||||
bic ip, ip, #0x000000ff
|
||||
tst ip, #0xf00 @ check the rotation field
|
||||
|
|
|
@ -66,6 +66,7 @@ static const char * const sun8i_board_dt_compat[] = {
|
|||
"allwinner,sun8i-h2-plus",
|
||||
"allwinner,sun8i-h3",
|
||||
"allwinner,sun8i-r40",
|
||||
"allwinner,sun8i-v3",
|
||||
"allwinner,sun8i-v3s",
|
||||
NULL,
|
||||
};
|
||||
|
|
|
@ -340,7 +340,7 @@
|
|||
eee-broken-1000t;
|
||||
|
||||
reset-assert-us = <10000>;
|
||||
reset-deassert-us = <30000>;
|
||||
reset-deassert-us = <80000>;
|
||||
reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
|
||||
|
||||
interrupt-parent = <&gpio_intc>;
|
||||
|
|
|
@ -165,7 +165,7 @@
|
|||
reg = <0>;
|
||||
|
||||
reset-assert-us = <10000>;
|
||||
reset-deassert-us = <30000>;
|
||||
reset-deassert-us = <80000>;
|
||||
reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
|
||||
|
||||
interrupt-parent = <&gpio_intc>;
|
||||
|
|
|
@ -138,7 +138,7 @@
|
|||
reg = <0>;
|
||||
|
||||
reset-assert-us = <10000>;
|
||||
reset-deassert-us = <30000>;
|
||||
reset-deassert-us = <80000>;
|
||||
reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
|
||||
|
||||
interrupt-parent = <&gpio_intc>;
|
||||
|
|
|
@ -126,7 +126,7 @@
|
|||
reg = <0>;
|
||||
|
||||
reset-assert-us = <10000>;
|
||||
reset-deassert-us = <30000>;
|
||||
reset-deassert-us = <80000>;
|
||||
reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
|
||||
|
||||
interrupt-parent = <&gpio_intc>;
|
||||
|
|
|
@ -147,7 +147,7 @@
|
|||
reg = <0>;
|
||||
|
||||
reset-assert-us = <10000>;
|
||||
reset-deassert-us = <30000>;
|
||||
reset-deassert-us = <80000>;
|
||||
reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -82,7 +82,7 @@
|
|||
|
||||
/* External PHY reset is shared with internal PHY Led signal */
|
||||
reset-assert-us = <10000>;
|
||||
reset-deassert-us = <30000>;
|
||||
reset-deassert-us = <80000>;
|
||||
reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
|
||||
|
||||
interrupt-parent = <&gpio_intc>;
|
||||
|
|
|
@ -251,7 +251,7 @@
|
|||
reg = <0>;
|
||||
|
||||
reset-assert-us = <10000>;
|
||||
reset-deassert-us = <30000>;
|
||||
reset-deassert-us = <80000>;
|
||||
reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
|
||||
|
||||
interrupt-parent = <&gpio_intc>;
|
||||
|
@ -395,7 +395,7 @@
|
|||
#size-cells = <1>;
|
||||
compatible = "winbond,w25q16", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <3000000>;
|
||||
spi-max-frequency = <104000000>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
@ -112,7 +112,7 @@
|
|||
max-speed = <1000>;
|
||||
|
||||
reset-assert-us = <10000>;
|
||||
reset-deassert-us = <30000>;
|
||||
reset-deassert-us = <80000>;
|
||||
reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -64,7 +64,7 @@
|
|||
|
||||
/* External PHY reset is shared with internal PHY Led signal */
|
||||
reset-assert-us = <10000>;
|
||||
reset-deassert-us = <30000>;
|
||||
reset-deassert-us = <80000>;
|
||||
reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
|
||||
|
||||
interrupt-parent = <&gpio_intc>;
|
||||
|
|
|
@ -114,7 +114,7 @@
|
|||
max-speed = <1000>;
|
||||
|
||||
reset-assert-us = <10000>;
|
||||
reset-deassert-us = <30000>;
|
||||
reset-deassert-us = <80000>;
|
||||
reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -90,7 +90,7 @@
|
|||
opp-microvolt = <790000>;
|
||||
};
|
||||
|
||||
opp-1512000000 {
|
||||
opp-1500000000 {
|
||||
opp-hz = /bits/ 64 <1500000000>;
|
||||
opp-microvolt = <800000>;
|
||||
};
|
||||
|
|
|
@ -90,8 +90,10 @@
|
|||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-0.2";
|
||||
compatible = "arm,psci";
|
||||
method = "smc";
|
||||
cpu_off = <0x84000002>;
|
||||
cpu_on = <0xC4000003>;
|
||||
};
|
||||
|
||||
soc: soc {
|
||||
|
@ -494,13 +496,6 @@
|
|||
pmu_system_controller: system-controller@105c0000 {
|
||||
compatible = "samsung,exynos7-pmu", "syscon";
|
||||
reg = <0x105c0000 0x5000>;
|
||||
|
||||
reboot: syscon-reboot {
|
||||
compatible = "syscon-reboot";
|
||||
regmap = <&pmu_system_controller>;
|
||||
offset = <0x0400>;
|
||||
mask = <0x1>;
|
||||
};
|
||||
};
|
||||
|
||||
rtc: rtc@10590000 {
|
||||
|
@ -650,3 +645,4 @@
|
|||
};
|
||||
|
||||
#include "exynos7-pinctrl.dtsi"
|
||||
#include "arm/exynos-syscon-restart.dtsi"
|
||||
|
|
|
@ -771,7 +771,7 @@
|
|||
ethernet@0,4 {
|
||||
compatible = "fsl,enetc-ptp";
|
||||
reg = <0x000400 0 0 0 0>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
clocks = <&clockgen 2 3>;
|
||||
little-endian;
|
||||
};
|
||||
|
||||
|
|
|
@ -144,7 +144,7 @@
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&rgmii_pins>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy = <&phy1>;
|
||||
phy-handle = <&phy1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
@ -144,7 +144,7 @@
|
|||
nvidia,schmitt = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,lpdr = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,io-hv = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
};
|
||||
|
@ -156,7 +156,7 @@
|
|||
nvidia,schmitt = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,lpdr = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,io-hv = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
};
|
||||
|
|
|
@ -244,23 +244,28 @@
|
|||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
hid@15 {
|
||||
tsel: hid@15 {
|
||||
compatible = "hid-over-i2c";
|
||||
reg = <0x15>;
|
||||
hid-descr-addr = <0x1>;
|
||||
|
||||
interrupts-extended = <&tlmm 37 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupts-extended = <&tlmm 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c3_hid_active>;
|
||||
};
|
||||
|
||||
hid@2c {
|
||||
tsc2: hid@2c {
|
||||
compatible = "hid-over-i2c";
|
||||
reg = <0x2c>;
|
||||
hid-descr-addr = <0x20>;
|
||||
|
||||
interrupts-extended = <&tlmm 37 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupts-extended = <&tlmm 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c2_hid_active>;
|
||||
pinctrl-0 = <&i2c3_hid_active>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
|
@ -268,15 +273,15 @@
|
|||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
hid@10 {
|
||||
tsc1: hid@10 {
|
||||
compatible = "hid-over-i2c";
|
||||
reg = <0x10>;
|
||||
hid-descr-addr = <0x1>;
|
||||
|
||||
interrupts-extended = <&tlmm 125 IRQ_TYPE_EDGE_FALLING>;
|
||||
interrupts-extended = <&tlmm 125 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c6_hid_active>;
|
||||
pinctrl-0 = <&i2c5_hid_active>;
|
||||
};
|
||||
};
|
||||
|
||||
|
@ -284,7 +289,7 @@
|
|||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
hid@5c {
|
||||
ecsh: hid@5c {
|
||||
compatible = "hid-over-i2c";
|
||||
reg = <0x5c>;
|
||||
hid-descr-addr = <0x1>;
|
||||
|
@ -292,7 +297,7 @@
|
|||
interrupts-extended = <&tlmm 92 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c12_hid_active>;
|
||||
pinctrl-0 = <&i2c11_hid_active>;
|
||||
};
|
||||
};
|
||||
|
||||
|
@ -335,7 +340,7 @@
|
|||
&tlmm {
|
||||
gpio-reserved-ranges = <0 4>, <81 4>;
|
||||
|
||||
i2c2_hid_active: i2c2-hid-active {
|
||||
i2c3_hid_active: i2c2-hid-active {
|
||||
pins = <37>;
|
||||
function = "gpio";
|
||||
|
||||
|
@ -344,7 +349,7 @@
|
|||
drive-strength = <2>;
|
||||
};
|
||||
|
||||
i2c6_hid_active: i2c6-hid-active {
|
||||
i2c5_hid_active: i2c5-hid-active {
|
||||
pins = <125>;
|
||||
function = "gpio";
|
||||
|
||||
|
@ -353,7 +358,7 @@
|
|||
drive-strength = <2>;
|
||||
};
|
||||
|
||||
i2c12_hid_active: i2c12-hid-active {
|
||||
i2c11_hid_active: i2c11-hid-active {
|
||||
pins = <92>;
|
||||
function = "gpio";
|
||||
|
||||
|
|
|
@ -22,7 +22,6 @@
|
|||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
rxc-skew-ps = <1500>;
|
||||
reg = <0>;
|
||||
interrupt-parent = <&gpio2>;
|
||||
interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
|
|
@ -23,7 +23,6 @@
|
|||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
rxc-skew-ps = <1500>;
|
||||
reg = <0>;
|
||||
interrupt-parent = <&gpio2>;
|
||||
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
|
|
@ -333,6 +333,7 @@
|
|||
};
|
||||
|
||||
&usb20_otg {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
@ -1190,8 +1190,8 @@
|
|||
|
||||
uart0 {
|
||||
uart0_xfer: uart0-xfer {
|
||||
rockchip,pins = <1 RK_PB1 1 &pcfg_pull_up>,
|
||||
<1 RK_PB0 1 &pcfg_pull_none>;
|
||||
rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>,
|
||||
<1 RK_PB0 1 &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
uart0_cts: uart0-cts {
|
||||
|
@ -1209,8 +1209,8 @@
|
|||
|
||||
uart1 {
|
||||
uart1_xfer: uart1-xfer {
|
||||
rockchip,pins = <3 RK_PA4 4 &pcfg_pull_up>,
|
||||
<3 RK_PA6 4 &pcfg_pull_none>;
|
||||
rockchip,pins = <3 RK_PA4 4 &pcfg_pull_none>,
|
||||
<3 RK_PA6 4 &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
uart1_cts: uart1-cts {
|
||||
|
@ -1228,15 +1228,15 @@
|
|||
|
||||
uart2-0 {
|
||||
uart2m0_xfer: uart2m0-xfer {
|
||||
rockchip,pins = <1 RK_PA0 2 &pcfg_pull_up>,
|
||||
<1 RK_PA1 2 &pcfg_pull_none>;
|
||||
rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>,
|
||||
<1 RK_PA1 2 &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
uart2-1 {
|
||||
uart2m1_xfer: uart2m1-xfer {
|
||||
rockchip,pins = <2 RK_PA0 1 &pcfg_pull_up>,
|
||||
<2 RK_PA1 1 &pcfg_pull_none>;
|
||||
rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>,
|
||||
<2 RK_PA1 1 &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
@ -182,6 +182,7 @@ enum vcpu_sysreg {
|
|||
#define c2_TTBR1 (TTBR1_EL1 * 2) /* Translation Table Base Register 1 */
|
||||
#define c2_TTBR1_high (c2_TTBR1 + 1) /* TTBR1 top 32 bits */
|
||||
#define c2_TTBCR (TCR_EL1 * 2) /* Translation Table Base Control R. */
|
||||
#define c2_TTBCR2 (c2_TTBCR + 1) /* Translation Table Base Control R. 2 */
|
||||
#define c3_DACR (DACR32_EL2 * 2)/* Domain Access Control Register */
|
||||
#define c5_DFSR (ESR_EL1 * 2) /* Data Fault Status Register */
|
||||
#define c5_IFSR (IFSR32_EL2 * 2)/* Instruction Fault Status Register */
|
||||
|
|
|
@ -102,8 +102,8 @@ static void el0_svc_common(struct pt_regs *regs, int scno, int sc_nr,
|
|||
regs->syscallno = scno;
|
||||
|
||||
cortex_a76_erratum_1463225_svc_handler();
|
||||
user_exit_irqoff();
|
||||
local_daif_restore(DAIF_PROCCTX);
|
||||
user_exit();
|
||||
|
||||
if (has_syscall_work(flags)) {
|
||||
/* set default errno for user-issued syscall(-1) */
|
||||
|
|
|
@ -1837,6 +1837,7 @@ static const struct sys_reg_desc cp15_regs[] = {
|
|||
{ Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
|
||||
{ Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, c2_TTBR1 },
|
||||
{ Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, c2_TTBCR },
|
||||
{ Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, c2_TTBCR2 },
|
||||
{ Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, c3_DACR },
|
||||
{ Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, c5_DFSR },
|
||||
{ Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, c5_IFSR },
|
||||
|
|
|
@ -27,6 +27,7 @@ config BCM47XX_BCMA
|
|||
select BCMA
|
||||
select BCMA_HOST_SOC
|
||||
select BCMA_DRIVER_MIPS
|
||||
select BCMA_DRIVER_PCI if PCI
|
||||
select BCMA_DRIVER_PCI_HOSTMODE if PCI
|
||||
select BCMA_DRIVER_GPIO
|
||||
default y
|
||||
|
|
|
@ -529,8 +529,8 @@ static void __init request_crashkernel(struct resource *res)
|
|||
|
||||
static void __init check_kernel_sections_mem(void)
|
||||
{
|
||||
phys_addr_t start = PFN_PHYS(PFN_DOWN(__pa_symbol(&_text)));
|
||||
phys_addr_t size = PFN_PHYS(PFN_UP(__pa_symbol(&_end))) - start;
|
||||
phys_addr_t start = __pa_symbol(&_text);
|
||||
phys_addr_t size = __pa_symbol(&_end) - start;
|
||||
|
||||
if (!memblock_is_region_memory(start, size)) {
|
||||
pr_info("Kernel sections are not in the memory maps\n");
|
||||
|
|
|
@ -217,15 +217,34 @@ static __inline__ void __clear_bit_unlock(int nr, volatile unsigned long *addr)
|
|||
*/
|
||||
static __inline__ int fls(unsigned int x)
|
||||
{
|
||||
return 32 - __builtin_clz(x);
|
||||
int lz;
|
||||
|
||||
if (__builtin_constant_p(x))
|
||||
return x ? 32 - __builtin_clz(x) : 0;
|
||||
asm("cntlzw %0,%1" : "=r" (lz) : "r" (x));
|
||||
return 32 - lz;
|
||||
}
|
||||
|
||||
#include <asm-generic/bitops/builtin-__fls.h>
|
||||
|
||||
/*
|
||||
* 64-bit can do this using one cntlzd (count leading zeroes doubleword)
|
||||
* instruction; for 32-bit we use the generic version, which does two
|
||||
* 32-bit fls calls.
|
||||
*/
|
||||
#ifdef CONFIG_PPC64
|
||||
static __inline__ int fls64(__u64 x)
|
||||
{
|
||||
return 64 - __builtin_clzll(x);
|
||||
int lz;
|
||||
|
||||
if (__builtin_constant_p(x))
|
||||
return x ? 64 - __builtin_clzll(x) : 0;
|
||||
asm("cntlzd %0,%1" : "=r" (lz) : "r" (x));
|
||||
return 64 - lz;
|
||||
}
|
||||
#else
|
||||
#include <asm-generic/bitops/fls64.h>
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PPC64
|
||||
unsigned int __arch_hweight8(unsigned int w);
|
||||
|
|
|
@ -557,9 +557,9 @@ static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
|
|||
if (pte_val(*ptep) & _PAGE_HASHPTE)
|
||||
flush_hash_entry(mm, ptep, addr);
|
||||
__asm__ __volatile__("\
|
||||
stw%U0%X0 %2,%0\n\
|
||||
stw%X0 %2,%0\n\
|
||||
eieio\n\
|
||||
stw%U0%X0 %L2,%1"
|
||||
stw%X1 %L2,%1"
|
||||
: "=m" (*ptep), "=m" (*((unsigned char *)ptep+4))
|
||||
: "r" (pte) : "memory");
|
||||
|
||||
|
|
|
@ -68,6 +68,7 @@ extern void cpm_reset(void);
|
|||
#define PROFF_SPI ((uint)0x0180)
|
||||
#define PROFF_SCC3 ((uint)0x0200)
|
||||
#define PROFF_SMC1 ((uint)0x0280)
|
||||
#define PROFF_DSP1 ((uint)0x02c0)
|
||||
#define PROFF_SCC4 ((uint)0x0300)
|
||||
#define PROFF_SMC2 ((uint)0x0380)
|
||||
|
||||
|
|
|
@ -379,7 +379,7 @@ static inline void cpu_feature_keys_init(void) { }
|
|||
CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
|
||||
#define CPU_FTRS_82XX (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_NOEXECUTE)
|
||||
#define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
|
||||
CPU_FTR_MAYBE_CAN_NAP)
|
||||
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NOEXECUTE)
|
||||
#define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \
|
||||
CPU_FTR_MAYBE_CAN_NAP | \
|
||||
CPU_FTR_COMMON | CPU_FTR_NOEXECUTE)
|
||||
|
@ -419,7 +419,6 @@ static inline void cpu_feature_keys_init(void) { }
|
|||
CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
|
||||
CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP | \
|
||||
CPU_FTR_CELL_TB_BUG | CPU_FTR_SMT)
|
||||
#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
|
||||
|
||||
/* 64-bit CPUs */
|
||||
#define CPU_FTRS_PPC970 (CPU_FTR_LWSYNC | \
|
||||
|
@ -519,8 +518,6 @@ enum {
|
|||
CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
|
||||
CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
|
||||
CPU_FTRS_CLASSIC32 |
|
||||
#else
|
||||
CPU_FTRS_GENERIC_32 |
|
||||
#endif
|
||||
#ifdef CONFIG_PPC_8xx
|
||||
CPU_FTRS_8XX |
|
||||
|
@ -597,8 +594,6 @@ enum {
|
|||
CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
|
||||
CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
|
||||
CPU_FTRS_CLASSIC32 &
|
||||
#else
|
||||
CPU_FTRS_GENERIC_32 &
|
||||
#endif
|
||||
#ifdef CONFIG_PPC_8xx
|
||||
CPU_FTRS_8XX &
|
||||
|
|
|
@ -199,9 +199,9 @@ static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
|
|||
*/
|
||||
if (IS_ENABLED(CONFIG_PPC32) && IS_ENABLED(CONFIG_PTE_64BIT) && !percpu) {
|
||||
__asm__ __volatile__("\
|
||||
stw%U0%X0 %2,%0\n\
|
||||
stw%X0 %2,%0\n\
|
||||
eieio\n\
|
||||
stw%U0%X0 %L2,%1"
|
||||
stw%X1 %L2,%1"
|
||||
: "=m" (*ptep), "=m" (*((unsigned char *)ptep+4))
|
||||
: "r" (pte) : "memory");
|
||||
return;
|
||||
|
|
|
@ -182,6 +182,9 @@ KCOV_INSTRUMENT_cputable.o := n
|
|||
KCOV_INSTRUMENT_setup_64.o := n
|
||||
KCOV_INSTRUMENT_paca.o := n
|
||||
|
||||
CFLAGS_setup_64.o += -fno-stack-protector
|
||||
CFLAGS_paca.o += -fno-stack-protector
|
||||
|
||||
extra-$(CONFIG_PPC_FPU) += fpu.o
|
||||
extra-$(CONFIG_ALTIVEC) += vector.o
|
||||
extra-$(CONFIG_PPC64) += entry_64.o
|
||||
|
|
|
@ -420,6 +420,10 @@ generic_secondary_common_init:
|
|||
/* From now on, r24 is expected to be logical cpuid */
|
||||
mr r24,r5
|
||||
|
||||
/* Create a temp kernel stack for use before relocation is on. */
|
||||
ld r1,PACAEMERGSP(r13)
|
||||
subi r1,r1,STACK_FRAME_OVERHEAD
|
||||
|
||||
/* See if we need to call a cpu state restore handler */
|
||||
LOAD_REG_ADDR(r23, cur_cpu_spec)
|
||||
ld r23,0(r23)
|
||||
|
@ -448,10 +452,6 @@ generic_secondary_common_init:
|
|||
sync /* order paca.run and cur_cpu_spec */
|
||||
isync /* In case code patching happened */
|
||||
|
||||
/* Create a temp kernel stack for use before relocation is on. */
|
||||
ld r1,PACAEMERGSP(r13)
|
||||
subi r1,r1,STACK_FRAME_OVERHEAD
|
||||
|
||||
b __secondary_start
|
||||
#endif /* SMP */
|
||||
|
||||
|
@ -992,7 +992,7 @@ start_here_common:
|
|||
bl start_kernel
|
||||
|
||||
/* Not reached */
|
||||
trap
|
||||
0: trap
|
||||
EMIT_BUG_ENTRY 0b, __FILE__, __LINE__, 0
|
||||
|
||||
/*
|
||||
|
|
|
@ -176,7 +176,7 @@ static struct slb_shadow * __init new_slb_shadow(int cpu, unsigned long limit)
|
|||
struct paca_struct **paca_ptrs __read_mostly;
|
||||
EXPORT_SYMBOL(paca_ptrs);
|
||||
|
||||
void __init __nostackprotector initialise_paca(struct paca_struct *new_paca, int cpu)
|
||||
void __init initialise_paca(struct paca_struct *new_paca, int cpu)
|
||||
{
|
||||
#ifdef CONFIG_PPC_PSERIES
|
||||
new_paca->lppaca_ptr = NULL;
|
||||
|
@ -205,7 +205,7 @@ void __init __nostackprotector initialise_paca(struct paca_struct *new_paca, int
|
|||
}
|
||||
|
||||
/* Put the paca pointer into r13 and SPRG_PACA */
|
||||
void __nostackprotector setup_paca(struct paca_struct *new_paca)
|
||||
void setup_paca(struct paca_struct *new_paca)
|
||||
{
|
||||
/* Setup r13 */
|
||||
local_paca = new_paca;
|
||||
|
|
|
@ -978,7 +978,7 @@ static struct rtas_filter rtas_filters[] __ro_after_init = {
|
|||
{ "ibm,display-message", -1, 0, -1, -1, -1 },
|
||||
{ "ibm,errinjct", -1, 2, -1, -1, -1, 1024 },
|
||||
{ "ibm,close-errinjct", -1, -1, -1, -1, -1 },
|
||||
{ "ibm,open-errinct", -1, -1, -1, -1, -1 },
|
||||
{ "ibm,open-errinjct", -1, -1, -1, -1, -1 },
|
||||
{ "ibm,get-config-addr-info2", -1, -1, -1, -1, -1 },
|
||||
{ "ibm,get-dynamic-sensor-state", -1, 1, -1, -1, -1 },
|
||||
{ "ibm,get-indices", -1, 2, 3, -1, -1 },
|
||||
|
|
|
@ -903,8 +903,6 @@ void __init setup_arch(char **cmdline_p)
|
|||
|
||||
/* On BookE, setup per-core TLB data structures. */
|
||||
setup_tlb_core_data();
|
||||
|
||||
smp_release_cpus();
|
||||
#endif
|
||||
|
||||
/* Print various info about the machine that has been gathered so far. */
|
||||
|
@ -925,6 +923,8 @@ void __init setup_arch(char **cmdline_p)
|
|||
exc_lvl_early_init();
|
||||
emergency_stack_init();
|
||||
|
||||
smp_release_cpus();
|
||||
|
||||
initmem_init();
|
||||
|
||||
early_memtest(min_low_pfn << PAGE_SHIFT, max_low_pfn << PAGE_SHIFT);
|
||||
|
|
|
@ -8,12 +8,6 @@
|
|||
#ifndef __ARCH_POWERPC_KERNEL_SETUP_H
|
||||
#define __ARCH_POWERPC_KERNEL_SETUP_H
|
||||
|
||||
#ifdef CONFIG_CC_IS_CLANG
|
||||
#define __nostackprotector
|
||||
#else
|
||||
#define __nostackprotector __attribute__((__optimize__("no-stack-protector")))
|
||||
#endif
|
||||
|
||||
void initialize_cache_info(void);
|
||||
void irqstack_early_init(void);
|
||||
|
||||
|
|
|
@ -284,7 +284,7 @@ void __init record_spr_defaults(void)
|
|||
* device-tree is not accessible via normal means at this point.
|
||||
*/
|
||||
|
||||
void __init __nostackprotector early_setup(unsigned long dt_ptr)
|
||||
void __init early_setup(unsigned long dt_ptr)
|
||||
{
|
||||
static __initdata struct paca_struct boot_paca;
|
||||
|
||||
|
|
|
@ -349,7 +349,6 @@ static inline void cmo_account_page_fault(void)
|
|||
static inline void cmo_account_page_fault(void) { }
|
||||
#endif /* CONFIG_PPC_SMLPAR */
|
||||
|
||||
#ifdef CONFIG_PPC_BOOK3S
|
||||
static void sanity_check_fault(bool is_write, bool is_user,
|
||||
unsigned long error_code, unsigned long address)
|
||||
{
|
||||
|
@ -366,6 +365,9 @@ static void sanity_check_fault(bool is_write, bool is_user,
|
|||
return;
|
||||
}
|
||||
|
||||
if (!IS_ENABLED(CONFIG_PPC_BOOK3S))
|
||||
return;
|
||||
|
||||
/*
|
||||
* For hash translation mode, we should never get a
|
||||
* PROTFAULT. Any update to pte to reduce access will result in us
|
||||
|
@ -400,10 +402,6 @@ static void sanity_check_fault(bool is_write, bool is_user,
|
|||
|
||||
WARN_ON_ONCE(error_code & DSISR_PROTFAULT);
|
||||
}
|
||||
#else
|
||||
static void sanity_check_fault(bool is_write, bool is_user,
|
||||
unsigned long error_code, unsigned long address) { }
|
||||
#endif /* CONFIG_PPC_BOOK3S */
|
||||
|
||||
/*
|
||||
* Define the correct "is_write" bit in error_code based
|
||||
|
|
|
@ -530,7 +530,7 @@ void __flush_dcache_icache(void *p)
|
|||
* space occurs, before returning to user space.
|
||||
*/
|
||||
|
||||
if (cpu_has_feature(MMU_FTR_TYPE_44x))
|
||||
if (mmu_has_feature(MMU_FTR_TYPE_44x))
|
||||
return;
|
||||
|
||||
invalidate_icache_range(addr, addr + PAGE_SIZE);
|
||||
|
|
|
@ -133,6 +133,9 @@ static void pmao_restore_workaround(bool ebb) { }
|
|||
|
||||
bool is_sier_available(void)
|
||||
{
|
||||
if (!ppmu)
|
||||
return false;
|
||||
|
||||
if (ppmu->flags & PPMU_HAS_SIER)
|
||||
return true;
|
||||
|
||||
|
@ -2086,6 +2089,16 @@ static void record_and_restart(struct perf_event *event, unsigned long val,
|
|||
local64_set(&event->hw.period_left, left);
|
||||
perf_event_update_userpage(event);
|
||||
|
||||
/*
|
||||
* Due to hardware limitation, sometimes SIAR could sample a kernel
|
||||
* address even when freeze on supervisor state (kernel) is set in
|
||||
* MMCR2. Check attr.exclude_kernel and address to drop the sample in
|
||||
* these cases.
|
||||
*/
|
||||
if (event->attr.exclude_kernel && record)
|
||||
if (is_kernel_addr(mfspr(SPRN_SIAR)))
|
||||
record = 0;
|
||||
|
||||
/*
|
||||
* Finally record data if requested.
|
||||
*/
|
||||
|
|
|
@ -361,6 +361,17 @@ void __init cpm_load_patch(cpm8xx_t *cp)
|
|||
if (IS_ENABLED(CONFIG_SMC_UCODE_PATCH)) {
|
||||
smc_uart_t *smp;
|
||||
|
||||
if (IS_ENABLED(CONFIG_PPC_EARLY_DEBUG_CPM)) {
|
||||
int i;
|
||||
|
||||
for (i = 0; i < sizeof(*smp); i += 4) {
|
||||
u32 __iomem *src = (u32 __iomem *)&cp->cp_dparam[PROFF_SMC1 + i];
|
||||
u32 __iomem *dst = (u32 __iomem *)&cp->cp_dparam[PROFF_DSP1 + i];
|
||||
|
||||
out_be32(dst, in_be32(src));
|
||||
}
|
||||
}
|
||||
|
||||
smp = (smc_uart_t *)&cp->cp_dparam[PROFF_SMC1];
|
||||
out_be16(&smp->smc_rpbase, 0x1ec0);
|
||||
smp = (smc_uart_t *)&cp->cp_dparam[PROFF_SMC2];
|
||||
|
|
|
@ -30,6 +30,7 @@ struct memtrace_entry {
|
|||
char name[16];
|
||||
};
|
||||
|
||||
static DEFINE_MUTEX(memtrace_mutex);
|
||||
static u64 memtrace_size;
|
||||
|
||||
static struct memtrace_entry *memtrace_array;
|
||||
|
@ -67,6 +68,23 @@ static int change_memblock_state(struct memory_block *mem, void *arg)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static void memtrace_clear_range(unsigned long start_pfn,
|
||||
unsigned long nr_pages)
|
||||
{
|
||||
unsigned long pfn;
|
||||
|
||||
/*
|
||||
* As pages are offline, we cannot trust the memmap anymore. As HIGHMEM
|
||||
* does not apply, avoid passing around "struct page" and use
|
||||
* clear_page() instead directly.
|
||||
*/
|
||||
for (pfn = start_pfn; pfn < start_pfn + nr_pages; pfn++) {
|
||||
if (IS_ALIGNED(pfn, PAGES_PER_SECTION))
|
||||
cond_resched();
|
||||
clear_page(__va(PFN_PHYS(pfn)));
|
||||
}
|
||||
}
|
||||
|
||||
/* called with device_hotplug_lock held */
|
||||
static bool memtrace_offline_pages(u32 nid, u64 start_pfn, u64 nr_pages)
|
||||
{
|
||||
|
@ -111,6 +129,11 @@ static u64 memtrace_alloc_node(u32 nid, u64 size)
|
|||
lock_device_hotplug();
|
||||
for (base_pfn = end_pfn; base_pfn > start_pfn; base_pfn -= nr_pages) {
|
||||
if (memtrace_offline_pages(nid, base_pfn, nr_pages) == true) {
|
||||
/*
|
||||
* Clear the range while we still have a linear
|
||||
* mapping.
|
||||
*/
|
||||
memtrace_clear_range(base_pfn, nr_pages);
|
||||
/*
|
||||
* Remove memory in memory block size chunks so that
|
||||
* iomem resources are always split to the same size and
|
||||
|
@ -268,6 +291,7 @@ static int memtrace_online(void)
|
|||
|
||||
static int memtrace_enable_set(void *data, u64 val)
|
||||
{
|
||||
int rc = -EAGAIN;
|
||||
u64 bytes;
|
||||
|
||||
/*
|
||||
|
@ -280,25 +304,31 @@ static int memtrace_enable_set(void *data, u64 val)
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
mutex_lock(&memtrace_mutex);
|
||||
|
||||
/* Re-add/online previously removed/offlined memory */
|
||||
if (memtrace_size) {
|
||||
if (memtrace_online())
|
||||
return -EAGAIN;
|
||||
goto out_unlock;
|
||||
}
|
||||
|
||||
if (!val)
|
||||
return 0;
|
||||
if (!val) {
|
||||
rc = 0;
|
||||
goto out_unlock;
|
||||
}
|
||||
|
||||
/* Offline and remove memory */
|
||||
if (memtrace_init_regions_runtime(val))
|
||||
return -EINVAL;
|
||||
goto out_unlock;
|
||||
|
||||
if (memtrace_init_debugfs())
|
||||
return -EINVAL;
|
||||
goto out_unlock;
|
||||
|
||||
memtrace_size = val;
|
||||
|
||||
return 0;
|
||||
rc = 0;
|
||||
out_unlock:
|
||||
mutex_unlock(&memtrace_mutex);
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int memtrace_enable_get(void *data, u64 *val)
|
||||
|
|
|
@ -384,7 +384,8 @@ static void pnv_npu_peers_take_ownership(struct iommu_table_group *table_group)
|
|||
for (i = 0; i < npucomp->pe_num; ++i) {
|
||||
struct pnv_ioda_pe *pe = npucomp->pe[i];
|
||||
|
||||
if (!pe->table_group.ops->take_ownership)
|
||||
if (!pe->table_group.ops ||
|
||||
!pe->table_group.ops->take_ownership)
|
||||
continue;
|
||||
pe->table_group.ops->take_ownership(&pe->table_group);
|
||||
}
|
||||
|
@ -400,7 +401,8 @@ static void pnv_npu_peers_release_ownership(
|
|||
for (i = 0; i < npucomp->pe_num; ++i) {
|
||||
struct pnv_ioda_pe *pe = npucomp->pe[i];
|
||||
|
||||
if (!pe->table_group.ops->release_ownership)
|
||||
if (!pe->table_group.ops ||
|
||||
!pe->table_group.ops->release_ownership)
|
||||
continue;
|
||||
pe->table_group.ops->release_ownership(&pe->table_group);
|
||||
}
|
||||
|
@ -560,6 +562,11 @@ int pnv_npu2_map_lpar_dev(struct pci_dev *gpdev, unsigned int lparid,
|
|||
return -ENODEV;
|
||||
|
||||
hose = pci_bus_to_host(npdev->bus);
|
||||
if (hose->npu == NULL) {
|
||||
dev_info_once(&npdev->dev, "Nvlink1 does not support contexts");
|
||||
return 0;
|
||||
}
|
||||
|
||||
nphb = hose->private_data;
|
||||
|
||||
dev_dbg(&gpdev->dev, "Map LPAR opalid=%llu lparid=%u\n",
|
||||
|
@ -607,6 +614,11 @@ int pnv_npu2_unmap_lpar_dev(struct pci_dev *gpdev)
|
|||
return -ENODEV;
|
||||
|
||||
hose = pci_bus_to_host(npdev->bus);
|
||||
if (hose->npu == NULL) {
|
||||
dev_info_once(&npdev->dev, "Nvlink1 does not support contexts");
|
||||
return 0;
|
||||
}
|
||||
|
||||
nphb = hose->private_data;
|
||||
|
||||
dev_dbg(&gpdev->dev, "destroy context opalid=%llu\n",
|
||||
|
|
|
@ -13,7 +13,6 @@
|
|||
#include <asm/mmu.h>
|
||||
#include <asm/rtas.h>
|
||||
#include <asm/topology.h>
|
||||
#include "../../kernel/cacheinfo.h"
|
||||
|
||||
static u64 stream_id;
|
||||
static struct device suspend_dev;
|
||||
|
@ -78,9 +77,7 @@ static void pseries_suspend_enable_irqs(void)
|
|||
* Update configuration which can be modified based on device tree
|
||||
* changes during resume.
|
||||
*/
|
||||
cacheinfo_cpu_offline(smp_processor_id());
|
||||
post_mobility_fixup();
|
||||
cacheinfo_cpu_online(smp_processor_id());
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -190,7 +187,6 @@ static struct bus_type suspend_subsys = {
|
|||
|
||||
static const struct platform_suspend_ops pseries_suspend_ops = {
|
||||
.valid = suspend_valid_only_mem,
|
||||
.begin = pseries_suspend_begin,
|
||||
.prepare_late = pseries_prepare_late,
|
||||
.enter = pseries_suspend_enter,
|
||||
};
|
||||
|
|
|
@ -191,7 +191,7 @@ static int mpic_msgr_probe(struct platform_device *dev)
|
|||
|
||||
/* IO map the message register block. */
|
||||
of_address_to_resource(np, 0, &rsrc);
|
||||
msgr_block_addr = ioremap(rsrc.start, resource_size(&rsrc));
|
||||
msgr_block_addr = devm_ioremap(&dev->dev, rsrc.start, resource_size(&rsrc));
|
||||
if (!msgr_block_addr) {
|
||||
dev_err(&dev->dev, "Failed to iomap MPIC message registers");
|
||||
return -EFAULT;
|
||||
|
|
|
@ -178,7 +178,7 @@ void xmon_printf(const char *format, ...)
|
|||
|
||||
if (n && rc == 0) {
|
||||
/* No udbg hooks, fallback to printk() - dangerous */
|
||||
printk("%s", xmon_outbuf);
|
||||
pr_cont("%s", xmon_outbuf);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -885,24 +885,12 @@ static void __no_sanitize_address smp_start_secondary(void *cpuvoid)
|
|||
/* Upping and downing of CPUs */
|
||||
int __cpu_up(unsigned int cpu, struct task_struct *tidle)
|
||||
{
|
||||
struct pcpu *pcpu;
|
||||
int base, i, rc;
|
||||
struct pcpu *pcpu = pcpu_devices + cpu;
|
||||
int rc;
|
||||
|
||||
pcpu = pcpu_devices + cpu;
|
||||
if (pcpu->state != CPU_STATE_CONFIGURED)
|
||||
return -EIO;
|
||||
base = smp_get_base_cpu(cpu);
|
||||
for (i = 0; i <= smp_cpu_mtid; i++) {
|
||||
if (base + i < nr_cpu_ids)
|
||||
if (cpu_online(base + i))
|
||||
break;
|
||||
}
|
||||
/*
|
||||
* If this is the first CPU of the core to get online
|
||||
* do an initial CPU reset.
|
||||
*/
|
||||
if (i > smp_cpu_mtid &&
|
||||
pcpu_sigp_retry(pcpu_devices + base, SIGP_INITIAL_CPU_RESET, 0) !=
|
||||
if (pcpu_sigp_retry(pcpu, SIGP_INITIAL_CPU_RESET, 0) !=
|
||||
SIGP_CC_ORDER_CODE_ACCEPTED)
|
||||
return -EIO;
|
||||
|
||||
|
|
|
@ -62,14 +62,15 @@
|
|||
jh 10b
|
||||
.endm
|
||||
|
||||
.macro START_NEXT_KERNEL base
|
||||
.macro START_NEXT_KERNEL base subcode
|
||||
lg %r4,kernel_entry-\base(%r13)
|
||||
lg %r5,load_psw_mask-\base(%r13)
|
||||
ogr %r4,%r5
|
||||
stg %r4,0(%r0)
|
||||
|
||||
xgr %r0,%r0
|
||||
diag %r0,%r0,0x308
|
||||
lghi %r1,\subcode
|
||||
diag %r0,%r1,0x308
|
||||
.endm
|
||||
|
||||
.text
|
||||
|
@ -123,7 +124,7 @@ ENTRY(purgatory_start)
|
|||
je .start_crash_kernel
|
||||
|
||||
/* start normal kernel */
|
||||
START_NEXT_KERNEL .base_crash
|
||||
START_NEXT_KERNEL .base_crash 0
|
||||
|
||||
.return_old_kernel:
|
||||
lmg %r6,%r15,gprregs-.base_crash(%r13)
|
||||
|
@ -227,7 +228,7 @@ ENTRY(purgatory_start)
|
|||
MEMCPY %r9,%r10,%r11
|
||||
|
||||
/* start crash kernel */
|
||||
START_NEXT_KERNEL .base_dst
|
||||
START_NEXT_KERNEL .base_dst 1
|
||||
|
||||
|
||||
load_psw_mask:
|
||||
|
|
|
@ -2904,7 +2904,7 @@ pgtable_t pte_alloc_one(struct mm_struct *mm)
|
|||
if (!page)
|
||||
return NULL;
|
||||
if (!pgtable_pte_page_ctor(page)) {
|
||||
free_unref_page(page);
|
||||
__free_page(page);
|
||||
return NULL;
|
||||
}
|
||||
return (pte_t *) page_address(page);
|
||||
|
|
|
@ -26,10 +26,10 @@ int generic_read(int fd, char *c_out, void *unused)
|
|||
n = read(fd, c_out, sizeof(*c_out));
|
||||
if (n > 0)
|
||||
return n;
|
||||
else if (errno == EAGAIN)
|
||||
return 0;
|
||||
else if (n == 0)
|
||||
return -EIO;
|
||||
else if (errno == EAGAIN)
|
||||
return 0;
|
||||
return -errno;
|
||||
}
|
||||
|
||||
|
|
|
@ -47,18 +47,25 @@
|
|||
/* Max request size is determined by sector mask - 32K */
|
||||
#define UBD_MAX_REQUEST (8 * sizeof(long))
|
||||
|
||||
struct io_desc {
|
||||
char *buffer;
|
||||
unsigned long length;
|
||||
unsigned long sector_mask;
|
||||
unsigned long long cow_offset;
|
||||
unsigned long bitmap_words[2];
|
||||
};
|
||||
|
||||
struct io_thread_req {
|
||||
struct request *req;
|
||||
int fds[2];
|
||||
unsigned long offsets[2];
|
||||
unsigned long long offset;
|
||||
unsigned long length;
|
||||
char *buffer;
|
||||
int sectorsize;
|
||||
unsigned long sector_mask;
|
||||
unsigned long long cow_offset;
|
||||
unsigned long bitmap_words[2];
|
||||
int error;
|
||||
|
||||
int desc_cnt;
|
||||
/* io_desc has to be the last element of the struct */
|
||||
struct io_desc io_desc[];
|
||||
};
|
||||
|
||||
|
||||
|
@ -524,12 +531,7 @@ static void ubd_handler(void)
|
|||
blk_queue_max_write_zeroes_sectors(io_req->req->q, 0);
|
||||
blk_queue_flag_clear(QUEUE_FLAG_DISCARD, io_req->req->q);
|
||||
}
|
||||
if ((io_req->error) || (io_req->buffer == NULL))
|
||||
blk_mq_end_request(io_req->req, io_req->error);
|
||||
else {
|
||||
if (!blk_update_request(io_req->req, io_req->error, io_req->length))
|
||||
__blk_mq_end_request(io_req->req, io_req->error);
|
||||
}
|
||||
blk_mq_end_request(io_req->req, io_req->error);
|
||||
kfree(io_req);
|
||||
}
|
||||
}
|
||||
|
@ -945,6 +947,7 @@ static int ubd_add(int n, char **error_out)
|
|||
blk_queue_write_cache(ubd_dev->queue, true, false);
|
||||
|
||||
blk_queue_max_segments(ubd_dev->queue, MAX_SG);
|
||||
blk_queue_segment_boundary(ubd_dev->queue, PAGE_SIZE - 1);
|
||||
err = ubd_disk_register(UBD_MAJOR, ubd_dev->size, n, &ubd_gendisk[n]);
|
||||
if(err){
|
||||
*error_out = "Failed to register device";
|
||||
|
@ -1288,37 +1291,74 @@ static void cowify_bitmap(__u64 io_offset, int length, unsigned long *cow_mask,
|
|||
*cow_offset += bitmap_offset;
|
||||
}
|
||||
|
||||
static void cowify_req(struct io_thread_req *req, unsigned long *bitmap,
|
||||
static void cowify_req(struct io_thread_req *req, struct io_desc *segment,
|
||||
unsigned long offset, unsigned long *bitmap,
|
||||
__u64 bitmap_offset, __u64 bitmap_len)
|
||||
{
|
||||
__u64 sector = req->offset >> SECTOR_SHIFT;
|
||||
__u64 sector = offset >> SECTOR_SHIFT;
|
||||
int i;
|
||||
|
||||
if (req->length > (sizeof(req->sector_mask) * 8) << SECTOR_SHIFT)
|
||||
if (segment->length > (sizeof(segment->sector_mask) * 8) << SECTOR_SHIFT)
|
||||
panic("Operation too long");
|
||||
|
||||
if (req_op(req->req) == REQ_OP_READ) {
|
||||
for (i = 0; i < req->length >> SECTOR_SHIFT; i++) {
|
||||
for (i = 0; i < segment->length >> SECTOR_SHIFT; i++) {
|
||||
if(ubd_test_bit(sector + i, (unsigned char *) bitmap))
|
||||
ubd_set_bit(i, (unsigned char *)
|
||||
&req->sector_mask);
|
||||
&segment->sector_mask);
|
||||
}
|
||||
} else {
|
||||
cowify_bitmap(offset, segment->length, &segment->sector_mask,
|
||||
&segment->cow_offset, bitmap, bitmap_offset,
|
||||
segment->bitmap_words, bitmap_len);
|
||||
}
|
||||
else cowify_bitmap(req->offset, req->length, &req->sector_mask,
|
||||
&req->cow_offset, bitmap, bitmap_offset,
|
||||
req->bitmap_words, bitmap_len);
|
||||
}
|
||||
|
||||
static int ubd_queue_one_vec(struct blk_mq_hw_ctx *hctx, struct request *req,
|
||||
u64 off, struct bio_vec *bvec)
|
||||
static void ubd_map_req(struct ubd *dev, struct io_thread_req *io_req,
|
||||
struct request *req)
|
||||
{
|
||||
struct ubd *dev = hctx->queue->queuedata;
|
||||
struct io_thread_req *io_req;
|
||||
int ret;
|
||||
struct bio_vec bvec;
|
||||
struct req_iterator iter;
|
||||
int i = 0;
|
||||
unsigned long byte_offset = io_req->offset;
|
||||
int op = req_op(req);
|
||||
|
||||
io_req = kmalloc(sizeof(struct io_thread_req), GFP_ATOMIC);
|
||||
if (op == REQ_OP_WRITE_ZEROES || op == REQ_OP_DISCARD) {
|
||||
io_req->io_desc[0].buffer = NULL;
|
||||
io_req->io_desc[0].length = blk_rq_bytes(req);
|
||||
} else {
|
||||
rq_for_each_segment(bvec, req, iter) {
|
||||
BUG_ON(i >= io_req->desc_cnt);
|
||||
|
||||
io_req->io_desc[i].buffer =
|
||||
page_address(bvec.bv_page) + bvec.bv_offset;
|
||||
io_req->io_desc[i].length = bvec.bv_len;
|
||||
i++;
|
||||
}
|
||||
}
|
||||
|
||||
if (dev->cow.file) {
|
||||
for (i = 0; i < io_req->desc_cnt; i++) {
|
||||
cowify_req(io_req, &io_req->io_desc[i], byte_offset,
|
||||
dev->cow.bitmap, dev->cow.bitmap_offset,
|
||||
dev->cow.bitmap_len);
|
||||
byte_offset += io_req->io_desc[i].length;
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
static struct io_thread_req *ubd_alloc_req(struct ubd *dev, struct request *req,
|
||||
int desc_cnt)
|
||||
{
|
||||
struct io_thread_req *io_req;
|
||||
int i;
|
||||
|
||||
io_req = kmalloc(sizeof(*io_req) +
|
||||
(desc_cnt * sizeof(struct io_desc)),
|
||||
GFP_ATOMIC);
|
||||
if (!io_req)
|
||||
return -ENOMEM;
|
||||
return NULL;
|
||||
|
||||
io_req->req = req;
|
||||
if (dev->cow.file)
|
||||
|
@ -1326,26 +1366,41 @@ static int ubd_queue_one_vec(struct blk_mq_hw_ctx *hctx, struct request *req,
|
|||
else
|
||||
io_req->fds[0] = dev->fd;
|
||||
io_req->error = 0;
|
||||
|
||||
if (bvec != NULL) {
|
||||
io_req->buffer = page_address(bvec->bv_page) + bvec->bv_offset;
|
||||
io_req->length = bvec->bv_len;
|
||||
} else {
|
||||
io_req->buffer = NULL;
|
||||
io_req->length = blk_rq_bytes(req);
|
||||
}
|
||||
|
||||
io_req->sectorsize = SECTOR_SIZE;
|
||||
io_req->fds[1] = dev->fd;
|
||||
io_req->cow_offset = -1;
|
||||
io_req->offset = off;
|
||||
io_req->sector_mask = 0;
|
||||
io_req->offset = (u64) blk_rq_pos(req) << SECTOR_SHIFT;
|
||||
io_req->offsets[0] = 0;
|
||||
io_req->offsets[1] = dev->cow.data_offset;
|
||||
|
||||
if (dev->cow.file)
|
||||
cowify_req(io_req, dev->cow.bitmap,
|
||||
dev->cow.bitmap_offset, dev->cow.bitmap_len);
|
||||
for (i = 0 ; i < desc_cnt; i++) {
|
||||
io_req->io_desc[i].sector_mask = 0;
|
||||
io_req->io_desc[i].cow_offset = -1;
|
||||
}
|
||||
|
||||
return io_req;
|
||||
}
|
||||
|
||||
static int ubd_submit_request(struct ubd *dev, struct request *req)
|
||||
{
|
||||
int segs = 0;
|
||||
struct io_thread_req *io_req;
|
||||
int ret;
|
||||
int op = req_op(req);
|
||||
|
||||
if (op == REQ_OP_FLUSH)
|
||||
segs = 0;
|
||||
else if (op == REQ_OP_WRITE_ZEROES || op == REQ_OP_DISCARD)
|
||||
segs = 1;
|
||||
else
|
||||
segs = blk_rq_nr_phys_segments(req);
|
||||
|
||||
io_req = ubd_alloc_req(dev, req, segs);
|
||||
if (!io_req)
|
||||
return -ENOMEM;
|
||||
|
||||
io_req->desc_cnt = segs;
|
||||
if (segs)
|
||||
ubd_map_req(dev, io_req, req);
|
||||
|
||||
ret = os_write_file(thread_fd, &io_req, sizeof(io_req));
|
||||
if (ret != sizeof(io_req)) {
|
||||
|
@ -1356,22 +1411,6 @@ static int ubd_queue_one_vec(struct blk_mq_hw_ctx *hctx, struct request *req,
|
|||
return ret;
|
||||
}
|
||||
|
||||
static int queue_rw_req(struct blk_mq_hw_ctx *hctx, struct request *req)
|
||||
{
|
||||
struct req_iterator iter;
|
||||
struct bio_vec bvec;
|
||||
int ret;
|
||||
u64 off = (u64)blk_rq_pos(req) << SECTOR_SHIFT;
|
||||
|
||||
rq_for_each_segment(bvec, req, iter) {
|
||||
ret = ubd_queue_one_vec(hctx, req, off, &bvec);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
off += bvec.bv_len;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static blk_status_t ubd_queue_rq(struct blk_mq_hw_ctx *hctx,
|
||||
const struct blk_mq_queue_data *bd)
|
||||
{
|
||||
|
@ -1384,17 +1423,12 @@ static blk_status_t ubd_queue_rq(struct blk_mq_hw_ctx *hctx,
|
|||
spin_lock_irq(&ubd_dev->lock);
|
||||
|
||||
switch (req_op(req)) {
|
||||
/* operations with no lentgth/offset arguments */
|
||||
case REQ_OP_FLUSH:
|
||||
ret = ubd_queue_one_vec(hctx, req, 0, NULL);
|
||||
break;
|
||||
case REQ_OP_READ:
|
||||
case REQ_OP_WRITE:
|
||||
ret = queue_rw_req(hctx, req);
|
||||
break;
|
||||
case REQ_OP_DISCARD:
|
||||
case REQ_OP_WRITE_ZEROES:
|
||||
ret = ubd_queue_one_vec(hctx, req, (u64)blk_rq_pos(req) << 9, NULL);
|
||||
ret = ubd_submit_request(ubd_dev, req);
|
||||
break;
|
||||
default:
|
||||
WARN_ON_ONCE(1);
|
||||
|
@ -1482,22 +1516,22 @@ static int map_error(int error_code)
|
|||
* will result in unpredictable behaviour and/or crashes.
|
||||
*/
|
||||
|
||||
static int update_bitmap(struct io_thread_req *req)
|
||||
static int update_bitmap(struct io_thread_req *req, struct io_desc *segment)
|
||||
{
|
||||
int n;
|
||||
|
||||
if(req->cow_offset == -1)
|
||||
if (segment->cow_offset == -1)
|
||||
return map_error(0);
|
||||
|
||||
n = os_pwrite_file(req->fds[1], &req->bitmap_words,
|
||||
sizeof(req->bitmap_words), req->cow_offset);
|
||||
if (n != sizeof(req->bitmap_words))
|
||||
n = os_pwrite_file(req->fds[1], &segment->bitmap_words,
|
||||
sizeof(segment->bitmap_words), segment->cow_offset);
|
||||
if (n != sizeof(segment->bitmap_words))
|
||||
return map_error(-n);
|
||||
|
||||
return map_error(0);
|
||||
}
|
||||
|
||||
static void do_io(struct io_thread_req *req)
|
||||
static void do_io(struct io_thread_req *req, struct io_desc *desc)
|
||||
{
|
||||
char *buf = NULL;
|
||||
unsigned long len;
|
||||
|
@ -1512,21 +1546,20 @@ static void do_io(struct io_thread_req *req)
|
|||
return;
|
||||
}
|
||||
|
||||
nsectors = req->length / req->sectorsize;
|
||||
nsectors = desc->length / req->sectorsize;
|
||||
start = 0;
|
||||
do {
|
||||
bit = ubd_test_bit(start, (unsigned char *) &req->sector_mask);
|
||||
bit = ubd_test_bit(start, (unsigned char *) &desc->sector_mask);
|
||||
end = start;
|
||||
while((end < nsectors) &&
|
||||
(ubd_test_bit(end, (unsigned char *)
|
||||
&req->sector_mask) == bit))
|
||||
(ubd_test_bit(end, (unsigned char *) &desc->sector_mask) == bit))
|
||||
end++;
|
||||
|
||||
off = req->offset + req->offsets[bit] +
|
||||
start * req->sectorsize;
|
||||
len = (end - start) * req->sectorsize;
|
||||
if (req->buffer != NULL)
|
||||
buf = &req->buffer[start * req->sectorsize];
|
||||
if (desc->buffer != NULL)
|
||||
buf = &desc->buffer[start * req->sectorsize];
|
||||
|
||||
switch (req_op(req->req)) {
|
||||
case REQ_OP_READ:
|
||||
|
@ -1566,7 +1599,8 @@ static void do_io(struct io_thread_req *req)
|
|||
start = end;
|
||||
} while(start < nsectors);
|
||||
|
||||
req->error = update_bitmap(req);
|
||||
req->offset += len;
|
||||
req->error = update_bitmap(req, desc);
|
||||
}
|
||||
|
||||
/* Changed in start_io_thread, which is serialized by being called only
|
||||
|
@ -1599,8 +1633,13 @@ int io_thread(void *arg)
|
|||
}
|
||||
|
||||
for (count = 0; count < n/sizeof(struct io_thread_req *); count++) {
|
||||
struct io_thread_req *req = (*io_req_buffer)[count];
|
||||
int i;
|
||||
|
||||
io_count++;
|
||||
do_io((*io_req_buffer)[count]);
|
||||
for (i = 0; !req->error && i < req->desc_cnt; i++)
|
||||
do_io(req, &(req->io_desc[i]));
|
||||
|
||||
}
|
||||
|
||||
written = 0;
|
||||
|
|
|
@ -18,6 +18,7 @@
|
|||
struct xterm_chan {
|
||||
int pid;
|
||||
int helper_pid;
|
||||
int chan_fd;
|
||||
char *title;
|
||||
int device;
|
||||
int raw;
|
||||
|
@ -33,6 +34,7 @@ static void *xterm_init(char *str, int device, const struct chan_opts *opts)
|
|||
return NULL;
|
||||
*data = ((struct xterm_chan) { .pid = -1,
|
||||
.helper_pid = -1,
|
||||
.chan_fd = -1,
|
||||
.device = device,
|
||||
.title = opts->xterm_title,
|
||||
.raw = opts->raw } );
|
||||
|
@ -149,6 +151,7 @@ static int xterm_open(int input, int output, int primary, void *d,
|
|||
goto out_kill;
|
||||
}
|
||||
|
||||
data->chan_fd = fd;
|
||||
new = xterm_fd(fd, &data->helper_pid);
|
||||
if (new < 0) {
|
||||
err = new;
|
||||
|
@ -206,6 +209,8 @@ static void xterm_close(int fd, void *d)
|
|||
os_kill_process(data->helper_pid, 0);
|
||||
data->helper_pid = -1;
|
||||
|
||||
if (data->chan_fd != -1)
|
||||
os_close_file(data->chan_fd);
|
||||
os_close_file(fd);
|
||||
}
|
||||
|
||||
|
|
|
@ -48,7 +48,7 @@ int os_epoll_triggered(int index, int events)
|
|||
int os_event_mask(int irq_type)
|
||||
{
|
||||
if (irq_type == IRQ_READ)
|
||||
return EPOLLIN | EPOLLPRI;
|
||||
return EPOLLIN | EPOLLPRI | EPOLLERR | EPOLLHUP | EPOLLRDHUP;
|
||||
if (irq_type == IRQ_WRITE)
|
||||
return EPOLLOUT;
|
||||
return 0;
|
||||
|
|
|
@ -137,20 +137,13 @@ static inline int is_umdir_used(char *dir)
|
|||
{
|
||||
char pid[sizeof("nnnnn\0")], *end, *file;
|
||||
int dead, fd, p, n, err;
|
||||
size_t filelen;
|
||||
size_t filelen = strlen(dir) + sizeof("/pid") + 1;
|
||||
|
||||
err = asprintf(&file, "%s/pid", dir);
|
||||
if (err < 0)
|
||||
return 0;
|
||||
file = malloc(filelen);
|
||||
if (!file)
|
||||
return -ENOMEM;
|
||||
|
||||
filelen = strlen(file);
|
||||
|
||||
n = snprintf(file, filelen, "%s/pid", dir);
|
||||
if (n >= filelen) {
|
||||
printk(UM_KERN_ERR "is_umdir_used - pid filename too long\n");
|
||||
err = -E2BIG;
|
||||
goto out;
|
||||
}
|
||||
snprintf(file, filelen, "%s/pid", dir);
|
||||
|
||||
dead = 0;
|
||||
fd = open(file, O_RDONLY);
|
||||
|
|
|
@ -253,7 +253,8 @@ static struct event_constraint intel_icl_event_constraints[] = {
|
|||
INTEL_EVENT_CONSTRAINT_RANGE(0x48, 0x54, 0xf),
|
||||
INTEL_EVENT_CONSTRAINT_RANGE(0x60, 0x8b, 0xf),
|
||||
INTEL_UEVENT_CONSTRAINT(0x04a3, 0xff), /* CYCLE_ACTIVITY.STALLS_TOTAL */
|
||||
INTEL_UEVENT_CONSTRAINT(0x10a3, 0xff), /* CYCLE_ACTIVITY.STALLS_MEM_ANY */
|
||||
INTEL_UEVENT_CONSTRAINT(0x10a3, 0xff), /* CYCLE_ACTIVITY.CYCLES_MEM_ANY */
|
||||
INTEL_UEVENT_CONSTRAINT(0x14a3, 0xff), /* CYCLE_ACTIVITY.STALLS_MEM_ANY */
|
||||
INTEL_EVENT_CONSTRAINT(0xa3, 0xf), /* CYCLE_ACTIVITY.* */
|
||||
INTEL_EVENT_CONSTRAINT_RANGE(0xa8, 0xb0, 0xf),
|
||||
INTEL_EVENT_CONSTRAINT_RANGE(0xb7, 0xbd, 0xf),
|
||||
|
@ -5057,7 +5058,7 @@ __init int intel_pmu_init(void)
|
|||
extra_skl_attr = skl_format_attr;
|
||||
mem_attr = icl_events_attrs;
|
||||
tsx_attr = icl_tsx_events_attrs;
|
||||
x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xca, .umask=0x02);
|
||||
x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04);
|
||||
x86_pmu.lbr_pt_coexist = true;
|
||||
intel_pmu_pebs_data_source_skl(pmem);
|
||||
pr_cont("Icelake events, ");
|
||||
|
|
|
@ -1912,7 +1912,7 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
|
|||
* that caused the PEBS record. It's called collision.
|
||||
* If collision happened, the record will be dropped.
|
||||
*/
|
||||
if (p->status != (1ULL << bit)) {
|
||||
if (pebs_status != (1ULL << bit)) {
|
||||
for_each_set_bit(i, (unsigned long *)&pebs_status, size)
|
||||
error[i]++;
|
||||
continue;
|
||||
|
|
|
@ -259,6 +259,7 @@ static inline u64 native_x2apic_icr_read(void)
|
|||
|
||||
extern int x2apic_mode;
|
||||
extern int x2apic_phys;
|
||||
extern void __init x2apic_set_max_apicid(u32 apicid);
|
||||
extern void __init check_x2apic(void);
|
||||
extern void x2apic_setup(void);
|
||||
static inline int x2apic_enabled(void)
|
||||
|
|
|
@ -2,7 +2,7 @@
|
|||
#ifndef _ASM_X86_CACHEINFO_H
|
||||
#define _ASM_X86_CACHEINFO_H
|
||||
|
||||
void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, int cpu, u8 node_id);
|
||||
void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *c, int cpu, u8 node_id);
|
||||
void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, int cpu);
|
||||
void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *c, int cpu);
|
||||
|
||||
#endif /* _ASM_X86_CACHEINFO_H */
|
||||
|
|
|
@ -1886,20 +1886,22 @@ static __init void try_to_enable_x2apic(int remap_mode)
|
|||
return;
|
||||
|
||||
if (remap_mode != IRQ_REMAP_X2APIC_MODE) {
|
||||
/* IR is required if there is APIC ID > 255 even when running
|
||||
* under KVM
|
||||
/*
|
||||
* Using X2APIC without IR is not architecturally supported
|
||||
* on bare metal but may be supported in guests.
|
||||
*/
|
||||
if (max_physical_apicid > 255 ||
|
||||
!x86_init.hyper.x2apic_available()) {
|
||||
if (!x86_init.hyper.x2apic_available()) {
|
||||
pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n");
|
||||
x2apic_disable();
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* without IR all CPUs can be addressed by IOAPIC/MSI
|
||||
* only in physical mode
|
||||
* Without IR, all CPUs can be addressed by IOAPIC/MSI only
|
||||
* in physical mode, and CPUs with an APIC ID that cannnot
|
||||
* be addressed must not be brought online.
|
||||
*/
|
||||
x2apic_set_max_apicid(255);
|
||||
x2apic_phys = 1;
|
||||
}
|
||||
x2apic_enable();
|
||||
|
|
|
@ -8,6 +8,12 @@
|
|||
int x2apic_phys;
|
||||
|
||||
static struct apic apic_x2apic_phys;
|
||||
static u32 x2apic_max_apicid __ro_after_init;
|
||||
|
||||
void __init x2apic_set_max_apicid(u32 apicid)
|
||||
{
|
||||
x2apic_max_apicid = apicid;
|
||||
}
|
||||
|
||||
static int __init set_x2apic_phys_mode(char *arg)
|
||||
{
|
||||
|
@ -98,6 +104,9 @@ static int x2apic_phys_probe(void)
|
|||
/* Common x2apic functions, also used by x2apic_cluster */
|
||||
int x2apic_apic_id_valid(u32 apicid)
|
||||
{
|
||||
if (x2apic_max_apicid && apicid > x2apic_max_apicid)
|
||||
return 0;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
|
|
@ -335,7 +335,6 @@ static void amd_get_topology_early(struct cpuinfo_x86 *c)
|
|||
*/
|
||||
static void amd_get_topology(struct cpuinfo_x86 *c)
|
||||
{
|
||||
u8 node_id;
|
||||
int cpu = smp_processor_id();
|
||||
|
||||
/* get information required for multi-node processors */
|
||||
|
@ -345,7 +344,7 @@ static void amd_get_topology(struct cpuinfo_x86 *c)
|
|||
|
||||
cpuid(0x8000001e, &eax, &ebx, &ecx, &edx);
|
||||
|
||||
node_id = ecx & 0xff;
|
||||
c->cpu_die_id = ecx & 0xff;
|
||||
|
||||
if (c->x86 == 0x15)
|
||||
c->cu_id = ebx & 0xff;
|
||||
|
@ -365,15 +364,15 @@ static void amd_get_topology(struct cpuinfo_x86 *c)
|
|||
if (!err)
|
||||
c->x86_coreid_bits = get_count_order(c->x86_max_cores);
|
||||
|
||||
cacheinfo_amd_init_llc_id(c, cpu, node_id);
|
||||
cacheinfo_amd_init_llc_id(c, cpu);
|
||||
|
||||
} else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) {
|
||||
u64 value;
|
||||
|
||||
rdmsrl(MSR_FAM10H_NODE_ID, value);
|
||||
node_id = value & 7;
|
||||
c->cpu_die_id = value & 7;
|
||||
|
||||
per_cpu(cpu_llc_id, cpu) = node_id;
|
||||
per_cpu(cpu_llc_id, cpu) = c->cpu_die_id;
|
||||
} else
|
||||
return;
|
||||
|
||||
|
@ -398,7 +397,7 @@ static void amd_detect_cmp(struct cpuinfo_x86 *c)
|
|||
/* Convert the initial APIC ID into the socket ID */
|
||||
c->phys_proc_id = c->initial_apicid >> bits;
|
||||
/* use socket ID also for last level cache */
|
||||
per_cpu(cpu_llc_id, cpu) = c->phys_proc_id;
|
||||
per_cpu(cpu_llc_id, cpu) = c->cpu_die_id = c->phys_proc_id;
|
||||
}
|
||||
|
||||
u16 amd_get_nb_id(int cpu)
|
||||
|
|
|
@ -646,7 +646,7 @@ static int find_num_cache_leaves(struct cpuinfo_x86 *c)
|
|||
return i;
|
||||
}
|
||||
|
||||
void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, int cpu, u8 node_id)
|
||||
void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, int cpu)
|
||||
{
|
||||
/*
|
||||
* We may have multiple LLCs if L3 caches exist, so check if we
|
||||
|
@ -657,7 +657,7 @@ void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, int cpu, u8 node_id)
|
|||
|
||||
if (c->x86 < 0x17) {
|
||||
/* LLC is at the node level. */
|
||||
per_cpu(cpu_llc_id, cpu) = node_id;
|
||||
per_cpu(cpu_llc_id, cpu) = c->cpu_die_id;
|
||||
} else if (c->x86 == 0x17 && c->x86_model <= 0x1F) {
|
||||
/*
|
||||
* LLC is at the core complex level.
|
||||
|
@ -684,7 +684,7 @@ void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, int cpu, u8 node_id)
|
|||
}
|
||||
}
|
||||
|
||||
void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *c, int cpu, u8 node_id)
|
||||
void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *c, int cpu)
|
||||
{
|
||||
/*
|
||||
* We may have multiple LLCs if L3 caches exist, so check if we
|
||||
|
|
|
@ -64,7 +64,6 @@ static void hygon_get_topology_early(struct cpuinfo_x86 *c)
|
|||
*/
|
||||
static void hygon_get_topology(struct cpuinfo_x86 *c)
|
||||
{
|
||||
u8 node_id;
|
||||
int cpu = smp_processor_id();
|
||||
|
||||
/* get information required for multi-node processors */
|
||||
|
@ -74,7 +73,7 @@ static void hygon_get_topology(struct cpuinfo_x86 *c)
|
|||
|
||||
cpuid(0x8000001e, &eax, &ebx, &ecx, &edx);
|
||||
|
||||
node_id = ecx & 0xff;
|
||||
c->cpu_die_id = ecx & 0xff;
|
||||
|
||||
c->cpu_core_id = ebx & 0xff;
|
||||
|
||||
|
@ -92,14 +91,14 @@ static void hygon_get_topology(struct cpuinfo_x86 *c)
|
|||
/* Socket ID is ApicId[6] for these processors. */
|
||||
c->phys_proc_id = c->apicid >> APICID_SOCKET_ID_BIT;
|
||||
|
||||
cacheinfo_hygon_init_llc_id(c, cpu, node_id);
|
||||
cacheinfo_hygon_init_llc_id(c, cpu);
|
||||
} else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) {
|
||||
u64 value;
|
||||
|
||||
rdmsrl(MSR_FAM10H_NODE_ID, value);
|
||||
node_id = value & 7;
|
||||
c->cpu_die_id = value & 7;
|
||||
|
||||
per_cpu(cpu_llc_id, cpu) = node_id;
|
||||
per_cpu(cpu_llc_id, cpu) = c->cpu_die_id;
|
||||
} else
|
||||
return;
|
||||
|
||||
|
@ -122,7 +121,7 @@ static void hygon_detect_cmp(struct cpuinfo_x86 *c)
|
|||
/* Convert the initial APIC ID into the socket ID */
|
||||
c->phys_proc_id = c->initial_apicid >> bits;
|
||||
/* use socket ID also for last level cache */
|
||||
per_cpu(cpu_llc_id, cpu) = c->phys_proc_id;
|
||||
per_cpu(cpu_llc_id, cpu) = c->cpu_die_id = c->phys_proc_id;
|
||||
}
|
||||
|
||||
static void srat_detect_node(struct cpuinfo_x86 *c)
|
||||
|
|
|
@ -1019,6 +1019,11 @@ int kprobe_fault_handler(struct pt_regs *regs, int trapnr)
|
|||
* So clear it by resetting the current kprobe:
|
||||
*/
|
||||
regs->flags &= ~X86_EFLAGS_TF;
|
||||
/*
|
||||
* Since the single step (trap) has been cancelled,
|
||||
* we need to restore BTF here.
|
||||
*/
|
||||
restore_btf();
|
||||
|
||||
/*
|
||||
* If the TF flag was set before the kprobe hit,
|
||||
|
|
|
@ -154,6 +154,20 @@ static inline int guest_cpuid_stepping(struct kvm_vcpu *vcpu)
|
|||
return x86_stepping(best->eax);
|
||||
}
|
||||
|
||||
static inline bool guest_has_spec_ctrl_msr(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
return (guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) ||
|
||||
guest_cpuid_has(vcpu, X86_FEATURE_AMD_STIBP) ||
|
||||
guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) ||
|
||||
guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD));
|
||||
}
|
||||
|
||||
static inline bool guest_has_pred_cmd_msr(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
return (guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) ||
|
||||
guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBPB));
|
||||
}
|
||||
|
||||
static inline bool supports_cpuid_fault(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
return vcpu->arch.msr_platform_info & MSR_PLATFORM_INFO_CPUID_FAULT;
|
||||
|
|
|
@ -4233,8 +4233,7 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
|
|||
break;
|
||||
case MSR_IA32_SPEC_CTRL:
|
||||
if (!msr_info->host_initiated &&
|
||||
!guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
|
||||
!guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
|
||||
!guest_has_spec_ctrl_msr(vcpu))
|
||||
return 1;
|
||||
|
||||
msr_info->data = svm->spec_ctrl;
|
||||
|
@ -4318,16 +4317,13 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
|
|||
break;
|
||||
case MSR_IA32_SPEC_CTRL:
|
||||
if (!msr->host_initiated &&
|
||||
!guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
|
||||
!guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
|
||||
!guest_has_spec_ctrl_msr(vcpu))
|
||||
return 1;
|
||||
|
||||
/* The STIBP bit doesn't fault even if it's not advertised */
|
||||
if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
|
||||
if (data & ~kvm_spec_ctrl_valid_bits(vcpu))
|
||||
return 1;
|
||||
|
||||
svm->spec_ctrl = data;
|
||||
|
||||
if (!data)
|
||||
break;
|
||||
|
||||
|
@ -4346,18 +4342,17 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
|
|||
break;
|
||||
case MSR_IA32_PRED_CMD:
|
||||
if (!msr->host_initiated &&
|
||||
!guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBPB))
|
||||
!guest_has_pred_cmd_msr(vcpu))
|
||||
return 1;
|
||||
|
||||
if (data & ~PRED_CMD_IBPB)
|
||||
return 1;
|
||||
|
||||
if (!boot_cpu_has(X86_FEATURE_IBPB))
|
||||
return 1;
|
||||
if (!data)
|
||||
break;
|
||||
|
||||
wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
|
||||
if (is_guest_mode(vcpu))
|
||||
break;
|
||||
set_msr_interception(svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
|
||||
break;
|
||||
case MSR_AMD64_VIRT_SPEC_CTRL:
|
||||
|
|
|
@ -1788,7 +1788,7 @@ static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
|
|||
break;
|
||||
case MSR_IA32_SPEC_CTRL:
|
||||
if (!msr_info->host_initiated &&
|
||||
!guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
|
||||
!guest_has_spec_ctrl_msr(vcpu))
|
||||
return 1;
|
||||
|
||||
msr_info->data = to_vmx(vcpu)->spec_ctrl;
|
||||
|
@ -1971,15 +1971,13 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
|
|||
break;
|
||||
case MSR_IA32_SPEC_CTRL:
|
||||
if (!msr_info->host_initiated &&
|
||||
!guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
|
||||
!guest_has_spec_ctrl_msr(vcpu))
|
||||
return 1;
|
||||
|
||||
/* The STIBP bit doesn't fault even if it's not advertised */
|
||||
if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
|
||||
if (data & ~kvm_spec_ctrl_valid_bits(vcpu))
|
||||
return 1;
|
||||
|
||||
vmx->spec_ctrl = data;
|
||||
|
||||
if (!data)
|
||||
break;
|
||||
|
||||
|
@ -2001,12 +1999,13 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
|
|||
break;
|
||||
case MSR_IA32_PRED_CMD:
|
||||
if (!msr_info->host_initiated &&
|
||||
!guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
|
||||
!guest_has_pred_cmd_msr(vcpu))
|
||||
return 1;
|
||||
|
||||
if (data & ~PRED_CMD_IBPB)
|
||||
return 1;
|
||||
|
||||
if (!boot_cpu_has(X86_FEATURE_IBPB))
|
||||
return 1;
|
||||
if (!data)
|
||||
break;
|
||||
|
||||
|
|
|
@ -10369,6 +10369,28 @@ bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
|
|||
}
|
||||
EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
|
||||
|
||||
u64 kvm_spec_ctrl_valid_bits(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
uint64_t bits = SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD;
|
||||
|
||||
/* The STIBP bit doesn't fault even if it's not advertised */
|
||||
if (!guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&
|
||||
!guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS))
|
||||
bits &= ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP);
|
||||
if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL) &&
|
||||
!boot_cpu_has(X86_FEATURE_AMD_IBRS))
|
||||
bits &= ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP);
|
||||
|
||||
if (!guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL_SSBD) &&
|
||||
!guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
|
||||
bits &= ~SPEC_CTRL_SSBD;
|
||||
if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) &&
|
||||
!boot_cpu_has(X86_FEATURE_AMD_SSBD))
|
||||
bits &= ~SPEC_CTRL_SSBD;
|
||||
|
||||
return bits;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(kvm_spec_ctrl_valid_bits);
|
||||
|
||||
EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
|
||||
EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
|
||||
|
|
|
@ -368,5 +368,6 @@ static inline bool kvm_pat_valid(u64 data)
|
|||
|
||||
void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu);
|
||||
void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu);
|
||||
u64 kvm_spec_ctrl_valid_bits(struct kvm_vcpu *vcpu);
|
||||
|
||||
#endif
|
||||
|
|
|
@ -62,6 +62,7 @@ static int ident_p4d_init(struct x86_mapping_info *info, p4d_t *p4d_page,
|
|||
unsigned long addr, unsigned long end)
|
||||
{
|
||||
unsigned long next;
|
||||
int result;
|
||||
|
||||
for (; addr < end; addr = next) {
|
||||
p4d_t *p4d = p4d_page + p4d_index(addr);
|
||||
|
@ -73,13 +74,20 @@ static int ident_p4d_init(struct x86_mapping_info *info, p4d_t *p4d_page,
|
|||
|
||||
if (p4d_present(*p4d)) {
|
||||
pud = pud_offset(p4d, 0);
|
||||
ident_pud_init(info, pud, addr, next);
|
||||
result = ident_pud_init(info, pud, addr, next);
|
||||
if (result)
|
||||
return result;
|
||||
|
||||
continue;
|
||||
}
|
||||
pud = (pud_t *)info->alloc_pgt_page(info->context);
|
||||
if (!pud)
|
||||
return -ENOMEM;
|
||||
ident_pud_init(info, pud, addr, next);
|
||||
|
||||
result = ident_pud_init(info, pud, addr, next);
|
||||
if (result)
|
||||
return result;
|
||||
|
||||
set_p4d(p4d, __p4d(__pa(pud) | info->kernpg_flag));
|
||||
}
|
||||
|
||||
|
|
|
@ -1205,6 +1205,23 @@ static void blk_mq_update_dispatch_busy(struct blk_mq_hw_ctx *hctx, bool busy)
|
|||
|
||||
#define BLK_MQ_RESOURCE_DELAY 3 /* ms units */
|
||||
|
||||
static void blk_mq_handle_dev_resource(struct request *rq,
|
||||
struct list_head *list)
|
||||
{
|
||||
struct request *next =
|
||||
list_first_entry_or_null(list, struct request, queuelist);
|
||||
|
||||
/*
|
||||
* If an I/O scheduler has been configured and we got a driver tag for
|
||||
* the next request already, free it.
|
||||
*/
|
||||
if (next)
|
||||
blk_mq_put_driver_tag(next);
|
||||
|
||||
list_add(&rq->queuelist, list);
|
||||
__blk_mq_requeue_request(rq);
|
||||
}
|
||||
|
||||
/*
|
||||
* Returns true if we did some work AND can potentially do more.
|
||||
*/
|
||||
|
@ -1216,6 +1233,7 @@ bool blk_mq_dispatch_rq_list(struct request_queue *q, struct list_head *list,
|
|||
bool no_tag = false;
|
||||
int errors, queued;
|
||||
blk_status_t ret = BLK_STS_OK;
|
||||
bool no_budget_avail = false;
|
||||
|
||||
if (list_empty(list))
|
||||
return false;
|
||||
|
@ -1234,6 +1252,7 @@ bool blk_mq_dispatch_rq_list(struct request_queue *q, struct list_head *list,
|
|||
hctx = rq->mq_hctx;
|
||||
if (!got_budget && !blk_mq_get_dispatch_budget(hctx)) {
|
||||
blk_mq_put_driver_tag(rq);
|
||||
no_budget_avail = true;
|
||||
break;
|
||||
}
|
||||
|
||||
|
@ -1274,17 +1293,7 @@ bool blk_mq_dispatch_rq_list(struct request_queue *q, struct list_head *list,
|
|||
|
||||
ret = q->mq_ops->queue_rq(hctx, &bd);
|
||||
if (ret == BLK_STS_RESOURCE || ret == BLK_STS_DEV_RESOURCE) {
|
||||
/*
|
||||
* If an I/O scheduler has been configured and we got a
|
||||
* driver tag for the next request already, free it
|
||||
* again.
|
||||
*/
|
||||
if (!list_empty(list)) {
|
||||
nxt = list_first_entry(list, struct request, queuelist);
|
||||
blk_mq_put_driver_tag(nxt);
|
||||
}
|
||||
list_add(&rq->queuelist, list);
|
||||
__blk_mq_requeue_request(rq);
|
||||
blk_mq_handle_dev_resource(rq, list);
|
||||
break;
|
||||
}
|
||||
|
||||
|
@ -1349,13 +1358,15 @@ bool blk_mq_dispatch_rq_list(struct request_queue *q, struct list_head *list,
|
|||
*
|
||||
* If driver returns BLK_STS_RESOURCE and SCHED_RESTART
|
||||
* bit is set, run queue after a delay to avoid IO stalls
|
||||
* that could otherwise occur if the queue is idle.
|
||||
* that could otherwise occur if the queue is idle. We'll do
|
||||
* similar if we couldn't get budget and SCHED_RESTART is set.
|
||||
*/
|
||||
needs_restart = blk_mq_sched_needs_restart(hctx);
|
||||
if (!needs_restart ||
|
||||
(no_tag && list_empty_careful(&hctx->dispatch_wait.entry)))
|
||||
blk_mq_run_hw_queue(hctx, true);
|
||||
else if (needs_restart && (ret == BLK_STS_RESOURCE))
|
||||
else if (needs_restart && (ret == BLK_STS_RESOURCE ||
|
||||
no_budget_avail))
|
||||
blk_mq_delay_run_hw_queue(hctx, BLK_MQ_RESOURCE_DELAY);
|
||||
|
||||
blk_mq_update_dispatch_busy(hctx, true);
|
||||
|
|
|
@ -67,6 +67,10 @@ int blk_pre_runtime_suspend(struct request_queue *q)
|
|||
|
||||
WARN_ON_ONCE(q->rpm_status != RPM_ACTIVE);
|
||||
|
||||
spin_lock_irq(&q->queue_lock);
|
||||
q->rpm_status = RPM_SUSPENDING;
|
||||
spin_unlock_irq(&q->queue_lock);
|
||||
|
||||
/*
|
||||
* Increase the pm_only counter before checking whether any
|
||||
* non-PM blk_queue_enter() calls are in progress to avoid that any
|
||||
|
@ -89,15 +93,14 @@ int blk_pre_runtime_suspend(struct request_queue *q)
|
|||
/* Switch q_usage_counter back to per-cpu mode. */
|
||||
blk_mq_unfreeze_queue(q);
|
||||
|
||||
spin_lock_irq(&q->queue_lock);
|
||||
if (ret < 0)
|
||||
if (ret < 0) {
|
||||
spin_lock_irq(&q->queue_lock);
|
||||
q->rpm_status = RPM_ACTIVE;
|
||||
pm_runtime_mark_last_busy(q->dev);
|
||||
else
|
||||
q->rpm_status = RPM_SUSPENDING;
|
||||
spin_unlock_irq(&q->queue_lock);
|
||||
spin_unlock_irq(&q->queue_lock);
|
||||
|
||||
if (ret)
|
||||
blk_clear_pm_only(q);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
|
@ -202,32 +202,14 @@ int blkdev_report_zones(struct block_device *bdev, sector_t sector,
|
|||
}
|
||||
EXPORT_SYMBOL_GPL(blkdev_report_zones);
|
||||
|
||||
/*
|
||||
* Special case of zone reset operation to reset all zones in one command,
|
||||
* useful for applications like mkfs.
|
||||
*/
|
||||
static int __blkdev_reset_all_zones(struct block_device *bdev, gfp_t gfp_mask)
|
||||
{
|
||||
struct bio *bio = bio_alloc(gfp_mask, 0);
|
||||
int ret;
|
||||
|
||||
/* across the zones operations, don't need any sectors */
|
||||
bio_set_dev(bio, bdev);
|
||||
bio_set_op_attrs(bio, REQ_OP_ZONE_RESET_ALL, 0);
|
||||
|
||||
ret = submit_bio_wait(bio);
|
||||
bio_put(bio);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static inline bool blkdev_allow_reset_all_zones(struct block_device *bdev,
|
||||
sector_t sector,
|
||||
sector_t nr_sectors)
|
||||
{
|
||||
if (!blk_queue_zone_resetall(bdev_get_queue(bdev)))
|
||||
return false;
|
||||
|
||||
if (nr_sectors != part_nr_sects_read(bdev->bd_part))
|
||||
if (sector || nr_sectors != part_nr_sects_read(bdev->bd_part))
|
||||
return false;
|
||||
/*
|
||||
* REQ_OP_ZONE_RESET_ALL can be executed only if the block device is
|
||||
|
@ -271,9 +253,6 @@ int blkdev_reset_zones(struct block_device *bdev,
|
|||
/* Out of range */
|
||||
return -EINVAL;
|
||||
|
||||
if (blkdev_allow_reset_all_zones(bdev, nr_sectors))
|
||||
return __blkdev_reset_all_zones(bdev, gfp_mask);
|
||||
|
||||
/* Check alignment (handle eventual smaller last zone) */
|
||||
zone_sectors = blk_queue_zone_sectors(q);
|
||||
if (sector & (zone_sectors - 1))
|
||||
|
@ -285,17 +264,24 @@ int blkdev_reset_zones(struct block_device *bdev,
|
|||
|
||||
blk_start_plug(&plug);
|
||||
while (sector < end_sector) {
|
||||
|
||||
bio = blk_next_bio(bio, 0, gfp_mask);
|
||||
bio->bi_iter.bi_sector = sector;
|
||||
bio_set_dev(bio, bdev);
|
||||
bio_set_op_attrs(bio, REQ_OP_ZONE_RESET, 0);
|
||||
|
||||
/*
|
||||
* Special case for the zone reset operation that reset all
|
||||
* zones, this is useful for applications like mkfs.
|
||||
*/
|
||||
if (blkdev_allow_reset_all_zones(bdev, sector, nr_sectors)) {
|
||||
bio->bi_opf = REQ_OP_ZONE_RESET_ALL;
|
||||
break;
|
||||
}
|
||||
|
||||
bio->bi_opf = REQ_OP_ZONE_RESET;
|
||||
bio->bi_iter.bi_sector = sector;
|
||||
sector += zone_sectors;
|
||||
|
||||
/* This may take a while, so be nice to others */
|
||||
cond_resched();
|
||||
|
||||
}
|
||||
|
||||
ret = submit_bio_wait(bio);
|
||||
|
|
|
@ -147,7 +147,7 @@ static int alg_bind(struct socket *sock, struct sockaddr *uaddr, int addr_len)
|
|||
const u32 allowed = CRYPTO_ALG_KERN_DRIVER_ONLY;
|
||||
struct sock *sk = sock->sk;
|
||||
struct alg_sock *ask = alg_sk(sk);
|
||||
struct sockaddr_alg *sa = (void *)uaddr;
|
||||
struct sockaddr_alg_new *sa = (void *)uaddr;
|
||||
const struct af_alg_type *type;
|
||||
void *private;
|
||||
int err;
|
||||
|
@ -155,7 +155,11 @@ static int alg_bind(struct socket *sock, struct sockaddr *uaddr, int addr_len)
|
|||
if (sock->state == SS_CONNECTED)
|
||||
return -EINVAL;
|
||||
|
||||
if (addr_len < sizeof(*sa))
|
||||
BUILD_BUG_ON(offsetof(struct sockaddr_alg_new, salg_name) !=
|
||||
offsetof(struct sockaddr_alg, salg_name));
|
||||
BUILD_BUG_ON(offsetof(struct sockaddr_alg, salg_name) != sizeof(*sa));
|
||||
|
||||
if (addr_len < sizeof(*sa) + 1)
|
||||
return -EINVAL;
|
||||
|
||||
/* If caller uses non-allowed flag, return error. */
|
||||
|
@ -163,7 +167,7 @@ static int alg_bind(struct socket *sock, struct sockaddr *uaddr, int addr_len)
|
|||
return -EINVAL;
|
||||
|
||||
sa->salg_type[sizeof(sa->salg_type) - 1] = 0;
|
||||
sa->salg_name[sizeof(sa->salg_name) + addr_len - sizeof(*sa) - 1] = 0;
|
||||
sa->salg_name[addr_len - sizeof(*sa) - 1] = 0;
|
||||
|
||||
type = alg_get_type(sa->salg_type);
|
||||
if (IS_ERR(type) && PTR_ERR(type) == -ENOENT) {
|
||||
|
|
|
@ -53,12 +53,13 @@ static int ecdh_set_secret(struct crypto_kpp *tfm, const void *buf,
|
|||
return ecc_gen_privkey(ctx->curve_id, ctx->ndigits,
|
||||
ctx->private_key);
|
||||
|
||||
if (ecc_is_key_valid(ctx->curve_id, ctx->ndigits,
|
||||
(const u64 *)params.key, params.key_size) < 0)
|
||||
return -EINVAL;
|
||||
|
||||
memcpy(ctx->private_key, params.key, params.key_size);
|
||||
|
||||
if (ecc_is_key_valid(ctx->curve_id, ctx->ndigits,
|
||||
ctx->private_key, params.key_size) < 0) {
|
||||
memzero_explicit(ctx->private_key, params.key_size);
|
||||
return -EINVAL;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue