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ARM: dts: r8a7743: Add CAN[01] SoC support 

Add the definitions for can0 and can1 to the SoC .dtsi.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Fabrizio Castro 2017-11-07 15:10:47 +00:00 committed by Simon Horman
parent d6033e7c65
commit 6ee6959fb8
1 changed files with 36 additions and 0 deletions
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36
arch/arm/boot/dts/r8a7743.dtsi
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@ -1067,6 +1067,34 @@
};
};
can0: can@e6e80000 {
compatible = "renesas,can-r8a7743",
"renesas,rcar-gen2-can";
reg = <0 0xe6e80000 0 0x1000>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 916>,
<&cpg CPG_CORE R8A7743_CLK_RCAN>,
<&can_clk>;
clock-names = "clkp1", "clkp2", "can_clk";
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 916>;
status = "disabled";
};
can1: can@e6e88000 {
compatible = "renesas,can-r8a7743",
"renesas,rcar-gen2-can";
reg = <0 0xe6e88000 0 0x1000>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 915>,
<&cpg CPG_CORE R8A7743_CLK_RCAN>,
<&can_clk>;
clock-names = "clkp1", "clkp2", "can_clk";
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 915>;
status = "disabled";
};
pci0: pci@ee090000 {
compatible = "renesas,pci-r8a7743",
"renesas,pci-rcar-gen2";
@ -1153,6 +1181,14 @@
clock-frequency = <48000000>;
};
/* External CAN clock */
can_clk: can {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board. */
clock-frequency = <0>;
};
/* External SCIF clock */
scif_clk: scif {
compatible = "fixed-clock";