MLK-23273-1 clk: imx: Add imx8dxl clk driver
Add files for imx8dxl clk driver which is based on imx8qxp clock driver. Signed-off-by: Teo Hall <teo.hall@nxp.com> Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
This commit is contained in:
Teo Hall
Anson Huang
parent
468868d88d
commit
6d813b5717
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@ -30,7 +30,8 @@ obj-$(CONFIG_CLK_IMX8MN) += clk-imx8mn.o
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obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp.o clk-audiomix.o clk-hdmimix.o clk-gate-shared.o
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obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o
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obj-$(CONFIG_CLK_IMX8QXP) += clk-imx8qxp.o clk-imx8qxp-lpcg.o clk-imx8qxp-acm.o \
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clk-imx8qxp-rsrc.o clk-imx8qm-rsrc.o clk-imx8qm-acm.o
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clk-imx8qxp-rsrc.o clk-imx8qm-rsrc.o clk-imx8qm-acm.o \
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clk-imx8dxl-rsrc.o clk-imx8dxl-acm.o
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obj-$(CONFIG_SOC_IMX1) += clk-imx1.o
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obj-$(CONFIG_SOC_IMX21) += clk-imx21.o
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obj-$(CONFIG_SOC_IMX25) += clk-imx25.o
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@ -0,0 +1,185 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019~2020 NXP
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*/
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/pm_domain.h>
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#include "clk.h"
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#include "clk-scu.h"
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#include <dt-bindings/clock/imx8-clock.h>
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static const char *aud_clk_sels[] = {
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"aud_rec_clk0_lpcg_clk",
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"aud_rec_clk1_lpcg_clk",
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"ext_aud_mclk0",
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"ext_aud_mclk1",
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"esai0_rx_clk",
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"esai0_rx_hf_clk",
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"esai0_tx_clk",
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"esai0_tx_hf_clk",
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"spdif0_rx",
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"sai0_rx_bclk",
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"sai0_tx_bclk",
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"sai1_rx_bclk",
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"sai1_tx_bclk",
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"sai2_rx_bclk",
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"sai3_rx_bclk",
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};
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static const char *mclk_out_sels[] = {
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"aud_rec_clk0_lpcg_clk",
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"aud_rec_clk1_lpcg_clk",
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"dummy",
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"dummy",
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"spdif0_rx",
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"dummy",
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"dummy",
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"sai4_rx_bclk",
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};
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static const char *sai_mclk_sels[] = {
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"aud_pll_div_clk0_lpcg_clk",
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"aud_pll_div_clk1_lpcg_clk",
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"acm_aud_clk0_sel",
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"acm_aud_clk1_sel",
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};
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static const char *esai_mclk_sels[] = {
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"aud_pll_div_clk0_lpcg_clk",
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"aud_pll_div_clk1_lpcg_clk",
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"acm_aud_clk0_sel",
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"acm_aud_clk1_sel",
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};
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static const char *spdif_mclk_sels[] = {
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"aud_pll_div_clk0_lpcg_clk",
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"aud_pll_div_clk1_lpcg_clk",
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"acm_aud_clk0_sel",
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"acm_aud_clk1_sel",
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};
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static const char *mqs_mclk_sels[] = {
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"aud_pll_div_clk0_lpcg_clk",
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"aud_pll_div_clk1_lpcg_clk",
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"acm_aud_clk0_sel",
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"acm_aud_clk1_sel",
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};
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static int imx8qxp_acm_clk_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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struct clk_onecell_data *clk_data;
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struct resource *res;
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struct clk **clks;
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void __iomem *base;
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int num_domains;
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int i;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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base = devm_ioremap(dev, res->start, resource_size(res));
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if (!base)
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return -ENOMEM;
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clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
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if (!clk_data)
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return -ENOMEM;
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clk_data->clks = kcalloc(IMX_ADMA_ACM_CLK_END,
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sizeof(*clk_data->clks), GFP_KERNEL);
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if (!clk_data->clks)
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return -ENOMEM;
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clk_data->clk_num = IMX_ADMA_ACM_CLK_END;
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clks = clk_data->clks;
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num_domains = of_count_phandle_with_args(dev->of_node, "power-domains",
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"#power-domain-cells");
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for (i = 0; i < num_domains; i++) {
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struct device *pd_dev;
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struct device_link *link;
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pd_dev = dev_pm_domain_attach_by_id(&pdev->dev, i);
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if (IS_ERR(pd_dev))
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return PTR_ERR(pd_dev);
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link = device_link_add(&pdev->dev, pd_dev,
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DL_FLAG_STATELESS |
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DL_FLAG_PM_RUNTIME |
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DL_FLAG_RPM_ACTIVE);
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if (IS_ERR(link))
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return PTR_ERR(link);
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}
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clks[IMX_ADMA_EXT_AUD_MCLK0] = imx_clk_fixed("ext_aud_mclk0", 0);
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clks[IMX_ADMA_EXT_AUD_MCLK1] = imx_clk_fixed("ext_aud_mclk1", 0);
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clks[IMX_ADMA_ESAI0_RX_CLK] = imx_clk_fixed("esai0_rx_clk", 0);
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clks[IMX_ADMA_ESAI0_RX_HF_CLK] = imx_clk_fixed("esai0_rx_hf_clk", 0);
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clks[IMX_ADMA_ESAI0_TX_CLK] = imx_clk_fixed("esai0_tx_clk", 0);
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clks[IMX_ADMA_ESAI0_TX_HF_CLK] = imx_clk_fixed("esai0_tx_hf_clk", 0);
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clks[IMX_ADMA_SPDIF0_RX] = imx_clk_fixed("spdif0_rx", 0);
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clks[IMX_ADMA_SAI0_RX_BCLK] = imx_clk_fixed("sai0_rx_bclk", 0);
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clks[IMX_ADMA_SAI0_TX_BCLK] = imx_clk_fixed("sai0_tx_bclk", 0);
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clks[IMX_ADMA_SAI1_RX_BCLK] = imx_clk_fixed("sai1_rx_bclk", 0);
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clks[IMX_ADMA_SAI1_TX_BCLK] = imx_clk_fixed("sai1_tx_bclk", 0);
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clks[IMX_ADMA_SAI2_RX_BCLK] = imx_clk_fixed("sai2_rx_bclk", 0);
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clks[IMX_ADMA_SAI3_RX_BCLK] = imx_clk_fixed("sai3_rx_bclk", 0);
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clks[IMX_ADMA_SAI4_RX_BCLK] = imx_clk_fixed("sai4_rx_bclk", 0);
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clks[IMX_ADMA_ACM_AUD_CLK0_SEL] = imx_clk_mux("acm_aud_clk0_sel", base+0x000000, 0, 5, aud_clk_sels, ARRAY_SIZE(aud_clk_sels));
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clks[IMX_ADMA_ACM_AUD_CLK1_CLK] = imx_clk_mux("acm_aud_clk1_sel", base+0x010000, 0, 5, aud_clk_sels, ARRAY_SIZE(aud_clk_sels));
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clks[IMX_ADMA_ACM_MCLKOUT0_SEL] = imx_clk_mux("acm_mclkout0_sel", base+0x020000, 0, 3, mclk_out_sels, ARRAY_SIZE(mclk_out_sels));
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clks[IMX_ADMA_ACM_MCLKOUT1_SEL] = imx_clk_mux("acm_mclkout1_sel", base+0x030000, 0, 3, mclk_out_sels, ARRAY_SIZE(mclk_out_sels));
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clks[IMX_ADMA_ACM_ESAI0_MCLK_SEL] = imx_clk_mux("acm_esai0_mclk_sel", base+0x060000, 0, 2, esai_mclk_sels, ARRAY_SIZE(esai_mclk_sels));
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clks[IMX_ADMA_ACM_SAI0_MCLK_SEL] = imx_clk_mux("acm_sai0_mclk_sel", base+0x0E0000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels));
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clks[IMX_ADMA_ACM_SAI1_MCLK_SEL] = imx_clk_mux("acm_sai1_mclk_sel", base+0x0F0000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels));
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clks[IMX_ADMA_ACM_SAI2_MCLK_SEL] = imx_clk_mux("acm_sai2_mclk_sel", base+0x100000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels));
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clks[IMX_ADMA_ACM_SAI3_MCLK_SEL] = imx_clk_mux("acm_sai3_mclk_sel", base+0x110000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels));
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clks[IMX_ADMA_ACM_SAI4_MCLK_SEL] = imx_clk_mux("acm_sai4_mclk_sel", base+0x140000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels));
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clks[IMX_ADMA_ACM_SAI5_MCLK_SEL] = imx_clk_mux("acm_sai5_mclk_sel", base+0x150000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels));
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clks[IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL] = imx_clk_mux("acm_spdif0_mclk_sel", base+0x1A0000, 0, 2, spdif_mclk_sels, ARRAY_SIZE(spdif_mclk_sels));
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clks[IMX_ADMA_ACM_MQS_TX_CLK_SEL] = imx_clk_mux("acm_mqs_mclk_sel", base+0x1C0000, 0, 2, mqs_mclk_sels, ARRAY_SIZE(mqs_mclk_sels));
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for (i = 0; i < clk_data->clk_num; i++) {
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if (IS_ERR(clks[i]))
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pr_warn("i.MX clk %u: register failed with %ld\n",
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i, PTR_ERR(clks[i]));
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}
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return of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
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}
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static const struct of_device_id imx8qxp_acm_match[] = {
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{ .compatible = "nxp,imx8qxp-acm", },
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{ /* sentinel */ }
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};
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static struct platform_driver imx8qxp_acm_clk_driver = {
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.driver = {
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.name = "imx8qxp-acm",
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.of_match_table = imx8qxp_acm_match,
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.suppress_bind_attrs = true,
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},
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.probe = imx8qxp_acm_clk_probe,
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};
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static int __init imx8qxp_acm_init(void)
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{
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return platform_driver_register(&imx8qxp_acm_clk_driver);
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}
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fs_initcall(imx8qxp_acm_init);
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@ -0,0 +1,65 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019~2020 NXP
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*/
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#include <dt-bindings/firmware/imx/rsrc.h>
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#include "clk-scu.h"
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/* Keep sorted in the ascending order */
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static u32 imx8dxl_clk_scu_rsrc_table[] = {
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IMX_SC_R_SPI_0,
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IMX_SC_R_SPI_1,
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IMX_SC_R_SPI_2,
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IMX_SC_R_SPI_3,
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IMX_SC_R_UART_0,
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IMX_SC_R_UART_1,
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IMX_SC_R_UART_2,
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IMX_SC_R_UART_3,
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IMX_SC_R_I2C_0,
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IMX_SC_R_I2C_1,
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IMX_SC_R_I2C_2,
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IMX_SC_R_I2C_3,
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IMX_SC_R_ADC_0,
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IMX_SC_R_FTM_0,
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IMX_SC_R_FTM_1,
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IMX_SC_R_CAN_0,
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IMX_SC_R_LCD_0,
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IMX_SC_R_LCD_0_PWM_0,
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IMX_SC_R_PWM_0,
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IMX_SC_R_PWM_1,
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IMX_SC_R_PWM_2,
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IMX_SC_R_PWM_3,
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IMX_SC_R_PWM_4,
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IMX_SC_R_PWM_5,
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IMX_SC_R_PWM_6,
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IMX_SC_R_PWM_7,
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IMX_SC_R_GPT_0,
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IMX_SC_R_GPT_1,
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IMX_SC_R_GPT_2,
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IMX_SC_R_GPT_3,
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IMX_SC_R_GPT_4,
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IMX_SC_R_FSPI_0,
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IMX_SC_R_FSPI_1,
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IMX_SC_R_SDHC_0,
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IMX_SC_R_SDHC_1,
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IMX_SC_R_SDHC_2,
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IMX_SC_R_ENET_0,
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IMX_SC_R_ENET_1,
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IMX_SC_R_MLB_0,
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IMX_SC_R_USB_1,
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IMX_SC_R_NAND,
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IMX_SC_R_M4_0_I2C,
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IMX_SC_R_ELCDIF_PLL,
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IMX_SC_R_AUDIO_PLL_0,
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IMX_SC_R_AUDIO_PLL_1,
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IMX_SC_R_AUDIO_CLK_0,
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IMX_SC_R_AUDIO_CLK_1,
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IMX_SC_R_A35
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};
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const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8dxl = {
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.rsrc = imx8dxl_clk_scu_rsrc_table,
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.num = ARRAY_SIZE(imx8dxl_clk_scu_rsrc_table),
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};
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@ -71,6 +71,7 @@ static const struct of_device_id imx8qxp_match[] = {
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{ .compatible = "fsl,scu-clk", },
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{ .compatible = "fsl,imx8qxp-clk", &imx_clk_scu_rsrc_imx8qxp, },
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{ .compatible = "fsl,imx8qm-clk", &imx_clk_scu_rsrc_imx8qm, },
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{ .compatible = "fsl,imx8dxl-clk", &imx_clk_scu_rsrc_imx8dxl, },
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{ /* sentinel */ }
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};
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@ -24,6 +24,7 @@ extern struct list_head imx_scu_clks[];
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extern const struct dev_pm_ops imx_clk_lpcg_scu_pm_ops;
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extern const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qxp;
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extern const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qm;
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extern const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8dxl;
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int imx_clk_scu_init(struct device_node *np, const void *data);
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struct clk_hw *imx_scu_of_clk_src_get(struct of_phandle_args *clkspec,
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