MLK-24012-04 arm64: dts: add imx8qxp pcie ep support
Add the iMX8QXP PCIe EP mode, and verified on MEK board. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
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@ -115,6 +115,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb imx8qxp-mek-dsp.dtb imx8qxp-mek-ov5640
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imx8qxp-mek-dpu-lcdif.dtb \
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imx8qxp-mek-dpu-lcdif-rpmsg.dtb \
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imx8qxp-mek-ov5640-rpmsg.dtb \
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imx8qxp-mek-pcie-ep.dtb \
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imx8dx-mek.dtb imx8dx-mek-dsp.dtb imx8dx-mek-rpmsg.dtb \
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imx8dx-mek-enet2-tja1100.dtb \
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imx8dx-mek-ov5640.dtb \
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@ -131,4 +131,34 @@ hsio_subsys: bus@5f000000 {
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local-addr = <0x80000000>;
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status = "disabled";
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};
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pcieb_ep: pcie_ep@0x5f010000 {
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compatible = "fsl,imx8qxp-pcie-ep";
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reg = <0x5f010000 0x00010000>,
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<0x5f080000 0xf0000>, /* lpcg, csr, msic, gpio */
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<0x70000000 0x10000000>;
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reg-names = "regs", "hsio", "addr_space";
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num-lanes = <1>;
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interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
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interrupt-names = "dma";
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clocks = <&pcieb_lpcg 0>,
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<&pcieb_lpcg 1>,
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<&pcieb_lpcg 2>,
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<&phyx1_lpcg 0>,
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<&phyx1_crr1_lpcg 0>,
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<&pcieb_crr3_lpcg 0>,
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<&misc_crr5_lpcg 0>;
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clock-names = "pcie", "pcie_bus", "pcie_inbound_axi",
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"pcie_phy", "phy_per", "pcie_per", "misc_per";
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power-domains = <&pd IMX_SC_R_PCIE_B>,
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<&pd IMX_SC_R_SERDES_1>,
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<&pd IMX_SC_R_HSIO_GPIO>;
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power-domain-names = "pcie", "pcie_phy", "hsio_gpio";
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fsl,max-link-speed = <3>;
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hsio-cfg = <PCIEAX2PCIEBX1>;
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local-addr = <0x80000000>;
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num-ib-windows = <6>;
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num-ob-windows = <6>;
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status = "disabled";
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};
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};
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@ -0,0 +1,19 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2020 NXP
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*/
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/dts-v1/;
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#include "imx8qxp-mek.dts"
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&pcieb{
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status = "disabled";
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};
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&pcieb_ep{
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pcieb>;
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ext_osc = <1>;
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status = "okay";
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};
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