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dt-bindings: pinctrl: Add SIUL2 definitions

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Add device tree bindings documentation and useful definitions for SIUL2 pin
controller, which is found on the S32V234 SoC.

Signed-off-by: Mihaela Martinas <Mihaela.Martinas@freescale.com>
Signed-off-by: Ghennadi Procopciuc <Ghennadi.Procopciuc@nxp.com>
Signed-off-by: Stefan-Gabriel Mirea <stefan-gabriel.mirea@nxp.com>
This commit is contained in:
Mihaela Martinas 2015-10-01 19:01:51 +03:00 committed by Dong Aisheng
parent 796ad640d7
commit 6ad9a554a1
2 changed files with 85 additions and 0 deletions
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Documentation/devicetree/bindings/pinctrl/fsl,s32v234-siul2.txt Normal file
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* Freescale SIUL2 iomux controller
See chapter 20 ("System Integration Unit Lite2 (SIUL2)") in the reference
manual[1].
Based on fsl,imx-pincontrol implementation.
Required properties:
- compatible: "fsl,s32v234-siul2"
- fsl,pins: two integers array, represents a group of pins mux and config
setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>
PIN_FUNC_ID - id of MSCR to be modified
CONFIG - configuration to be written in the MSCR/IMCR register
Even though IMCR register should be used as input register, it can be
set and addressed in the same way as MSCR, only instead of passing the
IMCR index, IMCR_IDX + 512 is passed[1].
[1] https://www.nxp.com/webapp/Download?colCode=S32V234RM

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include/dt-bindings/pinctrl/s32v234-pinctrl.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright 2015-2016 by Freescale Semiconductor
* Copyright 2016-2017 NXP
*/
#ifndef __DT_BINDINGS_S32V234_PINCTRL_H__
#define __DT_BINDINGS_S32V234_PINCTRL_H__
/*
* Use to set PAD control
*/
#define PAD_CTL_DCYLE_TRIM_OFS (22)
#define PAD_CTL_DCYLE_TRIM_NONE (0 << PAD_CTL_DCYLE_TRIM_OFS)
#define PAD_CTL_DCYLE_TRIM_LEFT (1 << PAD_CTL_DCYLE_TRIM_OFS)
#define PAD_CTL_DCYLE_TRIM_RIGHT (2 << PAD_CTL_DCYLE_TRIM_OFS)
#define PAD_CTL_OBE (1 << 21)
#define PAD_CTL_ODE (1 << 20)
#define PAD_CTL_IBE (1 << 19)
#define PAD_CTL_HYS (1 << 18)
#define PAD_CTL_INV (1 << 17)
#define PAD_CTL_PKE (1 << 16)
#define PAD_CTL_SRE_OFS (14)
#define PAD_CTL_SRE_LOW_50HZ (0 << PAD_CTL_SRE_OFS)
#define PAD_CTL_SRE_LOW_100MHZ (1 << PAD_CTL_SRE_OFS)
/* The manual reports the same value for SRE = 01 and SRE = 10 */
#define PAD_CTL_SRE_HIGH_100MHZ (2 << PAD_CTL_SRE_OFS)
#define PAD_CTL_SRE_HIGH_200MHZ (3 << PAD_CTL_SRE_OFS)
#define PAD_CTL_PUE (1 << 13)
#define PAD_CTL_PUS_OFS (11)
#define PAD_CTL_PUS_100K_DOWN (0 << PAD_CTL_PUS_OFS)
#define PAD_CTL_PUS_50K_UP (1 << PAD_CTL_PUS_OFS)
#define PAD_CTL_PUS_100K_UP (2 << PAD_CTL_PUS_OFS)
#define PAD_CTL_PUS_33K_UP (3 << PAD_CTL_PUS_OFS)
#define PAD_CTL_PUS_MASK (3 << PAD_CTL_PUS_OFS)
#define PAD_CTL_DSE_OFS (8)
#define PAD_CTL_DSE_OUT_DISABLE (0 << PAD_CTL_DSE_OFS)
#define PAD_CTL_DSE_240 (1 << PAD_CTL_DSE_OFS)
#define PAD_CTL_DSE_120 (2 << PAD_CTL_DSE_OFS)
#define PAD_CTL_DSE_80 (3 << PAD_CTL_DSE_OFS)
#define PAD_CTL_DSE_60 (4 << PAD_CTL_DSE_OFS)
#define PAD_CTL_DSE_48 (5 << PAD_CTL_DSE_OFS)
#define PAD_CTL_DSE_40 (6 << PAD_CTL_DSE_OFS)
#define PAD_CTL_DSE_34 (7 << PAD_CTL_DSE_OFS)
#define PAD_CTL_DSE_MASK (7 << PAD_CTL_DSE_OFS)
#define PAD_CTL_CRPOINT_TRIM (3 << 6)
#define PAD_CTL_SMC (1 << 5)
#define PAD_CTL_MUX_MODE_ALT0 (0)
#define PAD_CTL_MUX_MODE_ALT1 (1)
#define PAD_CTL_MUX_MODE_ALT2 (2)
#define PAD_CTL_MUX_MODE_ALT3 (3)
#define PAD_CTL_MUX_MODE_ALT4 (4)
#define PAD_CTL_MUX_MODE_ALT5 (5)
#define PAD_CTL_MUX_MODE_ALT6 (6)
#define PAD_CTL_MUX_MODE_ALT7 (7)
#define PAD_CTL_MUX_MODE_MASK (0xF)
#endif /* __DT_BINDINGS_S32V234_PINCTRL_H__ */