fsi: master-ast-cf: Add new FSI master using Aspeed ColdFire

The Aspeed AST2x00 can contain a ColdFire v1 coprocessor which
is currently unused on OpenPower systems.

This adds an alternative to the fsi-master-gpio driver that
uses that coprocessor instead of bit banging from the ARM
core itself. The end result is about 4 times faster.

The firmware for the coprocessor and its source code can be
found at https://github.com/ozbenh/cf-fsi and is system specific.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Benjamin Herrenschmidt 2018-06-12 09:55:04 +10:00
parent 2be5263c5d
commit 6a794a27da
5 changed files with 1755 additions and 0 deletions

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@ -27,6 +27,15 @@ config FSI_MASTER_HUB
allow chaining of FSI links to an arbitrary depth. This allows for
a high target device fanout.
config FSI_MASTER_AST_CF
tristate "FSI master based on Aspeed ColdFire coprocessor"
depends on GPIOLIB
depends on GPIO_ASPEED
---help---
This option enables a FSI master using the AST2400 and AST2500 GPIO
lines driven by the internal ColdFire coprocessor. This requires
the corresponding machine specific ColdFire firmware to be available.
config FSI_SCOM
tristate "SCOM FSI client device driver"
---help---

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@ -2,5 +2,6 @@
obj-$(CONFIG_FSI) += fsi-core.o
obj-$(CONFIG_FSI_MASTER_HUB) += fsi-master-hub.o
obj-$(CONFIG_FSI_MASTER_GPIO) += fsi-master-gpio.o
obj-$(CONFIG_FSI_MASTER_AST_CF) += fsi-master-ast-cf.o
obj-$(CONFIG_FSI_SCOM) += fsi-scom.o
obj-$(CONFIG_FSI_SBEFIFO) += fsi-sbefifo.o

157
drivers/fsi/cf-fsi-fw.h Normal file
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@ -0,0 +1,157 @@
// SPDX-License-Identifier: GPL-2.0+
#ifndef __CF_FSI_FW_H
#define __CF_FSI_FW_H
/*
* uCode file layout
*
* 0000...03ff : m68k exception vectors
* 0400...04ff : Header info & boot config block
* 0500....... : Code & stack
*/
/*
* Header info & boot config area
*
* The Header info is built into the ucode and provide version and
* platform information.
*
* the Boot config needs to be adjusted by the ARM prior to starting
* the ucode if the Command/Status area isn't at 0x320000 in CF space
* (ie. beginning of SRAM).
*/
#define HDR_OFFSET 0x400
/* Info: Signature & version */
#define HDR_SYS_SIG 0x00 /* 2 bytes system signature */
#define SYS_SIG_SHARED 0x5348
#define SYS_SIG_SPLIT 0x5350
#define HDR_FW_VERS 0x02 /* 2 bytes Major.Minor */
#define HDR_API_VERS 0x04 /* 2 bytes Major.Minor */
#define API_VERSION_MAJ 2 /* Current version */
#define API_VERSION_MIN 1
#define HDR_FW_OPTIONS 0x08 /* 4 bytes option flags */
#define FW_OPTION_TRACE_EN 0x00000001 /* FW tracing enabled */
#define FW_OPTION_CONT_CLOCK 0x00000002 /* Continuous clocking supported */
#define HDR_FW_SIZE 0x10 /* 4 bytes size for combo image */
/* Boot Config: Address of Command/Status area */
#define HDR_CMD_STAT_AREA 0x80 /* 4 bytes CF address */
#define HDR_FW_CONTROL 0x84 /* 4 bytes control flags */
#define FW_CONTROL_CONT_CLOCK 0x00000002 /* Continuous clocking enabled */
#define FW_CONTROL_DUMMY_RD 0x00000004 /* Extra dummy read (AST2400) */
#define FW_CONTROL_USE_STOP 0x00000008 /* Use STOP instructions */
#define HDR_CLOCK_GPIO_VADDR 0x90 /* 2 bytes offset from GPIO base */
#define HDR_CLOCK_GPIO_DADDR 0x92 /* 2 bytes offset from GPIO base */
#define HDR_DATA_GPIO_VADDR 0x94 /* 2 bytes offset from GPIO base */
#define HDR_DATA_GPIO_DADDR 0x96 /* 2 bytes offset from GPIO base */
#define HDR_TRANS_GPIO_VADDR 0x98 /* 2 bytes offset from GPIO base */
#define HDR_TRANS_GPIO_DADDR 0x9a /* 2 bytes offset from GPIO base */
#define HDR_CLOCK_GPIO_BIT 0x9c /* 1 byte bit number */
#define HDR_DATA_GPIO_BIT 0x9d /* 1 byte bit number */
#define HDR_TRANS_GPIO_BIT 0x9e /* 1 byte bit number */
/*
* Command/Status area layout: Main part
*/
/* Command/Status register:
*
* +---------------------------+
* | STAT | RLEN | CLEN | CMD |
* | 8 | 8 | 8 | 8 |
* +---------------------------+
* | | | |
* status | | |
* Response len | |
* (in bits) | |
* | |
* Command len |
* (in bits) |
* |
* Command code
*
* Due to the big endian layout, that means that a byte read will
* return the status byte
*/
#define CMD_STAT_REG 0x00
#define CMD_REG_CMD_MASK 0x000000ff
#define CMD_REG_CMD_SHIFT 0
#define CMD_NONE 0x00
#define CMD_COMMAND 0x01
#define CMD_BREAK 0x02
#define CMD_IDLE_CLOCKS 0x03 /* clen = #clocks */
#define CMD_INVALID 0xff
#define CMD_REG_CLEN_MASK 0x0000ff00
#define CMD_REG_CLEN_SHIFT 8
#define CMD_REG_RLEN_MASK 0x00ff0000
#define CMD_REG_RLEN_SHIFT 16
#define CMD_REG_STAT_MASK 0xff000000
#define CMD_REG_STAT_SHIFT 24
#define STAT_WORKING 0x00
#define STAT_COMPLETE 0x01
#define STAT_ERR_INVAL_CMD 0x80
#define STAT_ERR_INVAL_IRQ 0x81
#define STAT_ERR_MTOE 0x82
/* Response tag & CRC */
#define STAT_RTAG 0x04
/* Response CRC */
#define STAT_RCRC 0x05
/* Echo and Send delay */
#define ECHO_DLY_REG 0x08
#define SEND_DLY_REG 0x09
/* Command data area
*
* Last byte of message must be left aligned
*/
#define CMD_DATA 0x10 /* 64 bit of data */
/* Response data area, right aligned, unused top bits are 1 */
#define RSP_DATA 0x20 /* 32 bit of data */
/* Misc */
#define INT_CNT 0x30 /* 32-bit interrupt count */
#define BAD_INT_VEC 0x34 /* 32-bit bad interrupt vector # */
#define CF_STARTED 0x38 /* byte, set to -1 when copro started */
#define CLK_CNT 0x3c /* 32-bit, clock count (debug only) */
/*
* SRAM layout: GPIO arbitration part
*/
#define ARB_REG 0x40
#define ARB_ARM_REQ 0x01
#define ARB_ARM_ACK 0x02
/* Misc2 */
#define CF_RESET_D0 0x50
#define CF_RESET_D1 0x54
#define BAD_INT_S0 0x58
#define BAD_INT_S1 0x5c
#define STOP_CNT 0x60
/* Internal */
/*
* SRAM layout: Trace buffer (debug builds only)
*/
#define TRACEBUF 0x100
#define TR_CLKOBIT0 0xc0
#define TR_CLKOBIT1 0xc1
#define TR_CLKOSTART 0x82
#define TR_OLEN 0x83 /* + len */
#define TR_CLKZ 0x84 /* + count */
#define TR_CLKWSTART 0x85
#define TR_CLKTAG 0x86 /* + tag */
#define TR_CLKDATA 0x87 /* + len */
#define TR_CLKCRC 0x88 /* + raw crc */
#define TR_CLKIBIT0 0x90
#define TR_CLKIBIT1 0x91
#define TR_END 0xff
#endif /* __CF_FSI_FW_H */

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@ -0,0 +1,150 @@
#undef TRACE_SYSTEM
#define TRACE_SYSTEM fsi_master_ast_cf
#if !defined(_TRACE_FSI_MASTER_ACF_H) || defined(TRACE_HEADER_MULTI_READ)
#define _TRACE_FSI_MASTER_ACF_H
#include <linux/tracepoint.h>
TRACE_EVENT(fsi_master_acf_copro_command,
TP_PROTO(const struct fsi_master_acf *master, uint32_t op),
TP_ARGS(master, op),
TP_STRUCT__entry(
__field(int, master_idx)
__field(uint32_t, op)
),
TP_fast_assign(
__entry->master_idx = master->master.idx;
__entry->op = op;
),
TP_printk("fsi-acf%d command %08x",
__entry->master_idx, __entry->op
)
);
TRACE_EVENT(fsi_master_acf_send_request,
TP_PROTO(const struct fsi_master_acf *master, const struct fsi_msg *cmd, u8 rbits),
TP_ARGS(master, cmd, rbits),
TP_STRUCT__entry(
__field(int, master_idx)
__field(uint64_t, msg)
__field(u8, bits)
__field(u8, rbits)
),
TP_fast_assign(
__entry->master_idx = master->master.idx;
__entry->msg = cmd->msg;
__entry->bits = cmd->bits;
__entry->rbits = rbits;
),
TP_printk("fsi-acf%d cmd: %016llx/%d/%d",
__entry->master_idx, (unsigned long long)__entry->msg,
__entry->bits, __entry->rbits
)
);
TRACE_EVENT(fsi_master_acf_copro_response,
TP_PROTO(const struct fsi_master_acf *master, u8 rtag, u8 rcrc, __be32 rdata, bool crc_ok),
TP_ARGS(master, rtag, rcrc, rdata, crc_ok),
TP_STRUCT__entry(
__field(int, master_idx)
__field(u8, rtag)
__field(u8, rcrc)
__field(u32, rdata)
__field(bool, crc_ok)
),
TP_fast_assign(
__entry->master_idx = master->master.idx;
__entry->rtag = rtag;
__entry->rcrc = rcrc;
__entry->rdata = be32_to_cpu(rdata);
__entry->crc_ok = crc_ok;
),
TP_printk("fsi-acf%d rsp: tag=%04x crc=%04x data=%08x %c\n",
__entry->master_idx, __entry->rtag, __entry->rcrc,
__entry->rdata, __entry->crc_ok ? ' ' : '!'
)
);
TRACE_EVENT(fsi_master_acf_crc_rsp_error,
TP_PROTO(const struct fsi_master_acf *master, int retries),
TP_ARGS(master, retries),
TP_STRUCT__entry(
__field(int, master_idx)
__field(int, retries)
),
TP_fast_assign(
__entry->master_idx = master->master.idx;
__entry->retries = retries;
),
TP_printk("fsi-acf%d CRC error in response retry %d",
__entry->master_idx, __entry->retries
)
);
TRACE_EVENT(fsi_master_acf_poll_response_busy,
TP_PROTO(const struct fsi_master_acf *master, int busy_count),
TP_ARGS(master, busy_count),
TP_STRUCT__entry(
__field(int, master_idx)
__field(int, busy_count)
),
TP_fast_assign(
__entry->master_idx = master->master.idx;
__entry->busy_count = busy_count;
),
TP_printk("fsi-acf%d: device reported busy %d times",
__entry->master_idx, __entry->busy_count
)
);
TRACE_EVENT(fsi_master_acf_cmd_abs_addr,
TP_PROTO(const struct fsi_master_acf *master, u32 addr),
TP_ARGS(master, addr),
TP_STRUCT__entry(
__field(int, master_idx)
__field(u32, addr)
),
TP_fast_assign(
__entry->master_idx = master->master.idx;
__entry->addr = addr;
),
TP_printk("fsi-acf%d: Sending ABS_ADR %06x",
__entry->master_idx, __entry->addr
)
);
TRACE_EVENT(fsi_master_acf_cmd_rel_addr,
TP_PROTO(const struct fsi_master_acf *master, u32 rel_addr),
TP_ARGS(master, rel_addr),
TP_STRUCT__entry(
__field(int, master_idx)
__field(u32, rel_addr)
),
TP_fast_assign(
__entry->master_idx = master->master.idx;
__entry->rel_addr = rel_addr;
),
TP_printk("fsi-acf%d: Sending REL_ADR %03x",
__entry->master_idx, __entry->rel_addr
)
);
TRACE_EVENT(fsi_master_acf_cmd_same_addr,
TP_PROTO(const struct fsi_master_acf *master),
TP_ARGS(master),
TP_STRUCT__entry(
__field(int, master_idx)
),
TP_fast_assign(
__entry->master_idx = master->master.idx;
),
TP_printk("fsi-acf%d: Sending SAME_ADR",
__entry->master_idx
)
);
#endif /* _TRACE_FSI_MASTER_ACF_H */
#include <trace/define_trace.h>