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MIPS: memset: Limit excessive `noreorder' assembly mode use
Rewrite to use the `reorder' assembly mode and remove manually scheduled
delay slots except where GAS cannot schedule a delay-slot instruction
due to a data dependency or a section switch (as is the case with the EX
macro). No change in machine code produced.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
[paul.burton@mips.com:
Fix conflict with commit 932afdeec1 ("MIPS: Add Kconfig variable for
CPUs with unaligned load/store instructions")]
Signed-off-by: Paul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/20834/
Cc: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Maciej W. Rozycki
Paul Burton
parent
2f7619ae90
commit
68dec269ee
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@ -78,7 +78,6 @@
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#endif
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.endm
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.set noreorder
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.align 5
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/*
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@ -94,13 +93,16 @@
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.endif
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sltiu t0, a2, STORSIZE /* very small region? */
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.set noreorder
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bnez t0, .Lsmall_memset\@
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andi t0, a0, STORMASK /* aligned? */
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.set reorder
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#ifdef CONFIG_CPU_MICROMIPS
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move t8, a1 /* used by 'swp' instruction */
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move t9, a1
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#endif
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.set noreorder
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#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
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beqz t0, 1f
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PTR_SUBU t0, STORSIZE /* alignment in bytes */
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@ -111,6 +113,7 @@
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PTR_SUBU t0, AT /* alignment in bytes */
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.set at
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#endif
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.set reorder
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#ifdef CONFIG_CPU_HAS_LOAD_STORE_LR
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R10KCBARRIER(0(ra))
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@ -125,8 +128,10 @@
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#else /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
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#define STORE_BYTE(N) \
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EX(sb, a1, N(a0), .Lbyte_fixup\@); \
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.set noreorder; \
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beqz t0, 0f; \
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PTR_ADDU t0, 1;
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PTR_ADDU t0, 1; \
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.set reorder;
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PTR_ADDU a2, t0 /* correct size */
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PTR_ADDU t0, 1
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@ -148,16 +153,14 @@
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#endif /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
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1: ori t1, a2, 0x3f /* # of full blocks */
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xori t1, 0x3f
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andi t0, a2, 0x40-STORSIZE
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beqz t1, .Lmemset_partial\@ /* no block to fill */
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andi t0, a2, 0x40-STORSIZE
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PTR_ADDU t1, a0 /* end address */
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.set reorder
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1: PTR_ADDIU a0, 64
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R10KCBARRIER(0(ra))
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f_fill64 a0, -64, FILL64RG, .Lfwd_fixup\@, \mode
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bne t1, a0, 1b
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.set noreorder
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.Lmemset_partial\@:
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R10KCBARRIER(0(ra))
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@ -173,20 +176,18 @@
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PTR_SUBU t1, AT
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.set at
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#endif
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PTR_ADDU a0, t0 /* dest ptr */
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jr t1
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PTR_ADDU a0, t0 /* dest ptr */
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.set push
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.set noreorder
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.set nomacro
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/* ... but first do longs ... */
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f_fill64 a0, -64, FILL64RG, .Lpartial_fixup\@, \mode
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2: .set pop
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andi a2, STORMASK /* At most one long to go */
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2: andi a2, STORMASK /* At most one long to go */
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.set noreorder
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beqz a2, 1f
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#ifdef CONFIG_CPU_HAS_LOAD_STORE_LR
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PTR_ADDU a0, a2 /* What's left */
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.set reorder
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R10KCBARRIER(0(ra))
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#ifdef __MIPSEB__
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EX(LONG_S_R, a1, -1(a0), .Llast_fixup\@)
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@ -195,6 +196,7 @@
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#endif
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#else
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PTR_SUBU t0, $0, a2
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.set reorder
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move a2, zero /* No remaining longs */
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PTR_ADDIU t0, 1
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STORE_BYTE(0)
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@ -210,20 +212,22 @@
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#endif
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0:
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#endif
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1: jr ra
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move a2, zero
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1: move a2, zero
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jr ra
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.Lsmall_memset\@:
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PTR_ADDU t1, a0, a2
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beqz a2, 2f
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PTR_ADDU t1, a0, a2
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1: PTR_ADDIU a0, 1 /* fill bytewise */
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R10KCBARRIER(0(ra))
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.set noreorder
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bne t1, a0, 1b
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EX(sb, a1, -1(a0), .Lsmall_fixup\@)
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.set reorder
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2: jr ra /* done */
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move a2, zero
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2: move a2, zero
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jr ra /* done */
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.if __memset == 1
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END(memset)
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.set __memset, 0
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@ -237,14 +241,13 @@
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* a2 = a2 - t0 + 1
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*/
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PTR_SUBU a2, t0
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PTR_ADDIU a2, 1
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jr ra
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PTR_ADDIU a2, 1
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#endif /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
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.Lfirst_fixup\@:
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/* unset_bytes already in a2 */
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jr ra
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nop
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.Lfwd_fixup\@:
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/*
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@ -255,8 +258,8 @@
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andi a2, 0x3f
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LONG_L t0, THREAD_BUADDR(t0)
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LONG_ADDU a2, t1
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LONG_SUBU a2, t0
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jr ra
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LONG_SUBU a2, t0
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.Lpartial_fixup\@:
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/*
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@ -267,24 +270,21 @@
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andi a2, STORMASK
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LONG_L t0, THREAD_BUADDR(t0)
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LONG_ADDU a2, a0
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LONG_SUBU a2, t0
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jr ra
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LONG_SUBU a2, t0
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.Llast_fixup\@:
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/* unset_bytes already in a2 */
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jr ra
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nop
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.Lsmall_fixup\@:
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/*
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* unset_bytes = end_addr - current_addr + 1
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* a2 = t1 - a0 + 1
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*/
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.set reorder
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PTR_SUBU a2, t1, a0
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PTR_ADDIU a2, 1
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jr ra
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.set noreorder
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.endm
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@ -298,8 +298,8 @@
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LEAF(memset)
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EXPORT_SYMBOL(memset)
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move v0, a0 /* result */
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beqz a1, 1f
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move v0, a0 /* result */
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andi a1, 0xff /* spread fillword */
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LONG_SLL t1, a1, 8
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