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[ARM] Convert ARMv6 and ARMv7 to use new memory types

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Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King 2008-09-06 21:07:45 +01:00 committed by Russell King
parent 9e8b5199a7
commit 639b0ae7f5
7 changed files with 40 additions and 18 deletions
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8
arch/arm/include/asm/pgtable.h
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@ -175,8 +175,6 @@ extern void __pgd_error(const char *file, int line, unsigned long val);
/*
* These are the memory types, defined to be compatible with
* pre-ARMv6 CPUs cacheable and bufferable bits: XXCB
* (note: build_mem_type_table modifies these bits
* to work with our existing proc-*.S setup.)
*/
#define L_PTE_MT_UNCACHED (0x00 << 2) /* 0000 */
#define L_PTE_MT_BUFFERABLE (0x01 << 2) /* 0001 */
@ -184,12 +182,10 @@ extern void __pgd_error(const char *file, int line, unsigned long val);
#define L_PTE_MT_WRITEBACK (0x03 << 2) /* 0011 */
#define L_PTE_MT_MINICACHE (0x06 << 2) /* 0110 (sa1100, xscale) */
#define L_PTE_MT_WRITEALLOC (0x07 << 2) /* 0111 */
#define L_PTE_MT_DEV_SHARED (0x04 << 2) /* 0100 (pre-v6) */
#define L_PTE_MT_DEV_SHARED2 (0x05 << 2) /* 0101 (v6) */
#define L_PTE_MT_DEV_SHARED (0x04 << 2) /* 0100 */
#define L_PTE_MT_DEV_NONSHARED (0x0c << 2) /* 1100 */
#define L_PTE_MT_DEV_IXP2000 (0x0d << 2) /* 1101 */
#define L_PTE_MT_DEV_WC (0x09 << 2) /* 1001 (pre-v6) */
#define L_PTE_MT_DEV_WC2 (0x08 << 2) /* 1000 (v6) */
#define L_PTE_MT_DEV_WC (0x09 << 2) /* 1001 */
#define L_PTE_MT_DEV_CACHED (0x0b << 2) /* 1011 */
#define L_PTE_MT_MASK (0x0f << 2)

4
arch/arm/mm/mmu.c
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@ -194,7 +194,6 @@ static struct mem_type mem_types[] = {
},
[MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
.prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
.prot_pte_ext = PTE_EXT_TEX(2),
.prot_l1 = PMD_TYPE_TABLE,
.prot_sect = PROT_SECT_DEVICE | PMD_SECT_TEX(2),
.domain = DOMAIN_IO,
@ -289,8 +288,6 @@ static void __init build_mem_type_table(void)
* in xsc3 parlance, Uncached Normal in ARMv6 parlance).
*/
if (cpu_is_xsc3() || cpu_arch >= CPU_ARCH_ARMv6) {
mem_types[MT_DEVICE_WC].prot_pte_ext |= PTE_EXT_TEX(1);
mem_types[MT_DEVICE_WC].prot_pte &= ~L_PTE_BUFFERABLE;
mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
mem_types[MT_DEVICE_WC].prot_sect &= ~PMD_SECT_BUFFERABLE;
}
@ -351,7 +348,6 @@ static void __init build_mem_type_table(void)
/*
* Mark the device area as "shared device"
*/
mem_types[MT_DEVICE].prot_pte |= L_PTE_BUFFERABLE;
mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
#ifdef CONFIG_SMP

30
arch/arm/mm/proc-macros.S
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@ -104,14 +104,38 @@
* 11x0 0 1 0 r/w r/o
* 1111 0 1 1 r/w r/w
*/
.macro armv6_set_pte_ext
.macro armv6_mt_table pfx
\pfx\()_mt_table:
.long 0x00 @ L_PTE_MT_UNCACHED
.long PTE_EXT_TEX(1) @ L_PTE_MT_BUFFERABLE
.long PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH
.long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK
.long PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED
.long 0x00 @ unused
.long 0x00 @ L_PTE_MT_MINICACHE (not present)
.long PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC
.long 0x00 @ unused
.long PTE_EXT_TEX(1) @ L_PTE_MT_DEV_WC
.long 0x00 @ unused
.long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED
.long PTE_EXT_TEX(2) @ L_PTE_MT_DEV_NONSHARED
.long 0x00 @ L_PTE_MT_DEV_IXP2000
.long 0x00 @ unused
.long 0x00 @ unused
.endm
.macro armv6_set_pte_ext pfx
str r1, [r0], #-2048 @ linux version
bic r3, r1, #0x000003f0
bic r3, r1, #0x000003fc
bic r3, r3, #PTE_TYPE_MASK
orr r3, r3, r2
orr r3, r3, #PTE_EXT_AP0 | 2
adr ip, \pfx\()_mt_table
and r2, r1, #L_PTE_MT_MASK
ldr r2, [ip, r2]
tst r1, #L_PTE_WRITE
tstne r1, #L_PTE_DIRTY
orreq r3, r3, #PTE_EXT_APX
@ -124,6 +148,8 @@
tst r1, #L_PTE_EXEC
orreq r3, r3, #PTE_EXT_XN
orr r3, r3, r2
tst r1, #L_PTE_YOUNG
tstne r1, #L_PTE_PRESENT
moveq r3, #0

4
arch/arm/mm/proc-v6.S
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@ -115,9 +115,11 @@ ENTRY(cpu_v6_switch_mm)
* - pte - PTE value to store
* - ext - value for extended PTE bits
*/
armv6_mt_table cpu_v6
ENTRY(cpu_v6_set_pte_ext)
#ifdef CONFIG_MMU
armv6_set_pte_ext
armv6_set_pte_ext cpu_v6
#endif
mov pc, lr

4
arch/arm/mm/proc-v7.S
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@ -100,9 +100,11 @@ ENTRY(cpu_v7_switch_mm)
* - pte - PTE value to store
* - ext - value for extended PTE bits
*/
armv6_mt_table cpu_v7
ENTRY(cpu_v7_set_pte_ext)
#ifdef CONFIG_MMU
armv6_set_pte_ext
armv6_set_pte_ext cpu_v7
#endif
mov pc, lr

4
arch/arm/mm/proc-xsc3.S
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@ -354,10 +354,10 @@ cpu_xsc3_mt_table:
.long PTE_EXT_TEX(5) | PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH
.long PTE_EXT_TEX(5) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK
.long 0x00 @ L_PTE_MT_DEV_SHARED
.long 0x00 @ L_PTE_MT_DEV_SHARED2
.long 0x00 @ unused
.long 0x00 @ L_PTE_MT_MINICACHE (not present)
.long PTE_EXT_TEX(5) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC (not present?)
.long PTE_EXT_TEX(1) @ L_PTE_MT_DEV_WC2
.long 0x00 @ unused
.long PTE_EXT_TEX(1) @ L_PTE_MT_DEV_WC
.long 0x00 @ unused
.long PTE_EXT_TEX(5) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED

4
arch/arm/mm/proc-xscale.S
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@ -435,10 +435,10 @@ cpu_xscale_mt_table:
.long PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH
.long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK
.long 0x00 @ L_PTE_MT_DEV_SHARED
.long 0x00 @ L_PTE_MT_DEV_SHARED2
.long 0x00 @ unused
.long PTE_EXT_TEX(1) | PTE_CACHEABLE @ L_PTE_MT_MINICACHE
.long PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC
.long PTE_BUFFERABLE @ L_PTE_MT_DEV_WC2
.long 0x00 @ unused
.long PTE_BUFFERABLE @ L_PTE_MT_DEV_WC
.long 0x00 @ unused
.long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED