Add COH 901 318 DMA block driver v5
This patch adds support for the ST-Ericsson COH 901 318 DMA block, found in the U300 series platforms. It registers a DMA slave for device I/O and also a memcpy slave for memcpy. Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
This commit is contained in:
Linus Walleij
Dan Williams
parent
b419148e56
commit
61f135b92f
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@ -0,0 +1,281 @@
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/*
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*
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* include/linux/coh901318.h
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*
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*
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* Copyright (C) 2007-2009 ST-Ericsson
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* License terms: GNU General Public License (GPL) version 2
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* DMA driver for COH 901 318
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* Author: Per Friden <per.friden@stericsson.com>
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*/
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#ifndef COH901318_H
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#define COH901318_H
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#include <linux/device.h>
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#include <linux/dmaengine.h>
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#define MAX_DMA_PACKET_SIZE_SHIFT 11
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#define MAX_DMA_PACKET_SIZE (1 << MAX_DMA_PACKET_SIZE_SHIFT)
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/**
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* struct coh901318_lli - linked list item for DMAC
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* @control: control settings for DMAC
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* @src_addr: transfer source address
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* @dst_addr: transfer destination address
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* @link_addr: physical address to next lli
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* @virt_link_addr: virtual addres of next lli (only used by pool_free)
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* @phy_this: physical address of current lli (only used by pool_free)
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*/
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struct coh901318_lli {
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u32 control;
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dma_addr_t src_addr;
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dma_addr_t dst_addr;
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dma_addr_t link_addr;
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void *virt_link_addr;
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dma_addr_t phy_this;
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};
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/**
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* struct coh901318_params - parameters for DMAC configuration
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* @config: DMA config register
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* @ctrl_lli_last: DMA control register for the last lli in the list
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* @ctrl_lli: DMA control register for an lli
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* @ctrl_lli_chained: DMA control register for a chained lli
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*/
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struct coh901318_params {
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u32 config;
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u32 ctrl_lli_last;
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u32 ctrl_lli;
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u32 ctrl_lli_chained;
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};
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/**
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* struct coh_dma_channel - dma channel base
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* @name: ascii name of dma channel
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* @number: channel id number
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* @desc_nbr_max: number of preallocated descriptortors
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* @priority_high: prio of channel, 0 low otherwise high.
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* @param: configuration parameters
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* @dev_addr: physical address of periphal connected to channel
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*/
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struct coh_dma_channel {
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const char name[32];
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const int number;
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const int desc_nbr_max;
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const int priority_high;
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const struct coh901318_params param;
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const dma_addr_t dev_addr;
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};
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/**
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* dma_access_memory_state_t - register dma for memory access
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*
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* @dev: The dma device
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* @active: 1 means dma intends to access memory
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* 0 means dma wont access memory
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*/
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typedef void (*dma_access_memory_state_t)(struct device *dev,
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bool active);
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/**
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* struct powersave - DMA power save structure
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* @lock: lock protecting data in this struct
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* @started_channels: bit mask indicating active dma channels
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*/
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struct powersave {
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spinlock_t lock;
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u64 started_channels;
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};
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/**
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* struct coh901318_platform - platform arch structure
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* @chans_slave: specifying dma slave channels
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* @chans_memcpy: specifying dma memcpy channels
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* @access_memory_state: requesting DMA memeory access (on / off)
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* @chan_conf: dma channel configurations
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* @max_channels: max number of dma chanenls
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*/
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struct coh901318_platform {
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const int *chans_slave;
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const int *chans_memcpy;
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const dma_access_memory_state_t access_memory_state;
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const struct coh_dma_channel *chan_conf;
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const int max_channels;
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};
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/**
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* coh901318_get_bytes_left() - Get number of bytes left on a current transfer
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* @chan: dma channel handle
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* return number of bytes left, or negative on error
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*/
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u32 coh901318_get_bytes_left(struct dma_chan *chan);
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/**
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* coh901318_stop() - Stops dma transfer
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* @chan: dma channel handle
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* return 0 on success otherwise negative value
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*/
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void coh901318_stop(struct dma_chan *chan);
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/**
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* coh901318_continue() - Resumes a stopped dma transfer
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* @chan: dma channel handle
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* return 0 on success otherwise negative value
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*/
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void coh901318_continue(struct dma_chan *chan);
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/**
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* coh901318_filter_id() - DMA channel filter function
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* @chan: dma channel handle
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* @chan_id: id of dma channel to be filter out
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*
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* In dma_request_channel() it specifies what channel id to be requested
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*/
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bool coh901318_filter_id(struct dma_chan *chan, void *chan_id);
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/*
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* DMA Controller - this access the static mappings of the coh901318 dma.
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*
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*/
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#define COH901318_MOD32_MASK (0x1F)
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#define COH901318_WORD_MASK (0xFFFFFFFF)
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/* INT_STATUS - Interrupt Status Registers 32bit (R/-) */
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#define COH901318_INT_STATUS1 (0x0000)
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#define COH901318_INT_STATUS2 (0x0004)
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/* TC_INT_STATUS - Terminal Count Interrupt Status Registers 32bit (R/-) */
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#define COH901318_TC_INT_STATUS1 (0x0008)
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#define COH901318_TC_INT_STATUS2 (0x000C)
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/* TC_INT_CLEAR - Terminal Count Interrupt Clear Registers 32bit (-/W) */
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#define COH901318_TC_INT_CLEAR1 (0x0010)
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#define COH901318_TC_INT_CLEAR2 (0x0014)
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/* RAW_TC_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */
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#define COH901318_RAW_TC_INT_STATUS1 (0x0018)
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#define COH901318_RAW_TC_INT_STATUS2 (0x001C)
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/* BE_INT_STATUS - Bus Error Interrupt Status Registers 32bit (R/-) */
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#define COH901318_BE_INT_STATUS1 (0x0020)
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#define COH901318_BE_INT_STATUS2 (0x0024)
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/* BE_INT_CLEAR - Bus Error Interrupt Clear Registers 32bit (-/W) */
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#define COH901318_BE_INT_CLEAR1 (0x0028)
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#define COH901318_BE_INT_CLEAR2 (0x002C)
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/* RAW_BE_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */
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#define COH901318_RAW_BE_INT_STATUS1 (0x0030)
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#define COH901318_RAW_BE_INT_STATUS2 (0x0034)
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/*
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* CX_CFG - Channel Configuration Registers 32bit (R/W)
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*/
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#define COH901318_CX_CFG (0x0100)
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#define COH901318_CX_CFG_SPACING (0x04)
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/* Channel enable activates tha dma job */
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#define COH901318_CX_CFG_CH_ENABLE (0x00000001)
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#define COH901318_CX_CFG_CH_DISABLE (0x00000000)
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/* Request Mode */
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#define COH901318_CX_CFG_RM_MASK (0x00000006)
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#define COH901318_CX_CFG_RM_MEMORY_TO_MEMORY (0x0 << 1)
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#define COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY (0x1 << 1)
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#define COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY (0x1 << 1)
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#define COH901318_CX_CFG_RM_PRIMARY_TO_SECONDARY (0x3 << 1)
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#define COH901318_CX_CFG_RM_SECONDARY_TO_PRIMARY (0x3 << 1)
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/* Linked channel request field. RM must == 11 */
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#define COH901318_CX_CFG_LCRF_SHIFT 3
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#define COH901318_CX_CFG_LCRF_MASK (0x000001F8)
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#define COH901318_CX_CFG_LCR_DISABLE (0x00000000)
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/* Terminal Counter Interrupt Request Mask */
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#define COH901318_CX_CFG_TC_IRQ_ENABLE (0x00000200)
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#define COH901318_CX_CFG_TC_IRQ_DISABLE (0x00000000)
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/* Bus Error interrupt Mask */
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#define COH901318_CX_CFG_BE_IRQ_ENABLE (0x00000400)
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#define COH901318_CX_CFG_BE_IRQ_DISABLE (0x00000000)
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/*
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* CX_STAT - Channel Status Registers 32bit (R/-)
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*/
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#define COH901318_CX_STAT (0x0200)
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#define COH901318_CX_STAT_SPACING (0x04)
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#define COH901318_CX_STAT_RBE_IRQ_IND (0x00000008)
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#define COH901318_CX_STAT_RTC_IRQ_IND (0x00000004)
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#define COH901318_CX_STAT_ACTIVE (0x00000002)
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#define COH901318_CX_STAT_ENABLED (0x00000001)
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/*
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* CX_CTRL - Channel Control Registers 32bit (R/W)
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*/
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#define COH901318_CX_CTRL (0x0400)
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#define COH901318_CX_CTRL_SPACING (0x10)
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/* Transfer Count Enable */
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#define COH901318_CX_CTRL_TC_ENABLE (0x00001000)
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#define COH901318_CX_CTRL_TC_DISABLE (0x00000000)
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/* Transfer Count Value 0 - 4095 */
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#define COH901318_CX_CTRL_TC_VALUE_MASK (0x00000FFF)
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/* Burst count */
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#define COH901318_CX_CTRL_BURST_COUNT_MASK (0x0000E000)
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#define COH901318_CX_CTRL_BURST_COUNT_64_BYTES (0x7 << 13)
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#define COH901318_CX_CTRL_BURST_COUNT_48_BYTES (0x6 << 13)
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#define COH901318_CX_CTRL_BURST_COUNT_32_BYTES (0x5 << 13)
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#define COH901318_CX_CTRL_BURST_COUNT_16_BYTES (0x4 << 13)
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#define COH901318_CX_CTRL_BURST_COUNT_8_BYTES (0x3 << 13)
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#define COH901318_CX_CTRL_BURST_COUNT_4_BYTES (0x2 << 13)
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#define COH901318_CX_CTRL_BURST_COUNT_2_BYTES (0x1 << 13)
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#define COH901318_CX_CTRL_BURST_COUNT_1_BYTE (0x0 << 13)
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/* Source bus size */
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#define COH901318_CX_CTRL_SRC_BUS_SIZE_MASK (0x00030000)
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#define COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS (0x2 << 16)
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#define COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS (0x1 << 16)
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#define COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS (0x0 << 16)
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/* Source address increment */
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#define COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE (0x00040000)
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#define COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE (0x00000000)
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/* Destination Bus Size */
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#define COH901318_CX_CTRL_DST_BUS_SIZE_MASK (0x00180000)
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#define COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS (0x2 << 19)
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#define COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS (0x1 << 19)
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#define COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS (0x0 << 19)
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/* Destination address increment */
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#define COH901318_CX_CTRL_DST_ADDR_INC_ENABLE (0x00200000)
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#define COH901318_CX_CTRL_DST_ADDR_INC_DISABLE (0x00000000)
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/* Master Mode (Master2 is only connected to MSL) */
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#define COH901318_CX_CTRL_MASTER_MODE_MASK (0x00C00000)
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#define COH901318_CX_CTRL_MASTER_MODE_M2R_M1W (0x3 << 22)
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#define COH901318_CX_CTRL_MASTER_MODE_M1R_M2W (0x2 << 22)
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#define COH901318_CX_CTRL_MASTER_MODE_M2RW (0x1 << 22)
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#define COH901318_CX_CTRL_MASTER_MODE_M1RW (0x0 << 22)
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/* Terminal Count flag to PER enable */
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#define COH901318_CX_CTRL_TCP_ENABLE (0x01000000)
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#define COH901318_CX_CTRL_TCP_DISABLE (0x00000000)
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/* Terminal Count flags to CPU enable */
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#define COH901318_CX_CTRL_TC_IRQ_ENABLE (0x02000000)
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#define COH901318_CX_CTRL_TC_IRQ_DISABLE (0x00000000)
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/* Hand shake to peripheral */
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#define COH901318_CX_CTRL_HSP_ENABLE (0x04000000)
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#define COH901318_CX_CTRL_HSP_DISABLE (0x00000000)
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#define COH901318_CX_CTRL_HSS_ENABLE (0x08000000)
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#define COH901318_CX_CTRL_HSS_DISABLE (0x00000000)
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/* DMA mode */
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#define COH901318_CX_CTRL_DDMA_MASK (0x30000000)
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#define COH901318_CX_CTRL_DDMA_LEGACY (0x0 << 28)
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#define COH901318_CX_CTRL_DDMA_DEMAND_DMA1 (0x1 << 28)
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#define COH901318_CX_CTRL_DDMA_DEMAND_DMA2 (0x2 << 28)
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/* Primary Request Data Destination */
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#define COH901318_CX_CTRL_PRDD_MASK (0x40000000)
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#define COH901318_CX_CTRL_PRDD_DEST (0x1 << 30)
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#define COH901318_CX_CTRL_PRDD_SOURCE (0x0 << 30)
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/*
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* CX_SRC_ADDR - Channel Source Address Registers 32bit (R/W)
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*/
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#define COH901318_CX_SRC_ADDR (0x0404)
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#define COH901318_CX_SRC_ADDR_SPACING (0x10)
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/*
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* CX_DST_ADDR - Channel Destination Address Registers 32bit R/W
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*/
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#define COH901318_CX_DST_ADDR (0x0408)
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#define COH901318_CX_DST_ADDR_SPACING (0x10)
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/*
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* CX_LNK_ADDR - Channel Link Address Registers 32bit (R/W)
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*/
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#define COH901318_CX_LNK_ADDR (0x040C)
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#define COH901318_CX_LNK_ADDR_SPACING (0x10)
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#define COH901318_CX_LNK_LINK_IMMEDIATE (0x00000001)
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#endif /* COH901318_H */
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@ -109,6 +109,13 @@ config SH_DMAE
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help
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Enable support for the Renesas SuperH DMA controllers.
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config COH901318
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bool "ST-Ericsson COH901318 DMA support"
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select DMA_ENGINE
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depends on ARCH_U300
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help
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Enable support for ST-Ericsson COH 901 318 DMA.
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config DMA_ENGINE
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bool
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@ -10,3 +10,4 @@ obj-$(CONFIG_AT_HDMAC) += at_hdmac.o
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obj-$(CONFIG_MX3_IPU) += ipu/
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obj-$(CONFIG_TXX9_DMAC) += txx9dmac.o
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obj-$(CONFIG_SH_DMAE) += shdma.o
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obj-$(CONFIG_COH901318) += coh901318.o coh901318_lli.o
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,318 @@
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/*
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* driver/dma/coh901318_lli.c
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*
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* Copyright (C) 2007-2009 ST-Ericsson
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* License terms: GNU General Public License (GPL) version 2
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* Support functions for handling lli for dma
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* Author: Per Friden <per.friden@stericsson.com>
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*/
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#include <linux/dma-mapping.h>
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#include <linux/spinlock.h>
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#include <linux/dmapool.h>
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#include <linux/memory.h>
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#include <mach/coh901318.h>
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#include "coh901318_lli.h"
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#if (defined(CONFIG_DEBUG_FS) && defined(CONFIG_U300_DEBUG))
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#define DEBUGFS_POOL_COUNTER_RESET(pool) (pool->debugfs_pool_counter = 0)
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#define DEBUGFS_POOL_COUNTER_ADD(pool, add) (pool->debugfs_pool_counter += add)
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#else
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#define DEBUGFS_POOL_COUNTER_RESET(pool)
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#define DEBUGFS_POOL_COUNTER_ADD(pool, add)
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#endif
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static struct coh901318_lli *
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coh901318_lli_next(struct coh901318_lli *data)
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{
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if (data == NULL || data->link_addr == 0)
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return NULL;
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return (struct coh901318_lli *) data->virt_link_addr;
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}
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int coh901318_pool_create(struct coh901318_pool *pool,
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struct device *dev,
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size_t size, size_t align)
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{
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spin_lock_init(&pool->lock);
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pool->dev = dev;
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pool->dmapool = dma_pool_create("lli_pool", dev, size, align, 0);
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DEBUGFS_POOL_COUNTER_RESET(pool);
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return 0;
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}
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int coh901318_pool_destroy(struct coh901318_pool *pool)
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{
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dma_pool_destroy(pool->dmapool);
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return 0;
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}
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struct coh901318_lli *
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coh901318_lli_alloc(struct coh901318_pool *pool, unsigned int len)
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{
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int i;
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struct coh901318_lli *head;
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struct coh901318_lli *lli;
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struct coh901318_lli *lli_prev;
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dma_addr_t phy;
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if (len == 0)
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goto err;
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spin_lock(&pool->lock);
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head = dma_pool_alloc(pool->dmapool, GFP_NOWAIT, &phy);
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if (head == NULL)
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goto err;
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DEBUGFS_POOL_COUNTER_ADD(pool, 1);
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lli = head;
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lli->phy_this = phy;
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for (i = 1; i < len; i++) {
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lli_prev = lli;
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lli = dma_pool_alloc(pool->dmapool, GFP_NOWAIT, &phy);
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if (lli == NULL)
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goto err_clean_up;
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DEBUGFS_POOL_COUNTER_ADD(pool, 1);
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lli->phy_this = phy;
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|
||||
lli_prev->link_addr = phy;
|
||||
lli_prev->virt_link_addr = lli;
|
||||
}
|
||||
|
||||
lli->link_addr = 0x00000000U;
|
||||
|
||||
spin_unlock(&pool->lock);
|
||||
|
||||
return head;
|
||||
|
||||
err:
|
||||
spin_unlock(&pool->lock);
|
||||
return NULL;
|
||||
|
||||
err_clean_up:
|
||||
lli_prev->link_addr = 0x00000000U;
|
||||
spin_unlock(&pool->lock);
|
||||
coh901318_lli_free(pool, &head);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
void coh901318_lli_free(struct coh901318_pool *pool,
|
||||
struct coh901318_lli **lli)
|
||||
{
|
||||
struct coh901318_lli *l;
|
||||
struct coh901318_lli *next;
|
||||
|
||||
if (lli == NULL)
|
||||
return;
|
||||
|
||||
l = *lli;
|
||||
|
||||
if (l == NULL)
|
||||
return;
|
||||
|
||||
spin_lock(&pool->lock);
|
||||
|
||||
while (l->link_addr) {
|
||||
next = l->virt_link_addr;
|
||||
dma_pool_free(pool->dmapool, l, l->phy_this);
|
||||
DEBUGFS_POOL_COUNTER_ADD(pool, -1);
|
||||
l = next;
|
||||
}
|
||||
dma_pool_free(pool->dmapool, l, l->phy_this);
|
||||
DEBUGFS_POOL_COUNTER_ADD(pool, -1);
|
||||
|
||||
spin_unlock(&pool->lock);
|
||||
*lli = NULL;
|
||||
}
|
||||
|
||||
int
|
||||
coh901318_lli_fill_memcpy(struct coh901318_pool *pool,
|
||||
struct coh901318_lli *lli,
|
||||
dma_addr_t source, unsigned int size,
|
||||
dma_addr_t destination, u32 ctrl_chained,
|
||||
u32 ctrl_eom)
|
||||
{
|
||||
int s = size;
|
||||
dma_addr_t src = source;
|
||||
dma_addr_t dst = destination;
|
||||
|
||||
lli->src_addr = src;
|
||||
lli->dst_addr = dst;
|
||||
|
||||
while (lli->link_addr) {
|
||||
lli->control = ctrl_chained | MAX_DMA_PACKET_SIZE;
|
||||
lli->src_addr = src;
|
||||
lli->dst_addr = dst;
|
||||
|
||||
s -= MAX_DMA_PACKET_SIZE;
|
||||
lli = coh901318_lli_next(lli);
|
||||
|
||||
src += MAX_DMA_PACKET_SIZE;
|
||||
dst += MAX_DMA_PACKET_SIZE;
|
||||
}
|
||||
|
||||
lli->control = ctrl_eom | s;
|
||||
lli->src_addr = src;
|
||||
lli->dst_addr = dst;
|
||||
|
||||
/* One irq per single transfer */
|
||||
return 1;
|
||||
}
|
||||
|
||||
int
|
||||
coh901318_lli_fill_single(struct coh901318_pool *pool,
|
||||
struct coh901318_lli *lli,
|
||||
dma_addr_t buf, unsigned int size,
|
||||
dma_addr_t dev_addr, u32 ctrl_chained, u32 ctrl_eom,
|
||||
enum dma_data_direction dir)
|
||||
{
|
||||
int s = size;
|
||||
dma_addr_t src;
|
||||
dma_addr_t dst;
|
||||
|
||||
|
||||
if (dir == DMA_TO_DEVICE) {
|
||||
src = buf;
|
||||
dst = dev_addr;
|
||||
|
||||
} else if (dir == DMA_FROM_DEVICE) {
|
||||
|
||||
src = dev_addr;
|
||||
dst = buf;
|
||||
} else {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
while (lli->link_addr) {
|
||||
size_t block_size = MAX_DMA_PACKET_SIZE;
|
||||
lli->control = ctrl_chained | MAX_DMA_PACKET_SIZE;
|
||||
|
||||
/* If we are on the next-to-final block and there will
|
||||
* be less than half a DMA packet left for the last
|
||||
* block, then we want to make this block a little
|
||||
* smaller to balance the sizes. This is meant to
|
||||
* avoid too small transfers if the buffer size is
|
||||
* (MAX_DMA_PACKET_SIZE*N + 1) */
|
||||
if (s < (MAX_DMA_PACKET_SIZE + MAX_DMA_PACKET_SIZE/2))
|
||||
block_size = MAX_DMA_PACKET_SIZE/2;
|
||||
|
||||
s -= block_size;
|
||||
lli->src_addr = src;
|
||||
lli->dst_addr = dst;
|
||||
|
||||
lli = coh901318_lli_next(lli);
|
||||
|
||||
if (dir == DMA_TO_DEVICE)
|
||||
src += block_size;
|
||||
else if (dir == DMA_FROM_DEVICE)
|
||||
dst += block_size;
|
||||
}
|
||||
|
||||
lli->control = ctrl_eom | s;
|
||||
lli->src_addr = src;
|
||||
lli->dst_addr = dst;
|
||||
|
||||
/* One irq per single transfer */
|
||||
return 1;
|
||||
}
|
||||
|
||||
int
|
||||
coh901318_lli_fill_sg(struct coh901318_pool *pool,
|
||||
struct coh901318_lli *lli,
|
||||
struct scatterlist *sgl, unsigned int nents,
|
||||
dma_addr_t dev_addr, u32 ctrl_chained, u32 ctrl,
|
||||
u32 ctrl_last,
|
||||
enum dma_data_direction dir, u32 ctrl_irq_mask)
|
||||
{
|
||||
int i;
|
||||
struct scatterlist *sg;
|
||||
u32 ctrl_sg;
|
||||
dma_addr_t src = 0;
|
||||
dma_addr_t dst = 0;
|
||||
int nbr_of_irq = 0;
|
||||
u32 bytes_to_transfer;
|
||||
u32 elem_size;
|
||||
|
||||
if (lli == NULL)
|
||||
goto err;
|
||||
|
||||
spin_lock(&pool->lock);
|
||||
|
||||
if (dir == DMA_TO_DEVICE)
|
||||
dst = dev_addr;
|
||||
else if (dir == DMA_FROM_DEVICE)
|
||||
src = dev_addr;
|
||||
else
|
||||
goto err;
|
||||
|
||||
for_each_sg(sgl, sg, nents, i) {
|
||||
if (sg_is_chain(sg)) {
|
||||
/* sg continues to the next sg-element don't
|
||||
* send ctrl_finish until the last
|
||||
* sg-element in the chain
|
||||
*/
|
||||
ctrl_sg = ctrl_chained;
|
||||
} else if (i == nents - 1)
|
||||
ctrl_sg = ctrl_last;
|
||||
else
|
||||
ctrl_sg = ctrl ? ctrl : ctrl_last;
|
||||
|
||||
|
||||
if ((ctrl_sg & ctrl_irq_mask))
|
||||
nbr_of_irq++;
|
||||
|
||||
if (dir == DMA_TO_DEVICE)
|
||||
/* increment source address */
|
||||
src = sg_dma_address(sg);
|
||||
else
|
||||
/* increment destination address */
|
||||
dst = sg_dma_address(sg);
|
||||
|
||||
bytes_to_transfer = sg_dma_len(sg);
|
||||
|
||||
while (bytes_to_transfer) {
|
||||
u32 val;
|
||||
|
||||
if (bytes_to_transfer > MAX_DMA_PACKET_SIZE) {
|
||||
elem_size = MAX_DMA_PACKET_SIZE;
|
||||
val = ctrl_chained;
|
||||
} else {
|
||||
elem_size = bytes_to_transfer;
|
||||
val = ctrl_sg;
|
||||
}
|
||||
|
||||
lli->control = val | elem_size;
|
||||
lli->src_addr = src;
|
||||
lli->dst_addr = dst;
|
||||
|
||||
if (dir == DMA_FROM_DEVICE)
|
||||
dst += elem_size;
|
||||
else
|
||||
src += elem_size;
|
||||
|
||||
BUG_ON(lli->link_addr & 3);
|
||||
|
||||
bytes_to_transfer -= elem_size;
|
||||
lli = coh901318_lli_next(lli);
|
||||
}
|
||||
|
||||
}
|
||||
spin_unlock(&pool->lock);
|
||||
|
||||
/* There can be many IRQs per sg transfer */
|
||||
return nbr_of_irq;
|
||||
err:
|
||||
spin_unlock(&pool->lock);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
|
@ -0,0 +1,124 @@
|
|||
/*
|
||||
* driver/dma/coh901318_lli.h
|
||||
*
|
||||
* Copyright (C) 2007-2009 ST-Ericsson
|
||||
* License terms: GNU General Public License (GPL) version 2
|
||||
* Support functions for handling lli for coh901318
|
||||
* Author: Per Friden <per.friden@stericsson.com>
|
||||
*/
|
||||
|
||||
#ifndef COH901318_LLI_H
|
||||
#define COH901318_LLI_H
|
||||
|
||||
#include <mach/coh901318.h>
|
||||
|
||||
struct device;
|
||||
|
||||
struct coh901318_pool {
|
||||
spinlock_t lock;
|
||||
struct dma_pool *dmapool;
|
||||
struct device *dev;
|
||||
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
int debugfs_pool_counter;
|
||||
#endif
|
||||
};
|
||||
|
||||
struct device;
|
||||
/**
|
||||
* coh901318_pool_create() - Creates an dma pool for lli:s
|
||||
* @pool: pool handle
|
||||
* @dev: dma device
|
||||
* @lli_nbr: number of lli:s in the pool
|
||||
* @algin: adress alignemtn of lli:s
|
||||
* returns 0 on success otherwise none zero
|
||||
*/
|
||||
int coh901318_pool_create(struct coh901318_pool *pool,
|
||||
struct device *dev,
|
||||
size_t lli_nbr, size_t align);
|
||||
|
||||
/**
|
||||
* coh901318_pool_destroy() - Destroys the dma pool
|
||||
* @pool: pool handle
|
||||
* returns 0 on success otherwise none zero
|
||||
*/
|
||||
int coh901318_pool_destroy(struct coh901318_pool *pool);
|
||||
|
||||
/**
|
||||
* coh901318_lli_alloc() - Allocates a linked list
|
||||
*
|
||||
* @pool: pool handle
|
||||
* @len: length to list
|
||||
* return: none NULL if success otherwise NULL
|
||||
*/
|
||||
struct coh901318_lli *
|
||||
coh901318_lli_alloc(struct coh901318_pool *pool,
|
||||
unsigned int len);
|
||||
|
||||
/**
|
||||
* coh901318_lli_free() - Returns the linked list items to the pool
|
||||
* @pool: pool handle
|
||||
* @lli: reference to lli pointer to be freed
|
||||
*/
|
||||
void coh901318_lli_free(struct coh901318_pool *pool,
|
||||
struct coh901318_lli **lli);
|
||||
|
||||
/**
|
||||
* coh901318_lli_fill_memcpy() - Prepares the lli:s for dma memcpy
|
||||
* @pool: pool handle
|
||||
* @lli: allocated lli
|
||||
* @src: src address
|
||||
* @size: transfer size
|
||||
* @dst: destination address
|
||||
* @ctrl_chained: ctrl for chained lli
|
||||
* @ctrl_last: ctrl for the last lli
|
||||
* returns number of CPU interrupts for the lli, negative on error.
|
||||
*/
|
||||
int
|
||||
coh901318_lli_fill_memcpy(struct coh901318_pool *pool,
|
||||
struct coh901318_lli *lli,
|
||||
dma_addr_t src, unsigned int size,
|
||||
dma_addr_t dst, u32 ctrl_chained, u32 ctrl_last);
|
||||
|
||||
/**
|
||||
* coh901318_lli_fill_single() - Prepares the lli:s for dma single transfer
|
||||
* @pool: pool handle
|
||||
* @lli: allocated lli
|
||||
* @buf: transfer buffer
|
||||
* @size: transfer size
|
||||
* @dev_addr: address of periphal
|
||||
* @ctrl_chained: ctrl for chained lli
|
||||
* @ctrl_last: ctrl for the last lli
|
||||
* @dir: direction of transfer (to or from device)
|
||||
* returns number of CPU interrupts for the lli, negative on error.
|
||||
*/
|
||||
int
|
||||
coh901318_lli_fill_single(struct coh901318_pool *pool,
|
||||
struct coh901318_lli *lli,
|
||||
dma_addr_t buf, unsigned int size,
|
||||
dma_addr_t dev_addr, u32 ctrl_chained, u32 ctrl_last,
|
||||
enum dma_data_direction dir);
|
||||
|
||||
/**
|
||||
* coh901318_lli_fill_single() - Prepares the lli:s for dma scatter list transfer
|
||||
* @pool: pool handle
|
||||
* @lli: allocated lli
|
||||
* @sg: scatter gather list
|
||||
* @nents: number of entries in sg
|
||||
* @dev_addr: address of periphal
|
||||
* @ctrl_chained: ctrl for chained lli
|
||||
* @ctrl: ctrl of middle lli
|
||||
* @ctrl_last: ctrl for the last lli
|
||||
* @dir: direction of transfer (to or from device)
|
||||
* @ctrl_irq_mask: ctrl mask for CPU interrupt
|
||||
* returns number of CPU interrupts for the lli, negative on error.
|
||||
*/
|
||||
int
|
||||
coh901318_lli_fill_sg(struct coh901318_pool *pool,
|
||||
struct coh901318_lli *lli,
|
||||
struct scatterlist *sg, unsigned int nents,
|
||||
dma_addr_t dev_addr, u32 ctrl_chained,
|
||||
u32 ctrl, u32 ctrl_last,
|
||||
enum dma_data_direction dir, u32 ctrl_irq_mask);
|
||||
|
||||
#endif /* COH901318_LLI_H */
|
||||
Loading…
Reference in New Issue