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dt-bindings: display: imx-drm: Add pixel combiner descriptions
Pixel combiner found in i.MX8 SoCs may combine two display streams(one master and the other slave) to drive a high pixel rate display. This patch adds DT property descriptions in imx-drm device tree documentation for pixel combiner. Signed-off-by: Liu Ying <victor.liu@nxp.com>
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@ -133,6 +133,7 @@ Required properties:
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- power-domain-names: power domain names relevant to power-domains phandles.
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- fsl,dpr-channels: phandles to the DPR channels attached to this DPU,
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sorted by memory map addresses.
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- fsl,pixel-combiner: phandle to the pixel combiner unit attached to this DPU.
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Optional properties:
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- port@[0-1]: Port nodes with endpoint definitions as defined in
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Documentation/devicetree/bindings/media/video-interfaces.txt.
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@ -219,6 +220,7 @@ dpu: dpu@56180000 {
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fsl,dpr-channels = <&dc0_dpr1_channel1>, <&dc0_dpr1_channel2>,
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<&dc0_dpr1_channel3>, <&dc0_dpr2_channel1>,
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<&dc0_dpr2_channel2>, <&dc0_dpr2_channel3>;
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fsl,pixel-combiner = <&dc0_pc>;
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dpu_disp0: port@0 {
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reg = <0>;
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@ -251,6 +253,22 @@ dpu: dpu@56180000 {
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};
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};
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Freescale i.MX8 PC (Pixel Combiner)
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=============================================
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Required properties:
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- compatible: should be "fsl,<chip>-pixel-combiner"
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- reg: should be register base and length as documented in the
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datasheet
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- power-domains: phandle pointing to power domain
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example:
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pixel-combiner@56020000 {
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compatible = "fsl,imx8qm-pixel-combiner";
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reg = <0x56020000 0x10000>;
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power-domains = <&pd IMX_SC_R_DC_0>;
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};
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Freescale i.MX8 PRG (Prefetch Resolve Gasket)
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=============================================
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Required properties:
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