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fmd: SDK DPAA 1.x FMan driver 

Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
This commit is contained in:
Madalin Bucur 2017-05-10 16:36:36 +03:00 committed by Dong Aisheng
parent 16ff861424
commit 60bb3db8cf
198 changed files with 115457 additions and 0 deletions
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153
drivers/net/ethernet/freescale/sdk_fman/Kconfig Normal file
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menu "Frame Manager support"
menuconfig FSL_SDK_FMAN
bool "Freescale Frame Manager (datapath) support - SDK driver"
depends on (FSL_SOC || ARM64 || ARM) && FSL_SDK_BMAN && FSL_SDK_QMAN && !FSL_FMAN
default y
---help---
If unsure, say Y.
if FSL_SDK_FMAN
config FSL_SDK_FMAN_TEST
bool "FMan test module"
default n
select FSL_DPAA_HOOKS
---help---
This option compiles test code for FMan.
menu "FMAN Processor support"
choice
depends on FSL_SDK_FMAN
prompt "Processor Type"
config FMAN_ARM
bool "LS1043"
depends on ARM64 || ARM
---help---
Choose "LS1043" for the ARM platforms:
LS1043
config FMAN_P3040_P4080_P5020
bool "P3040 P4080 5020"
config FMAN_P1023
bool "P1023"
config FMAN_V3H
bool "FmanV3H"
---help---
Choose "FmanV3H" for Fman rev3H:
B4860, T4240, T4160, etc
config FMAN_V3L
bool "FmanV3L"
---help---
Choose "FmanV3L" for Fman rev3L:
T1040, T1042, T1020, T1022, T1023, T1024, etc
endchoice
endmenu
config FMAN_MIB_CNT_OVF_IRQ_EN
bool "Enable the dTSEC MIB counters overflow interrupt"
default n
---help---
Enable the dTSEC MIB counters overflow interrupt to get
accurate MIB counters values. Enabled it compensates
for the counters overflow but reduces performance and
triggers error messages in HV setups.
config FSL_FM_MAX_FRAME_SIZE
int "Maximum L2 frame size"
depends on FSL_SDK_FMAN
range 64 9600
default "1522"
help
Configure this in relation to the maximum possible MTU of your
network configuration. In particular, one would need to
increase this value in order to use jumbo frames.
FSL_FM_MAX_FRAME_SIZE must accommodate the Ethernet FCS (4 bytes)
and one ETH+VLAN header (18 bytes), to a total of 22 bytes in
excess of the desired L3 MTU.
Note that having too large a FSL_FM_MAX_FRAME_SIZE (much larger
than the actual MTU) may lead to buffer exhaustion, especially
in the case of badly fragmented datagrams on the Rx path.
Conversely, having a FSL_FM_MAX_FRAME_SIZE smaller than the actual
MTU will lead to frames being dropped.
This can be overridden by specifying "fsl_fm_max_frm" in
the kernel bootargs:
* in Hypervisor-based scenarios, by adding a "chosen" node
with the "bootargs" property specifying
"fsl_fm_max_frm=<YourValue>";
* in non-Hypervisor-based scenarios, via u-boot's env, by
modifying the "bootargs" env variable.
config FSL_FM_RX_EXTRA_HEADROOM
int "Add extra headroom at beginning of data buffers"
depends on FSL_SDK_FMAN
range 16 384
default "64"
help
Configure this to tell the Frame Manager to reserve some extra
space at the beginning of a data buffer on the receive path,
before Internal Context fields are copied. This is in addition
to the private data area already reserved for driver internal
use. The provided value must be a multiple of 16.
This setting can be overridden by specifying
"fsl_fm_rx_extra_headroom" in the kernel bootargs:
* in Hypervisor-based scenarios, by adding a "chosen" node
with the "bootargs" property specifying
"fsl_fm_rx_extra_headroom=<YourValue>";
* in non-Hypervisor-based scenarios, via u-boot's env, by
modifying the "bootargs" env variable.
config FMAN_PFC
bool "FMan PFC support (EXPERIMENTAL)"
depends on ( FMAN_V3H || FMAN_V3L || FMAN_ARM) && FSL_SDK_FMAN
default n
help
This option enables PFC support on FMan v3 ports.
Data Center Bridging defines Classes of Service that are
flow-controlled using PFC pause frames.
if FMAN_PFC
config FMAN_PFC_COS_COUNT
int "Number of PFC Classes of Service"
depends on FMAN_PFC && FSL_SDK_FMAN
range 1 4
default "3"
help
The number of Classes of Service controlled by PFC.
config FMAN_PFC_QUANTA_0
int "The pause quanta for PFC CoS 0"
depends on FMAN_PFC && FSL_SDK_FMAN
range 0 65535
default "65535"
config FMAN_PFC_QUANTA_1
int "The pause quanta for PFC CoS 1"
depends on FMAN_PFC && FSL_SDK_FMAN
range 0 65535
default "65535"
config FMAN_PFC_QUANTA_2
int "The pause quanta for PFC CoS 2"
depends on FMAN_PFC && FSL_SDK_FMAN
range 0 65535
default "65535"
config FMAN_PFC_QUANTA_3
int "The pause quanta for PFC CoS 3"
depends on FMAN_PFC && FSL_SDK_FMAN
range 0 65535
default "65535"
endif
endif # FSL_SDK_FMAN
endmenu

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drivers/net/ethernet/freescale/sdk_fman/Makefile Normal file
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#
# Makefile for the Freescale Ethernet controllers
#
ccflags-y += -DVERSION=\"\"
#
#Include netcomm SW specific definitions
include $(srctree)/drivers/net/ethernet/freescale/sdk_fman/ncsw_config.mk
#
obj-y += etc/
obj-y += Peripherals/FM/
obj-y += src/

15
drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/HC/Makefile Normal file
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#
# Makefile for the Freescale Ethernet controllers
#
ccflags-y += -DVERSION=\"\"
#
#Include netcomm SW specific definitions
include $(srctree)/drivers/net/ethernet/freescale/sdk_fman/ncsw_config.mk
NCSW_FM_INC = $(srctree)/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/inc
ccflags-y += -I$(NCSW_FM_INC)
obj-y += fsl-ncsw-Hc.o
fsl-ncsw-Hc-objs := hc.o

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drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/HC/hc.c Normal file
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drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/Makefile Normal file
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#
# Makefile for the Freescale Ethernet controllers
#
ccflags-y += -DVERSION=\"\"
#
#Include netcomm SW specific definitions
include $(srctree)/drivers/net/ethernet/freescale/sdk_fman/ncsw_config.mk
NCSW_FM_INC = $(srctree)/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/inc
ccflags-y += -I$(NCSW_FM_INC)
obj-y += fsl-ncsw-MAC.o
fsl-ncsw-MAC-objs := dtsec.o dtsec_mii_acc.o fm_mac.o tgec.o tgec_mii_acc.o \
fman_dtsec.o fman_dtsec_mii_acc.o fman_memac.o \
fman_tgec.o fman_crc32.o
ifeq ($(CONFIG_FMAN_V3H),y)
fsl-ncsw-MAC-objs += memac.o memac_mii_acc.o fman_memac_mii_acc.o
endif
ifeq ($(CONFIG_FMAN_V3L),y)
fsl-ncsw-MAC-objs += memac.o memac_mii_acc.o fman_memac_mii_acc.o
endif
ifeq ($(CONFIG_FMAN_ARM),y)
fsl-ncsw-MAC-objs += memac.o memac_mii_acc.o fman_memac_mii_acc.o
endif

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drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/dtsec.c Normal file
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228
drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/dtsec.h Normal file
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/*
* Copyright 2008-2013 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File dtsec.h
@Description FM dTSEC ...
*//***************************************************************************/
#ifndef __DTSEC_H
#define __DTSEC_H
#include "std_ext.h"
#include "error_ext.h"
#include "list_ext.h"
#include "enet_ext.h"
#include "dtsec_mii_acc.h"
#include "fm_mac.h"
#define DEFAULT_exceptions \
((uint32_t)(DTSEC_IMASK_BREN | \
DTSEC_IMASK_RXCEN | \
DTSEC_IMASK_BTEN | \
DTSEC_IMASK_TXCEN | \
DTSEC_IMASK_TXEEN | \
DTSEC_IMASK_ABRTEN | \
DTSEC_IMASK_LCEN | \
DTSEC_IMASK_CRLEN | \
DTSEC_IMASK_XFUNEN | \
DTSEC_IMASK_IFERREN | \
DTSEC_IMASK_MAGEN | \
DTSEC_IMASK_TDPEEN | \
DTSEC_IMASK_RDPEEN))
#define GET_EXCEPTION_FLAG(bitMask, exception) switch (exception){ \
case e_FM_MAC_EX_1G_BAB_RX: \
bitMask = DTSEC_IMASK_BREN; break; \
case e_FM_MAC_EX_1G_RX_CTL: \
bitMask = DTSEC_IMASK_RXCEN; break; \
case e_FM_MAC_EX_1G_GRATEFUL_TX_STP_COMPLET: \
bitMask = DTSEC_IMASK_GTSCEN ; break; \
case e_FM_MAC_EX_1G_BAB_TX: \
bitMask = DTSEC_IMASK_BTEN ; break; \
case e_FM_MAC_EX_1G_TX_CTL: \
bitMask = DTSEC_IMASK_TXCEN ; break; \
case e_FM_MAC_EX_1G_TX_ERR: \
bitMask = DTSEC_IMASK_TXEEN ; break; \
case e_FM_MAC_EX_1G_LATE_COL: \
bitMask = DTSEC_IMASK_LCEN ; break; \
case e_FM_MAC_EX_1G_COL_RET_LMT: \
bitMask = DTSEC_IMASK_CRLEN ; break; \
case e_FM_MAC_EX_1G_TX_FIFO_UNDRN: \
bitMask = DTSEC_IMASK_XFUNEN ; break; \
case e_FM_MAC_EX_1G_MAG_PCKT: \
bitMask = DTSEC_IMASK_MAGEN ; break; \
case e_FM_MAC_EX_1G_MII_MNG_RD_COMPLET: \
bitMask = DTSEC_IMASK_MMRDEN; break; \
case e_FM_MAC_EX_1G_MII_MNG_WR_COMPLET: \
bitMask = DTSEC_IMASK_MMWREN ; break; \
case e_FM_MAC_EX_1G_GRATEFUL_RX_STP_COMPLET: \
bitMask = DTSEC_IMASK_GRSCEN; break; \
case e_FM_MAC_EX_1G_TX_DATA_ERR: \
bitMask = DTSEC_IMASK_TDPEEN; break; \
case e_FM_MAC_EX_1G_RX_MIB_CNT_OVFL: \
bitMask = DTSEC_IMASK_MSROEN ; break; \
default: bitMask = 0;break;}
#define MAX_PACKET_ALIGNMENT 31
#define MAX_INTER_PACKET_GAP 0x7f
#define MAX_INTER_PALTERNATE_BEB 0x0f
#define MAX_RETRANSMISSION 0x0f
#define MAX_COLLISION_WINDOW 0x03ff
/********************* From mac ext ******************************************/
typedef uint32_t t_ErrorDisable;
#define ERROR_DISABLE_TRANSMIT 0x00400000
#define ERROR_DISABLE_LATE_COLLISION 0x00040000
#define ERROR_DISABLE_COLLISION_RETRY_LIMIT 0x00020000
#define ERROR_DISABLE_TxFIFO_UNDERRUN 0x00010000
#define ERROR_DISABLE_TxABORT 0x00008000
#define ERROR_DISABLE_INTERFACE 0x00004000
#define ERROR_DISABLE_TxDATA_PARITY 0x00000002
#define ERROR_DISABLE_RxDATA_PARITY 0x00000001
/*****************************************************************************/
#define DTSEC_NUM_OF_PADDRS 15 /* number of pattern match registers (entries) */
#define GROUP_ADDRESS 0x0000010000000000LL /* Group address bit indication */
#define HASH_TABLE_SIZE 256 /* Hash table size (= 32 bits * 8 regs) */
#define HASH_TABLE_SIZE 256 /* Hash table size (32 bits * 8 regs) */
#define EXTENDED_HASH_TABLE_SIZE 512 /* Extended Hash table size (32 bits * 16 regs) */
#define DTSEC_TO_MII_OFFSET 0x1000 /* number of pattern match registers (entries) */
#define MAX_PHYS 32 /* maximum number of phys */
#define VAL32BIT 0x100000000LL
#define VAL22BIT 0x00400000
#define VAL16BIT 0x00010000
#define VAL12BIT 0x00001000
/* CAR1/2 bits */
#define CAR1_TR64 0x80000000
#define CAR1_TR127 0x40000000
#define CAR1_TR255 0x20000000
#define CAR1_TR511 0x10000000
#define CAR1_TRK1 0x08000000
#define CAR1_TRMAX 0x04000000
#define CAR1_TRMGV 0x02000000
#define CAR1_RBYT 0x00010000
#define CAR1_RPKT 0x00008000
#define CAR1_RMCA 0x00002000
#define CAR1_RBCA 0x00001000
#define CAR1_RXPF 0x00000400
#define CAR1_RALN 0x00000100
#define CAR1_RFLR 0x00000080
#define CAR1_RCDE 0x00000040
#define CAR1_RCSE 0x00000020
#define CAR1_RUND 0x00000010
#define CAR1_ROVR 0x00000008
#define CAR1_RFRG 0x00000004
#define CAR1_RJBR 0x00000002
#define CAR1_RDRP 0x00000001
#define CAR2_TFCS 0x00040000
#define CAR2_TBYT 0x00002000
#define CAR2_TPKT 0x00001000
#define CAR2_TMCA 0x00000800
#define CAR2_TBCA 0x00000400
#define CAR2_TXPF 0x00000200
#define CAR2_TDRP 0x00000001
typedef struct t_InternalStatistics
{
uint64_t tr64;
uint64_t tr127;
uint64_t tr255;
uint64_t tr511;
uint64_t tr1k;
uint64_t trmax;
uint64_t trmgv;
uint64_t rfrg;
uint64_t rjbr;
uint64_t rdrp;
uint64_t raln;
uint64_t rund;
uint64_t rovr;
uint64_t rxpf;
uint64_t txpf;
uint64_t rbyt;
uint64_t rpkt;
uint64_t rmca;
uint64_t rbca;
uint64_t rflr;
uint64_t rcde;
uint64_t rcse;
uint64_t tbyt;
uint64_t tpkt;
uint64_t tmca;
uint64_t tbca;
uint64_t tdrp;
uint64_t tfcs;
} t_InternalStatistics;
typedef struct {
t_FmMacControllerDriver fmMacControllerDriver;
t_Handle h_App; /**< Handle to the upper layer application */
struct dtsec_regs *p_MemMap; /**< pointer to dTSEC memory mapped registers. */
struct dtsec_mii_reg *p_MiiMemMap; /**< pointer to dTSEC MII memory mapped registers. */
uint64_t addr; /**< MAC address of device; */
e_EnetMode enetMode; /**< Ethernet physical interface */
t_FmMacExceptionCallback *f_Exception;
int mdioIrq;
t_FmMacExceptionCallback *f_Event;
bool indAddrRegUsed[DTSEC_NUM_OF_PADDRS]; /**< Whether a particular individual address recognition register is being used */
uint64_t paddr[DTSEC_NUM_OF_PADDRS]; /**< MAC address for particular individual address recognition register */
uint8_t numOfIndAddrInRegs; /**< Number of individual addresses in registers for this station. */
bool halfDuplex;
t_InternalStatistics internalStatistics;
t_EthHash *p_MulticastAddrHash; /* pointer to driver's global address hash table */
t_EthHash *p_UnicastAddrHash; /* pointer to driver's individual address hash table */
uint8_t macId;
uint8_t tbi_phy_addr;
uint32_t exceptions;
bool ptpTsuEnabled;
bool enTsuErrExeption;
e_FmMacStatisticsLevel statisticsLevel;
struct dtsec_cfg *p_DtsecDriverParam;
} t_Dtsec;
#endif /* __DTSEC_H */

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drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/dtsec_mii_acc.c Normal file
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/*
* Copyright 2008-2013 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File dtsec_mii_acc.c
@Description FM dtsec MII register access MAC ...
*//***************************************************************************/
#include "error_ext.h"
#include "std_ext.h"
#include "fm_mac.h"
#include "dtsec.h"
#include "fsl_fman_dtsec_mii_acc.h"
/*****************************************************************************/
t_Error DTSEC_MII_WritePhyReg(t_Handle h_Dtsec,
uint8_t phyAddr,
uint8_t reg,
uint16_t data)
{
t_Dtsec *p_Dtsec = (t_Dtsec *)h_Dtsec;
struct dtsec_mii_reg *miiregs;
uint16_t dtsec_freq;
t_Error err;
SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_Dtsec->p_MiiMemMap, E_INVALID_HANDLE);
dtsec_freq = (uint16_t)(p_Dtsec->fmMacControllerDriver.clkFreq >> 1);
miiregs = p_Dtsec->p_MiiMemMap;
err = (t_Error)fman_dtsec_mii_write_reg(miiregs, phyAddr, reg, data, dtsec_freq);
return err;
}
/*****************************************************************************/
t_Error DTSEC_MII_ReadPhyReg(t_Handle h_Dtsec,
uint8_t phyAddr,
uint8_t reg,
uint16_t *p_Data)
{
t_Dtsec *p_Dtsec = (t_Dtsec *)h_Dtsec;
struct dtsec_mii_reg *miiregs;
uint16_t dtsec_freq;
t_Error err;
SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_Dtsec->p_MiiMemMap, E_INVALID_HANDLE);
dtsec_freq = (uint16_t)(p_Dtsec->fmMacControllerDriver.clkFreq >> 1);
miiregs = p_Dtsec->p_MiiMemMap;
err = fman_dtsec_mii_read_reg(miiregs, phyAddr, reg, p_Data, dtsec_freq);
if (*p_Data == 0xffff)
RETURN_ERROR(MINOR, E_NO_DEVICE,
("Read wrong data (0xffff): phyAddr 0x%x, reg 0x%x",
phyAddr, reg));
if (err)
RETURN_ERROR(MINOR, (t_Error)err, NO_MSG);
return E_OK;
}

42
drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/dtsec_mii_acc.h Normal file
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/*
* Copyright 2008-2013 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __DTSEC_MII_ACC_H
#define __DTSEC_MII_ACC_H
#include "std_ext.h"
t_Error DTSEC_MII_WritePhyReg(t_Handle h_Dtsec, uint8_t phyAddr, uint8_t reg, uint16_t data);
t_Error DTSEC_MII_ReadPhyReg(t_Handle h_Dtsec, uint8_t phyAddr, uint8_t reg, uint16_t *p_Data);
#endif /* __DTSEC_MII_ACC_H */

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/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_mac.c
@Description FM MAC ...
*//***************************************************************************/
#include "std_ext.h"
#include "string_ext.h"
#include "sprint_ext.h"
#include "error_ext.h"
#include "fm_ext.h"
#include "fm_common.h"
#include "fm_mac.h"
/* ......................................................................... */
t_Handle FM_MAC_Config (t_FmMacParams *p_FmMacParam)
{
t_FmMacControllerDriver *p_FmMacControllerDriver;
uint16_t fmClkFreq;
SANITY_CHECK_RETURN_VALUE(p_FmMacParam, E_INVALID_HANDLE, NULL);
fmClkFreq = FmGetClockFreq(p_FmMacParam->h_Fm);
if (fmClkFreq == 0)
{
REPORT_ERROR(MAJOR, E_INVALID_STATE, ("Can't get clock for MAC!"));
return NULL;
}
#if (DPAA_VERSION == 10)
if (ENET_SPEED_FROM_MODE(p_FmMacParam->enetMode) < e_ENET_SPEED_10000)
p_FmMacControllerDriver = (t_FmMacControllerDriver *)DTSEC_Config(p_FmMacParam);
else
#if FM_MAX_NUM_OF_10G_MACS > 0
p_FmMacControllerDriver = (t_FmMacControllerDriver *)TGEC_Config(p_FmMacParam);
#else
p_FmMacControllerDriver = NULL;
#endif /* FM_MAX_NUM_OF_10G_MACS > 0 */
#else
p_FmMacControllerDriver = (t_FmMacControllerDriver *)MEMAC_Config(p_FmMacParam);
#endif /* (DPAA_VERSION == 10) */
if (!p_FmMacControllerDriver)
return NULL;
p_FmMacControllerDriver->h_Fm = p_FmMacParam->h_Fm;
p_FmMacControllerDriver->enetMode = p_FmMacParam->enetMode;
p_FmMacControllerDriver->macId = p_FmMacParam->macId;
p_FmMacControllerDriver->resetOnInit = DEFAULT_resetOnInit;
p_FmMacControllerDriver->clkFreq = fmClkFreq;
return (t_Handle)p_FmMacControllerDriver;
}
/* ......................................................................... */
t_Error FM_MAC_Init (t_Handle h_FmMac)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->resetOnInit &&
!p_FmMacControllerDriver->f_FM_MAC_ConfigResetOnInit &&
(FmResetMac(p_FmMacControllerDriver->h_Fm,
((ENET_INTERFACE_FROM_MODE(p_FmMacControllerDriver->enetMode) == e_ENET_IF_XGMII) ?
e_FM_MAC_10G : e_FM_MAC_1G),
p_FmMacControllerDriver->macId) != E_OK))
RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Can't reset MAC!"));
if (p_FmMacControllerDriver->f_FM_MAC_Init)
return p_FmMacControllerDriver->f_FM_MAC_Init(h_FmMac);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ......................................................................... */
t_Error FM_MAC_Free (t_Handle h_FmMac)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_Free)
return p_FmMacControllerDriver->f_FM_MAC_Free(h_FmMac);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ......................................................................... */
t_Error FM_MAC_ConfigResetOnInit (t_Handle h_FmMac, bool enable)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_ConfigResetOnInit)
return p_FmMacControllerDriver->f_FM_MAC_ConfigResetOnInit(h_FmMac, enable);
p_FmMacControllerDriver->resetOnInit = enable;
return E_OK;
}
/* ......................................................................... */
t_Error FM_MAC_ConfigLoopback (t_Handle h_FmMac, bool newVal)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_ConfigLoopback)
return p_FmMacControllerDriver->f_FM_MAC_ConfigLoopback(h_FmMac, newVal);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ......................................................................... */
t_Error FM_MAC_ConfigMaxFrameLength (t_Handle h_FmMac, uint16_t newVal)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_ConfigMaxFrameLength)
return p_FmMacControllerDriver->f_FM_MAC_ConfigMaxFrameLength(h_FmMac, newVal);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ......................................................................... */
t_Error FM_MAC_ConfigWan (t_Handle h_FmMac, bool flag)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_ConfigWan)
return p_FmMacControllerDriver->f_FM_MAC_ConfigWan(h_FmMac, flag);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ......................................................................... */
t_Error FM_MAC_ConfigPadAndCrc (t_Handle h_FmMac, bool newVal)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_ConfigPadAndCrc)
return p_FmMacControllerDriver->f_FM_MAC_ConfigPadAndCrc(h_FmMac, newVal);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ......................................................................... */
t_Error FM_MAC_ConfigHalfDuplex (t_Handle h_FmMac, bool newVal)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_ConfigHalfDuplex)
return p_FmMacControllerDriver->f_FM_MAC_ConfigHalfDuplex(h_FmMac,newVal);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ......................................................................... */
t_Error FM_MAC_ConfigTbiPhyAddr (t_Handle h_FmMac, uint8_t newVal)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_ConfigTbiPhyAddr)
return p_FmMacControllerDriver->f_FM_MAC_ConfigTbiPhyAddr(h_FmMac,newVal);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ......................................................................... */
t_Error FM_MAC_ConfigLengthCheck (t_Handle h_FmMac, bool newVal)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_ConfigLengthCheck)
return p_FmMacControllerDriver->f_FM_MAC_ConfigLengthCheck(h_FmMac,newVal);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ......................................................................... */
t_Error FM_MAC_ConfigException (t_Handle h_FmMac, e_FmMacExceptions ex, bool enable)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_ConfigException)
return p_FmMacControllerDriver->f_FM_MAC_ConfigException(h_FmMac, ex, enable);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
#ifdef FM_TX_ECC_FRMS_ERRATA_10GMAC_A004
/* ......................................................................... */
t_Error FM_MAC_ConfigSkipFman11Workaround (t_Handle h_FmMac)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_ConfigSkipFman11Workaround)
return p_FmMacControllerDriver->f_FM_MAC_ConfigSkipFman11Workaround(h_FmMac);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
#endif /* FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 */
/*****************************************************************************/
/* Run Time Control */
/*****************************************************************************/
/* ......................................................................... */
t_Error FM_MAC_Enable (t_Handle h_FmMac, e_CommMode mode)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_Enable)
return p_FmMacControllerDriver->f_FM_MAC_Enable(h_FmMac, mode);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ......................................................................... */
t_Error FM_MAC_Disable (t_Handle h_FmMac, e_CommMode mode)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_Disable)
return p_FmMacControllerDriver->f_FM_MAC_Disable(h_FmMac, mode);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
t_Error FM_MAC_Resume (t_Handle h_FmMac)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_Resume)
return p_FmMacControllerDriver->f_FM_MAC_Resume(h_FmMac);
return E_OK;
}
/* ......................................................................... */
t_Error FM_MAC_Enable1588TimeStamp (t_Handle h_FmMac)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_Enable1588TimeStamp)
return p_FmMacControllerDriver->f_FM_MAC_Enable1588TimeStamp(h_FmMac);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ......................................................................... */
t_Error FM_MAC_Disable1588TimeStamp (t_Handle h_FmMac)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_Disable1588TimeStamp)
return p_FmMacControllerDriver->f_FM_MAC_Disable1588TimeStamp(h_FmMac);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ......................................................................... */
t_Error FM_MAC_SetTxAutoPauseFrames(t_Handle h_FmMac,
uint16_t pauseTime)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_SetTxAutoPauseFrames)
return p_FmMacControllerDriver->f_FM_MAC_SetTxAutoPauseFrames(h_FmMac,
pauseTime);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ......................................................................... */
t_Error FM_MAC_SetTxPauseFrames(t_Handle h_FmMac,
uint8_t priority,
uint16_t pauseTime,
uint16_t threshTime)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_SetTxPauseFrames)
return p_FmMacControllerDriver->f_FM_MAC_SetTxPauseFrames(h_FmMac,
priority,
pauseTime,
threshTime);
RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ......................................................................... */
t_Error FM_MAC_SetRxIgnorePauseFrames (t_Handle h_FmMac, bool en)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_SetRxIgnorePauseFrames)
return p_FmMacControllerDriver->f_FM_MAC_SetRxIgnorePauseFrames(h_FmMac, en);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ......................................................................... */
t_Error FM_MAC_SetWakeOnLan (t_Handle h_FmMac, bool en)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_SetWakeOnLan)
return p_FmMacControllerDriver->f_FM_MAC_SetWakeOnLan(h_FmMac, en);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ......................................................................... */
t_Error FM_MAC_ResetCounters (t_Handle h_FmMac)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_ResetCounters)
return p_FmMacControllerDriver->f_FM_MAC_ResetCounters(h_FmMac);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ......................................................................... */
t_Error FM_MAC_SetException(t_Handle h_FmMac, e_FmMacExceptions ex, bool enable)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_SetException)
return p_FmMacControllerDriver->f_FM_MAC_SetException(h_FmMac, ex, enable);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ......................................................................... */
t_Error FM_MAC_SetStatistics (t_Handle h_FmMac, e_FmMacStatisticsLevel statisticsLevel)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_SetStatistics)
return p_FmMacControllerDriver->f_FM_MAC_SetStatistics(h_FmMac, statisticsLevel);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ......................................................................... */
t_Error FM_MAC_GetStatistics (t_Handle h_FmMac, t_FmMacStatistics *p_Statistics)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_GetStatistics)
return p_FmMacControllerDriver->f_FM_MAC_GetStatistics(h_FmMac, p_Statistics);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ......................................................................... */
t_Error FM_MAC_ModifyMacAddr (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_ModifyMacAddr)
return p_FmMacControllerDriver->f_FM_MAC_ModifyMacAddr(h_FmMac, p_EnetAddr);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ......................................................................... */
t_Error FM_MAC_AddHashMacAddr (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_AddHashMacAddr)
return p_FmMacControllerDriver->f_FM_MAC_AddHashMacAddr(h_FmMac, p_EnetAddr);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ......................................................................... */
t_Error FM_MAC_RemoveHashMacAddr (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_RemoveHashMacAddr)
return p_FmMacControllerDriver->f_FM_MAC_RemoveHashMacAddr(h_FmMac, p_EnetAddr);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ......................................................................... */
t_Error FM_MAC_AddExactMatchMacAddr (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_AddExactMatchMacAddr)
return p_FmMacControllerDriver->f_FM_MAC_AddExactMatchMacAddr(h_FmMac, p_EnetAddr);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ......................................................................... */
t_Error FM_MAC_RemovelExactMatchMacAddr (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_RemovelExactMatchMacAddr)
return p_FmMacControllerDriver->f_FM_MAC_RemovelExactMatchMacAddr(h_FmMac, p_EnetAddr);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ......................................................................... */
t_Error FM_MAC_GetVesrion (t_Handle h_FmMac, uint32_t *macVresion)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_GetVersion)
return p_FmMacControllerDriver->f_FM_MAC_GetVersion(h_FmMac, macVresion);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ......................................................................... */
t_Error FM_MAC_GetId (t_Handle h_FmMac, uint32_t *macId)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_GetId)
return p_FmMacControllerDriver->f_FM_MAC_GetId(h_FmMac, macId);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ......................................................................... */
t_Error FM_MAC_SetPromiscuous (t_Handle h_FmMac, bool newVal)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_SetPromiscuous)
return p_FmMacControllerDriver->f_FM_MAC_SetPromiscuous(h_FmMac, newVal);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ......................................................................... */
t_Error FM_MAC_AdjustLink(t_Handle h_FmMac, e_EnetSpeed speed, bool fullDuplex)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_AdjustLink)
return p_FmMacControllerDriver->f_FM_MAC_AdjustLink(h_FmMac, speed, fullDuplex);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ......................................................................... */
t_Error FM_MAC_RestartAutoneg(t_Handle h_FmMac)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_RestartAutoneg)
return p_FmMacControllerDriver->f_FM_MAC_RestartAutoneg(h_FmMac);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ......................................................................... */
t_Error FM_MAC_MII_WritePhyReg (t_Handle h_FmMac, uint8_t phyAddr, uint8_t reg, uint16_t data)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_MII_WritePhyReg)
return p_FmMacControllerDriver->f_FM_MAC_MII_WritePhyReg(h_FmMac, phyAddr, reg, data);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ......................................................................... */
t_Error FM_MAC_MII_ReadPhyReg(t_Handle h_FmMac, uint8_t phyAddr, uint8_t reg, uint16_t *p_Data)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_MII_ReadPhyReg)
return p_FmMacControllerDriver->f_FM_MAC_MII_ReadPhyReg(h_FmMac, phyAddr, reg, p_Data);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ......................................................................... */
uint16_t FM_MAC_GetMaxFrameLength(t_Handle h_FmMac)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_VALUE(p_FmMacControllerDriver, E_INVALID_HANDLE, 0);
if (p_FmMacControllerDriver->f_FM_MAC_GetMaxFrameLength)
return p_FmMacControllerDriver->f_FM_MAC_GetMaxFrameLength(h_FmMac);
REPORT_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
return 0;
}
#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0))
/*****************************************************************************/
t_Error FM_MAC_DumpRegs(t_Handle h_FmMac)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_DumpRegs)
return p_FmMacControllerDriver->f_FM_MAC_DumpRegs(h_FmMac);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
#endif /* (defined(DEBUG_ERRORS) && ... */

225
drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fm_mac.h Normal file
View File

@ -0,0 +1,225 @@
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_mac.h
@Description FM MAC ...
*//***************************************************************************/
#ifndef __FM_MAC_H
#define __FM_MAC_H
#include "std_ext.h"
#include "error_ext.h"
#include "list_ext.h"
#include "fm_mac_ext.h"
#include "fm_common.h"
#define __ERR_MODULE__ MODULE_FM_MAC
/**************************************************************************//**
@Description defaults
*//***************************************************************************/
#define DEFAULT_halfDuplex FALSE
#define DEFAULT_padAndCrcEnable TRUE
#define DEFAULT_resetOnInit FALSE
typedef struct {
uint64_t addr; /* Ethernet Address */
t_List node;
} t_EthHashEntry;
#define ETH_HASH_ENTRY_OBJ(ptr) LIST_OBJECT(ptr, t_EthHashEntry, node)
typedef struct {
uint16_t size;
t_List *p_Lsts;
} t_EthHash;
typedef struct {
t_Error (*f_FM_MAC_Init) (t_Handle h_FmMac);
t_Error (*f_FM_MAC_Free) (t_Handle h_FmMac);
t_Error (*f_FM_MAC_SetStatistics) (t_Handle h_FmMac, e_FmMacStatisticsLevel statisticsLevel);
t_Error (*f_FM_MAC_ConfigLoopback) (t_Handle h_FmMac, bool newVal);
t_Error (*f_FM_MAC_ConfigMaxFrameLength) (t_Handle h_FmMac, uint16_t newVal);
t_Error (*f_FM_MAC_ConfigWan) (t_Handle h_FmMac, bool flag);
t_Error (*f_FM_MAC_ConfigPadAndCrc) (t_Handle h_FmMac, bool newVal);
t_Error (*f_FM_MAC_ConfigHalfDuplex) (t_Handle h_FmMac, bool newVal);
t_Error (*f_FM_MAC_ConfigLengthCheck) (t_Handle h_FmMac, bool newVal);
t_Error (*f_FM_MAC_ConfigTbiPhyAddr) (t_Handle h_FmMac, uint8_t newVal);
t_Error (*f_FM_MAC_ConfigException) (t_Handle h_FmMac, e_FmMacExceptions, bool enable);
t_Error (*f_FM_MAC_ConfigResetOnInit) (t_Handle h_FmMac, bool enable);
#ifdef FM_TX_ECC_FRMS_ERRATA_10GMAC_A004
t_Error (*f_FM_MAC_ConfigSkipFman11Workaround) (t_Handle h_FmMac);
#endif /* FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 */
t_Error (*f_FM_MAC_SetException) (t_Handle h_FmMac, e_FmMacExceptions ex, bool enable);
t_Error (*f_FM_MAC_Enable) (t_Handle h_FmMac, e_CommMode mode);
t_Error (*f_FM_MAC_Disable) (t_Handle h_FmMac, e_CommMode mode);
t_Error (*f_FM_MAC_Resume) (t_Handle h_FmMac);
t_Error (*f_FM_MAC_Enable1588TimeStamp) (t_Handle h_FmMac);
t_Error (*f_FM_MAC_Disable1588TimeStamp) (t_Handle h_FmMac);
t_Error (*f_FM_MAC_Reset) (t_Handle h_FmMac, bool wait);
t_Error (*f_FM_MAC_SetTxAutoPauseFrames) (t_Handle h_FmMac,
uint16_t pauseTime);
t_Error (*f_FM_MAC_SetTxPauseFrames) (t_Handle h_FmMac,
uint8_t priority,
uint16_t pauseTime,
uint16_t threshTime);
t_Error (*f_FM_MAC_SetRxIgnorePauseFrames) (t_Handle h_FmMac, bool en);
t_Error (*f_FM_MAC_ResetCounters) (t_Handle h_FmMac);
t_Error (*f_FM_MAC_GetStatistics) (t_Handle h_FmMac, t_FmMacStatistics *p_Statistics);
t_Error (*f_FM_MAC_ModifyMacAddr) (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr);
t_Error (*f_FM_MAC_AddHashMacAddr) (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr);
t_Error (*f_FM_MAC_RemoveHashMacAddr) (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr);
t_Error (*f_FM_MAC_AddExactMatchMacAddr) (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr);
t_Error (*f_FM_MAC_RemovelExactMatchMacAddr) (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr);
t_Error (*f_FM_MAC_SetPromiscuous) (t_Handle h_FmMac, bool newVal);
t_Error (*f_FM_MAC_AdjustLink) (t_Handle h_FmMac, e_EnetSpeed speed, bool fullDuplex);
t_Error (*f_FM_MAC_RestartAutoneg) (t_Handle h_FmMac);
t_Error (*f_FM_MAC_SetWakeOnLan) (t_Handle h_FmMac, bool en);
t_Error (*f_FM_MAC_GetId) (t_Handle h_FmMac, uint32_t *macId);
t_Error (*f_FM_MAC_GetVersion) (t_Handle h_FmMac, uint32_t *macVersion);
uint16_t (*f_FM_MAC_GetMaxFrameLength) (t_Handle h_FmMac);
t_Error (*f_FM_MAC_MII_WritePhyReg)(t_Handle h_FmMac, uint8_t phyAddr, uint8_t reg, uint16_t data);
t_Error (*f_FM_MAC_MII_ReadPhyReg)(t_Handle h_FmMac, uint8_t phyAddr, uint8_t reg, uint16_t *p_Data);
#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0))
t_Error (*f_FM_MAC_DumpRegs) (t_Handle h_FmMac);
#endif /* (defined(DEBUG_ERRORS) && ... */
t_Handle h_Fm;
t_FmRevisionInfo fmRevInfo;
e_EnetMode enetMode;
uint8_t macId;
bool resetOnInit;
uint16_t clkFreq;
} t_FmMacControllerDriver;
#if (DPAA_VERSION == 10)
t_Handle DTSEC_Config(t_FmMacParams *p_FmMacParam);
t_Handle TGEC_Config(t_FmMacParams *p_FmMacParams);
#else
t_Handle MEMAC_Config(t_FmMacParams *p_FmMacParam);
#endif /* (DPAA_VERSION == 10) */
uint16_t FM_MAC_GetMaxFrameLength(t_Handle FmMac);
/* ........................................................................... */
static __inline__ t_EthHashEntry *DequeueAddrFromHashEntry(t_List *p_AddrLst)
{
t_EthHashEntry *p_HashEntry = NULL;
if (!LIST_IsEmpty(p_AddrLst))
{
p_HashEntry = ETH_HASH_ENTRY_OBJ(p_AddrLst->p_Next);
LIST_DelAndInit(&p_HashEntry->node);
}
return p_HashEntry;
}
/* ........................................................................... */
static __inline__ void FreeHashTable(t_EthHash *p_Hash)
{
t_EthHashEntry *p_HashEntry;
int i = 0;
if (p_Hash)
{
if (p_Hash->p_Lsts)
{
for (i=0; i<p_Hash->size; i++)
{
p_HashEntry = DequeueAddrFromHashEntry(&p_Hash->p_Lsts[i]);
while (p_HashEntry)
{
XX_Free(p_HashEntry);
p_HashEntry = DequeueAddrFromHashEntry(&p_Hash->p_Lsts[i]);
}
}
XX_Free(p_Hash->p_Lsts);
}
XX_Free(p_Hash);
}
}
/* ........................................................................... */
static __inline__ t_EthHash * AllocHashTable(uint16_t size)
{
uint32_t i;
t_EthHash *p_Hash;
/* Allocate address hash table */
p_Hash = (t_EthHash *)XX_Malloc(sizeof(t_EthHash));
if (!p_Hash)
{
REPORT_ERROR(MAJOR, E_NO_MEMORY, ("Address hash table"));
return NULL;
}
p_Hash->size = size;
p_Hash->p_Lsts = (t_List *)XX_Malloc(p_Hash->size*sizeof(t_List));
if (!p_Hash->p_Lsts)
{
REPORT_ERROR(MAJOR, E_NO_MEMORY, ("Address hash table"));
XX_Free(p_Hash);
return NULL;
}
for (i=0 ; i<p_Hash->size; i++)
INIT_LIST(&p_Hash->p_Lsts[i]);
return p_Hash;
}
#endif /* __FM_MAC_H */

119
drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fman_crc32.c Normal file
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/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fman_crc32.h"
#include "common/general.h"
/* precomputed CRC values for address hashing */
static const uint32_t crc_tbl[256] = {
0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f,
0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988,
0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, 0x1db71064, 0x6ab020f2,
0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,
0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9,
0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172,
0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, 0x35b5a8fa, 0x42b2986c,
0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,
0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423,
0xcfba9599, 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924,
0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190, 0x01db7106,
0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433,
0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d,
0x91646c97, 0xe6635c01, 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e,
0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950,
0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,
0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7,
0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0,
0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa,
0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,
0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81,
0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a,
0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, 0xe3630b12, 0x94643b84,
0x0d6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1,
0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb,
0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc,
0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, 0xd6d6a3e8, 0xa1d1937e,
0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,
0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55,
0x316e8eef, 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236,
0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe, 0xb2bd0b28,
0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,
0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, 0x9c0906a9, 0xeb0e363f,
0x72076785, 0x05005713, 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38,
0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242,
0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,
0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69,
0x616bffd3, 0x166ccf45, 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2,
0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc,
0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,
0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693,
0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94,
0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d
};
/* Get the mirrored value of a byte size number. (0x11010011 --> 0x11001011) */
static inline uint8_t get_mirror8(uint8_t n)
{
uint8_t mirror[16] = {
0x00, 0x08, 0x04, 0x0c, 0x02, 0x0a, 0x06, 0x0e,
0x01, 0x09, 0x05, 0x0d, 0x03, 0x0b, 0x07, 0x0f
};
return (uint8_t)(((mirror[n & 0x0f] << 4) | (mirror[n >> 4])));
}
static inline uint32_t get_mirror32(uint32_t n)
{
return ((uint32_t)get_mirror8((uint8_t)(n))<<24) |
((uint32_t)get_mirror8((uint8_t)(n>>8))<<16) |
((uint32_t)get_mirror8((uint8_t)(n>>16))<<8) |
((uint32_t)get_mirror8((uint8_t)(n>>24)));
}
uint32_t get_mac_addr_crc(uint64_t _addr)
{
uint32_t i;
uint8_t data;
uint32_t crc;
/* CRC calculation */
crc = 0xffffffff;
for (i = 0; i < 6; i++) {
data = (uint8_t)(_addr >> ((5-i)*8));
crc = crc ^ data;
crc = crc_tbl[crc&0xff] ^ (crc>>8);
}
crc = get_mirror32(crc);
return crc;
}

43
drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fman_crc32.h Normal file
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/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __FMAN_CRC32_H
#define __FMAN_CRC32_H
#include "common/general.h"
uint32_t get_mac_addr_crc(uint64_t _addr);
#endif /* __FMAN_CRC32_H */

845
drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fman_dtsec.c Normal file
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/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_fman_dtsec.h"
void fman_dtsec_stop_rx(struct dtsec_regs *regs)
{
/* Assert the graceful stop bit */
iowrite32be(ioread32be(&regs->rctrl) | RCTRL_GRS, &regs->rctrl);
}
void fman_dtsec_stop_tx(struct dtsec_regs *regs)
{
/* Assert the graceful stop bit */
iowrite32be(ioread32be(&regs->tctrl) | DTSEC_TCTRL_GTS, &regs->tctrl);
}
void fman_dtsec_start_tx(struct dtsec_regs *regs)
{
/* clear the graceful stop bit */
iowrite32be(ioread32be(&regs->tctrl) & ~DTSEC_TCTRL_GTS, &regs->tctrl);
}
void fman_dtsec_start_rx(struct dtsec_regs *regs)
{
/* clear the graceful stop bit */
iowrite32be(ioread32be(&regs->rctrl) & ~RCTRL_GRS, &regs->rctrl);
}
void fman_dtsec_defconfig(struct dtsec_cfg *cfg)
{
cfg->halfdup_on = DEFAULT_HALFDUP_ON;
cfg->halfdup_retransmit = DEFAULT_HALFDUP_RETRANSMIT;
cfg->halfdup_coll_window = DEFAULT_HALFDUP_COLL_WINDOW;
cfg->halfdup_excess_defer = DEFAULT_HALFDUP_EXCESS_DEFER;
cfg->halfdup_no_backoff = DEFAULT_HALFDUP_NO_BACKOFF;
cfg->halfdup_bp_no_backoff = DEFAULT_HALFDUP_BP_NO_BACKOFF;
cfg->halfdup_alt_backoff_val = DEFAULT_HALFDUP_ALT_BACKOFF_VAL;
cfg->halfdup_alt_backoff_en = DEFAULT_HALFDUP_ALT_BACKOFF_EN;
cfg->rx_drop_bcast = DEFAULT_RX_DROP_BCAST;
cfg->rx_short_frm = DEFAULT_RX_SHORT_FRM;
cfg->rx_len_check = DEFAULT_RX_LEN_CHECK;
cfg->tx_pad_crc = DEFAULT_TX_PAD_CRC;
cfg->tx_crc = DEFAULT_TX_CRC;
cfg->rx_ctrl_acc = DEFAULT_RX_CTRL_ACC;
cfg->tx_pause_time = DEFAULT_TX_PAUSE_TIME;
cfg->tbipa = DEFAULT_TBIPA; /* PHY address 0 is reserved (DPAA RM)*/
cfg->rx_prepend = DEFAULT_RX_PREPEND;
cfg->ptp_tsu_en = DEFAULT_PTP_TSU_EN;
cfg->ptp_exception_en = DEFAULT_PTP_EXCEPTION_EN;
cfg->preamble_len = DEFAULT_PREAMBLE_LEN;
cfg->rx_preamble = DEFAULT_RX_PREAMBLE;
cfg->tx_preamble = DEFAULT_TX_PREAMBLE;
cfg->loopback = DEFAULT_LOOPBACK;
cfg->rx_time_stamp_en = DEFAULT_RX_TIME_STAMP_EN;
cfg->tx_time_stamp_en = DEFAULT_TX_TIME_STAMP_EN;
cfg->rx_flow = DEFAULT_RX_FLOW;
cfg->tx_flow = DEFAULT_TX_FLOW;
cfg->rx_group_hash_exd = DEFAULT_RX_GROUP_HASH_EXD;
cfg->tx_pause_time_extd = DEFAULT_TX_PAUSE_TIME_EXTD;
cfg->rx_promisc = DEFAULT_RX_PROMISC;
cfg->non_back_to_back_ipg1 = DEFAULT_NON_BACK_TO_BACK_IPG1;
cfg->non_back_to_back_ipg2 = DEFAULT_NON_BACK_TO_BACK_IPG2;
cfg->min_ifg_enforcement = DEFAULT_MIN_IFG_ENFORCEMENT;
cfg->back_to_back_ipg = DEFAULT_BACK_TO_BACK_IPG;
cfg->maximum_frame = DEFAULT_MAXIMUM_FRAME;
cfg->tbi_phy_addr = DEFAULT_TBI_PHY_ADDR;
cfg->wake_on_lan = DEFAULT_WAKE_ON_LAN;
}
int fman_dtsec_init(struct dtsec_regs *regs, struct dtsec_cfg *cfg,
enum enet_interface iface_mode,
enum enet_speed iface_speed,
uint8_t *macaddr,
uint8_t fm_rev_maj,
uint8_t fm_rev_min,
uint32_t exception_mask)
{
bool is_rgmii = FALSE;
bool is_sgmii = FALSE;
bool is_qsgmii = FALSE;
int i;
uint32_t tmp;
UNUSED(fm_rev_maj);UNUSED(fm_rev_min);
/* let's start with a soft reset */
iowrite32be(MACCFG1_SOFT_RESET, &regs->maccfg1);
iowrite32be(0, &regs->maccfg1);
/*************dtsec_id2******************/
tmp = ioread32be(&regs->tsec_id2);
/* check RGMII support */
if (iface_mode == E_ENET_IF_RGMII ||
iface_mode == E_ENET_IF_RMII)
if (tmp & DTSEC_ID2_INT_REDUCED_OFF)
return -EINVAL;
if (iface_mode == E_ENET_IF_SGMII ||
iface_mode == E_ENET_IF_MII)
if (tmp & DTSEC_ID2_INT_REDUCED_OFF)
return -EINVAL;
/***************ECNTRL************************/
is_rgmii = (bool)((iface_mode == E_ENET_IF_RGMII) ? TRUE : FALSE);
is_sgmii = (bool)((iface_mode == E_ENET_IF_SGMII) ? TRUE : FALSE);
is_qsgmii = (bool)((iface_mode == E_ENET_IF_QSGMII) ? TRUE : FALSE);
tmp = 0;
if (is_rgmii || iface_mode == E_ENET_IF_GMII)
tmp |= DTSEC_ECNTRL_GMIIM;
if (is_sgmii)
tmp |= (DTSEC_ECNTRL_SGMIIM | DTSEC_ECNTRL_TBIM);
if (is_qsgmii)
tmp |= (DTSEC_ECNTRL_SGMIIM | DTSEC_ECNTRL_TBIM |
DTSEC_ECNTRL_QSGMIIM);
if (is_rgmii)
tmp |= DTSEC_ECNTRL_RPM;
if (iface_speed == E_ENET_SPEED_100)
tmp |= DTSEC_ECNTRL_R100M;
iowrite32be(tmp, &regs->ecntrl);
/***************ECNTRL************************/
/***************TCTRL************************/
tmp = 0;
if (cfg->halfdup_on)
tmp |= DTSEC_TCTRL_THDF;
if (cfg->tx_time_stamp_en)
tmp |= DTSEC_TCTRL_TTSE;
iowrite32be(tmp, &regs->tctrl);
/***************TCTRL************************/
/***************PTV************************/
tmp = 0;
#ifdef FM_SHORT_PAUSE_TIME_ERRATA_DTSEC1
if ((fm_rev_maj == 1) && (fm_rev_min == 0))
cfg->tx_pause_time += 2;
#endif /* FM_SHORT_PAUSE_TIME_ERRATA_DTSEC1 */
if (cfg->tx_pause_time)
tmp |= cfg->tx_pause_time;
if (cfg->tx_pause_time_extd)
tmp |= cfg->tx_pause_time_extd << PTV_PTE_OFST;
iowrite32be(tmp, &regs->ptv);
/***************RCTRL************************/
tmp = 0;
tmp |= ((uint32_t)(cfg->rx_prepend & 0x0000001f)) << 16;
if (cfg->rx_ctrl_acc)
tmp |= RCTRL_CFA;
if (cfg->rx_group_hash_exd)
tmp |= RCTRL_GHTX;
if (cfg->rx_time_stamp_en)
tmp |= RCTRL_RTSE;
if (cfg->rx_drop_bcast)
tmp |= RCTRL_BC_REJ;
if (cfg->rx_short_frm)
tmp |= RCTRL_RSF;
if (cfg->rx_promisc)
tmp |= RCTRL_PROM;
iowrite32be(tmp, &regs->rctrl);
/***************RCTRL************************/
/*
* Assign a Phy Address to the TBI (TBIPA).
* Done also in cases where TBI is not selected to avoid conflict with
* the external PHY's Physical address
*/
iowrite32be(cfg->tbipa, &regs->tbipa);
/***************TMR_CTL************************/
iowrite32be(0, &regs->tmr_ctrl);
if (cfg->ptp_tsu_en) {
tmp = 0;
tmp |= TMR_PEVENT_TSRE;
iowrite32be(tmp, &regs->tmr_pevent);
if (cfg->ptp_exception_en) {
tmp = 0;
tmp |= TMR_PEMASK_TSREEN;
iowrite32be(tmp, &regs->tmr_pemask);
}
}
/***************MACCFG1***********************/
tmp = 0;
if (cfg->loopback)
tmp |= MACCFG1_LOOPBACK;
if (cfg->rx_flow)
tmp |= MACCFG1_RX_FLOW;
if (cfg->tx_flow)
tmp |= MACCFG1_TX_FLOW;
iowrite32be(tmp, &regs->maccfg1);
/***************MACCFG1***********************/
/***************MACCFG2***********************/
tmp = 0;
if (iface_speed < E_ENET_SPEED_1000)
tmp |= MACCFG2_NIBBLE_MODE;
else if (iface_speed == E_ENET_SPEED_1000)
tmp |= MACCFG2_BYTE_MODE;
tmp |= ((uint32_t) cfg->preamble_len & 0x0000000f)
<< PREAMBLE_LENGTH_SHIFT;
if (cfg->rx_preamble)
tmp |= MACCFG2_PRE_AM_Rx_EN;
if (cfg->tx_preamble)
tmp |= MACCFG2_PRE_AM_Tx_EN;
if (cfg->rx_len_check)
tmp |= MACCFG2_LENGTH_CHECK;
if (cfg->tx_pad_crc)
tmp |= MACCFG2_PAD_CRC_EN;
if (cfg->tx_crc)
tmp |= MACCFG2_CRC_EN;
if (!cfg->halfdup_on)
tmp |= MACCFG2_FULL_DUPLEX;
iowrite32be(tmp, &regs->maccfg2);
/***************MACCFG2***********************/
/***************IPGIFG************************/
tmp = (((cfg->non_back_to_back_ipg1 <<
IPGIFG_NON_BACK_TO_BACK_IPG_1_SHIFT)
& IPGIFG_NON_BACK_TO_BACK_IPG_1)
| ((cfg->non_back_to_back_ipg2 <<
IPGIFG_NON_BACK_TO_BACK_IPG_2_SHIFT)
& IPGIFG_NON_BACK_TO_BACK_IPG_2)
| ((cfg->min_ifg_enforcement <<
IPGIFG_MIN_IFG_ENFORCEMENT_SHIFT)
& IPGIFG_MIN_IFG_ENFORCEMENT)
| (cfg->back_to_back_ipg & IPGIFG_BACK_TO_BACK_IPG));
iowrite32be(tmp, &regs->ipgifg);
/***************IPGIFG************************/
/***************HAFDUP************************/
tmp = 0;
if (cfg->halfdup_alt_backoff_en)
tmp = (uint32_t)(HAFDUP_ALT_BEB |
((cfg->halfdup_alt_backoff_val & 0x0000000f)
<< HAFDUP_ALTERNATE_BEB_TRUNCATION_SHIFT));
if (cfg->halfdup_bp_no_backoff)
tmp |= HAFDUP_BP_NO_BACKOFF;
if (cfg->halfdup_no_backoff)
tmp |= HAFDUP_NO_BACKOFF;
if (cfg->halfdup_excess_defer)
tmp |= HAFDUP_EXCESS_DEFER;
tmp |= ((cfg->halfdup_retransmit << HAFDUP_RETRANSMISSION_MAX_SHIFT)
& HAFDUP_RETRANSMISSION_MAX);
tmp |= (cfg->halfdup_coll_window & HAFDUP_COLLISION_WINDOW);
iowrite32be(tmp, &regs->hafdup);
/***************HAFDUP************************/
/***************MAXFRM************************/
/* Initialize MAXFRM */
iowrite32be(cfg->maximum_frame, &regs->maxfrm);
/***************MAXFRM************************/
/***************CAM1************************/
iowrite32be(0xffffffff, &regs->cam1);
iowrite32be(0xffffffff, &regs->cam2);
/***************IMASK************************/
iowrite32be(exception_mask, &regs->imask);
/***************IMASK************************/
/***************IEVENT************************/
iowrite32be(0xffffffff, &regs->ievent);
/***************MACSTNADDR1/2*****************/
tmp = (uint32_t)((macaddr[5] << 24) |
(macaddr[4] << 16) |
(macaddr[3] << 8) |
macaddr[2]);
iowrite32be(tmp, &regs->macstnaddr1);
tmp = (uint32_t)((macaddr[1] << 24) |
(macaddr[0] << 16));
iowrite32be(tmp, &regs->macstnaddr2);
/***************MACSTNADDR1/2*****************/
/*****************HASH************************/
for (i = 0; i < NUM_OF_HASH_REGS ; i++) {
/* Initialize IADDRx */
iowrite32be(0, &regs->igaddr[i]);
/* Initialize GADDRx */
iowrite32be(0, &regs->gaddr[i]);
}
fman_dtsec_reset_stat(regs);
return 0;
}
uint16_t fman_dtsec_get_max_frame_len(struct dtsec_regs *regs)
{
return (uint16_t)ioread32be(&regs->maxfrm);
}
void fman_dtsec_set_max_frame_len(struct dtsec_regs *regs, uint16_t length)
{
iowrite32be(length, &regs->maxfrm);
}
void fman_dtsec_set_mac_address(struct dtsec_regs *regs, uint8_t *adr)
{
uint32_t tmp;
tmp = (uint32_t)((adr[5] << 24) |
(adr[4] << 16) |
(adr[3] << 8) |
adr[2]);
iowrite32be(tmp, &regs->macstnaddr1);
tmp = (uint32_t)((adr[1] << 24) |
(adr[0] << 16));
iowrite32be(tmp, &regs->macstnaddr2);
}
void fman_dtsec_get_mac_address(struct dtsec_regs *regs, uint8_t *macaddr)
{
uint32_t tmp1, tmp2;
tmp1 = ioread32be(&regs->macstnaddr1);
tmp2 = ioread32be(&regs->macstnaddr2);
macaddr[0] = (uint8_t)((tmp2 & 0x00ff0000) >> 16);
macaddr[1] = (uint8_t)((tmp2 & 0xff000000) >> 24);
macaddr[2] = (uint8_t)(tmp1 & 0x000000ff);
macaddr[3] = (uint8_t)((tmp1 & 0x0000ff00) >> 8);
macaddr[4] = (uint8_t)((tmp1 & 0x00ff0000) >> 16);
macaddr[5] = (uint8_t)((tmp1 & 0xff000000) >> 24);
}
void fman_dtsec_set_hash_table(struct dtsec_regs *regs, uint32_t crc, bool mcast, bool ghtx)
{
int32_t bucket;
if (ghtx)
bucket = (int32_t)((crc >> 23) & 0x1ff);
else {
bucket = (int32_t)((crc >> 24) & 0xff);
/* if !ghtx and mcast the bit must be set in gaddr instead of igaddr. */
if (mcast)
bucket += 0x100;
}
fman_dtsec_set_bucket(regs, bucket, TRUE);
}
void fman_dtsec_set_bucket(struct dtsec_regs *regs, int bucket, bool enable)
{
int reg_idx = (bucket >> 5) & 0xf;
int bit_idx = bucket & 0x1f;
uint32_t bit_mask = 0x80000000 >> bit_idx;
uint32_t *reg;
if (reg_idx > 7)
reg = &regs->gaddr[reg_idx-8];
else
reg = &regs->igaddr[reg_idx];
if (enable)
iowrite32be(ioread32be(reg) | bit_mask, reg);
else
iowrite32be(ioread32be(reg) & (~bit_mask), reg);
}
void fman_dtsec_reset_filter_table(struct dtsec_regs *regs, bool mcast, bool ucast)
{
int i;
bool ghtx;
ghtx = (bool)((ioread32be(&regs->rctrl) & RCTRL_GHTX) ? TRUE : FALSE);
if (ucast || (ghtx && mcast)) {
for (i = 0; i < NUM_OF_HASH_REGS; i++)
iowrite32be(0, &regs->igaddr[i]);
}
if (mcast) {
for (i = 0; i < NUM_OF_HASH_REGS; i++)
iowrite32be(0, &regs->gaddr[i]);
}
}
int fman_dtsec_set_tbi_phy_addr(struct dtsec_regs *regs,
uint8_t addr)
{
if (addr > 0 && addr < 32)
iowrite32be(addr, &regs->tbipa);
else
return -EINVAL;
return 0;
}
void fman_dtsec_set_wol(struct dtsec_regs *regs, bool en)
{
uint32_t tmp;
tmp = ioread32be(&regs->maccfg2);
if (en)
tmp |= MACCFG2_MAGIC_PACKET_EN;
else
tmp &= ~MACCFG2_MAGIC_PACKET_EN;
iowrite32be(tmp, &regs->maccfg2);
}
int fman_dtsec_adjust_link(struct dtsec_regs *regs,
enum enet_interface iface_mode,
enum enet_speed speed, bool full_dx)
{
uint32_t tmp;
UNUSED(iface_mode);
if ((speed == E_ENET_SPEED_1000) && !full_dx)
return -EINVAL;
tmp = ioread32be(&regs->maccfg2);
if (!full_dx)
tmp &= ~MACCFG2_FULL_DUPLEX;
else
tmp |= MACCFG2_FULL_DUPLEX;
tmp &= ~(MACCFG2_NIBBLE_MODE | MACCFG2_BYTE_MODE);
if (speed < E_ENET_SPEED_1000)
tmp |= MACCFG2_NIBBLE_MODE;
else if (speed == E_ENET_SPEED_1000)
tmp |= MACCFG2_BYTE_MODE;
iowrite32be(tmp, &regs->maccfg2);
tmp = ioread32be(&regs->ecntrl);
if (speed == E_ENET_SPEED_100)
tmp |= DTSEC_ECNTRL_R100M;
else
tmp &= ~DTSEC_ECNTRL_R100M;
iowrite32be(tmp, &regs->ecntrl);
return 0;
}
void fman_dtsec_set_uc_promisc(struct dtsec_regs *regs, bool enable)
{
uint32_t tmp;
tmp = ioread32be(&regs->rctrl);
if (enable)
tmp |= RCTRL_UPROM;
else
tmp &= ~RCTRL_UPROM;
iowrite32be(tmp, &regs->rctrl);
}
void fman_dtsec_set_mc_promisc(struct dtsec_regs *regs, bool enable)
{
uint32_t tmp;
tmp = ioread32be(&regs->rctrl);
if (enable)
tmp |= RCTRL_MPROM;
else
tmp &= ~RCTRL_MPROM;
iowrite32be(tmp, &regs->rctrl);
}
bool fman_dtsec_get_clear_carry_regs(struct dtsec_regs *regs,
uint32_t *car1, uint32_t *car2)
{
/* read carry registers */
*car1 = ioread32be(&regs->car1);
*car2 = ioread32be(&regs->car2);
/* clear carry registers */
if (*car1)
iowrite32be(*car1, &regs->car1);
if (*car2)
iowrite32be(*car2, &regs->car2);
return (bool)((*car1 | *car2) ? TRUE : FALSE);
}
void fman_dtsec_reset_stat(struct dtsec_regs *regs)
{
/* clear HW counters */
iowrite32be(ioread32be(&regs->ecntrl) |
DTSEC_ECNTRL_CLRCNT, &regs->ecntrl);
}
int fman_dtsec_set_stat_level(struct dtsec_regs *regs, enum dtsec_stat_level level)
{
switch (level) {
case E_MAC_STAT_NONE:
iowrite32be(0xffffffff, &regs->cam1);
iowrite32be(0xffffffff, &regs->cam2);
iowrite32be(ioread32be(&regs->ecntrl) & ~DTSEC_ECNTRL_STEN,
&regs->ecntrl);
iowrite32be(ioread32be(&regs->imask) & ~DTSEC_IMASK_MSROEN,
&regs->imask);
break;
case E_MAC_STAT_PARTIAL:
iowrite32be(CAM1_ERRORS_ONLY, &regs->cam1);
iowrite32be(CAM2_ERRORS_ONLY, &regs->cam2);
iowrite32be(ioread32be(&regs->ecntrl) | DTSEC_ECNTRL_STEN,
&regs->ecntrl);
iowrite32be(ioread32be(&regs->imask) | DTSEC_IMASK_MSROEN,
&regs->imask);
break;
case E_MAC_STAT_MIB_GRP1:
iowrite32be((uint32_t)~CAM1_MIB_GRP_1, &regs->cam1);
iowrite32be((uint32_t)~CAM2_MIB_GRP_1, &regs->cam2);
iowrite32be(ioread32be(&regs->ecntrl) | DTSEC_ECNTRL_STEN,
&regs->ecntrl);
iowrite32be(ioread32be(&regs->imask) | DTSEC_IMASK_MSROEN,
&regs->imask);
break;
case E_MAC_STAT_FULL:
iowrite32be(0, &regs->cam1);
iowrite32be(0, &regs->cam2);
iowrite32be(ioread32be(&regs->ecntrl) | DTSEC_ECNTRL_STEN,
&regs->ecntrl);
iowrite32be(ioread32be(&regs->imask) | DTSEC_IMASK_MSROEN,
&regs->imask);
break;
default:
return -EINVAL;
}
return 0;
}
void fman_dtsec_set_ts(struct dtsec_regs *regs, bool en)
{
if (en) {
iowrite32be(ioread32be(&regs->rctrl) | RCTRL_RTSE,
&regs->rctrl);
iowrite32be(ioread32be(&regs->tctrl) | DTSEC_TCTRL_TTSE,
&regs->tctrl);
} else {
iowrite32be(ioread32be(&regs->rctrl) & ~RCTRL_RTSE,
&regs->rctrl);
iowrite32be(ioread32be(&regs->tctrl) & ~DTSEC_TCTRL_TTSE,
&regs->tctrl);
}
}
void fman_dtsec_enable(struct dtsec_regs *regs, bool apply_rx, bool apply_tx)
{
uint32_t tmp;
tmp = ioread32be(&regs->maccfg1);
if (apply_rx)
tmp |= MACCFG1_RX_EN ;
if (apply_tx)
tmp |= MACCFG1_TX_EN ;
iowrite32be(tmp, &regs->maccfg1);
}
void fman_dtsec_clear_addr_in_paddr(struct dtsec_regs *regs, uint8_t paddr_num)
{
iowrite32be(0, &regs->macaddr[paddr_num].exact_match1);
iowrite32be(0, &regs->macaddr[paddr_num].exact_match2);
}
void fman_dtsec_add_addr_in_paddr(struct dtsec_regs *regs,
uint64_t addr,
uint8_t paddr_num)
{
uint32_t tmp;
tmp = (uint32_t)(addr);
/* swap */
tmp = (((tmp & 0x000000FF) << 24) |
((tmp & 0x0000FF00) << 8) |
((tmp & 0x00FF0000) >> 8) |
((tmp & 0xFF000000) >> 24));
iowrite32be(tmp, &regs->macaddr[paddr_num].exact_match1);
tmp = (uint32_t)(addr>>32);
/* swap */
tmp = (((tmp & 0x000000FF) << 24) |
((tmp & 0x0000FF00) << 8) |
((tmp & 0x00FF0000) >> 8) |
((tmp & 0xFF000000) >> 24));
iowrite32be(tmp, &regs->macaddr[paddr_num].exact_match2);
}
void fman_dtsec_disable(struct dtsec_regs *regs, bool apply_rx, bool apply_tx)
{
uint32_t tmp;
tmp = ioread32be(&regs->maccfg1);
if (apply_rx)
tmp &= ~MACCFG1_RX_EN;
if (apply_tx)
tmp &= ~MACCFG1_TX_EN;
iowrite32be(tmp, &regs->maccfg1);
}
void fman_dtsec_set_tx_pause_frames(struct dtsec_regs *regs, uint16_t time)
{
uint32_t ptv = 0;
/* fixme: don't enable tx pause for half-duplex */
if (time) {
ptv = ioread32be(&regs->ptv);
ptv &= 0xffff0000;
ptv |= time & 0x0000ffff;
iowrite32be(ptv, &regs->ptv);
/* trigger the transmission of a flow-control pause frame */
iowrite32be(ioread32be(&regs->maccfg1) | MACCFG1_TX_FLOW,
&regs->maccfg1);
} else
iowrite32be(ioread32be(&regs->maccfg1) & ~MACCFG1_TX_FLOW,
&regs->maccfg1);
}
void fman_dtsec_handle_rx_pause(struct dtsec_regs *regs, bool en)
{
uint32_t tmp;
/* todo: check if mac is set to full-duplex */
tmp = ioread32be(&regs->maccfg1);
if (en)
tmp |= MACCFG1_RX_FLOW;
else
tmp &= ~MACCFG1_RX_FLOW;
iowrite32be(tmp, &regs->maccfg1);
}
uint32_t fman_dtsec_get_rctrl(struct dtsec_regs *regs)
{
return ioread32be(&regs->rctrl);
}
uint32_t fman_dtsec_get_revision(struct dtsec_regs *regs)
{
return ioread32be(&regs->tsec_id);
}
uint32_t fman_dtsec_get_event(struct dtsec_regs *regs, uint32_t ev_mask)
{
return ioread32be(&regs->ievent) & ev_mask;
}
void fman_dtsec_ack_event(struct dtsec_regs *regs, uint32_t ev_mask)
{
iowrite32be(ev_mask, &regs->ievent);
}
uint32_t fman_dtsec_get_interrupt_mask(struct dtsec_regs *regs)
{
return ioread32be(&regs->imask);
}
uint32_t fman_dtsec_check_and_clear_tmr_event(struct dtsec_regs *regs)
{
uint32_t event;
event = ioread32be(&regs->tmr_pevent);
event &= ioread32be(&regs->tmr_pemask);
if (event)
iowrite32be(event, &regs->tmr_pevent);
return event;
}
void fman_dtsec_enable_tmr_interrupt(struct dtsec_regs *regs)
{
iowrite32be(ioread32be(&regs->tmr_pemask) | TMR_PEMASK_TSREEN,
&regs->tmr_pemask);
}
void fman_dtsec_disable_tmr_interrupt(struct dtsec_regs *regs)
{
iowrite32be(ioread32be(&regs->tmr_pemask) & ~TMR_PEMASK_TSREEN,
&regs->tmr_pemask);
}
void fman_dtsec_enable_interrupt(struct dtsec_regs *regs, uint32_t ev_mask)
{
iowrite32be(ioread32be(&regs->imask) | ev_mask, &regs->imask);
}
void fman_dtsec_disable_interrupt(struct dtsec_regs *regs, uint32_t ev_mask)
{
iowrite32be(ioread32be(&regs->imask) & ~ev_mask, &regs->imask);
}
uint32_t fman_dtsec_get_stat_counter(struct dtsec_regs *regs,
enum dtsec_stat_counters reg_name)
{
uint32_t ret_val;
switch (reg_name) {
case E_DTSEC_STAT_TR64:
ret_val = ioread32be(&regs->tr64);
break;
case E_DTSEC_STAT_TR127:
ret_val = ioread32be(&regs->tr127);
break;
case E_DTSEC_STAT_TR255:
ret_val = ioread32be(&regs->tr255);
break;
case E_DTSEC_STAT_TR511:
ret_val = ioread32be(&regs->tr511);
break;
case E_DTSEC_STAT_TR1K:
ret_val = ioread32be(&regs->tr1k);
break;
case E_DTSEC_STAT_TRMAX:
ret_val = ioread32be(&regs->trmax);
break;
case E_DTSEC_STAT_TRMGV:
ret_val = ioread32be(&regs->trmgv);
break;
case E_DTSEC_STAT_RBYT:
ret_val = ioread32be(&regs->rbyt);
break;
case E_DTSEC_STAT_RPKT:
ret_val = ioread32be(&regs->rpkt);
break;
case E_DTSEC_STAT_RMCA:
ret_val = ioread32be(&regs->rmca);
break;
case E_DTSEC_STAT_RBCA:
ret_val = ioread32be(&regs->rbca);
break;
case E_DTSEC_STAT_RXPF:
ret_val = ioread32be(&regs->rxpf);
break;
case E_DTSEC_STAT_RALN:
ret_val = ioread32be(&regs->raln);
break;
case E_DTSEC_STAT_RFLR:
ret_val = ioread32be(&regs->rflr);
break;
case E_DTSEC_STAT_RCDE:
ret_val = ioread32be(&regs->rcde);
break;
case E_DTSEC_STAT_RCSE:
ret_val = ioread32be(&regs->rcse);
break;
case E_DTSEC_STAT_RUND:
ret_val = ioread32be(&regs->rund);
break;
case E_DTSEC_STAT_ROVR:
ret_val = ioread32be(&regs->rovr);
break;
case E_DTSEC_STAT_RFRG:
ret_val = ioread32be(&regs->rfrg);
break;
case E_DTSEC_STAT_RJBR:
ret_val = ioread32be(&regs->rjbr);
break;
case E_DTSEC_STAT_RDRP:
ret_val = ioread32be(&regs->rdrp);
break;
case E_DTSEC_STAT_TFCS:
ret_val = ioread32be(&regs->tfcs);
break;
case E_DTSEC_STAT_TBYT:
ret_val = ioread32be(&regs->tbyt);
break;
case E_DTSEC_STAT_TPKT:
ret_val = ioread32be(&regs->tpkt);
break;
case E_DTSEC_STAT_TMCA:
ret_val = ioread32be(&regs->tmca);
break;
case E_DTSEC_STAT_TBCA:
ret_val = ioread32be(&regs->tbca);
break;
case E_DTSEC_STAT_TXPF:
ret_val = ioread32be(&regs->txpf);
break;
case E_DTSEC_STAT_TNCL:
ret_val = ioread32be(&regs->tncl);
break;
case E_DTSEC_STAT_TDRP:
ret_val = ioread32be(&regs->tdrp);
break;
default:
ret_val = 0;
}
return ret_val;
}

163
drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fman_dtsec_mii_acc.c Normal file
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@ -0,0 +1,163 @@
/*
* Copyright 2008-2013 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "common/general.h"
#include "fsl_fman_dtsec_mii_acc.h"
/**
* dtsec_mii_get_div() - calculates the value of the dtsec mii divider
* @dtsec_freq: dtsec clock frequency (in Mhz)
*
* This function calculates the dtsec mii clock divider that determines
* the MII MDC clock. MII MDC clock will be set to work in the range
* of 1.5 to 2.5Mhz
* The output of this function is the value of MIIMCFG[MgmtClk] which
* implicitly determines the divider value.
* Note: the dTSEC system clock is equal to 1/2 of the FMan clock.
*
* The table below which reflects dtsec_mii_get_div() functionality
* shows the relations among dtsec_freq, MgmtClk, actual divider
* and the MII frequency:
*
* dtsec freq MgmtClk div MII freq Mhz
* [0.....80] 1 (1/4)(1/8) [0 to 2.5]
* [81...120] 2 (1/6)(1/8) [1.6 to 2.5]
* [121..160] 3 (1/8)(1/8) [1.8 to 2.5]
* [161..200] 4 (1/10)(1/8) [2.0 to 2.5]
* [201..280] 5 (1/14)(1/8) [1.8 to 2.5]
* [281..400] 6 (1/20)(1/8) [1.1 to 2.5]
* [401..560] 7 (1/28)(1/8) [1.8 to 2.5]
* [560..frq] 7 (1/28)(1/8) [frq/224]
*
* Returns: the MIIMCFG[MgmtClk] appropriate value
*/
static uint8_t dtsec_mii_get_div(uint16_t dtsec_freq)
{
uint16_t mgmt_clk;
if (dtsec_freq < 80) mgmt_clk = 1;
else if (dtsec_freq < 120) mgmt_clk = 2;
else if (dtsec_freq < 160) mgmt_clk = 3;
else if (dtsec_freq < 200) mgmt_clk = 4;
else if (dtsec_freq < 280) mgmt_clk = 5;
else if (dtsec_freq < 400) mgmt_clk = 6;
else mgmt_clk = 7;
return (uint8_t)mgmt_clk;
}
void fman_dtsec_mii_reset(struct dtsec_mii_reg *regs)
{
/* Reset the management interface */
iowrite32be(ioread32be(&regs->miimcfg) | MIIMCFG_RESET_MGMT,
&regs->miimcfg);
iowrite32be(ioread32be(&regs->miimcfg) & ~MIIMCFG_RESET_MGMT,
&regs->miimcfg);
}
int fman_dtsec_mii_write_reg(struct dtsec_mii_reg *regs, uint8_t addr,
uint8_t reg, uint16_t data, uint16_t dtsec_freq)
{
uint32_t tmp;
/* Setup the MII Mgmt clock speed */
iowrite32be((uint32_t)dtsec_mii_get_div(dtsec_freq), &regs->miimcfg);
wmb();
/* Stop the MII management read cycle */
iowrite32be(0, &regs->miimcom);
/* Dummy read to make sure MIIMCOM is written */
tmp = ioread32be(&regs->miimcom);
wmb();
/* Setting up MII Management Address Register */
tmp = (uint32_t)((addr << MIIMADD_PHY_ADDR_SHIFT) | reg);
iowrite32be(tmp, &regs->miimadd);
wmb();
/* Setting up MII Management Control Register with data */
iowrite32be((uint32_t)data, &regs->miimcon);
/* Dummy read to make sure MIIMCON is written */
tmp = ioread32be(&regs->miimcon);
wmb();
/* Wait until MII management write is complete */
/* todo: a timeout could be useful here */
while ((ioread32be(&regs->miimind)) & MIIMIND_BUSY)
/* busy wait */;
return 0;
}
int fman_dtsec_mii_read_reg(struct dtsec_mii_reg *regs, uint8_t addr,
uint8_t reg, uint16_t *data, uint16_t dtsec_freq)
{
uint32_t tmp;
/* Setup the MII Mgmt clock speed */
iowrite32be((uint32_t)dtsec_mii_get_div(dtsec_freq), &regs->miimcfg);
wmb();
/* Setting up the MII Management Address Register */
tmp = (uint32_t)((addr << MIIMADD_PHY_ADDR_SHIFT) | reg);
iowrite32be(tmp, &regs->miimadd);
wmb();
/* Perform an MII management read cycle */
iowrite32be(MIIMCOM_READ_CYCLE, &regs->miimcom);
/* Dummy read to make sure MIIMCOM is written */
tmp = ioread32be(&regs->miimcom);
wmb();
/* Wait until MII management read is complete */
/* todo: a timeout could be useful here */
while ((ioread32be(&regs->miimind)) & MIIMIND_BUSY)
/* busy wait */;
/* Read MII management status */
*data = (uint16_t)ioread32be(&regs->miimstat);
wmb();
iowrite32be(0, &regs->miimcom);
/* Dummy read to make sure MIIMCOM is written */
tmp = ioread32be(&regs->miimcom);
if (*data == 0xffff)
return -ENXIO;
return 0;
}

511
drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fman_memac.c Normal file
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/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_fman_memac.h"
uint32_t fman_memac_get_event(struct memac_regs *regs, uint32_t ev_mask)
{
return ioread32be(&regs->ievent) & ev_mask;
}
uint32_t fman_memac_get_interrupt_mask(struct memac_regs *regs)
{
return ioread32be(&regs->imask);
}
void fman_memac_ack_event(struct memac_regs *regs, uint32_t ev_mask)
{
iowrite32be(ev_mask, &regs->ievent);
}
void fman_memac_set_promiscuous(struct memac_regs *regs, bool val)
{
uint32_t tmp;
tmp = ioread32be(&regs->command_config);
if (val)
tmp |= CMD_CFG_PROMIS_EN;
else
tmp &= ~CMD_CFG_PROMIS_EN;
iowrite32be(tmp, &regs->command_config);
}
void fman_memac_clear_addr_in_paddr(struct memac_regs *regs,
uint8_t paddr_num)
{
if (paddr_num == 0) {
iowrite32be(0, &regs->mac_addr0.mac_addr_l);
iowrite32be(0, &regs->mac_addr0.mac_addr_u);
} else {
iowrite32be(0x0, &regs->mac_addr[paddr_num - 1].mac_addr_l);
iowrite32be(0x0, &regs->mac_addr[paddr_num - 1].mac_addr_u);
}
}
void fman_memac_add_addr_in_paddr(struct memac_regs *regs,
uint8_t *adr,
uint8_t paddr_num)
{
uint32_t tmp0, tmp1;
tmp0 = (uint32_t)(adr[0] |
adr[1] << 8 |
adr[2] << 16 |
adr[3] << 24);
tmp1 = (uint32_t)(adr[4] | adr[5] << 8);
if (paddr_num == 0) {
iowrite32be(tmp0, &regs->mac_addr0.mac_addr_l);
iowrite32be(tmp1, &regs->mac_addr0.mac_addr_u);
} else {
iowrite32be(tmp0, &regs->mac_addr[paddr_num-1].mac_addr_l);
iowrite32be(tmp1, &regs->mac_addr[paddr_num-1].mac_addr_u);
}
}
void fman_memac_enable(struct memac_regs *regs, bool apply_rx, bool apply_tx)
{
uint32_t tmp;
tmp = ioread32be(&regs->command_config);
if (apply_rx)
tmp |= CMD_CFG_RX_EN;
if (apply_tx)
tmp |= CMD_CFG_TX_EN;
iowrite32be(tmp, &regs->command_config);
}
void fman_memac_disable(struct memac_regs *regs, bool apply_rx, bool apply_tx)
{
uint32_t tmp;
tmp = ioread32be(&regs->command_config);
if (apply_rx)
tmp &= ~CMD_CFG_RX_EN;
if (apply_tx)
tmp &= ~CMD_CFG_TX_EN;
iowrite32be(tmp, &regs->command_config);
}
void fman_memac_reset_stat(struct memac_regs *regs)
{
uint32_t tmp;
tmp = ioread32be(&regs->statn_config);
tmp |= STATS_CFG_CLR;
iowrite32be(tmp, &regs->statn_config);
while (ioread32be(&regs->statn_config) & STATS_CFG_CLR);
}
void fman_memac_reset(struct memac_regs *regs)
{
uint32_t tmp;
tmp = ioread32be(&regs->command_config);
tmp |= CMD_CFG_SW_RESET;
iowrite32be(tmp, &regs->command_config);
while (ioread32be(&regs->command_config) & CMD_CFG_SW_RESET);
}
int fman_memac_init(struct memac_regs *regs,
struct memac_cfg *cfg,
enum enet_interface enet_interface,
enum enet_speed enet_speed,
bool slow_10g_if,
uint32_t exceptions)
{
uint32_t tmp;
/* Config */
tmp = 0;
if (cfg->wan_mode_enable)
tmp |= CMD_CFG_WAN_MODE;
if (cfg->promiscuous_mode_enable)
tmp |= CMD_CFG_PROMIS_EN;
if (cfg->pause_forward_enable)
tmp |= CMD_CFG_PAUSE_FWD;
if (cfg->pause_ignore)
tmp |= CMD_CFG_PAUSE_IGNORE;
if (cfg->tx_addr_ins_enable)
tmp |= CMD_CFG_TX_ADDR_INS;
if (cfg->loopback_enable)
tmp |= CMD_CFG_LOOPBACK_EN;
if (cfg->cmd_frame_enable)
tmp |= CMD_CFG_CNT_FRM_EN;
if (cfg->send_idle_enable)
tmp |= CMD_CFG_SEND_IDLE;
if (cfg->no_length_check_enable)
tmp |= CMD_CFG_NO_LEN_CHK;
if (cfg->rx_sfd_any)
tmp |= CMD_CFG_SFD_ANY;
if (cfg->pad_enable)
tmp |= CMD_CFG_TX_PAD_EN;
if (cfg->wake_on_lan)
tmp |= CMD_CFG_MG;
tmp |= CMD_CFG_CRC_FWD;
iowrite32be(tmp, &regs->command_config);
/* Max Frame Length */
iowrite32be((uint32_t)cfg->max_frame_length, &regs->maxfrm);
/* Pause Time */
iowrite32be((uint32_t)cfg->pause_quanta, &regs->pause_quanta[0]);
iowrite32be((uint32_t)0, &regs->pause_thresh[0]);
/* IF_MODE */
tmp = 0;
switch (enet_interface) {
case E_ENET_IF_XGMII:
case E_ENET_IF_XFI:
tmp |= IF_MODE_XGMII;
break;
default:
tmp |= IF_MODE_GMII;
if (enet_interface == E_ENET_IF_RGMII && !cfg->loopback_enable)
tmp |= IF_MODE_RGMII | IF_MODE_RGMII_AUTO;
}
iowrite32be(tmp, &regs->if_mode);
/* TX_FIFO_SECTIONS */
tmp = 0;
if (enet_interface == E_ENET_IF_XGMII ||
enet_interface == E_ENET_IF_XFI) {
if(slow_10g_if) {
tmp |= (TX_FIFO_SECTIONS_TX_AVAIL_SLOW_10G |
TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G);
} else {
tmp |= (TX_FIFO_SECTIONS_TX_AVAIL_10G |
TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G);
}
} else {
tmp |= (TX_FIFO_SECTIONS_TX_AVAIL_1G |
TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G);
}
iowrite32be(tmp, &regs->tx_fifo_sections);
/* clear all pending events and set-up interrupts */
fman_memac_ack_event(regs, 0xffffffff);
fman_memac_set_exception(regs, exceptions, TRUE);
return 0;
}
void fman_memac_set_exception(struct memac_regs *regs, uint32_t val, bool enable)
{
uint32_t tmp;
tmp = ioread32be(&regs->imask);
if (enable)
tmp |= val;
else
tmp &= ~val;
iowrite32be(tmp, &regs->imask);
}
void fman_memac_reset_filter_table(struct memac_regs *regs)
{
uint32_t i;
for (i = 0; i < 64; i++)
iowrite32be(i & ~HASH_CTRL_MCAST_EN, &regs->hashtable_ctrl);
}
void fman_memac_set_hash_table_entry(struct memac_regs *regs, uint32_t crc)
{
iowrite32be(crc | HASH_CTRL_MCAST_EN, &regs->hashtable_ctrl);
}
void fman_memac_set_hash_table(struct memac_regs *regs, uint32_t val)
{
iowrite32be(val, &regs->hashtable_ctrl);
}
uint16_t fman_memac_get_max_frame_len(struct memac_regs *regs)
{
uint32_t tmp;
tmp = ioread32be(&regs->maxfrm);
return(uint16_t)tmp;
}
void fman_memac_set_tx_pause_frames(struct memac_regs *regs,
uint8_t priority,
uint16_t pause_time,
uint16_t thresh_time)
{
uint32_t tmp;
tmp = ioread32be(&regs->tx_fifo_sections);
if (priority == 0xff) {
GET_TX_EMPTY_DEFAULT_VALUE(tmp);
iowrite32be(tmp, &regs->tx_fifo_sections);
tmp = ioread32be(&regs->command_config);
tmp &= ~CMD_CFG_PFC_MODE;
priority = 0;
} else {
GET_TX_EMPTY_PFC_VALUE(tmp);
iowrite32be(tmp, &regs->tx_fifo_sections);
tmp = ioread32be(&regs->command_config);
tmp |= CMD_CFG_PFC_MODE;
}
iowrite32be(tmp, &regs->command_config);
tmp = ioread32be(&regs->pause_quanta[priority / 2]);
if (priority % 2)
tmp &= 0x0000FFFF;
else
tmp &= 0xFFFF0000;
tmp |= ((uint32_t)pause_time << (16 * (priority % 2)));
iowrite32be(tmp, &regs->pause_quanta[priority / 2]);
tmp = ioread32be(&regs->pause_thresh[priority / 2]);
if (priority % 2)
tmp &= 0x0000FFFF;
else
tmp &= 0xFFFF0000;
tmp |= ((uint32_t)thresh_time<<(16 * (priority % 2)));
iowrite32be(tmp, &regs->pause_thresh[priority / 2]);
}
void fman_memac_set_rx_ignore_pause_frames(struct memac_regs *regs,bool enable)
{
uint32_t tmp;
tmp = ioread32be(&regs->command_config);
if (enable)
tmp |= CMD_CFG_PAUSE_IGNORE;
else
tmp &= ~CMD_CFG_PAUSE_IGNORE;
iowrite32be(tmp, &regs->command_config);
}
void fman_memac_set_wol(struct memac_regs *regs, bool enable)
{
uint32_t tmp;
tmp = ioread32be(&regs->command_config);
if (enable)
tmp |= CMD_CFG_MG;
else
tmp &= ~CMD_CFG_MG;
iowrite32be(tmp, &regs->command_config);
}
#define GET_MEMAC_CNTR_64(bn) \
(ioread32be(&regs->bn ## _l) | \
((uint64_t)ioread32be(&regs->bn ## _u) << 32))
uint64_t fman_memac_get_counter(struct memac_regs *regs,
enum memac_counters reg_name)
{
uint64_t ret_val;
switch (reg_name) {
case E_MEMAC_COUNTER_R64:
ret_val = GET_MEMAC_CNTR_64(r64);
break;
case E_MEMAC_COUNTER_R127:
ret_val = GET_MEMAC_CNTR_64(r127);
break;
case E_MEMAC_COUNTER_R255:
ret_val = GET_MEMAC_CNTR_64(r255);
break;
case E_MEMAC_COUNTER_R511:
ret_val = GET_MEMAC_CNTR_64(r511);
break;
case E_MEMAC_COUNTER_R1023:
ret_val = GET_MEMAC_CNTR_64(r1023);
break;
case E_MEMAC_COUNTER_R1518:
ret_val = GET_MEMAC_CNTR_64(r1518);
break;
case E_MEMAC_COUNTER_R1519X:
ret_val = GET_MEMAC_CNTR_64(r1519x);
break;
case E_MEMAC_COUNTER_RFRG:
ret_val = GET_MEMAC_CNTR_64(rfrg);
break;
case E_MEMAC_COUNTER_RJBR:
ret_val = GET_MEMAC_CNTR_64(rjbr);
break;
case E_MEMAC_COUNTER_RDRP:
ret_val = GET_MEMAC_CNTR_64(rdrp);
break;
case E_MEMAC_COUNTER_RALN:
ret_val = GET_MEMAC_CNTR_64(raln);
break;
case E_MEMAC_COUNTER_TUND:
ret_val = GET_MEMAC_CNTR_64(tund);
break;
case E_MEMAC_COUNTER_ROVR:
ret_val = GET_MEMAC_CNTR_64(rovr);
break;
case E_MEMAC_COUNTER_RXPF:
ret_val = GET_MEMAC_CNTR_64(rxpf);
break;
case E_MEMAC_COUNTER_TXPF:
ret_val = GET_MEMAC_CNTR_64(txpf);
break;
case E_MEMAC_COUNTER_ROCT:
ret_val = GET_MEMAC_CNTR_64(roct);
break;
case E_MEMAC_COUNTER_RMCA:
ret_val = GET_MEMAC_CNTR_64(rmca);
break;
case E_MEMAC_COUNTER_RBCA:
ret_val = GET_MEMAC_CNTR_64(rbca);
break;
case E_MEMAC_COUNTER_RPKT:
ret_val = GET_MEMAC_CNTR_64(rpkt);
break;
case E_MEMAC_COUNTER_RUCA:
ret_val = GET_MEMAC_CNTR_64(ruca);
break;
case E_MEMAC_COUNTER_RERR:
ret_val = GET_MEMAC_CNTR_64(rerr);
break;
case E_MEMAC_COUNTER_TOCT:
ret_val = GET_MEMAC_CNTR_64(toct);
break;
case E_MEMAC_COUNTER_TMCA:
ret_val = GET_MEMAC_CNTR_64(tmca);
break;
case E_MEMAC_COUNTER_TBCA:
ret_val = GET_MEMAC_CNTR_64(tbca);
break;
case E_MEMAC_COUNTER_TUCA:
ret_val = GET_MEMAC_CNTR_64(tuca);
break;
case E_MEMAC_COUNTER_TERR:
ret_val = GET_MEMAC_CNTR_64(terr);
break;
default:
ret_val = 0;
}
return ret_val;
}
void fman_memac_adjust_link(struct memac_regs *regs,
enum enet_interface iface_mode,
enum enet_speed speed, bool full_dx)
{
uint32_t tmp;
tmp = ioread32be(&regs->if_mode);
if (full_dx)
tmp &= ~IF_MODE_HD;
else
tmp |= IF_MODE_HD;
if (iface_mode == E_ENET_IF_RGMII) {
/* Configure RGMII in manual mode */
tmp &= ~IF_MODE_RGMII_AUTO;
tmp &= ~IF_MODE_RGMII_SP_MASK;
if (full_dx)
tmp |= IF_MODE_RGMII_FD;
else
tmp &= ~IF_MODE_RGMII_FD;
switch (speed) {
case E_ENET_SPEED_1000:
tmp |= IF_MODE_RGMII_1000;
break;
case E_ENET_SPEED_100:
tmp |= IF_MODE_RGMII_100;
break;
case E_ENET_SPEED_10:
tmp |= IF_MODE_RGMII_10;
break;
default:
break;
}
}
iowrite32be(tmp, &regs->if_mode);
}
void fman_memac_defconfig(struct memac_cfg *cfg)
{
cfg->reset_on_init = FALSE;
cfg->wan_mode_enable = FALSE;
cfg->promiscuous_mode_enable = FALSE;
cfg->pause_forward_enable = FALSE;
cfg->pause_ignore = FALSE;
cfg->tx_addr_ins_enable = FALSE;
cfg->loopback_enable = FALSE;
cfg->cmd_frame_enable = FALSE;
cfg->rx_error_discard = FALSE;
cfg->send_idle_enable = FALSE;
cfg->no_length_check_enable = TRUE;
cfg->lgth_check_nostdr = FALSE;
cfg->time_stamp_enable = FALSE;
cfg->tx_ipg_length = DEFAULT_TX_IPG_LENGTH;
cfg->max_frame_length = DEFAULT_FRAME_LENGTH;
cfg->pause_quanta = DEFAULT_PAUSE_QUANTA;
cfg->pad_enable = TRUE;
cfg->phy_tx_ena_on = FALSE;
cfg->rx_sfd_any = FALSE;
cfg->rx_pbl_fwd = FALSE;
cfg->tx_pbl_fwd = FALSE;
cfg->debug_mode = FALSE;
cfg->wake_on_lan = FALSE;
}

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drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fman_memac_mii_acc.c Executable file
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/*
* Copyright 2008-2013 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_fman_memac_mii_acc.h"
static void write_phy_reg_10g(struct memac_mii_access_mem_map *mii_regs,
uint8_t phy_addr, uint8_t reg, uint16_t data)
{
uint32_t tmp_reg;
tmp_reg = ioread32be(&mii_regs->mdio_cfg);
/* Leave only MDIO_CLK_DIV bits set on */
tmp_reg &= MDIO_CFG_CLK_DIV_MASK;
/* Set maximum MDIO_HOLD value to allow phy to see
change of data signal */
tmp_reg |= MDIO_CFG_HOLD_MASK;
/* Add 10G interface mode */
tmp_reg |= MDIO_CFG_ENC45;
iowrite32be(tmp_reg, &mii_regs->mdio_cfg);
/* Wait for command completion */
while ((ioread32be(&mii_regs->mdio_cfg)) & MDIO_CFG_BSY)
udelay(1);
/* Specify phy and register to be accessed */
iowrite32be(phy_addr, &mii_regs->mdio_ctrl);
iowrite32be(reg, &mii_regs->mdio_addr);
wmb();
while ((ioread32be(&mii_regs->mdio_cfg)) & MDIO_CFG_BSY)
udelay(1);
/* Write data */
iowrite32be(data, &mii_regs->mdio_data);
wmb();
/* Wait for write transaction end */
while ((ioread32be(&mii_regs->mdio_data)) & MDIO_DATA_BSY)
udelay(1);
}
static uint32_t read_phy_reg_10g(struct memac_mii_access_mem_map *mii_regs,
uint8_t phy_addr, uint8_t reg, uint16_t *data)
{
uint32_t tmp_reg;
tmp_reg = ioread32be(&mii_regs->mdio_cfg);
/* Leave only MDIO_CLK_DIV bits set on */
tmp_reg &= MDIO_CFG_CLK_DIV_MASK;
/* Set maximum MDIO_HOLD value to allow phy to see
change of data signal */
tmp_reg |= MDIO_CFG_HOLD_MASK;
/* Add 10G interface mode */
tmp_reg |= MDIO_CFG_ENC45;
iowrite32be(tmp_reg, &mii_regs->mdio_cfg);
/* Wait for command completion */
while ((ioread32be(&mii_regs->mdio_cfg)) & MDIO_CFG_BSY)
udelay(1);
/* Specify phy and register to be accessed */
iowrite32be(phy_addr, &mii_regs->mdio_ctrl);
iowrite32be(reg, &mii_regs->mdio_addr);
wmb();
while ((ioread32be(&mii_regs->mdio_cfg)) & MDIO_CFG_BSY)
udelay(1);
/* Read cycle */
tmp_reg = phy_addr;
tmp_reg |= MDIO_CTL_READ;
iowrite32be(tmp_reg, &mii_regs->mdio_ctrl);
wmb();
/* Wait for data to be available */
while ((ioread32be(&mii_regs->mdio_data)) & MDIO_DATA_BSY)
udelay(1);
*data = (uint16_t)ioread32be(&mii_regs->mdio_data);
/* Check if there was an error */
return ioread32be(&mii_regs->mdio_cfg);
}
static void write_phy_reg_1g(struct memac_mii_access_mem_map *mii_regs,
uint8_t phy_addr, uint8_t reg, uint16_t data)
{
uint32_t tmp_reg;
/* Leave only MDIO_CLK_DIV and MDIO_HOLD bits set on */
tmp_reg = ioread32be(&mii_regs->mdio_cfg);
tmp_reg &= (MDIO_CFG_CLK_DIV_MASK | MDIO_CFG_HOLD_MASK);
iowrite32be(tmp_reg, &mii_regs->mdio_cfg);
/* Wait for command completion */
while ((ioread32be(&mii_regs->mdio_cfg)) & MDIO_CFG_BSY)
udelay(1);
/* Write transaction */
tmp_reg = (phy_addr << MDIO_CTL_PHY_ADDR_SHIFT);
tmp_reg |= reg;
iowrite32be(tmp_reg, &mii_regs->mdio_ctrl);
while ((ioread32be(&mii_regs->mdio_cfg)) & MDIO_CFG_BSY)
udelay(1);
iowrite32be(data, &mii_regs->mdio_data);
wmb();
/* Wait for write transaction to end */
while ((ioread32be(&mii_regs->mdio_data)) & MDIO_DATA_BSY)
udelay(1);
}
static uint32_t read_phy_reg_1g(struct memac_mii_access_mem_map *mii_regs,
uint8_t phy_addr, uint8_t reg, uint16_t *data)
{
uint32_t tmp_reg;
/* Leave only MDIO_CLK_DIV and MDIO_HOLD bits set on */
tmp_reg = ioread32be(&mii_regs->mdio_cfg);
tmp_reg &= (MDIO_CFG_CLK_DIV_MASK | MDIO_CFG_HOLD_MASK);
iowrite32be(tmp_reg, &mii_regs->mdio_cfg);
/* Wait for command completion */
while ((ioread32be(&mii_regs->mdio_cfg)) & MDIO_CFG_BSY)
udelay(1);
/* Read transaction */
tmp_reg = (phy_addr << MDIO_CTL_PHY_ADDR_SHIFT);
tmp_reg |= reg;
tmp_reg |= MDIO_CTL_READ;
iowrite32be(tmp_reg, &mii_regs->mdio_ctrl);
while ((ioread32be(&mii_regs->mdio_cfg)) & MDIO_CFG_BSY)
udelay(1);
/* Wait for data to be available */
while ((ioread32be(&mii_regs->mdio_data)) & MDIO_DATA_BSY)
udelay(1);
*data = (uint16_t)ioread32be(&mii_regs->mdio_data);
/* Check error */
return ioread32be(&mii_regs->mdio_cfg);
}
/*****************************************************************************/
int fman_memac_mii_write_phy_reg(struct memac_mii_access_mem_map *mii_regs,
uint8_t phy_addr, uint8_t reg, uint16_t data,
enum enet_speed enet_speed)
{
/* Figure out interface type - 10G vs 1G.
In 10G interface both phy_addr and devAddr present. */
if (enet_speed == E_ENET_SPEED_10000)
write_phy_reg_10g(mii_regs, phy_addr, reg, data);
else
write_phy_reg_1g(mii_regs, phy_addr, reg, data);
return 0;
}
/*****************************************************************************/
int fman_memac_mii_read_phy_reg(struct memac_mii_access_mem_map *mii_regs,
uint8_t phy_addr, uint8_t reg, uint16_t *data,
enum enet_speed enet_speed)
{
uint32_t ans;
/* Figure out interface type - 10G vs 1G.
In 10G interface both phy_addr and devAddr present. */
if (enet_speed == E_ENET_SPEED_10000)
ans = read_phy_reg_10g(mii_regs, phy_addr, reg, data);
else
ans = read_phy_reg_1g(mii_regs, phy_addr, reg, data);
if (ans & MDIO_CFG_READ_ERR)
return -EINVAL;
return 0;
}
/* ......................................................................... */

367
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/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_fman_tgec.h"
void fman_tgec_set_mac_address(struct tgec_regs *regs, uint8_t *adr)
{
uint32_t tmp0, tmp1;
tmp0 = (uint32_t)(adr[0] |
adr[1] << 8 |
adr[2] << 16 |
adr[3] << 24);
tmp1 = (uint32_t)(adr[4] | adr[5] << 8);
iowrite32be(tmp0, &regs->mac_addr_0);
iowrite32be(tmp1, &regs->mac_addr_1);
}
void fman_tgec_reset_stat(struct tgec_regs *regs)
{
uint32_t tmp;
tmp = ioread32be(&regs->command_config);
tmp |= CMD_CFG_STAT_CLR;
iowrite32be(tmp, &regs->command_config);
while (ioread32be(&regs->command_config) & CMD_CFG_STAT_CLR) ;
}
#define GET_TGEC_CNTR_64(bn) \
(((uint64_t)ioread32be(&regs->bn ## _u) << 32) | \
ioread32be(&regs->bn ## _l))
uint64_t fman_tgec_get_counter(struct tgec_regs *regs, enum tgec_counters reg_name)
{
uint64_t ret_val;
switch (reg_name) {
case E_TGEC_COUNTER_R64:
ret_val = GET_TGEC_CNTR_64(r64);
break;
case E_TGEC_COUNTER_R127:
ret_val = GET_TGEC_CNTR_64(r127);
break;
case E_TGEC_COUNTER_R255:
ret_val = GET_TGEC_CNTR_64(r255);
break;
case E_TGEC_COUNTER_R511:
ret_val = GET_TGEC_CNTR_64(r511);
break;
case E_TGEC_COUNTER_R1023:
ret_val = GET_TGEC_CNTR_64(r1023);
break;
case E_TGEC_COUNTER_R1518:
ret_val = GET_TGEC_CNTR_64(r1518);
break;
case E_TGEC_COUNTER_R1519X:
ret_val = GET_TGEC_CNTR_64(r1519x);
break;
case E_TGEC_COUNTER_TRFRG:
ret_val = GET_TGEC_CNTR_64(trfrg);
break;
case E_TGEC_COUNTER_TRJBR:
ret_val = GET_TGEC_CNTR_64(trjbr);
break;
case E_TGEC_COUNTER_RDRP:
ret_val = GET_TGEC_CNTR_64(rdrp);
break;
case E_TGEC_COUNTER_RALN:
ret_val = GET_TGEC_CNTR_64(raln);
break;
case E_TGEC_COUNTER_TRUND:
ret_val = GET_TGEC_CNTR_64(trund);
break;
case E_TGEC_COUNTER_TROVR:
ret_val = GET_TGEC_CNTR_64(trovr);
break;
case E_TGEC_COUNTER_RXPF:
ret_val = GET_TGEC_CNTR_64(rxpf);
break;
case E_TGEC_COUNTER_TXPF:
ret_val = GET_TGEC_CNTR_64(txpf);
break;
case E_TGEC_COUNTER_ROCT:
ret_val = GET_TGEC_CNTR_64(roct);
break;
case E_TGEC_COUNTER_RMCA:
ret_val = GET_TGEC_CNTR_64(rmca);
break;
case E_TGEC_COUNTER_RBCA:
ret_val = GET_TGEC_CNTR_64(rbca);
break;
case E_TGEC_COUNTER_RPKT:
ret_val = GET_TGEC_CNTR_64(rpkt);
break;
case E_TGEC_COUNTER_RUCA:
ret_val = GET_TGEC_CNTR_64(ruca);
break;
case E_TGEC_COUNTER_RERR:
ret_val = GET_TGEC_CNTR_64(rerr);
break;
case E_TGEC_COUNTER_TOCT:
ret_val = GET_TGEC_CNTR_64(toct);
break;
case E_TGEC_COUNTER_TMCA:
ret_val = GET_TGEC_CNTR_64(tmca);
break;
case E_TGEC_COUNTER_TBCA:
ret_val = GET_TGEC_CNTR_64(tbca);
break;
case E_TGEC_COUNTER_TUCA:
ret_val = GET_TGEC_CNTR_64(tuca);
break;
case E_TGEC_COUNTER_TERR:
ret_val = GET_TGEC_CNTR_64(terr);
break;
default:
ret_val = 0;
}
return ret_val;
}
void fman_tgec_enable(struct tgec_regs *regs, bool apply_rx, bool apply_tx)
{
uint32_t tmp;
tmp = ioread32be(&regs->command_config);
if (apply_rx)
tmp |= CMD_CFG_RX_EN;
if (apply_tx)
tmp |= CMD_CFG_TX_EN;
iowrite32be(tmp, &regs->command_config);
}
void fman_tgec_disable(struct tgec_regs *regs, bool apply_rx, bool apply_tx)
{
uint32_t tmp_reg_32;
tmp_reg_32 = ioread32be(&regs->command_config);
if (apply_rx)
tmp_reg_32 &= ~CMD_CFG_RX_EN;
if (apply_tx)
tmp_reg_32 &= ~CMD_CFG_TX_EN;
iowrite32be(tmp_reg_32, &regs->command_config);
}
void fman_tgec_set_promiscuous(struct tgec_regs *regs, bool val)
{
uint32_t tmp;
tmp = ioread32be(&regs->command_config);
if (val)
tmp |= CMD_CFG_PROMIS_EN;
else
tmp &= ~CMD_CFG_PROMIS_EN;
iowrite32be(tmp, &regs->command_config);
}
void fman_tgec_reset_filter_table(struct tgec_regs *regs)
{
uint32_t i;
for (i = 0; i < 512; i++)
iowrite32be(i & ~TGEC_HASH_MCAST_EN, &regs->hashtable_ctrl);
}
void fman_tgec_set_hash_table_entry(struct tgec_regs *regs, uint32_t crc)
{
uint32_t hash = (crc >> TGEC_HASH_MCAST_SHIFT) & TGEC_HASH_ADR_MSK; /* Take 9 MSB bits */
iowrite32be(hash | TGEC_HASH_MCAST_EN, &regs->hashtable_ctrl);
}
void fman_tgec_set_hash_table(struct tgec_regs *regs, uint32_t value)
{
iowrite32be(value, &regs->hashtable_ctrl);
}
void fman_tgec_set_tx_pause_frames(struct tgec_regs *regs, uint16_t pause_time)
{
iowrite32be((uint32_t)pause_time, &regs->pause_quant);
}
void fman_tgec_set_rx_ignore_pause_frames(struct tgec_regs *regs, bool en)
{
uint32_t tmp;
tmp = ioread32be(&regs->command_config);
if (en)
tmp |= CMD_CFG_PAUSE_IGNORE;
else
tmp &= ~CMD_CFG_PAUSE_IGNORE;
iowrite32be(tmp, &regs->command_config);
}
void fman_tgec_enable_1588_time_stamp(struct tgec_regs *regs, bool en)
{
uint32_t tmp;
tmp = ioread32be(&regs->command_config);
if (en)
tmp |= CMD_CFG_EN_TIMESTAMP;
else
tmp &= ~CMD_CFG_EN_TIMESTAMP;
iowrite32be(tmp, &regs->command_config);
}
uint32_t fman_tgec_get_event(struct tgec_regs *regs, uint32_t ev_mask)
{
return ioread32be(&regs->ievent) & ev_mask;
}
void fman_tgec_ack_event(struct tgec_regs *regs, uint32_t ev_mask)
{
iowrite32be(ev_mask, &regs->ievent);
}
uint32_t fman_tgec_get_interrupt_mask(struct tgec_regs *regs)
{
return ioread32be(&regs->imask);
}
void fman_tgec_add_addr_in_paddr(struct tgec_regs *regs, uint8_t *adr)
{
uint32_t tmp0, tmp1;
tmp0 = (uint32_t)(adr[0] |
adr[1] << 8 |
adr[2] << 16 |
adr[3] << 24);
tmp1 = (uint32_t)(adr[4] | adr[5] << 8);
iowrite32be(tmp0, &regs->mac_addr_2);
iowrite32be(tmp1, &regs->mac_addr_3);
}
void fman_tgec_clear_addr_in_paddr(struct tgec_regs *regs)
{
iowrite32be(0, &regs->mac_addr_2);
iowrite32be(0, &regs->mac_addr_3);
}
uint32_t fman_tgec_get_revision(struct tgec_regs *regs)
{
return ioread32be(&regs->tgec_id);
}
void fman_tgec_enable_interrupt(struct tgec_regs *regs, uint32_t ev_mask)
{
iowrite32be(ioread32be(&regs->imask) | ev_mask, &regs->imask);
}
void fman_tgec_disable_interrupt(struct tgec_regs *regs, uint32_t ev_mask)
{
iowrite32be(ioread32be(&regs->imask) & ~ev_mask, &regs->imask);
}
uint16_t fman_tgec_get_max_frame_len(struct tgec_regs *regs)
{
return (uint16_t) ioread32be(&regs->maxfrm);
}
void fman_tgec_defconfig(struct tgec_cfg *cfg)
{
cfg->wan_mode_enable = DEFAULT_WAN_MODE_ENABLE;
cfg->promiscuous_mode_enable = DEFAULT_PROMISCUOUS_MODE_ENABLE;
cfg->pause_forward_enable = DEFAULT_PAUSE_FORWARD_ENABLE;
cfg->pause_ignore = DEFAULT_PAUSE_IGNORE;
cfg->tx_addr_ins_enable = DEFAULT_TX_ADDR_INS_ENABLE;
cfg->loopback_enable = DEFAULT_LOOPBACK_ENABLE;
cfg->cmd_frame_enable = DEFAULT_CMD_FRAME_ENABLE;
cfg->rx_error_discard = DEFAULT_RX_ERROR_DISCARD;
cfg->send_idle_enable = DEFAULT_SEND_IDLE_ENABLE;
cfg->no_length_check_enable = DEFAULT_NO_LENGTH_CHECK_ENABLE;
cfg->lgth_check_nostdr = DEFAULT_LGTH_CHECK_NOSTDR;
cfg->time_stamp_enable = DEFAULT_TIME_STAMP_ENABLE;
cfg->tx_ipg_length = DEFAULT_TX_IPG_LENGTH;
cfg->max_frame_length = DEFAULT_MAX_FRAME_LENGTH;
cfg->pause_quant = DEFAULT_PAUSE_QUANT;
#ifdef FM_TX_ECC_FRMS_ERRATA_10GMAC_A004
cfg->skip_fman11_workaround = FALSE;
#endif /* FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 */
}
int fman_tgec_init(struct tgec_regs *regs, struct tgec_cfg *cfg,
uint32_t exception_mask)
{
uint32_t tmp;
/* Config */
tmp = 0x40; /* CRC forward */
if (cfg->wan_mode_enable)
tmp |= CMD_CFG_WAN_MODE;
if (cfg->promiscuous_mode_enable)
tmp |= CMD_CFG_PROMIS_EN;
if (cfg->pause_forward_enable)
tmp |= CMD_CFG_PAUSE_FWD;
if (cfg->pause_ignore)
tmp |= CMD_CFG_PAUSE_IGNORE;
if (cfg->tx_addr_ins_enable)
tmp |= CMD_CFG_TX_ADDR_INS;
if (cfg->loopback_enable)
tmp |= CMD_CFG_LOOPBACK_EN;
if (cfg->cmd_frame_enable)
tmp |= CMD_CFG_CMD_FRM_EN;
if (cfg->rx_error_discard)
tmp |= CMD_CFG_RX_ER_DISC;
if (cfg->send_idle_enable)
tmp |= CMD_CFG_SEND_IDLE;
if (cfg->no_length_check_enable)
tmp |= CMD_CFG_NO_LEN_CHK;
if (cfg->time_stamp_enable)
tmp |= CMD_CFG_EN_TIMESTAMP;
iowrite32be(tmp, &regs->command_config);
/* Max Frame Length */
iowrite32be((uint32_t)cfg->max_frame_length, &regs->maxfrm);
/* Pause Time */
iowrite32be(cfg->pause_quant, &regs->pause_quant);
/* clear all pending events and set-up interrupts */
fman_tgec_ack_event(regs, 0xffffffff);
fman_tgec_enable_interrupt(regs, exception_mask);
return 0;
}
void fman_tgec_set_erratum_tx_fifo_corruption_10gmac_a007(struct tgec_regs *regs)
{
uint32_t tmp;
/* restore the default tx ipg Length */
tmp = (ioread32be(&regs->tx_ipg_len) & ~TGEC_TX_IPG_LENGTH_MASK) | 12;
iowrite32be(tmp, &regs->tx_ipg_len);
}

1096
drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/memac.c Normal file
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110
drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/memac.h Normal file
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/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File memac.h
@Description FM Multirate Ethernet MAC (mEMAC)
*//***************************************************************************/
#ifndef __MEMAC_H
#define __MEMAC_H
#include "std_ext.h"
#include "error_ext.h"
#include "list_ext.h"
#include "fsl_fman_memac_mii_acc.h"
#include "fm_mac.h"
#include "fsl_fman_memac.h"
#define MEMAC_default_exceptions \
((uint32_t)(MEMAC_IMASK_TSECC_ER | MEMAC_IMASK_TECC_ER | MEMAC_IMASK_RECC_ER | MEMAC_IMASK_MGI))
#define GET_EXCEPTION_FLAG(bitMask, exception) switch (exception){ \
case e_FM_MAC_EX_10G_1TX_ECC_ER: \
bitMask = MEMAC_IMASK_TECC_ER; break; \
case e_FM_MAC_EX_10G_RX_ECC_ER: \
bitMask = MEMAC_IMASK_RECC_ER; break; \
case e_FM_MAC_EX_TS_FIFO_ECC_ERR: \
bitMask = MEMAC_IMASK_TSECC_ER; break; \
case e_FM_MAC_EX_MAGIC_PACKET_INDICATION: \
bitMask = MEMAC_IMASK_MGI; break; \
default: bitMask = 0;break;}
typedef struct
{
t_FmMacControllerDriver fmMacControllerDriver; /**< Upper Mac control block */
t_Handle h_App; /**< Handle to the upper layer application */
struct memac_regs *p_MemMap; /**< Pointer to MAC memory mapped registers */
struct memac_mii_access_mem_map *p_MiiMemMap; /**< Pointer to MII memory mapped registers */
uint64_t addr; /**< MAC address of device */
e_EnetMode enetMode; /**< Ethernet physical interface */
t_FmMacExceptionCallback *f_Exception;
int mdioIrq;
t_FmMacExceptionCallback *f_Event;
bool indAddrRegUsed[MEMAC_NUM_OF_PADDRS]; /**< Whether a particular individual address recognition register is being used */
uint64_t paddr[MEMAC_NUM_OF_PADDRS]; /**< MAC address for particular individual address recognition register */
uint8_t numOfIndAddrInRegs; /**< Number of individual addresses in registers for this station. */
t_EthHash *p_MulticastAddrHash; /**< Pointer to driver's global address hash table */
t_EthHash *p_UnicastAddrHash; /**< Pointer to driver's individual address hash table */
bool debugMode;
uint8_t macId;
uint32_t exceptions;
struct memac_cfg *p_MemacDriverParam;
} t_Memac;
/* Internal PHY access */
#define PHY_MDIO_ADDR 0
/* Internal PHY Registers - SGMII */
#define PHY_SGMII_CR_PHY_RESET 0x8000
#define PHY_SGMII_CR_RESET_AN 0x0200
#define PHY_SGMII_CR_DEF_VAL 0x1140
#define PHY_SGMII_DEV_ABILITY_SGMII 0x4001
#define PHY_SGMII_DEV_ABILITY_1000X 0x01A0
#define PHY_SGMII_IF_SPEED_GIGABIT 0x0008
#define PHY_SGMII_IF_MODE_AN 0x0002
#define PHY_SGMII_IF_MODE_SGMII 0x0001
#define PHY_SGMII_IF_MODE_1000X 0x0000
#define MEMAC_TO_MII_OFFSET 0x030 /* Offset from the MEM map to the MDIO mem map */
t_Error MEMAC_MII_WritePhyReg(t_Handle h_Memac, uint8_t phyAddr, uint8_t reg, uint16_t data);
t_Error MEMAC_MII_ReadPhyReg(t_Handle h_Memac, uint8_t phyAddr, uint8_t reg, uint16_t *p_Data);
#endif /* __MEMAC_H */

78
drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/memac_mii_acc.c Normal file
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/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "error_ext.h"
#include "std_ext.h"
#include "fm_mac.h"
#include "memac.h"
#include "xx_ext.h"
#include "fm_common.h"
#include "memac_mii_acc.h"
/*****************************************************************************/
t_Error MEMAC_MII_WritePhyReg(t_Handle h_Memac,
uint8_t phyAddr,
uint8_t reg,
uint16_t data)
{
t_Memac *p_Memac = (t_Memac *)h_Memac;
SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_Memac->p_MiiMemMap, E_INVALID_HANDLE);
return (t_Error)fman_memac_mii_write_phy_reg(p_Memac->p_MiiMemMap,
phyAddr,
reg,
data,
(enum enet_speed)ENET_SPEED_FROM_MODE(p_Memac->enetMode));
}
/*****************************************************************************/
t_Error MEMAC_MII_ReadPhyReg(t_Handle h_Memac,
uint8_t phyAddr,
uint8_t reg,
uint16_t *p_Data)
{
t_Memac *p_Memac = (t_Memac *)h_Memac;
SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_Memac->p_MiiMemMap, E_INVALID_HANDLE);
return fman_memac_mii_read_phy_reg(p_Memac->p_MiiMemMap,
phyAddr,
reg,
p_Data,
(enum enet_speed)ENET_SPEED_FROM_MODE(p_Memac->enetMode));
}

73
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@ -0,0 +1,73 @@
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __MEMAC_MII_ACC_H
#define __MEMAC_MII_ACC_H
#include "std_ext.h"
/* MII Management Registers */
#define MDIO_CFG_CLK_DIV_MASK 0x0080ff80
#define MDIO_CFG_CLK_DIV_SHIFT 7
#define MDIO_CFG_HOLD_MASK 0x0000001c
#define MDIO_CFG_ENC45 0x00000040
#define MDIO_CFG_READ_ERR 0x00000002
#define MDIO_CFG_BSY 0x00000001
#define MDIO_CTL_PHY_ADDR_SHIFT 5
#define MDIO_CTL_READ 0x00008000
#define MDIO_DATA_BSY 0x80000000
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(push,1)
#endif /* defined(__MWERKS__) && ... */
/*----------------------------------------------------*/
/* MII Configuration Control Memory Map Registers */
/*----------------------------------------------------*/
typedef struct t_MemacMiiAccessMemMap
{
volatile uint32_t mdio_cfg; /* 0x030 */
volatile uint32_t mdio_ctrl; /* 0x034 */
volatile uint32_t mdio_data; /* 0x038 */
volatile uint32_t mdio_addr; /* 0x03c */
} t_MemacMiiAccessMemMap ;
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(pop)
#endif /* defined(__MWERKS__) && ... */
#endif /* __MEMAC_MII_ACC_H */

975
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/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File tgec.c
@Description FM 10G MAC ...
*//***************************************************************************/
#include "std_ext.h"
#include "string_ext.h"
#include "error_ext.h"
#include "xx_ext.h"
#include "endian_ext.h"
#include "debug_ext.h"
#include "crc_mac_addr_ext.h"
#include "fm_common.h"
#include "fsl_fman_tgec.h"
#include "tgec.h"
/*****************************************************************************/
/* Internal routines */
/*****************************************************************************/
static t_Error CheckInitParameters(t_Tgec *p_Tgec)
{
if (ENET_SPEED_FROM_MODE(p_Tgec->enetMode) < e_ENET_SPEED_10000)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Ethernet 10G MAC driver only support 10G speed"));
#if (FM_MAX_NUM_OF_10G_MACS > 0)
if (p_Tgec->macId >= FM_MAX_NUM_OF_10G_MACS)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("macId of 10G can not be greater than 0"));
#endif /* (FM_MAX_NUM_OF_10G_MACS > 0) */
if (p_Tgec->addr == 0)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Ethernet 10G MAC Must have a valid MAC Address"));
if (!p_Tgec->f_Exception)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("uninitialized f_Exception"));
if (!p_Tgec->f_Event)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("uninitialized f_Event"));
#ifdef FM_LEN_CHECK_ERRATA_FMAN_SW002
if (!p_Tgec->p_TgecDriverParam->no_length_check_enable)
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, ("LengthCheck!"));
#endif /* FM_LEN_CHECK_ERRATA_FMAN_SW002 */
return E_OK;
}
/* ......................................................................... */
static uint32_t GetMacAddrHashCode(uint64_t ethAddr)
{
uint32_t crc;
/* CRC calculation */
GET_MAC_ADDR_CRC(ethAddr, crc);
crc = GetMirror32(crc);
return crc;
}
/* ......................................................................... */
static void TgecErrException(t_Handle h_Tgec)
{
t_Tgec *p_Tgec = (t_Tgec *)h_Tgec;
uint32_t event;
struct tgec_regs *p_TgecMemMap = p_Tgec->p_MemMap;
/* do not handle MDIO events */
event = fman_tgec_get_event(p_TgecMemMap, ~(TGEC_IMASK_MDIO_SCAN_EVENT | TGEC_IMASK_MDIO_CMD_CMPL));
event &= fman_tgec_get_interrupt_mask(p_TgecMemMap);
fman_tgec_ack_event(p_TgecMemMap, event);
if (event & TGEC_IMASK_REM_FAULT)
p_Tgec->f_Exception(p_Tgec->h_App, e_FM_MAC_EX_10G_REM_FAULT);
if (event & TGEC_IMASK_LOC_FAULT)
p_Tgec->f_Exception(p_Tgec->h_App, e_FM_MAC_EX_10G_LOC_FAULT);
if (event & TGEC_IMASK_TX_ECC_ER)
p_Tgec->f_Exception(p_Tgec->h_App, e_FM_MAC_EX_10G_1TX_ECC_ER);
if (event & TGEC_IMASK_TX_FIFO_UNFL)
p_Tgec->f_Exception(p_Tgec->h_App, e_FM_MAC_EX_10G_TX_FIFO_UNFL);
if (event & TGEC_IMASK_TX_FIFO_OVFL)
p_Tgec->f_Exception(p_Tgec->h_App, e_FM_MAC_EX_10G_TX_FIFO_OVFL);
if (event & TGEC_IMASK_TX_ER)
p_Tgec->f_Exception(p_Tgec->h_App, e_FM_MAC_EX_10G_TX_ER);
if (event & TGEC_IMASK_RX_FIFO_OVFL)
p_Tgec->f_Exception(p_Tgec->h_App, e_FM_MAC_EX_10G_RX_FIFO_OVFL);
if (event & TGEC_IMASK_RX_ECC_ER)
p_Tgec->f_Exception(p_Tgec->h_App, e_FM_MAC_EX_10G_RX_ECC_ER);
if (event & TGEC_IMASK_RX_JAB_FRM)
p_Tgec->f_Exception(p_Tgec->h_App, e_FM_MAC_EX_10G_RX_JAB_FRM);
if (event & TGEC_IMASK_RX_OVRSZ_FRM)
p_Tgec->f_Exception(p_Tgec->h_App, e_FM_MAC_EX_10G_RX_OVRSZ_FRM);
if (event & TGEC_IMASK_RX_RUNT_FRM)
p_Tgec->f_Exception(p_Tgec->h_App, e_FM_MAC_EX_10G_RX_RUNT_FRM);
if (event & TGEC_IMASK_RX_FRAG_FRM)
p_Tgec->f_Exception(p_Tgec->h_App, e_FM_MAC_EX_10G_RX_FRAG_FRM);
if (event & TGEC_IMASK_RX_LEN_ER)
p_Tgec->f_Exception(p_Tgec->h_App, e_FM_MAC_EX_10G_RX_LEN_ER);
if (event & TGEC_IMASK_RX_CRC_ER)
p_Tgec->f_Exception(p_Tgec->h_App, e_FM_MAC_EX_10G_RX_CRC_ER);
if (event & TGEC_IMASK_RX_ALIGN_ER)
p_Tgec->f_Exception(p_Tgec->h_App, e_FM_MAC_EX_10G_RX_ALIGN_ER);
}
/* ......................................................................... */
static void TgecException(t_Handle h_Tgec)
{
t_Tgec *p_Tgec = (t_Tgec *)h_Tgec;
uint32_t event;
struct tgec_regs *p_TgecMemMap = p_Tgec->p_MemMap;
/* handle only MDIO events */
event = fman_tgec_get_event(p_TgecMemMap, (TGEC_IMASK_MDIO_SCAN_EVENT | TGEC_IMASK_MDIO_CMD_CMPL));
event &= fman_tgec_get_interrupt_mask(p_TgecMemMap);
fman_tgec_ack_event(p_TgecMemMap, event);
if (event & TGEC_IMASK_MDIO_SCAN_EVENT)
p_Tgec->f_Event(p_Tgec->h_App, e_FM_MAC_EX_10G_MDIO_SCAN_EVENTMDIO);
if (event & TGEC_IMASK_MDIO_CMD_CMPL)
p_Tgec->f_Event(p_Tgec->h_App, e_FM_MAC_EX_10G_MDIO_CMD_CMPL);
}
/* ......................................................................... */
static void FreeInitResources(t_Tgec *p_Tgec)
{
if (p_Tgec->mdioIrq != NO_IRQ)
{
XX_DisableIntr(p_Tgec->mdioIrq);
XX_FreeIntr(p_Tgec->mdioIrq);
}
FmUnregisterIntr(p_Tgec->fmMacControllerDriver.h_Fm, e_FM_MOD_10G_MAC, p_Tgec->macId, e_FM_INTR_TYPE_ERR);
/* release the driver's group hash table */
FreeHashTable(p_Tgec->p_MulticastAddrHash);
p_Tgec->p_MulticastAddrHash = NULL;
/* release the driver's individual hash table */
FreeHashTable(p_Tgec->p_UnicastAddrHash);
p_Tgec->p_UnicastAddrHash = NULL;
}
/*****************************************************************************/
/* 10G MAC API routines */
/*****************************************************************************/
/* ......................................................................... */
static t_Error TgecEnable(t_Handle h_Tgec, e_CommMode mode)
{
t_Tgec *p_Tgec = (t_Tgec *)h_Tgec;
SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE);
fman_tgec_enable(p_Tgec->p_MemMap, (mode & e_COMM_MODE_RX), (mode & e_COMM_MODE_TX));
return E_OK;
}
/* ......................................................................... */
static t_Error TgecDisable (t_Handle h_Tgec, e_CommMode mode)
{
t_Tgec *p_Tgec = (t_Tgec *)h_Tgec;
SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE);
fman_tgec_disable(p_Tgec->p_MemMap, (mode & e_COMM_MODE_RX), (mode & e_COMM_MODE_TX));
return E_OK;
}
/* ......................................................................... */
static t_Error TgecSetPromiscuous(t_Handle h_Tgec, bool newVal)
{
t_Tgec *p_Tgec = (t_Tgec *)h_Tgec;
SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE);
fman_tgec_set_promiscuous(p_Tgec->p_MemMap, newVal);
return E_OK;
}
/*****************************************************************************/
/* Tgec Configs modification functions */
/*****************************************************************************/
/* ......................................................................... */
static t_Error TgecConfigLoopback(t_Handle h_Tgec, bool newVal)
{
t_Tgec *p_Tgec = (t_Tgec *)h_Tgec;
SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_Tgec->p_TgecDriverParam, E_INVALID_STATE);
p_Tgec->p_TgecDriverParam->loopback_enable = newVal;
return E_OK;
}
/* ......................................................................... */
static t_Error TgecConfigWan(t_Handle h_Tgec, bool newVal)
{
t_Tgec *p_Tgec = (t_Tgec *)h_Tgec;
SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_Tgec->p_TgecDriverParam, E_INVALID_STATE);
p_Tgec->p_TgecDriverParam->wan_mode_enable = newVal;
return E_OK;
}
/* ......................................................................... */
static t_Error TgecConfigMaxFrameLength(t_Handle h_Tgec, uint16_t newVal)
{
t_Tgec *p_Tgec = (t_Tgec *)h_Tgec;
SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_Tgec->p_TgecDriverParam, E_INVALID_STATE);
p_Tgec->p_TgecDriverParam->max_frame_length = newVal;
return E_OK;
}
/* ......................................................................... */
static t_Error TgecConfigLengthCheck(t_Handle h_Tgec, bool newVal)
{
t_Tgec *p_Tgec = (t_Tgec *)h_Tgec;
UNUSED(newVal);
SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_Tgec->p_TgecDriverParam, E_INVALID_STATE);
p_Tgec->p_TgecDriverParam->no_length_check_enable = !newVal;
return E_OK;
}
/* ......................................................................... */
static t_Error TgecConfigException(t_Handle h_Tgec, e_FmMacExceptions exception, bool enable)
{
t_Tgec *p_Tgec = (t_Tgec *)h_Tgec;
uint32_t bitMask = 0;
SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_Tgec->p_TgecDriverParam, E_INVALID_STATE);
GET_EXCEPTION_FLAG(bitMask, exception);
if (bitMask)
{
if (enable)
p_Tgec->exceptions |= bitMask;
else
p_Tgec->exceptions &= ~bitMask;
}
else
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Undefined exception"));
return E_OK;
}
#ifdef FM_TX_ECC_FRMS_ERRATA_10GMAC_A004
/* ......................................................................... */
static t_Error TgecConfigSkipFman11Workaround(t_Handle h_Tgec)
{
t_Tgec *p_Tgec = (t_Tgec *)h_Tgec;
SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_Tgec->p_TgecDriverParam, E_INVALID_STATE);
p_Tgec->p_TgecDriverParam->skip_fman11_workaround = TRUE;
return E_OK;
}
#endif /* FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 */
/*****************************************************************************/
/* Tgec Run Time API functions */
/*****************************************************************************/
/* ......................................................................... */
/* backward compatibility. will be removed in the future. */
static t_Error TgecTxMacPause(t_Handle h_Tgec, uint16_t pauseTime)
{
t_Tgec *p_Tgec = (t_Tgec *)h_Tgec;
SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_STATE);
SANITY_CHECK_RETURN_ERROR(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE);
fman_tgec_set_tx_pause_frames(p_Tgec->p_MemMap, pauseTime);
return E_OK;
}
/* ......................................................................... */
static t_Error TgecSetTxPauseFrames(t_Handle h_Tgec,
uint8_t priority,
uint16_t pauseTime,
uint16_t threshTime)
{
t_Tgec *p_Tgec = (t_Tgec *)h_Tgec;
SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_STATE);
SANITY_CHECK_RETURN_ERROR(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE);
UNUSED(priority); UNUSED(threshTime);
fman_tgec_set_tx_pause_frames(p_Tgec->p_MemMap, pauseTime);
return E_OK;
}
/* ......................................................................... */
static t_Error TgecRxIgnoreMacPause(t_Handle h_Tgec, bool en)
{
t_Tgec *p_Tgec = (t_Tgec *)h_Tgec;
SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_STATE);
SANITY_CHECK_RETURN_ERROR(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE);
fman_tgec_set_rx_ignore_pause_frames(p_Tgec->p_MemMap, en);
return E_OK;
}
/* ......................................................................... */
static t_Error TgecGetStatistics(t_Handle h_Tgec, t_FmMacStatistics *p_Statistics)
{
t_Tgec *p_Tgec = (t_Tgec *)h_Tgec;
struct tgec_regs *p_TgecMemMap;
SANITY_CHECK_RETURN_ERROR(p_Tgec, E_NULL_POINTER);
SANITY_CHECK_RETURN_ERROR(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE);
SANITY_CHECK_RETURN_ERROR(p_Statistics, E_NULL_POINTER);
p_TgecMemMap = p_Tgec->p_MemMap;
p_Statistics->eStatPkts64 = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_R64);
p_Statistics->eStatPkts65to127 = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_R127);
p_Statistics->eStatPkts128to255 = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_R255);
p_Statistics->eStatPkts256to511 = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_R511);
p_Statistics->eStatPkts512to1023 = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_R1023);
p_Statistics->eStatPkts1024to1518 = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_R1518);
p_Statistics->eStatPkts1519to1522 = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_R1519X);
/* */
p_Statistics->eStatFragments = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_TRFRG);
p_Statistics->eStatJabbers = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_TRJBR);
p_Statistics->eStatsDropEvents = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_RDRP);
p_Statistics->eStatCRCAlignErrors = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_RALN);
p_Statistics->eStatUndersizePkts = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_TRUND);
p_Statistics->eStatOversizePkts = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_TROVR);
/* Pause */
p_Statistics->reStatPause = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_RXPF);
p_Statistics->teStatPause = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_TXPF);
/* MIB II */
p_Statistics->ifInOctets = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_ROCT);
p_Statistics->ifInUcastPkts = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_RUCA);
p_Statistics->ifInMcastPkts = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_RMCA);
p_Statistics->ifInBcastPkts = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_RBCA);
p_Statistics->ifInPkts = p_Statistics->ifInUcastPkts
+ p_Statistics->ifInMcastPkts
+ p_Statistics->ifInBcastPkts;
p_Statistics->ifInDiscards = 0;
p_Statistics->ifInErrors = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_RERR);
p_Statistics->ifOutOctets = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_TOCT);
p_Statistics->ifOutUcastPkts = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_TUCA);
p_Statistics->ifOutMcastPkts = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_TMCA);
p_Statistics->ifOutBcastPkts = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_TBCA);
p_Statistics->ifOutPkts = p_Statistics->ifOutUcastPkts
+ p_Statistics->ifOutMcastPkts
+ p_Statistics->ifOutBcastPkts;
p_Statistics->ifOutDiscards = 0;
p_Statistics->ifOutErrors = fman_tgec_get_counter(p_TgecMemMap, E_TGEC_COUNTER_TERR);
return E_OK;
}
/* ......................................................................... */
static t_Error TgecEnable1588TimeStamp(t_Handle h_Tgec)
{
t_Tgec *p_Tgec = (t_Tgec *)h_Tgec;
SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE);
fman_tgec_enable_1588_time_stamp(p_Tgec->p_MemMap, 1);
return E_OK;
}
/* ......................................................................... */
static t_Error TgecDisable1588TimeStamp(t_Handle h_Tgec)
{
t_Tgec *p_Tgec = (t_Tgec *)h_Tgec;
SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE);
fman_tgec_enable_1588_time_stamp(p_Tgec->p_MemMap, 0);
return E_OK;
}
/* ......................................................................... */
static t_Error TgecModifyMacAddress (t_Handle h_Tgec, t_EnetAddr *p_EnetAddr)
{
t_Tgec *p_Tgec = (t_Tgec *)h_Tgec;
SANITY_CHECK_RETURN_ERROR(p_Tgec, E_NULL_POINTER);
SANITY_CHECK_RETURN_ERROR(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE);
p_Tgec->addr = ENET_ADDR_TO_UINT64(*p_EnetAddr);
fman_tgec_set_mac_address(p_Tgec->p_MemMap, (uint8_t *)(*p_EnetAddr));
return E_OK;
}
/* ......................................................................... */
static t_Error TgecResetCounters (t_Handle h_Tgec)
{
t_Tgec *p_Tgec = (t_Tgec *)h_Tgec;
SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE);
fman_tgec_reset_stat(p_Tgec->p_MemMap);
return E_OK;
}
/* ......................................................................... */
static t_Error TgecAddExactMatchMacAddress(t_Handle h_Tgec, t_EnetAddr *p_EthAddr)
{
t_Tgec *p_Tgec = (t_Tgec *) h_Tgec;
uint64_t ethAddr;
uint8_t paddrNum;
SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE);
ethAddr = ENET_ADDR_TO_UINT64(*p_EthAddr);
if (ethAddr & GROUP_ADDRESS)
/* Multicast address has no effect in PADDR */
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Multicast address"));
/* Make sure no PADDR contains this address */
for (paddrNum = 0; paddrNum < TGEC_NUM_OF_PADDRS; paddrNum++)
if (p_Tgec->indAddrRegUsed[paddrNum])
if (p_Tgec->paddr[paddrNum] == ethAddr)
RETURN_ERROR(MAJOR, E_ALREADY_EXISTS, NO_MSG);
/* Find first unused PADDR */
for (paddrNum = 0; paddrNum < TGEC_NUM_OF_PADDRS; paddrNum++)
{
if (!(p_Tgec->indAddrRegUsed[paddrNum]))
{
/* mark this PADDR as used */
p_Tgec->indAddrRegUsed[paddrNum] = TRUE;
/* store address */
p_Tgec->paddr[paddrNum] = ethAddr;
/* put in hardware */
fman_tgec_add_addr_in_paddr(p_Tgec->p_MemMap, (uint8_t*)(*p_EthAddr)/* , paddrNum */);
p_Tgec->numOfIndAddrInRegs++;
return E_OK;
}
}
/* No free PADDR */
RETURN_ERROR(MAJOR, E_FULL, NO_MSG);
}
/* ......................................................................... */
static t_Error TgecDelExactMatchMacAddress(t_Handle h_Tgec, t_EnetAddr *p_EthAddr)
{
t_Tgec *p_Tgec = (t_Tgec *) h_Tgec;
uint64_t ethAddr;
uint8_t paddrNum;
SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE);
ethAddr = ENET_ADDR_TO_UINT64(*p_EthAddr);
/* Find used PADDR containing this address */
for (paddrNum = 0; paddrNum < TGEC_NUM_OF_PADDRS; paddrNum++)
{
if ((p_Tgec->indAddrRegUsed[paddrNum]) &&
(p_Tgec->paddr[paddrNum] == ethAddr))
{
/* mark this PADDR as not used */
p_Tgec->indAddrRegUsed[paddrNum] = FALSE;
/* clear in hardware */
fman_tgec_clear_addr_in_paddr(p_Tgec->p_MemMap /*, paddrNum */);
p_Tgec->numOfIndAddrInRegs--;
return E_OK;
}
}
RETURN_ERROR(MAJOR, E_NOT_FOUND, NO_MSG);
}
/* ......................................................................... */
static t_Error TgecAddHashMacAddress(t_Handle h_Tgec, t_EnetAddr *p_EthAddr)
{
t_Tgec *p_Tgec = (t_Tgec *)h_Tgec;
t_EthHashEntry *p_HashEntry;
uint32_t crc;
uint32_t hash;
uint64_t ethAddr;
SANITY_CHECK_RETURN_ERROR(p_Tgec, E_NULL_POINTER);
SANITY_CHECK_RETURN_ERROR(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE);
ethAddr = ENET_ADDR_TO_UINT64(*p_EthAddr);
if (!(ethAddr & GROUP_ADDRESS))
/* Unicast addresses not supported in hash */
RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, ("Unicast Address"));
/* CRC calculation */
crc = GetMacAddrHashCode(ethAddr);
hash = (crc >> TGEC_HASH_MCAST_SHIFT) & TGEC_HASH_ADR_MSK; /* Take 9 MSB bits */
/* Create element to be added to the driver hash table */
p_HashEntry = (t_EthHashEntry *)XX_Malloc(sizeof(t_EthHashEntry));
p_HashEntry->addr = ethAddr;
INIT_LIST(&p_HashEntry->node);
LIST_AddToTail(&(p_HashEntry->node), &(p_Tgec->p_MulticastAddrHash->p_Lsts[hash]));
fman_tgec_set_hash_table(p_Tgec->p_MemMap, (hash | TGEC_HASH_MCAST_EN));
return E_OK;
}
/* ......................................................................... */
static t_Error TgecDelHashMacAddress(t_Handle h_Tgec, t_EnetAddr *p_EthAddr)
{
t_Tgec *p_Tgec = (t_Tgec *)h_Tgec;
t_EthHashEntry *p_HashEntry = NULL;
t_List *p_Pos;
uint32_t crc;
uint32_t hash;
uint64_t ethAddr;
SANITY_CHECK_RETURN_ERROR(p_Tgec, E_NULL_POINTER);
SANITY_CHECK_RETURN_ERROR(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE);
ethAddr = ((*(uint64_t *)p_EthAddr) >> 16);
/* CRC calculation */
crc = GetMacAddrHashCode(ethAddr);
hash = (crc >> TGEC_HASH_MCAST_SHIFT) & TGEC_HASH_ADR_MSK; /* Take 9 MSB bits */
LIST_FOR_EACH(p_Pos, &(p_Tgec->p_MulticastAddrHash->p_Lsts[hash]))
{
p_HashEntry = ETH_HASH_ENTRY_OBJ(p_Pos);
if (p_HashEntry->addr == ethAddr)
{
LIST_DelAndInit(&p_HashEntry->node);
XX_Free(p_HashEntry);
break;
}
}
if (LIST_IsEmpty(&p_Tgec->p_MulticastAddrHash->p_Lsts[hash]))
fman_tgec_set_hash_table(p_Tgec->p_MemMap, (hash & ~TGEC_HASH_MCAST_EN));
return E_OK;
}
/* ......................................................................... */
static t_Error TgecGetId(t_Handle h_Tgec, uint32_t *macId)
{
t_Tgec *p_Tgec = (t_Tgec *)h_Tgec;
SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE);
UNUSED(p_Tgec);
UNUSED(macId);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, ("TgecGetId Not Supported"));
}
/* ......................................................................... */
static t_Error TgecGetVersion(t_Handle h_Tgec, uint32_t *macVersion)
{
t_Tgec *p_Tgec = (t_Tgec *)h_Tgec;
SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE);
*macVersion = fman_tgec_get_revision(p_Tgec->p_MemMap);
return E_OK;
}
/* ......................................................................... */
static t_Error TgecSetExcpetion(t_Handle h_Tgec, e_FmMacExceptions exception, bool enable)
{
t_Tgec *p_Tgec = (t_Tgec *)h_Tgec;
uint32_t bitMask = 0;
SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE);
GET_EXCEPTION_FLAG(bitMask, exception);
if (bitMask)
{
if (enable)
p_Tgec->exceptions |= bitMask;
else
p_Tgec->exceptions &= ~bitMask;
}
else
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Undefined exception"));
if (enable)
fman_tgec_enable_interrupt(p_Tgec->p_MemMap, bitMask);
else
fman_tgec_disable_interrupt(p_Tgec->p_MemMap, bitMask);
return E_OK;
}
/* ......................................................................... */
static uint16_t TgecGetMaxFrameLength(t_Handle h_Tgec)
{
t_Tgec *p_Tgec = (t_Tgec *)h_Tgec;
SANITY_CHECK_RETURN_VALUE(p_Tgec, E_INVALID_HANDLE, 0);
SANITY_CHECK_RETURN_VALUE(!p_Tgec->p_TgecDriverParam, E_INVALID_STATE, 0);
return fman_tgec_get_max_frame_len(p_Tgec->p_MemMap);
}
/* ......................................................................... */
#ifdef FM_TX_ECC_FRMS_ERRATA_10GMAC_A004
static t_Error TgecTxEccWorkaround(t_Tgec *p_Tgec)
{
t_Error err;
#if defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)
XX_Print("Applying 10G TX ECC workaround (10GMAC-A004) ... ");
#endif /* (DEBUG_ERRORS > 0) */
/* enable and set promiscuous */
fman_tgec_enable(p_Tgec->p_MemMap, TRUE, TRUE);
fman_tgec_set_promiscuous(p_Tgec->p_MemMap, TRUE);
err = Fm10GTxEccWorkaround(p_Tgec->fmMacControllerDriver.h_Fm, p_Tgec->macId);
/* disable */
fman_tgec_set_promiscuous(p_Tgec->p_MemMap, FALSE);
fman_tgec_enable(p_Tgec->p_MemMap, FALSE, FALSE);
fman_tgec_reset_stat(p_Tgec->p_MemMap);
fman_tgec_ack_event(p_Tgec->p_MemMap, 0xffffffff);
#if defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)
if (err)
XX_Print("FAILED!\n");
else
XX_Print("done.\n");
#endif /* (DEBUG_ERRORS > 0) */
return err;
}
#endif /* FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 */
/*****************************************************************************/
/* FM Init & Free API */
/*****************************************************************************/
/* ......................................................................... */
static t_Error TgecInit(t_Handle h_Tgec)
{
t_Tgec *p_Tgec = (t_Tgec *)h_Tgec;
struct tgec_cfg *p_TgecDriverParam;
t_EnetAddr ethAddr;
t_Error err;
SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_Tgec->p_TgecDriverParam, E_INVALID_STATE);
SANITY_CHECK_RETURN_ERROR(p_Tgec->fmMacControllerDriver.h_Fm, E_INVALID_HANDLE);
FM_GetRevision(p_Tgec->fmMacControllerDriver.h_Fm, &p_Tgec->fmMacControllerDriver.fmRevInfo);
CHECK_INIT_PARAMETERS(p_Tgec, CheckInitParameters);
p_TgecDriverParam = p_Tgec->p_TgecDriverParam;
MAKE_ENET_ADDR_FROM_UINT64(p_Tgec->addr, ethAddr);
fman_tgec_set_mac_address(p_Tgec->p_MemMap, (uint8_t *)ethAddr);
/* interrupts */
#ifdef FM_10G_REM_N_LCL_FLT_EX_10GMAC_ERRATA_SW005
{
if (p_Tgec->fmMacControllerDriver.fmRevInfo.majorRev <=2)
p_Tgec->exceptions &= ~(TGEC_IMASK_REM_FAULT | TGEC_IMASK_LOC_FAULT);
}
#endif /* FM_10G_REM_N_LCL_FLT_EX_10GMAC_ERRATA_SW005 */
#ifdef FM_TX_ECC_FRMS_ERRATA_10GMAC_A004
if (!p_Tgec->p_TgecDriverParam->skip_fman11_workaround &&
((err = TgecTxEccWorkaround(p_Tgec)) != E_OK))
{
FreeInitResources(p_Tgec);
REPORT_ERROR(MINOR, err, ("TgecTxEccWorkaround FAILED"));
}
#endif /* FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 */
err = fman_tgec_init(p_Tgec->p_MemMap, p_TgecDriverParam, p_Tgec->exceptions);
if (err)
{
FreeInitResources(p_Tgec);
RETURN_ERROR(MAJOR, err, ("This TGEC version does not support the required i/f mode"));
}
/* Max Frame Length */
err = FmSetMacMaxFrame(p_Tgec->fmMacControllerDriver.h_Fm,
e_FM_MAC_10G,
p_Tgec->fmMacControllerDriver.macId,
p_TgecDriverParam->max_frame_length);
if (err != E_OK)
{
FreeInitResources(p_Tgec);
RETURN_ERROR(MINOR, err, NO_MSG);
}
/* we consider having no IPC a non crasher... */
#ifdef FM_TX_FIFO_CORRUPTION_ERRATA_10GMAC_A007
if (p_Tgec->fmMacControllerDriver.fmRevInfo.majorRev == 2)
fman_tgec_set_erratum_tx_fifo_corruption_10gmac_a007(p_Tgec->p_MemMap);
#endif /* FM_TX_FIFO_CORRUPTION_ERRATA_10GMAC_A007 */
p_Tgec->p_MulticastAddrHash = AllocHashTable(HASH_TABLE_SIZE);
if (!p_Tgec->p_MulticastAddrHash)
{
FreeInitResources(p_Tgec);
RETURN_ERROR(MAJOR, E_NO_MEMORY, ("allocation hash table is FAILED"));
}
p_Tgec->p_UnicastAddrHash = AllocHashTable(HASH_TABLE_SIZE);
if (!p_Tgec->p_UnicastAddrHash)
{
FreeInitResources(p_Tgec);
RETURN_ERROR(MAJOR, E_NO_MEMORY, ("allocation hash table is FAILED"));
}
FmRegisterIntr(p_Tgec->fmMacControllerDriver.h_Fm,
e_FM_MOD_10G_MAC,
p_Tgec->macId,
e_FM_INTR_TYPE_ERR,
TgecErrException,
p_Tgec);
if (p_Tgec->mdioIrq != NO_IRQ)
{
XX_SetIntr(p_Tgec->mdioIrq, TgecException, p_Tgec);
XX_EnableIntr(p_Tgec->mdioIrq);
}
XX_Free(p_TgecDriverParam);
p_Tgec->p_TgecDriverParam = NULL;
return E_OK;
}
/* ......................................................................... */
static t_Error TgecFree(t_Handle h_Tgec)
{
t_Tgec *p_Tgec = (t_Tgec *)h_Tgec;
SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE);
if (p_Tgec->p_TgecDriverParam)
{
/* Called after config */
XX_Free(p_Tgec->p_TgecDriverParam);
p_Tgec->p_TgecDriverParam = NULL;
}
else
/* Called after init */
FreeInitResources(p_Tgec);
XX_Free(p_Tgec);
return E_OK;
}
/* ......................................................................... */
static void InitFmMacControllerDriver(t_FmMacControllerDriver *p_FmMacControllerDriver)
{
p_FmMacControllerDriver->f_FM_MAC_Init = TgecInit;
p_FmMacControllerDriver->f_FM_MAC_Free = TgecFree;
p_FmMacControllerDriver->f_FM_MAC_SetStatistics = NULL;
p_FmMacControllerDriver->f_FM_MAC_ConfigLoopback = TgecConfigLoopback;
p_FmMacControllerDriver->f_FM_MAC_ConfigMaxFrameLength = TgecConfigMaxFrameLength;
p_FmMacControllerDriver->f_FM_MAC_ConfigWan = TgecConfigWan;
p_FmMacControllerDriver->f_FM_MAC_ConfigPadAndCrc = NULL; /* TGEC always works with pad+crc */
p_FmMacControllerDriver->f_FM_MAC_ConfigHalfDuplex = NULL; /* half-duplex is not supported in xgec */
p_FmMacControllerDriver->f_FM_MAC_ConfigLengthCheck = TgecConfigLengthCheck;
p_FmMacControllerDriver->f_FM_MAC_ConfigException = TgecConfigException;
p_FmMacControllerDriver->f_FM_MAC_ConfigResetOnInit = NULL;
#ifdef FM_TX_ECC_FRMS_ERRATA_10GMAC_A004
p_FmMacControllerDriver->f_FM_MAC_ConfigSkipFman11Workaround= TgecConfigSkipFman11Workaround;
#endif /* FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 */
p_FmMacControllerDriver->f_FM_MAC_SetException = TgecSetExcpetion;
p_FmMacControllerDriver->f_FM_MAC_Enable1588TimeStamp = TgecEnable1588TimeStamp;
p_FmMacControllerDriver->f_FM_MAC_Disable1588TimeStamp = TgecDisable1588TimeStamp;
p_FmMacControllerDriver->f_FM_MAC_SetPromiscuous = TgecSetPromiscuous;
p_FmMacControllerDriver->f_FM_MAC_AdjustLink = NULL;
p_FmMacControllerDriver->f_FM_MAC_SetWakeOnLan = NULL;
p_FmMacControllerDriver->f_FM_MAC_RestartAutoneg = NULL;
p_FmMacControllerDriver->f_FM_MAC_Enable = TgecEnable;
p_FmMacControllerDriver->f_FM_MAC_Disable = TgecDisable;
p_FmMacControllerDriver->f_FM_MAC_Resume = NULL;
p_FmMacControllerDriver->f_FM_MAC_SetTxAutoPauseFrames = TgecTxMacPause;
p_FmMacControllerDriver->f_FM_MAC_SetTxPauseFrames = TgecSetTxPauseFrames;
p_FmMacControllerDriver->f_FM_MAC_SetRxIgnorePauseFrames = TgecRxIgnoreMacPause;
p_FmMacControllerDriver->f_FM_MAC_ResetCounters = TgecResetCounters;
p_FmMacControllerDriver->f_FM_MAC_GetStatistics = TgecGetStatistics;
p_FmMacControllerDriver->f_FM_MAC_ModifyMacAddr = TgecModifyMacAddress;
p_FmMacControllerDriver->f_FM_MAC_AddHashMacAddr = TgecAddHashMacAddress;
p_FmMacControllerDriver->f_FM_MAC_RemoveHashMacAddr = TgecDelHashMacAddress;
p_FmMacControllerDriver->f_FM_MAC_AddExactMatchMacAddr = TgecAddExactMatchMacAddress;
p_FmMacControllerDriver->f_FM_MAC_RemovelExactMatchMacAddr = TgecDelExactMatchMacAddress;
p_FmMacControllerDriver->f_FM_MAC_GetId = TgecGetId;
p_FmMacControllerDriver->f_FM_MAC_GetVersion = TgecGetVersion;
p_FmMacControllerDriver->f_FM_MAC_GetMaxFrameLength = TgecGetMaxFrameLength;
p_FmMacControllerDriver->f_FM_MAC_MII_WritePhyReg = TGEC_MII_WritePhyReg;
p_FmMacControllerDriver->f_FM_MAC_MII_ReadPhyReg = TGEC_MII_ReadPhyReg;
}
/*****************************************************************************/
/* Tgec Config Main Entry */
/*****************************************************************************/
/* ......................................................................... */
t_Handle TGEC_Config(t_FmMacParams *p_FmMacParam)
{
t_Tgec *p_Tgec;
struct tgec_cfg *p_TgecDriverParam;
uintptr_t baseAddr;
SANITY_CHECK_RETURN_VALUE(p_FmMacParam, E_NULL_POINTER, NULL);
baseAddr = p_FmMacParam->baseAddr;
/* allocate memory for the UCC GETH data structure. */
p_Tgec = (t_Tgec *)XX_Malloc(sizeof(t_Tgec));
if (!p_Tgec)
{
REPORT_ERROR(MAJOR, E_NO_MEMORY, ("10G MAC driver structure"));
return NULL;
}
memset(p_Tgec, 0, sizeof(t_Tgec));
InitFmMacControllerDriver(&p_Tgec->fmMacControllerDriver);
/* allocate memory for the 10G MAC driver parameters data structure. */
p_TgecDriverParam = (struct tgec_cfg *) XX_Malloc(sizeof(struct tgec_cfg));
if (!p_TgecDriverParam)
{
REPORT_ERROR(MAJOR, E_NO_MEMORY, ("10G MAC driver parameters"));
XX_Free(p_Tgec);
return NULL;
}
memset(p_TgecDriverParam, 0, sizeof(struct tgec_cfg));
/* Plant parameter structure pointer */
p_Tgec->p_TgecDriverParam = p_TgecDriverParam;
fman_tgec_defconfig(p_TgecDriverParam);
p_Tgec->p_MemMap = (struct tgec_regs *)UINT_TO_PTR(baseAddr);
p_Tgec->p_MiiMemMap = (t_TgecMiiAccessMemMap *)UINT_TO_PTR(baseAddr + TGEC_TO_MII_OFFSET);
p_Tgec->addr = ENET_ADDR_TO_UINT64(p_FmMacParam->addr);
p_Tgec->enetMode = p_FmMacParam->enetMode;
p_Tgec->macId = p_FmMacParam->macId;
p_Tgec->exceptions = DEFAULT_exceptions;
p_Tgec->mdioIrq = p_FmMacParam->mdioIrq;
p_Tgec->f_Exception = p_FmMacParam->f_Exception;
p_Tgec->f_Event = p_FmMacParam->f_Event;
p_Tgec->h_App = p_FmMacParam->h_App;
return p_Tgec;
}

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drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/tgec.h Normal file
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@ -0,0 +1,151 @@
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File tgec.h
@Description FM 10G MAC ...
*//***************************************************************************/
#ifndef __TGEC_H
#define __TGEC_H
#include "std_ext.h"
#include "error_ext.h"
#include "list_ext.h"
#include "enet_ext.h"
#include "tgec_mii_acc.h"
#include "fm_mac.h"
#define DEFAULT_exceptions \
((uint32_t)(TGEC_IMASK_MDIO_SCAN_EVENT | \
TGEC_IMASK_REM_FAULT | \
TGEC_IMASK_LOC_FAULT | \
TGEC_IMASK_TX_ECC_ER | \
TGEC_IMASK_TX_FIFO_UNFL | \
TGEC_IMASK_TX_FIFO_OVFL | \
TGEC_IMASK_TX_ER | \
TGEC_IMASK_RX_FIFO_OVFL | \
TGEC_IMASK_RX_ECC_ER | \
TGEC_IMASK_RX_JAB_FRM | \
TGEC_IMASK_RX_OVRSZ_FRM | \
TGEC_IMASK_RX_RUNT_FRM | \
TGEC_IMASK_RX_FRAG_FRM | \
TGEC_IMASK_RX_CRC_ER | \
TGEC_IMASK_RX_ALIGN_ER))
#define GET_EXCEPTION_FLAG(bitMask, exception) switch (exception){ \
case e_FM_MAC_EX_10G_MDIO_SCAN_EVENTMDIO: \
bitMask = TGEC_IMASK_MDIO_SCAN_EVENT ; break; \
case e_FM_MAC_EX_10G_MDIO_CMD_CMPL: \
bitMask = TGEC_IMASK_MDIO_CMD_CMPL ; break; \
case e_FM_MAC_EX_10G_REM_FAULT: \
bitMask = TGEC_IMASK_REM_FAULT ; break; \
case e_FM_MAC_EX_10G_LOC_FAULT: \
bitMask = TGEC_IMASK_LOC_FAULT ; break; \
case e_FM_MAC_EX_10G_1TX_ECC_ER: \
bitMask = TGEC_IMASK_TX_ECC_ER ; break; \
case e_FM_MAC_EX_10G_TX_FIFO_UNFL: \
bitMask = TGEC_IMASK_TX_FIFO_UNFL ; break; \
case e_FM_MAC_EX_10G_TX_FIFO_OVFL: \
bitMask = TGEC_IMASK_TX_FIFO_OVFL ; break; \
case e_FM_MAC_EX_10G_TX_ER: \
bitMask = TGEC_IMASK_TX_ER ; break; \
case e_FM_MAC_EX_10G_RX_FIFO_OVFL: \
bitMask = TGEC_IMASK_RX_FIFO_OVFL ; break; \
case e_FM_MAC_EX_10G_RX_ECC_ER: \
bitMask = TGEC_IMASK_RX_ECC_ER ; break; \
case e_FM_MAC_EX_10G_RX_JAB_FRM: \
bitMask = TGEC_IMASK_RX_JAB_FRM ; break; \
case e_FM_MAC_EX_10G_RX_OVRSZ_FRM: \
bitMask = TGEC_IMASK_RX_OVRSZ_FRM ; break; \
case e_FM_MAC_EX_10G_RX_RUNT_FRM: \
bitMask = TGEC_IMASK_RX_RUNT_FRM ; break; \
case e_FM_MAC_EX_10G_RX_FRAG_FRM: \
bitMask = TGEC_IMASK_RX_FRAG_FRM ; break; \
case e_FM_MAC_EX_10G_RX_LEN_ER: \
bitMask = TGEC_IMASK_RX_LEN_ER ; break; \
case e_FM_MAC_EX_10G_RX_CRC_ER: \
bitMask = TGEC_IMASK_RX_CRC_ER ; break; \
case e_FM_MAC_EX_10G_RX_ALIGN_ER: \
bitMask = TGEC_IMASK_RX_ALIGN_ER ; break; \
default: bitMask = 0;break;}
#define MAX_PACKET_ALIGNMENT 31
#define MAX_INTER_PACKET_GAP 0x7f
#define MAX_INTER_PALTERNATE_BEB 0x0f
#define MAX_RETRANSMISSION 0x0f
#define MAX_COLLISION_WINDOW 0x03ff
#define TGEC_NUM_OF_PADDRS 1 /* number of pattern match registers (entries) */
#define GROUP_ADDRESS 0x0000010000000000LL /* Group address bit indication */
#define HASH_TABLE_SIZE 512 /* Hash table size (= 32 bits * 8 regs) */
#define TGEC_TO_MII_OFFSET 0x1030 /* Offset from the MEM map to the MDIO mem map */
/* 10-gigabit Ethernet MAC Controller ID (10GEC_ID) */
#define TGEC_ID_ID 0xffff0000
#define TGEC_ID_MAC_VERSION 0x0000FF00
#define TGEC_ID_MAC_REV 0x000000ff
typedef struct {
t_FmMacControllerDriver fmMacControllerDriver; /**< Upper Mac control block */
t_Handle h_App; /**< Handle to the upper layer application */
struct tgec_regs *p_MemMap; /**< pointer to 10G memory mapped registers. */
t_TgecMiiAccessMemMap *p_MiiMemMap; /**< pointer to MII memory mapped registers. */
uint64_t addr; /**< MAC address of device; */
e_EnetMode enetMode; /**< Ethernet physical interface */
t_FmMacExceptionCallback *f_Exception;
int mdioIrq;
t_FmMacExceptionCallback *f_Event;
bool indAddrRegUsed[TGEC_NUM_OF_PADDRS]; /**< Whether a particular individual address recognition register is being used */
uint64_t paddr[TGEC_NUM_OF_PADDRS]; /**< MAC address for particular individual address recognition register */
uint8_t numOfIndAddrInRegs; /**< Number of individual addresses in registers for this station. */
t_EthHash *p_MulticastAddrHash; /**< pointer to driver's global address hash table */
t_EthHash *p_UnicastAddrHash; /**< pointer to driver's individual address hash table */
bool debugMode;
uint8_t macId;
uint32_t exceptions;
struct tgec_cfg *p_TgecDriverParam;
} t_Tgec;
t_Error TGEC_MII_WritePhyReg(t_Handle h_Tgec, uint8_t phyAddr, uint8_t reg, uint16_t data);
t_Error TGEC_MII_ReadPhyReg(t_Handle h_Tgec, uint8_t phyAddr, uint8_t reg, uint16_t *p_Data);
#endif /* __TGEC_H */

139
drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/tgec_mii_acc.c Normal file
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/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "error_ext.h"
#include "std_ext.h"
#include "fm_mac.h"
#include "tgec.h"
#include "xx_ext.h"
#include "fm_common.h"
/*****************************************************************************/
t_Error TGEC_MII_WritePhyReg(t_Handle h_Tgec,
uint8_t phyAddr,
uint8_t reg,
uint16_t data)
{
t_Tgec *p_Tgec = (t_Tgec *)h_Tgec;
t_TgecMiiAccessMemMap *p_MiiAccess;
uint32_t cfgStatusReg;
SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_Tgec->p_MiiMemMap, E_INVALID_HANDLE);
p_MiiAccess = p_Tgec->p_MiiMemMap;
/* Configure MII */
cfgStatusReg = GET_UINT32(p_MiiAccess->mdio_cfg_status);
cfgStatusReg &= ~MIIMCOM_DIV_MASK;
/* (one half of fm clock => 2.5Mhz) */
cfgStatusReg |=((((p_Tgec->fmMacControllerDriver.clkFreq*10)/2)/25) << MIIMCOM_DIV_SHIFT);
WRITE_UINT32(p_MiiAccess->mdio_cfg_status, cfgStatusReg);
while ((GET_UINT32(p_MiiAccess->mdio_cfg_status)) & MIIMIND_BUSY)
XX_UDelay (1);
WRITE_UINT32(p_MiiAccess->mdio_command, phyAddr);
WRITE_UINT32(p_MiiAccess->mdio_regaddr, reg);
CORE_MemoryBarrier();
while ((GET_UINT32(p_MiiAccess->mdio_cfg_status)) & MIIMIND_BUSY)
XX_UDelay (1);
WRITE_UINT32(p_MiiAccess->mdio_data, data);
CORE_MemoryBarrier();
while ((GET_UINT32(p_MiiAccess->mdio_data)) & MIIDATA_BUSY)
XX_UDelay (1);
return E_OK;
}
/*****************************************************************************/
t_Error TGEC_MII_ReadPhyReg(t_Handle h_Tgec,
uint8_t phyAddr,
uint8_t reg,
uint16_t *p_Data)
{
t_Tgec *p_Tgec = (t_Tgec *)h_Tgec;
t_TgecMiiAccessMemMap *p_MiiAccess;
uint32_t cfgStatusReg;
SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_Tgec->p_MiiMemMap, E_INVALID_HANDLE);
p_MiiAccess = p_Tgec->p_MiiMemMap;
/* Configure MII */
cfgStatusReg = GET_UINT32(p_MiiAccess->mdio_cfg_status);
cfgStatusReg &= ~MIIMCOM_DIV_MASK;
/* (one half of fm clock => 2.5Mhz) */
cfgStatusReg |=((((p_Tgec->fmMacControllerDriver.clkFreq*10)/2)/25) << MIIMCOM_DIV_SHIFT);
WRITE_UINT32(p_MiiAccess->mdio_cfg_status, cfgStatusReg);
while ((GET_UINT32(p_MiiAccess->mdio_cfg_status)) & MIIMIND_BUSY)
XX_UDelay (1);
WRITE_UINT32(p_MiiAccess->mdio_command, phyAddr);
WRITE_UINT32(p_MiiAccess->mdio_regaddr, reg);
CORE_MemoryBarrier();
while ((GET_UINT32(p_MiiAccess->mdio_cfg_status)) & MIIMIND_BUSY)
XX_UDelay (1);
WRITE_UINT32(p_MiiAccess->mdio_command, (uint32_t)(phyAddr | MIIMCOM_READ_CYCLE));
CORE_MemoryBarrier();
while ((GET_UINT32(p_MiiAccess->mdio_data)) & MIIDATA_BUSY)
XX_UDelay (1);
*p_Data = (uint16_t)GET_UINT32(p_MiiAccess->mdio_data);
cfgStatusReg = GET_UINT32(p_MiiAccess->mdio_cfg_status);
if (cfgStatusReg & MIIMIND_READ_ERROR)
RETURN_ERROR(MINOR, E_INVALID_VALUE,
("Read Error: phyAddr 0x%x, dev 0x%x, reg 0x%x, cfgStatusReg 0x%x",
((phyAddr & 0xe0)>>5), (phyAddr & 0x1f), reg, cfgStatusReg));
return E_OK;
}

80
drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/tgec_mii_acc.h Normal file
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/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __TGEC_MII_ACC_H
#define __TGEC_MII_ACC_H
#include "std_ext.h"
/* MII Management Command Register */
#define MIIMCOM_READ_POST_INCREMENT 0x00004000
#define MIIMCOM_READ_CYCLE 0x00008000
#define MIIMCOM_SCAN_CYCLE 0x00000800
#define MIIMCOM_PREAMBLE_DISABLE 0x00000400
#define MIIMCOM_MDIO_HOLD_1_REG_CLK 0
#define MIIMCOM_MDIO_HOLD_2_REG_CLK 1
#define MIIMCOM_MDIO_HOLD_3_REG_CLK 2
#define MIIMCOM_MDIO_HOLD_4_REG_CLK 3
#define MIIMCOM_DIV_MASK 0x0000ff00
#define MIIMCOM_DIV_SHIFT 8
/* MII Management Indicator Register */
#define MIIMIND_BUSY 0x00000001
#define MIIMIND_READ_ERROR 0x00000002
#define MIIDATA_BUSY 0x80000000
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(push,1)
#endif /* defined(__MWERKS__) && ... */
/*----------------------------------------------------*/
/* MII Configuration Control Memory Map Registers */
/*----------------------------------------------------*/
typedef _Packed struct t_TgecMiiAccessMemMap
{
volatile uint32_t mdio_cfg_status; /* 0x030 */
volatile uint32_t mdio_command; /* 0x034 */
volatile uint32_t mdio_data; /* 0x038 */
volatile uint32_t mdio_regaddr; /* 0x03c */
} _PackedType t_TgecMiiAccessMemMap ;
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(pop)
#endif /* defined(__MWERKS__) && ... */
#endif /* __TGEC_MII_ACC_H */

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#
# Makefile for the Freescale Ethernet controllers
#
ccflags-y += -DVERSION=\"\"
#
#Include netcomm SW specific definitions
include $(srctree)/drivers/net/ethernet/freescale/sdk_fman/ncsw_config.mk
NCSW_FM_INC = $(srctree)/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/inc
ccflags-y += -I$(NCSW_FM_INC)
obj-y += fsl-ncsw-macsec.o
fsl-ncsw-macsec-objs := fm_macsec.o fm_macsec_guest.o fm_macsec_master.o fm_macsec_secy.o

237
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/*
* Copyright 2008-2015 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_macsec.c
@Description FM MACSEC driver routines implementation.
*//***************************************************************************/
#include "std_ext.h"
#include "error_ext.h"
#include "xx_ext.h"
#include "string_ext.h"
#include "sprint_ext.h"
#include "debug_ext.h"
#include "fm_macsec.h"
/****************************************/
/* API Init unit functions */
/****************************************/
t_Handle FM_MACSEC_Config(t_FmMacsecParams *p_FmMacsecParam)
{
t_FmMacsecControllerDriver *p_FmMacsecControllerDriver;
SANITY_CHECK_RETURN_VALUE(p_FmMacsecParam, E_INVALID_HANDLE, NULL);
if (p_FmMacsecParam->guestMode)
p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)FM_MACSEC_GUEST_Config(p_FmMacsecParam);
else
p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)FM_MACSEC_MASTER_Config(p_FmMacsecParam);
if (!p_FmMacsecControllerDriver)
return NULL;
return (t_Handle)p_FmMacsecControllerDriver;
}
t_Error FM_MACSEC_Init(t_Handle h_FmMacsec)
{
t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE);
if (p_FmMacsecControllerDriver->f_FM_MACSEC_Init)
return p_FmMacsecControllerDriver->f_FM_MACSEC_Init(h_FmMacsec);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
t_Error FM_MACSEC_Free(t_Handle h_FmMacsec)
{
t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE);
if (p_FmMacsecControllerDriver->f_FM_MACSEC_Free)
return p_FmMacsecControllerDriver->f_FM_MACSEC_Free(h_FmMacsec);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
t_Error FM_MACSEC_ConfigUnknownSciFrameTreatment(t_Handle h_FmMacsec, e_FmMacsecUnknownSciFrameTreatment treatMode)
{
t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE);
if (p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigUnknownSciFrameTreatment)
return p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigUnknownSciFrameTreatment(h_FmMacsec, treatMode);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
t_Error FM_MACSEC_ConfigInvalidTagsFrameTreatment(t_Handle h_FmMacsec, bool deliverUncontrolled)
{
t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE);
if (p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigInvalidTagsFrameTreatment)
return p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigInvalidTagsFrameTreatment(h_FmMacsec, deliverUncontrolled);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
t_Error FM_MACSEC_ConfigEncryptWithNoChangedTextFrameTreatment(t_Handle h_FmMacsec, bool discardUncontrolled)
{
t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE);
if (p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigEncryptWithNoChangedTextFrameTreatment)
return p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigEncryptWithNoChangedTextFrameTreatment(h_FmMacsec, discardUncontrolled);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
t_Error FM_MACSEC_ConfigUntagFrameTreatment(t_Handle h_FmMacsec, e_FmMacsecUntagFrameTreatment treatMode)
{
t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE);
if (p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigUntagFrameTreatment)
return p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigUntagFrameTreatment(h_FmMacsec, treatMode);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
t_Error FM_MACSEC_ConfigPnExhaustionThreshold(t_Handle h_FmMacsec, uint32_t pnExhThr)
{
t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE);
if (p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigPnExhaustionThreshold)
return p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigPnExhaustionThreshold(h_FmMacsec, pnExhThr);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
t_Error FM_MACSEC_ConfigKeysUnreadable(t_Handle h_FmMacsec)
{
t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE);
if (p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigKeysUnreadable)
return p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigKeysUnreadable(h_FmMacsec);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
t_Error FM_MACSEC_ConfigSectagWithoutSCI(t_Handle h_FmMacsec)
{
t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE);
if (p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigSectagWithoutSCI)
return p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigSectagWithoutSCI(h_FmMacsec);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
t_Error FM_MACSEC_ConfigException(t_Handle h_FmMacsec, e_FmMacsecExceptions exception, bool enable)
{
t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE);
if (p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigException)
return p_FmMacsecControllerDriver->f_FM_MACSEC_ConfigException(h_FmMacsec, exception, enable);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
t_Error FM_MACSEC_GetRevision(t_Handle h_FmMacsec, uint32_t *p_MacsecRevision)
{
t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE);
if (p_FmMacsecControllerDriver->f_FM_MACSEC_GetRevision)
return p_FmMacsecControllerDriver->f_FM_MACSEC_GetRevision(h_FmMacsec, p_MacsecRevision);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
t_Error FM_MACSEC_Enable(t_Handle h_FmMacsec)
{
t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE);
if (p_FmMacsecControllerDriver->f_FM_MACSEC_Enable)
return p_FmMacsecControllerDriver->f_FM_MACSEC_Enable(h_FmMacsec);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
t_Error FM_MACSEC_Disable(t_Handle h_FmMacsec)
{
t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE);
if (p_FmMacsecControllerDriver->f_FM_MACSEC_Disable)
return p_FmMacsecControllerDriver->f_FM_MACSEC_Disable(h_FmMacsec);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
t_Error FM_MACSEC_SetException(t_Handle h_FmMacsec, e_FmMacsecExceptions exception, bool enable)
{
t_FmMacsecControllerDriver *p_FmMacsecControllerDriver = (t_FmMacsecControllerDriver *)h_FmMacsec;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecControllerDriver, E_INVALID_HANDLE);
if (p_FmMacsecControllerDriver->f_FM_MACSEC_SetException)
return p_FmMacsecControllerDriver->f_FM_MACSEC_SetException(h_FmMacsec, exception, enable);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}

203
drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MACSEC/fm_macsec.h Normal file
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/*
* Copyright 2008-2015 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_macsec.h
@Description FM MACSEC internal structures and definitions.
*//***************************************************************************/
#ifndef __FM_MACSEC_H
#define __FM_MACSEC_H
#include "error_ext.h"
#include "std_ext.h"
#include "fm_macsec_ext.h"
#include "fm_common.h"
#define __ERR_MODULE__ MODULE_FM_MACSEC
typedef struct
{
t_Error (*f_FM_MACSEC_Init) (t_Handle h_FmMacsec);
t_Error (*f_FM_MACSEC_Free) (t_Handle h_FmMacsec);
t_Error (*f_FM_MACSEC_ConfigUnknownSciFrameTreatment) (t_Handle h_FmMacsec, e_FmMacsecUnknownSciFrameTreatment treatMode);
t_Error (*f_FM_MACSEC_ConfigInvalidTagsFrameTreatment) (t_Handle h_FmMacsec, bool deliverUncontrolled);
t_Error (*f_FM_MACSEC_ConfigEncryptWithNoChangedTextFrameTreatment) (t_Handle h_FmMacsec, bool discardUncontrolled);
t_Error (*f_FM_MACSEC_ConfigChangedTextWithNoEncryptFrameTreatment) (t_Handle h_FmMacsec, bool deliverUncontrolled);
t_Error (*f_FM_MACSEC_ConfigUntagFrameTreatment) (t_Handle h_FmMacsec, e_FmMacsecUntagFrameTreatment treatMode);
t_Error (*f_FM_MACSEC_ConfigOnlyScbIsSetFrameTreatment) (t_Handle h_FmMacsec, bool deliverUncontrolled);
t_Error (*f_FM_MACSEC_ConfigPnExhaustionThreshold) (t_Handle h_FmMacsec, uint32_t pnExhThr);
t_Error (*f_FM_MACSEC_ConfigKeysUnreadable) (t_Handle h_FmMacsec);
t_Error (*f_FM_MACSEC_ConfigSectagWithoutSCI) (t_Handle h_FmMacsec);
t_Error (*f_FM_MACSEC_ConfigException) (t_Handle h_FmMacsec, e_FmMacsecExceptions exception, bool enable);
t_Error (*f_FM_MACSEC_GetRevision) (t_Handle h_FmMacsec, uint32_t *p_MacsecRevision);
t_Error (*f_FM_MACSEC_Enable) (t_Handle h_FmMacsec);
t_Error (*f_FM_MACSEC_Disable) (t_Handle h_FmMacsec);
t_Error (*f_FM_MACSEC_SetException) (t_Handle h_FmMacsec, e_FmMacsecExceptions exception, bool enable);
} t_FmMacsecControllerDriver;
t_Handle FM_MACSEC_GUEST_Config(t_FmMacsecParams *p_FmMacsecParam);
t_Handle FM_MACSEC_MASTER_Config(t_FmMacsecParams *p_FmMacsecParams);
/***********************************************************************/
/* MACSEC internal routines */
/***********************************************************************/
/**************************************************************************//**
@Group FM_MACSEC_InterModule_grp FM MACSEC Inter-Module Unit
@Description FM MACSEC Inter Module functions -
These are not User API routines but routines that may be called
from other modules. This will be the case in a single core environment,
where instead of using the XX messaging mechanism, the routines may be
called from other modules. In a multicore environment, the other modules may
be run by other cores and therefore these routines may not be called directly.
@{
*//***************************************************************************/
#define MAX_NUM_OF_SA_PER_SC 4
typedef enum
{
e_SC_RX = 0,
e_SC_TX
} e_ScType;
typedef enum
{
e_SC_SA_A = 0,
e_SC_SA_B ,
e_SC_SA_C ,
e_SC_SA_D
} e_ScSaId;
typedef struct
{
uint32_t scId;
macsecSCI_t sci;
bool replayProtect;
uint32_t replayWindow;
e_FmMacsecValidFrameBehavior validateFrames;
uint16_t confidentialityOffset;
e_FmMacsecSecYCipherSuite cipherSuite;
} t_RxScParams;
typedef struct
{
uint32_t scId;
macsecSCI_t sci;
bool protectFrames;
e_FmMacsecSciInsertionMode sciInsertionMode;
bool confidentialityEnable;
uint16_t confidentialityOffset;
e_FmMacsecSecYCipherSuite cipherSuite;
} t_TxScParams;
typedef enum e_FmMacsecGlobalExceptions {
e_FM_MACSEC_EX_TX_SC, /**< Tx Sc 0 frame discarded error. */
e_FM_MACSEC_EX_ECC /**< MACSEC memory ECC multiple-bit error. */
} e_FmMacsecGlobalExceptions;
typedef enum e_FmMacsecGlobalEvents {
e_FM_MACSEC_EV_TX_SC_NEXT_PN /**< Tx Sc 0 Next Pn exhaustion threshold reached. */
} e_FmMacsecGlobalEvents;
/**************************************************************************//**
@Description Enum for inter-module interrupts registration
*//***************************************************************************/
typedef enum e_FmMacsecEventModules{
e_FM_MACSEC_MOD_SC_TX,
e_FM_MACSEC_MOD_DUMMY_LAST
} e_FmMacsecEventModules;
typedef enum e_FmMacsecInterModuleEvent {
e_FM_MACSEC_EV_SC_TX,
e_FM_MACSEC_EV_ERR_SC_TX,
e_FM_MACSEC_EV_DUMMY_LAST
} e_FmMacsecInterModuleEvent;
#define NUM_OF_INTER_MODULE_EVENTS (NUM_OF_TX_SC * 2)
#define GET_MACSEC_MODULE_EVENT(mod, id, intrType, event) \
switch(mod){ \
case e_FM_MACSEC_MOD_SC_TX: \
event = (intrType == e_FM_INTR_TYPE_ERR) ? \
e_FM_MACSEC_EV_ERR_SC_TX: \
e_FM_MACSEC_EV_SC_TX; \
event += (uint8_t)(2 * id);break; \
break; \
default:event = e_FM_MACSEC_EV_DUMMY_LAST; \
break;}
void FmMacsecRegisterIntr(t_Handle h_FmMacsec,
e_FmMacsecEventModules module,
uint8_t modId,
e_FmIntrType intrType,
void (*f_Isr) (t_Handle h_Arg, uint32_t id),
t_Handle h_Arg);
void FmMacsecUnregisterIntr(t_Handle h_FmMacsec,
e_FmMacsecEventModules module,
uint8_t modId,
e_FmIntrType intrType);
t_Error FmMacsecAllocScs(t_Handle h_FmMacsec, e_ScType type, bool isPtp, uint32_t numOfScs, uint32_t *p_ScIds);
t_Error FmMacsecFreeScs(t_Handle h_FmMacsec, e_ScType type, uint32_t numOfScs, uint32_t *p_ScIds);
t_Error FmMacsecCreateRxSc(t_Handle h_FmMacsec, t_RxScParams *p_RxScParams);
t_Error FmMacsecDeleteRxSc(t_Handle h_FmMacsec, uint32_t scId);
t_Error FmMacsecCreateTxSc(t_Handle h_FmMacsec, t_TxScParams *p_RxScParams);
t_Error FmMacsecDeleteTxSc(t_Handle h_FmMacsec, uint32_t scId);
t_Error FmMacsecCreateRxSa(t_Handle h_FmMacsec, uint32_t scId, e_ScSaId saId, macsecAN_t an, uint32_t lowestPn, macsecSAKey_t key);
t_Error FmMacsecCreateTxSa(t_Handle h_FmMacsec, uint32_t scId, e_ScSaId saId, macsecSAKey_t key);
t_Error FmMacsecDeleteRxSa(t_Handle h_FmMacsec, uint32_t scId, e_ScSaId saId);
t_Error FmMacsecDeleteTxSa(t_Handle h_FmMacsec, uint32_t scId, e_ScSaId saId);
t_Error FmMacsecRxSaSetReceive(t_Handle h_FmMacsec, uint32_t scId, e_ScSaId saId, bool enableReceive);
t_Error FmMacsecRxSaUpdateNextPn(t_Handle h_FmMacsec, uint32_t scId, e_ScSaId saId, uint32_t updtNextPN);
t_Error FmMacsecRxSaUpdateLowestPn(t_Handle h_FmMacsec, uint32_t scId, e_ScSaId saId, uint32_t updtLowestPN);
t_Error FmMacsecTxSaSetActive(t_Handle h_FmMacsec, uint32_t scId, e_ScSaId saId, macsecAN_t an);
t_Error FmMacsecTxSaGetActive(t_Handle h_FmMacsec, uint32_t scId, macsecAN_t *p_An);
t_Error FmMacsecSetPTP(t_Handle h_FmMacsec, bool enable);
t_Error FmMacsecSetException(t_Handle h_FmMacsec, e_FmMacsecGlobalExceptions exception, uint32_t scId, bool enable);
t_Error FmMacsecSetEvent(t_Handle h_FmMacsec, e_FmMacsecGlobalEvents event, uint32_t scId, bool enable);
#endif /* __FM_MACSEC_H */

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/*
* Copyright 2008-2015 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_macsec.c
@Description FM MACSEC driver routines implementation.
*//***************************************************************************/
#include "std_ext.h"
#include "error_ext.h"
#include "xx_ext.h"
#include "string_ext.h"
#include "sprint_ext.h"
#include "debug_ext.h"
#include "fm_macsec.h"
/****************************************/
/* static functions */
/****************************************/
/****************************************/
/* API Init unit functions */
/****************************************/
t_Handle FM_MACSEC_GUEST_Config(t_FmMacsecParams *p_FmMacsecParam)
{
UNUSED(p_FmMacsecParam);
return NULL;
}

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/*
* Copyright 2008-2015 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_macsec_master.h
@Description FM MACSEC internal structures and definitions.
*//***************************************************************************/
#ifndef __FM_MACSEC_MASTER_H
#define __FM_MACSEC_MASTER_H
#include "error_ext.h"
#include "std_ext.h"
#include "fm_macsec.h"
#define MACSEC_ICV_SIZE 16
#define MACSEC_SECTAG_SIZE 16
#define MACSEC_SCI_SIZE 8
#define MACSEC_FCS_SIZE 4
/**************************************************************************//**
@Description Exceptions
*//***************************************************************************/
#define FM_MACSEC_EX_TX_SC_0 0x80000000
#define FM_MACSEC_EX_TX_SC(sc) (FM_MACSEC_EX_TX_SC_0 >> (sc))
#define FM_MACSEC_EX_ECC 0x00000001
#define GET_EXCEPTION_FLAG(bitMask, exception, id) switch (exception){ \
case e_FM_MACSEC_EX_TX_SC: \
bitMask = FM_MACSEC_EX_TX_SC(id); break; \
case e_FM_MACSEC_EX_ECC: \
bitMask = FM_MACSEC_EX_ECC; break; \
default: bitMask = 0;break;}
#define FM_MACSEC_USER_EX_SINGLE_BIT_ECC 0x80000000
#define FM_MACSEC_USER_EX_MULTI_BIT_ECC 0x40000000
#define GET_USER_EXCEPTION_FLAG(bitMask, exception) switch (exception){ \
case e_FM_MACSEC_EX_SINGLE_BIT_ECC: \
bitMask = FM_MACSEC_USER_EX_SINGLE_BIT_ECC; break; \
case e_FM_MACSEC_EX_MULTI_BIT_ECC: \
bitMask = FM_MACSEC_USER_EX_MULTI_BIT_ECC; break; \
default: bitMask = 0;break;}
/**************************************************************************//**
@Description Events
*//***************************************************************************/
#define FM_MACSEC_EV_TX_SC_0_NEXT_PN 0x80000000
#define FM_MACSEC_EV_TX_SC_NEXT_PN(sc) (FM_MACSEC_EV_TX_SC_0_NEXT_PN >> (sc))
#define GET_EVENT_FLAG(bitMask, event, id) switch (event){ \
case e_FM_MACSEC_EV_TX_SC_NEXT_PN: \
bitMask = FM_MACSEC_EV_TX_SC_NEXT_PN(id); break; \
default: bitMask = 0;break;}
/**************************************************************************//**
@Description Defaults
*//***************************************************************************/
#define DEFAULT_userExceptions (FM_MACSEC_USER_EX_SINGLE_BIT_ECC |\
FM_MACSEC_USER_EX_MULTI_BIT_ECC)
#define DEFAULT_exceptions (FM_MACSEC_EX_TX_SC(0) |\
FM_MACSEC_EX_TX_SC(1) |\
FM_MACSEC_EX_TX_SC(2) |\
FM_MACSEC_EX_TX_SC(3) |\
FM_MACSEC_EX_TX_SC(4) |\
FM_MACSEC_EX_TX_SC(5) |\
FM_MACSEC_EX_TX_SC(6) |\
FM_MACSEC_EX_TX_SC(7) |\
FM_MACSEC_EX_TX_SC(8) |\
FM_MACSEC_EX_TX_SC(9) |\
FM_MACSEC_EX_TX_SC(10) |\
FM_MACSEC_EX_TX_SC(11) |\
FM_MACSEC_EX_TX_SC(12) |\
FM_MACSEC_EX_TX_SC(13) |\
FM_MACSEC_EX_TX_SC(14) |\
FM_MACSEC_EX_TX_SC(15) |\
FM_MACSEC_EX_ECC )
#define DEFAULT_events (FM_MACSEC_EV_TX_SC_NEXT_PN(0) |\
FM_MACSEC_EV_TX_SC_NEXT_PN(1) |\
FM_MACSEC_EV_TX_SC_NEXT_PN(2) |\
FM_MACSEC_EV_TX_SC_NEXT_PN(3) |\
FM_MACSEC_EV_TX_SC_NEXT_PN(4) |\
FM_MACSEC_EV_TX_SC_NEXT_PN(5) |\
FM_MACSEC_EV_TX_SC_NEXT_PN(6) |\
FM_MACSEC_EV_TX_SC_NEXT_PN(7) |\
FM_MACSEC_EV_TX_SC_NEXT_PN(8) |\
FM_MACSEC_EV_TX_SC_NEXT_PN(9) |\
FM_MACSEC_EV_TX_SC_NEXT_PN(10) |\
FM_MACSEC_EV_TX_SC_NEXT_PN(11) |\
FM_MACSEC_EV_TX_SC_NEXT_PN(12) |\
FM_MACSEC_EV_TX_SC_NEXT_PN(13) |\
FM_MACSEC_EV_TX_SC_NEXT_PN(14) |\
FM_MACSEC_EV_TX_SC_NEXT_PN(15) )
#define DEFAULT_unknownSciFrameTreatment e_FM_MACSEC_UNKNOWN_SCI_FRAME_TREATMENT_DISCARD_BOTH
#define DEFAULT_invalidTagsFrameTreatment FALSE
#define DEFAULT_encryptWithNoChangedTextFrameTreatment FALSE
#define DEFAULT_untagFrameTreatment e_FM_MACSEC_UNTAG_FRAME_TREATMENT_DELIVER_UNCONTROLLED_DISCARD_CONTROLLED
#define DEFAULT_changedTextWithNoEncryptFrameTreatment FALSE
#define DEFAULT_onlyScbIsSetFrameTreatment FALSE
#define DEFAULT_keysUnreadable FALSE
#define DEFAULT_normalMode TRUE
#define DEFAULT_sc0ReservedForPTP FALSE
#define DEFAULT_initNextPn 1
#define DEFAULT_pnExhThr 0xffffffff
#define DEFAULT_sectagOverhead (MACSEC_ICV_SIZE + MACSEC_SECTAG_SIZE)
#define DEFAULT_mflSubtract MACSEC_FCS_SIZE
/**************************************************************************//**
@Description Memory Mapped Registers
*//***************************************************************************/
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(push,1)
#endif /* defined(__MWERKS__) && ... */
typedef _Packed struct
{
/* MACsec configuration */
volatile uint32_t cfg; /**< MACsec configuration */
volatile uint32_t et; /**< MACsec EtherType */
volatile uint8_t res1[56]; /**< reserved */
volatile uint32_t mfl; /**< Maximum Frame Length */
volatile uint32_t tpnet; /**< TX Packet Number exhaustion threshold */
volatile uint8_t res2[56]; /**< reserved */
volatile uint32_t rxsca; /**< RX SC access select */
volatile uint8_t res3[60]; /**< reserved */
volatile uint32_t txsca; /**< TX SC access select */
volatile uint8_t res4[60]; /**< reserved */
/* RX configuration, status and statistic */
volatile uint32_t rxsci1h; /**< RX Secure Channel Identifier first half */
volatile uint32_t rxsci2h; /**< RX Secure Channel Identifier second half */
volatile uint8_t res5[8]; /**< reserved */
volatile uint32_t ifio1hs; /**< ifInOctets first half Statistic */
volatile uint32_t ifio2hs; /**< ifInOctets second half Statistic */
volatile uint32_t ifiups; /**< ifInUcastPkts Statistic */
volatile uint8_t res6[4]; /**< reserved */
volatile uint32_t ifimps; /**< ifInMulticastPkts Statistic */
volatile uint32_t ifibps; /**< ifInBroadcastPkts Statistic */
volatile uint32_t rxsccfg; /**< RX Secure Channel configuration */
volatile uint32_t rpw; /**< replayWindow */
volatile uint8_t res7[16]; /**< reserved */
volatile uint32_t inov1hs; /**< InOctetsValidated first half Statistic */
volatile uint32_t inov2hs; /**< InOctetsValidated second half Statistic */
volatile uint32_t inod1hs; /**< InOctetsDecrypted first half Statistic */
volatile uint32_t inod2hs; /**< InOctetsDecrypted second half Statistic */
volatile uint32_t rxscipus; /**< RX Secure Channel InPktsUnchecked Statistic */
volatile uint32_t rxscipds; /**< RX Secure Channel InPktsDelayed Statistic */
volatile uint32_t rxscipls; /**< RX Secure Channel InPktsLate Statistic */
volatile uint8_t res8[4]; /**< reserved */
volatile uint32_t rxaninuss[MAX_NUM_OF_SA_PER_SC]; /**< RX AN 0-3 InNotUsingSA Statistic */
volatile uint32_t rxanipuss[MAX_NUM_OF_SA_PER_SC]; /**< RX AN 0-3 InPktsUnusedSA Statistic */
_Packed struct
{
volatile uint32_t rxsacs; /**< RX Security Association configuration and status */
volatile uint32_t rxsanpn; /**< RX Security Association nextPN */
volatile uint32_t rxsalpn; /**< RX Security Association lowestPN */
volatile uint32_t rxsaipos; /**< RX Security Association InPktsOK Statistic */
volatile uint32_t rxsak[4]; /**< RX Security Association key (128 bit) */
volatile uint32_t rxsah[4]; /**< RX Security Association hash (128 bit) */
volatile uint32_t rxsaipis; /**< RX Security Association InPktsInvalid Statistic */
volatile uint32_t rxsaipnvs; /**< RX Security Association InPktsNotValid Statistic */
volatile uint8_t res9[8]; /**< reserved */
} _PackedType fmMacsecRxScSa[NUM_OF_SA_PER_RX_SC];
/* TX configuration, status and statistic */
volatile uint32_t txsci1h; /**< TX Secure Channel Identifier first half */
volatile uint32_t txsci2h; /**< TX Secure Channel Identifier second half */
volatile uint8_t res10[8]; /**< reserved */
volatile uint32_t ifoo1hs; /**< ifOutOctets first half Statistic */
volatile uint32_t ifoo2hs; /**< ifOutOctets second half Statistic */
volatile uint32_t ifoups; /**< ifOutUcastPkts Statistic */
volatile uint32_t opus; /**< OutPktsUntagged Statistic */
volatile uint32_t ifomps; /**< ifOutMulticastPkts Statistic */
volatile uint32_t ifobps; /**< ifOutBroadcastPkts Statistic */
volatile uint32_t txsccfg; /**< TX Secure Channel configuration */
volatile uint32_t optls; /**< OutPktsTooLong Statistic */
volatile uint8_t res11[16]; /**< reserved */
volatile uint32_t oop1hs; /**< OutOctetsProtected first half Statistic */
volatile uint32_t oop2hs; /**< OutOctetsProtected second half Statistic */
volatile uint32_t ooe1hs; /**< OutOctetsEncrypted first half Statistic */
volatile uint32_t ooe2hs; /**< OutOctetsEncrypted second half Statistic */
volatile uint8_t res12[48]; /**< reserved */
_Packed struct
{
volatile uint32_t txsacs; /**< TX Security Association configuration and status */
volatile uint32_t txsanpn; /**< TX Security Association nextPN */
volatile uint32_t txsaopps; /**< TX Security Association OutPktsProtected Statistic */
volatile uint32_t txsaopes; /**< TX Security Association OutPktsEncrypted Statistic */
volatile uint32_t txsak[4]; /**< TX Security Association key (128 bit) */
volatile uint32_t txsah[4]; /**< TX Security Association hash (128 bit) */
volatile uint8_t res13[16]; /**< reserved */
} _PackedType fmMacsecTxScSa[NUM_OF_SA_PER_TX_SC];
volatile uint8_t res14[248]; /**< reserved */
/* Global configuration and status */
volatile uint32_t ip_rev1; /**< MACsec IP Block Revision 1 register */
volatile uint32_t ip_rev2; /**< MACsec IP Block Revision 2 register */
volatile uint32_t evr; /**< MACsec Event Register */
volatile uint32_t ever; /**< MACsec Event Enable Register */
volatile uint32_t evfr; /**< MACsec Event Force Register */
volatile uint32_t err; /**< MACsec Error Register */
volatile uint32_t erer; /**< MACsec Error Enable Register */
volatile uint32_t erfr; /**< MACsec Error Force Register */
volatile uint8_t res15[40]; /**< reserved */
volatile uint32_t meec; /**< MACsec Memory ECC Error Capture Register */
volatile uint32_t idle; /**< MACsec Idle status Register */
volatile uint8_t res16[184]; /**< reserved */
/* DEBUG */
volatile uint32_t rxec; /**< MACsec RX error capture Register */
volatile uint8_t res17[28]; /**< reserved */
volatile uint32_t txec; /**< MACsec TX error capture Register */
volatile uint8_t res18[220]; /**< reserved */
/* Macsec Rx global statistic */
volatile uint32_t ifiocp1hs; /**< ifInOctetsCp first half Statistic */
volatile uint32_t ifiocp2hs; /**< ifInOctetsCp second half Statistic */
volatile uint32_t ifiupcps; /**< ifInUcastPktsCp Statistic */
volatile uint8_t res19[4]; /**< reserved */
volatile uint32_t ifioup1hs; /**< ifInOctetsUp first half Statistic */
volatile uint32_t ifioup2hs; /**< ifInOctetsUp second half Statistic */
volatile uint32_t ifiupups; /**< ifInUcastPktsUp Statistic */
volatile uint8_t res20[4]; /**< reserved */
volatile uint32_t ifimpcps; /**< ifInMulticastPktsCp Statistic */
volatile uint32_t ifibpcps; /**< ifInBroadcastPktsCp Statistic */
volatile uint32_t ifimpups; /**< ifInMulticastPktsUp Statistic */
volatile uint32_t ifibpups; /**< ifInBroadcastPktsUp Statistic */
volatile uint32_t ipwts; /**< InPktsWithoutTag Statistic */
volatile uint32_t ipkays; /**< InPktsKaY Statistic */
volatile uint32_t ipbts; /**< InPktsBadTag Statistic */
volatile uint32_t ipsnfs; /**< InPktsSCINotFound Statistic */
volatile uint32_t ipuecs; /**< InPktsUnsupportedEC Statistic */
volatile uint32_t ipescbs; /**< InPktsEponSingleCopyBroadcast Statistic */
volatile uint32_t iptls; /**< InPktsTooLong Statistic */
volatile uint8_t res21[52]; /**< reserved */
/* Macsec Tx global statistic */
volatile uint32_t opds; /**< OutPktsDiscarded Statistic */
#if (DPAA_VERSION >= 11)
volatile uint8_t res22[124]; /**< reserved */
_Packed struct
{
volatile uint32_t rxsak[8]; /**< RX Security Association key (128/256 bit) */
volatile uint8_t res23[32]; /**< reserved */
} _PackedType rxScSaKey[NUM_OF_SA_PER_RX_SC];
_Packed struct
{
volatile uint32_t txsak[8]; /**< TX Security Association key (128/256 bit) */
volatile uint8_t res24[32]; /**< reserved */
} _PackedType txScSaKey[NUM_OF_SA_PER_TX_SC];
#endif /* (DPAA_VERSION >= 11) */
} _PackedType t_FmMacsecRegs;
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(pop)
#endif /* defined(__MWERKS__) && ... */
/**************************************************************************//**
@Description General defines
*//***************************************************************************/
#define SCI_HIGH_MASK 0xffffffff00000000LL
#define SCI_LOW_MASK 0x00000000ffffffffLL
#define LONG_SHIFT 32
#define GET_SCI_FIRST_HALF(sci) (uint32_t)((macsecSCI_t)((macsecSCI_t)(sci) & SCI_HIGH_MASK) >> LONG_SHIFT)
#define GET_SCI_SECOND_HALF(sci) (uint32_t)((macsecSCI_t)(sci) & SCI_LOW_MASK)
/**************************************************************************//**
@Description Configuration defines
*//***************************************************************************/
/* masks */
#define CFG_UECT 0x00000800
#define CFG_ESCBT 0x00000400
#define CFG_USFT 0x00000300
#define CFG_ITT 0x00000080
#define CFG_KFT 0x00000040
#define CFG_UFT 0x00000030
#define CFG_KSS 0x00000004
#define CFG_BYPN 0x00000002
#define CFG_S0I 0x00000001
#define ET_TYPE 0x0000ffff
#define MFL_MAX_LEN 0x0000ffff
#define RXSCA_SC_SEL 0x0000000f
#define TXSCA_SC_SEL 0x0000000f
#define IP_REV_1_IP_ID 0xffff0000
#define IP_REV_1_IP_MJ 0x0000ff00
#define IP_REV_1_IP_MM 0x000000ff
#define IP_REV_2_IP_INT 0x00ff0000
#define IP_REV_2_IP_ERR 0x0000ff00
#define IP_REV_2_IP_CFG 0x000000ff
#define MECC_CAP 0x80000000
#define MECC_CET 0x40000000
#define MECC_SERCNT 0x00ff0000
#define MECC_MEMADDR 0x000001ff
/* shifts */
#define CFG_UECT_SHIFT (31-20)
#define CFG_ESCBT_SHIFT (31-21)
#define CFG_USFT_SHIFT (31-23)
#define CFG_ITT_SHIFT (31-24)
#define CFG_KFT_SHIFT (31-25)
#define CFG_UFT_SHIFT (31-27)
#define CFG_KSS_SHIFT (31-29)
#define CFG_BYPN_SHIFT (31-30)
#define CFG_S0I_SHIFT (31-31)
#define IP_REV_1_IP_ID_SHIFT (31-15)
#define IP_REV_1_IP_MJ_SHIFT (31-23)
#define IP_REV_1_IP_MM_SHIFT (31-31)
#define IP_REV_2_IP_INT_SHIFT (31-15)
#define IP_REV_2_IP_ERR_SHIFT (31-23)
#define IP_REV_2_IP_CFG_SHIFT (31-31)
#define MECC_CAP_SHIFT (31-0)
#define MECC_CET_SHIFT (31-1)
#define MECC_SERCNT_SHIFT (31-15)
#define MECC_MEMADDR_SHIFT (31-31)
/**************************************************************************//**
@Description RX SC defines
*//***************************************************************************/
/* masks */
#define RX_SCCFG_SCI_EN_MASK 0x00000800
#define RX_SCCFG_RP_MASK 0x00000400
#define RX_SCCFG_VF_MASK 0x00000300
#define RX_SCCFG_CO_MASK 0x0000003f
/* shifts */
#define RX_SCCFG_SCI_EN_SHIFT (31-20)
#define RX_SCCFG_RP_SHIFT (31-21)
#define RX_SCCFG_VF_SHIFT (31-23)
#define RX_SCCFG_CO_SHIFT (31-31)
#define RX_SCCFG_CS_SHIFT (31-7)
/**************************************************************************//**
@Description RX SA defines
*//***************************************************************************/
/* masks */
#define RX_SACFG_ACTIVE 0x80000000
#define RX_SACFG_AN_MASK 0x00000006
#define RX_SACFG_EN_MASK 0x00000001
/* shifts */
#define RX_SACFG_AN_SHIFT (31-30)
#define RX_SACFG_EN_SHIFT (31-31)
/**************************************************************************//**
@Description TX SC defines
*//***************************************************************************/
/* masks */
#define TX_SCCFG_AN_MASK 0x000c0000
#define TX_SCCFG_ASA_MASK 0x00020000
#define TX_SCCFG_SCE_MASK 0x00010000
#define TX_SCCFG_CO_MASK 0x00003f00
#define TX_SCCFG_CE_MASK 0x00000010
#define TX_SCCFG_PF_MASK 0x00000008
#define TX_SCCFG_AIS_MASK 0x00000004
#define TX_SCCFG_UES_MASK 0x00000002
#define TX_SCCFG_USCB_MASK 0x00000001
/* shifts */
#define TX_SCCFG_AN_SHIFT (31-13)
#define TX_SCCFG_ASA_SHIFT (31-14)
#define TX_SCCFG_SCE_SHIFT (31-15)
#define TX_SCCFG_CO_SHIFT (31-23)
#define TX_SCCFG_CE_SHIFT (31-27)
#define TX_SCCFG_PF_SHIFT (31-28)
#define TX_SCCFG_AIS_SHIFT (31-29)
#define TX_SCCFG_UES_SHIFT (31-30)
#define TX_SCCFG_USCB_SHIFT (31-31)
#define TX_SCCFG_CS_SHIFT (31-7)
/**************************************************************************//**
@Description TX SA defines
*//***************************************************************************/
/* masks */
#define TX_SACFG_ACTIVE 0x80000000
typedef struct
{
void (*f_Isr) (t_Handle h_Arg, uint32_t id);
t_Handle h_SrcHandle;
} t_FmMacsecIntrSrc;
typedef struct
{
e_FmMacsecUnknownSciFrameTreatment unknownSciTreatMode;
bool invalidTagsDeliverUncontrolled;
bool changedTextWithNoEncryptDeliverUncontrolled;
bool onlyScbIsSetDeliverUncontrolled;
bool encryptWithNoChangedTextDiscardUncontrolled;
e_FmMacsecUntagFrameTreatment untagTreatMode;
uint32_t pnExhThr;
bool keysUnreadable;
bool byPassMode;
bool reservedSc0;
uint32_t sectagOverhead;
uint32_t mflSubtract;
} t_FmMacsecDriverParam;
typedef struct
{
t_FmMacsecControllerDriver fmMacsecControllerDriver;
t_Handle h_Fm;
t_FmMacsecRegs *p_FmMacsecRegs;
t_Handle h_FmMac; /**< A handle to the FM MAC object related to */
char fmMacsecModuleName[MODULE_NAME_SIZE];
t_FmMacsecIntrSrc intrMng[NUM_OF_INTER_MODULE_EVENTS];
uint32_t events;
uint32_t exceptions;
uint32_t userExceptions;
t_FmMacsecExceptionsCallback *f_Exception; /**< Exception Callback Routine */
t_Handle h_App; /**< A handle to an application layer object; This handle will
be passed by the driver upon calling the above callbacks */
bool rxScTable[NUM_OF_RX_SC];
uint32_t numRxScAvailable;
bool txScTable[NUM_OF_TX_SC];
uint32_t numTxScAvailable;
t_Handle rxScSpinLock;
t_Handle txScSpinLock;
t_FmMacsecDriverParam *p_FmMacsecDriverParam;
} t_FmMacsec;
#endif /* __FM_MACSEC_MASTER_H */

883
drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MACSEC/fm_macsec_secy.c Normal file
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@ -0,0 +1,883 @@
/*
* Copyright 2008-2015 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_macsec_secy.c
@Description FM MACSEC SECY driver routines implementation.
*//***************************************************************************/
#include "std_ext.h"
#include "error_ext.h"
#include "xx_ext.h"
#include "string_ext.h"
#include "sprint_ext.h"
#include "fm_macsec_secy.h"
/****************************************/
/* static functions */
/****************************************/
static void FmMacsecSecYExceptionsIsr(t_Handle h_FmMacsecSecY, uint32_t id)
{
t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
UNUSED(id);
SANITY_CHECK_RETURN(p_FmMacsecSecY, E_INVALID_HANDLE);
if (p_FmMacsecSecY->exceptions & FM_MACSEC_SECY_EX_FRAME_DISCARDED)
p_FmMacsecSecY->f_Exception(p_FmMacsecSecY->h_App, e_FM_MACSEC_SECY_EX_FRAME_DISCARDED);
}
static void FmMacsecSecYEventsIsr(t_Handle h_FmMacsecSecY, uint32_t id)
{
t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
UNUSED(id);
SANITY_CHECK_RETURN(p_FmMacsecSecY, E_INVALID_HANDLE);
if (p_FmMacsecSecY->events & FM_MACSEC_SECY_EV_NEXT_PN)
p_FmMacsecSecY->f_Event(p_FmMacsecSecY->h_App, e_FM_MACSEC_SECY_EV_NEXT_PN);
}
static t_Error CheckFmMacsecSecYParameters(t_FmMacsecSecY *p_FmMacsecSecY)
{
if (!p_FmMacsecSecY->f_Exception)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Exceptions callback not provided"));
if (!p_FmMacsecSecY->f_Event)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Events callback not provided"));
if (!p_FmMacsecSecY->numOfRxSc)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Num of Rx Scs must be greater than '0'"));
return E_OK;
}
static t_Handle FmMacsecSecYCreateSc(t_FmMacsecSecY *p_FmMacsecSecY,
macsecSCI_t sci,
e_FmMacsecSecYCipherSuite cipherSuite,
e_ScType type)
{
t_SecYSc *p_ScTable;
void *p_Params;
uint32_t numOfSc,i;
t_Error err = E_OK;
t_RxScParams rxScParams;
t_TxScParams txScParams;
ASSERT_COND(p_FmMacsecSecY);
ASSERT_COND(p_FmMacsecSecY->h_FmMacsec);
if (type == e_SC_RX)
{
memset(&rxScParams, 0, sizeof(rxScParams));
i = (NUM_OF_RX_SC - 1);
p_ScTable = p_FmMacsecSecY->p_RxSc;
numOfSc = p_FmMacsecSecY->numOfRxSc;
rxScParams.confidentialityOffset = p_FmMacsecSecY->confidentialityOffset;
rxScParams.replayProtect = p_FmMacsecSecY->replayProtect;
rxScParams.replayWindow = p_FmMacsecSecY->replayWindow;
rxScParams.validateFrames = p_FmMacsecSecY->validateFrames;
rxScParams.cipherSuite = cipherSuite;
p_Params = &rxScParams;
}
else
{
memset(&txScParams, 0, sizeof(txScParams));
i = (NUM_OF_TX_SC - 1);
p_ScTable = p_FmMacsecSecY->p_TxSc;
numOfSc = p_FmMacsecSecY->numOfTxSc;
txScParams.sciInsertionMode = p_FmMacsecSecY->sciInsertionMode;
txScParams.protectFrames = p_FmMacsecSecY->protectFrames;
txScParams.confidentialityEnable = p_FmMacsecSecY->confidentialityEnable;
txScParams.confidentialityOffset = p_FmMacsecSecY->confidentialityOffset;
txScParams.cipherSuite = cipherSuite;
p_Params = &txScParams;
}
for (i=0;i<numOfSc;i++)
if (!p_ScTable[i].inUse)
break;
if (i == numOfSc)
{
REPORT_ERROR(MAJOR, E_FULL, ("FM MACSEC SECY SC"));
return NULL;
}
if (type == e_SC_RX)
{
((t_RxScParams *)p_Params)->scId = p_ScTable[i].scId;
((t_RxScParams *)p_Params)->sci = sci;
if ((err = FmMacsecCreateRxSc(p_FmMacsecSecY->h_FmMacsec, (t_RxScParams *)p_Params)) != E_OK)
{
REPORT_ERROR(MAJOR, E_NO_MEMORY, ("FM MACSEC SECY RX SC"));
return NULL;
}
}
else
{
((t_TxScParams *)p_Params)->scId = p_ScTable[i].scId;
((t_TxScParams *)p_Params)->sci = sci;
if ((err = FmMacsecCreateTxSc(p_FmMacsecSecY->h_FmMacsec, (t_TxScParams *)p_Params)) != E_OK)
{
REPORT_ERROR(MAJOR, E_NO_MEMORY, ("FM MACSEC SECY TX SC"));
return NULL;
}
}
p_ScTable[i].inUse = TRUE;
return &p_ScTable[i];
}
static t_Error FmMacsecSecYDeleteSc(t_FmMacsecSecY *p_FmMacsecSecY, t_SecYSc *p_FmSecYSc, e_ScType type)
{
t_Error err = E_OK;
ASSERT_COND(p_FmMacsecSecY);
ASSERT_COND(p_FmMacsecSecY->h_FmMacsec);
ASSERT_COND(p_FmSecYSc);
if (type == e_SC_RX)
{
if ((err = FmMacsecDeleteRxSc(p_FmMacsecSecY->h_FmMacsec, p_FmSecYSc->scId)) != E_OK)
RETURN_ERROR(MINOR, err, NO_MSG);
}
else
if ((err = FmMacsecDeleteTxSc(p_FmMacsecSecY->h_FmMacsec, p_FmSecYSc->scId)) != E_OK)
RETURN_ERROR(MINOR, err, NO_MSG);
p_FmSecYSc->inUse = FALSE;
return err;
}
/****************************************/
/* API Init unit functions */
/****************************************/
t_Handle FM_MACSEC_SECY_Config(t_FmMacsecSecYParams *p_FmMacsecSecYParam)
{
t_FmMacsecSecY *p_FmMacsecSecY;
/* Allocate FM MACSEC structure */
p_FmMacsecSecY = (t_FmMacsecSecY *) XX_Malloc(sizeof(t_FmMacsecSecY));
if (!p_FmMacsecSecY)
{
REPORT_ERROR(MAJOR, E_NO_MEMORY, ("FM MACSEC SECY driver structure"));
return NULL;
}
memset(p_FmMacsecSecY, 0, sizeof(t_FmMacsecSecY));
/* Allocate the FM MACSEC driver's parameters structure */
p_FmMacsecSecY->p_FmMacsecSecYDriverParam = (t_FmMacsecSecYDriverParam *)XX_Malloc(sizeof(t_FmMacsecSecYDriverParam));
if (!p_FmMacsecSecY->p_FmMacsecSecYDriverParam)
{
XX_Free(p_FmMacsecSecY);
REPORT_ERROR(MAJOR, E_NO_MEMORY, ("FM MACSEC SECY driver parameters"));
return NULL;
}
memset(p_FmMacsecSecY->p_FmMacsecSecYDriverParam, 0, sizeof(t_FmMacsecSecYDriverParam));
/* Initialize FM MACSEC SECY parameters which will be kept by the driver */
p_FmMacsecSecY->h_FmMacsec = p_FmMacsecSecYParam->h_FmMacsec;
p_FmMacsecSecY->f_Event = p_FmMacsecSecYParam->f_Event;
p_FmMacsecSecY->f_Exception = p_FmMacsecSecYParam->f_Exception;
p_FmMacsecSecY->h_App = p_FmMacsecSecYParam->h_App;
p_FmMacsecSecY->confidentialityEnable = DEFAULT_confidentialityEnable;
p_FmMacsecSecY->confidentialityOffset = DEFAULT_confidentialityOffset;
p_FmMacsecSecY->validateFrames = DEFAULT_validateFrames;
p_FmMacsecSecY->replayProtect = DEFAULT_replayEnable;
p_FmMacsecSecY->replayWindow = DEFAULT_replayWindow;
p_FmMacsecSecY->protectFrames = DEFAULT_protectFrames;
p_FmMacsecSecY->sciInsertionMode = DEFAULT_sciInsertionMode;
p_FmMacsecSecY->isPointToPoint = DEFAULT_ptp;
p_FmMacsecSecY->numOfRxSc = p_FmMacsecSecYParam->numReceiveChannels;
p_FmMacsecSecY->numOfTxSc = DEFAULT_numOfTxSc;
p_FmMacsecSecY->exceptions = DEFAULT_exceptions;
p_FmMacsecSecY->events = DEFAULT_events;
memcpy(&p_FmMacsecSecY->p_FmMacsecSecYDriverParam->txScParams,
&p_FmMacsecSecYParam->txScParams,
sizeof(t_FmMacsecSecYSCParams));
return p_FmMacsecSecY;
}
t_Error FM_MACSEC_SECY_Init(t_Handle h_FmMacsecSecY)
{
t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
t_FmMacsecSecYDriverParam *p_FmMacsecSecYDriverParam = NULL;
uint32_t rxScIds[NUM_OF_RX_SC], txScIds[NUM_OF_TX_SC], i, j;
t_Error err;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_HANDLE);
CHECK_INIT_PARAMETERS(p_FmMacsecSecY, CheckFmMacsecSecYParameters);
p_FmMacsecSecYDriverParam = p_FmMacsecSecY->p_FmMacsecSecYDriverParam;
if ((p_FmMacsecSecY->isPointToPoint) &&
((err = FmMacsecSetPTP(p_FmMacsecSecY->h_FmMacsec, TRUE)) != E_OK))
RETURN_ERROR(MAJOR, err, ("Can't set Poin-to-Point"));
/* Rx Sc Allocation */
p_FmMacsecSecY->p_RxSc = (t_SecYSc *)XX_Malloc(sizeof(t_SecYSc) * p_FmMacsecSecY->numOfRxSc);
if (!p_FmMacsecSecY->p_RxSc)
RETURN_ERROR(MAJOR, E_NO_MEMORY, ("FM MACSEC SECY RX SC"));
memset(p_FmMacsecSecY->p_RxSc, 0, sizeof(t_SecYSc) * p_FmMacsecSecY->numOfRxSc);
if ((err = FmMacsecAllocScs(p_FmMacsecSecY->h_FmMacsec, e_SC_RX, p_FmMacsecSecY->isPointToPoint, p_FmMacsecSecY->numOfRxSc, rxScIds)) != E_OK)
{
if (p_FmMacsecSecY->p_TxSc)
XX_Free(p_FmMacsecSecY->p_TxSc);
if (p_FmMacsecSecY->p_RxSc)
XX_Free(p_FmMacsecSecY->p_RxSc);
return ERROR_CODE(err);
}
for (i=0; i<p_FmMacsecSecY->numOfRxSc; i++)
{
p_FmMacsecSecY->p_RxSc[i].scId = rxScIds[i];
p_FmMacsecSecY->p_RxSc[i].type = e_SC_RX;
for (j=0; j<MAX_NUM_OF_SA_PER_SC;j++)
p_FmMacsecSecY->p_RxSc[i].sa[j].saId = (e_ScSaId)SECY_AN_FREE_VALUE;
}
/* Tx Sc Allocation */
p_FmMacsecSecY->p_TxSc = (t_SecYSc *)XX_Malloc(sizeof(t_SecYSc) * p_FmMacsecSecY->numOfTxSc);
if (!p_FmMacsecSecY->p_TxSc)
RETURN_ERROR(MAJOR, E_NO_MEMORY, ("FM MACSEC SECY TX SC"));
memset(p_FmMacsecSecY->p_TxSc, 0, sizeof(t_SecYSc) * p_FmMacsecSecY->numOfTxSc);
if ((err = FmMacsecAllocScs(p_FmMacsecSecY->h_FmMacsec, e_SC_TX, p_FmMacsecSecY->isPointToPoint, p_FmMacsecSecY->numOfTxSc, txScIds)) != E_OK)
{
if (p_FmMacsecSecY->p_TxSc)
XX_Free(p_FmMacsecSecY->p_TxSc);
if (p_FmMacsecSecY->p_RxSc)
XX_Free(p_FmMacsecSecY->p_RxSc);
return ERROR_CODE(err);
}
for (i=0; i<p_FmMacsecSecY->numOfTxSc; i++)
{
p_FmMacsecSecY->p_TxSc[i].scId = txScIds[i];
p_FmMacsecSecY->p_TxSc[i].type = e_SC_TX;
for (j=0; j<MAX_NUM_OF_SA_PER_SC;j++)
p_FmMacsecSecY->p_TxSc[i].sa[j].saId = (e_ScSaId)SECY_AN_FREE_VALUE;
FmMacsecRegisterIntr(p_FmMacsecSecY->h_FmMacsec,
e_FM_MACSEC_MOD_SC_TX,
(uint8_t)txScIds[i],
e_FM_INTR_TYPE_ERR,
FmMacsecSecYExceptionsIsr,
p_FmMacsecSecY);
FmMacsecRegisterIntr(p_FmMacsecSecY->h_FmMacsec,
e_FM_MACSEC_MOD_SC_TX,
(uint8_t)txScIds[i],
e_FM_INTR_TYPE_NORMAL,
FmMacsecSecYEventsIsr,
p_FmMacsecSecY);
if (p_FmMacsecSecY->exceptions & FM_MACSEC_SECY_EX_FRAME_DISCARDED)
FmMacsecSetException(p_FmMacsecSecY->h_FmMacsec, e_FM_MACSEC_EX_TX_SC, txScIds[i], TRUE);
if (p_FmMacsecSecY->events & FM_MACSEC_SECY_EV_NEXT_PN)
FmMacsecSetEvent(p_FmMacsecSecY->h_FmMacsec, e_FM_MACSEC_EV_TX_SC_NEXT_PN, txScIds[i], TRUE);
}
FmMacsecSecYCreateSc(p_FmMacsecSecY,
p_FmMacsecSecYDriverParam->txScParams.sci,
p_FmMacsecSecYDriverParam->txScParams.cipherSuite,
e_SC_TX);
XX_Free(p_FmMacsecSecYDriverParam);
p_FmMacsecSecY->p_FmMacsecSecYDriverParam = NULL;
return E_OK;
}
t_Error FM_MACSEC_SECY_Free(t_Handle h_FmMacsecSecY)
{
t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
t_Error err = E_OK;
uint32_t rxScIds[NUM_OF_RX_SC], txScIds[NUM_OF_TX_SC], i;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
if (p_FmMacsecSecY->isPointToPoint)
FmMacsecSetPTP(p_FmMacsecSecY->h_FmMacsec, FALSE);
if (p_FmMacsecSecY->p_RxSc)
{
for (i=0; i<p_FmMacsecSecY->numOfRxSc; i++)
rxScIds[i] = p_FmMacsecSecY->p_RxSc[i].scId;
if ((err = FmMacsecFreeScs(p_FmMacsecSecY->h_FmMacsec, e_SC_RX, p_FmMacsecSecY->numOfRxSc, rxScIds)) != E_OK)
return ERROR_CODE(err);
XX_Free(p_FmMacsecSecY->p_RxSc);
}
if (p_FmMacsecSecY->p_TxSc)
{
FmMacsecSecYDeleteSc(p_FmMacsecSecY, &p_FmMacsecSecY->p_TxSc[0], e_SC_TX);
for (i=0; i<p_FmMacsecSecY->numOfTxSc; i++) {
txScIds[i] = p_FmMacsecSecY->p_TxSc[i].scId;
FmMacsecUnregisterIntr(p_FmMacsecSecY->h_FmMacsec,
e_FM_MACSEC_MOD_SC_TX,
(uint8_t)txScIds[i],
e_FM_INTR_TYPE_ERR);
FmMacsecUnregisterIntr(p_FmMacsecSecY->h_FmMacsec,
e_FM_MACSEC_MOD_SC_TX,
(uint8_t)txScIds[i],
e_FM_INTR_TYPE_NORMAL);
if (p_FmMacsecSecY->exceptions & FM_MACSEC_SECY_EX_FRAME_DISCARDED)
FmMacsecSetException(p_FmMacsecSecY->h_FmMacsec, e_FM_MACSEC_EX_TX_SC, txScIds[i], FALSE);
if (p_FmMacsecSecY->events & FM_MACSEC_SECY_EV_NEXT_PN)
FmMacsecSetEvent(p_FmMacsecSecY->h_FmMacsec, e_FM_MACSEC_EV_TX_SC_NEXT_PN, txScIds[i], FALSE);
}
if ((err = FmMacsecFreeScs(p_FmMacsecSecY->h_FmMacsec, e_SC_TX, p_FmMacsecSecY->numOfTxSc, txScIds)) != E_OK)
return ERROR_CODE(err);
XX_Free(p_FmMacsecSecY->p_TxSc);
}
XX_Free(p_FmMacsecSecY);
return err;
}
t_Error FM_MACSEC_SECY_ConfigSciInsertionMode(t_Handle h_FmMacsecSecY, e_FmMacsecSciInsertionMode sciInsertionMode)
{
t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
p_FmMacsecSecY->sciInsertionMode = sciInsertionMode;
return E_OK;
}
t_Error FM_MACSEC_SECY_ConfigProtectFrames(t_Handle h_FmMacsecSecY, bool protectFrames)
{
t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
p_FmMacsecSecY->protectFrames = protectFrames;
return E_OK;
}
t_Error FM_MACSEC_SECY_ConfigReplayWindow(t_Handle h_FmMacsecSecY, bool replayProtect, uint32_t replayWindow)
{
t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
p_FmMacsecSecY->replayProtect = replayProtect;
p_FmMacsecSecY->replayWindow = replayWindow;
return E_OK;
}
t_Error FM_MACSEC_SECY_ConfigValidationMode(t_Handle h_FmMacsecSecY, e_FmMacsecValidFrameBehavior validateFrames)
{
t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
p_FmMacsecSecY->validateFrames = validateFrames;
return E_OK;
}
t_Error FM_MACSEC_SECY_ConfigConfidentiality(t_Handle h_FmMacsecSecY, bool confidentialityEnable, uint16_t confidentialityOffset)
{
t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
p_FmMacsecSecY->confidentialityEnable = confidentialityEnable;
p_FmMacsecSecY->confidentialityOffset = confidentialityOffset;
return E_OK;
}
t_Error FM_MACSEC_SECY_ConfigPointToPoint(t_Handle h_FmMacsecSecY)
{
t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
p_FmMacsecSecY->numOfRxSc = 1;
p_FmMacsecSecY->isPointToPoint = TRUE;
p_FmMacsecSecY->sciInsertionMode = e_FM_MACSEC_SCI_INSERTION_MODE_IMPLICT_PTP;
return E_OK;
}
t_Error FM_MACSEC_SECY_ConfigException(t_Handle h_FmMacsecSecY, e_FmMacsecSecYExceptions exception, bool enable)
{
t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
uint32_t bitMask = 0;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
GET_EXCEPTION_FLAG(bitMask, exception);
if (bitMask)
{
if (enable)
p_FmMacsecSecY->exceptions |= bitMask;
else
p_FmMacsecSecY->exceptions &= ~bitMask;
}
else
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Undefined exception"));
return E_OK;
}
t_Error FM_MACSEC_SECY_ConfigEvent(t_Handle h_FmMacsecSecY, e_FmMacsecSecYEvents event, bool enable)
{
t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
uint32_t bitMask = 0;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
GET_EVENT_FLAG(bitMask, event);
if (bitMask)
{
if (enable)
p_FmMacsecSecY->events |= bitMask;
else
p_FmMacsecSecY->events &= ~bitMask;
}
else
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Undefined event"));
return E_OK;
}
t_Handle FM_MACSEC_SECY_CreateRxSc(t_Handle h_FmMacsecSecY, t_FmMacsecSecYSCParams *p_ScParams)
{
t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
SANITY_CHECK_RETURN_VALUE(p_FmMacsecSecY, E_INVALID_HANDLE, NULL);
SANITY_CHECK_RETURN_VALUE(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE, NULL);
SANITY_CHECK_RETURN_VALUE(p_ScParams, E_NULL_POINTER, NULL);
SANITY_CHECK_RETURN_VALUE(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE, NULL);
return FmMacsecSecYCreateSc(p_FmMacsecSecY, p_ScParams->sci, p_ScParams->cipherSuite, e_SC_RX);
}
t_Error FM_MACSEC_SECY_DeleteRxSc(t_Handle h_FmMacsecSecY, t_Handle h_Sc)
{
t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
t_SecYSc *p_FmSecYSc = (t_SecYSc *)h_Sc;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE);
return FmMacsecSecYDeleteSc(p_FmMacsecSecY, p_FmSecYSc, e_SC_RX);
}
t_Error FM_MACSEC_SECY_CreateRxSa(t_Handle h_FmMacsecSecY, t_Handle h_Sc, macsecAN_t an, uint32_t lowestPn, macsecSAKey_t key)
{
t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
t_SecYSc *p_FmSecYSc = (t_SecYSc *)h_Sc;
t_Error err = E_OK;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(an < MAX_NUM_OF_SA_PER_SC, E_INVALID_STATE);
if (p_FmSecYSc->sa[an].saId != SECY_AN_FREE_VALUE)
RETURN_ERROR(MINOR, E_INVALID_STATE, ("An %d is already assigned",an));
if ((err = FmMacsecCreateRxSa(p_FmMacsecSecY->h_FmMacsec, p_FmSecYSc->scId, (e_ScSaId)p_FmSecYSc->numOfSa, an, lowestPn, key)) != E_OK)
RETURN_ERROR(MINOR, err, NO_MSG);
p_FmSecYSc->sa[an].saId = (e_ScSaId)p_FmSecYSc->numOfSa++;
return err;
}
t_Error FM_MACSEC_SECY_DeleteRxSa(t_Handle h_FmMacsecSecY, t_Handle h_Sc, macsecAN_t an)
{
t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
t_SecYSc *p_FmSecYSc = (t_SecYSc *)h_Sc;
t_Error err = E_OK;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(an < MAX_NUM_OF_SA_PER_SC, E_INVALID_STATE);
if (p_FmSecYSc->sa[an].saId == SECY_AN_FREE_VALUE)
RETURN_ERROR(MINOR, E_INVALID_STATE, ("An %d is already deleted",an));
if ((err = FmMacsecDeleteRxSa(p_FmMacsecSecY->h_FmMacsec, p_FmSecYSc->scId, p_FmSecYSc->sa[an].saId)) != E_OK)
RETURN_ERROR(MINOR, err, NO_MSG);
p_FmSecYSc->numOfSa--;
p_FmSecYSc->sa[an].saId = (e_ScSaId)SECY_AN_FREE_VALUE;
/* TODO - check if statistics need to be read*/
return err;
}
t_Error FM_MACSEC_SECY_RxSaEnableReceive(t_Handle h_FmMacsecSecY, t_Handle h_Sc, macsecAN_t an)
{
t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
t_SecYSc *p_FmSecYSc = (t_SecYSc *)h_Sc;
t_Error err = E_OK;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(an < MAX_NUM_OF_SA_PER_SC, E_INVALID_STATE);
if (p_FmSecYSc->sa[an].saId == SECY_AN_FREE_VALUE)
RETURN_ERROR(MINOR, E_INVALID_STATE, ("An %d is not configured",an));
if ((err = FmMacsecRxSaSetReceive(p_FmMacsecSecY->h_FmMacsec,p_FmSecYSc->scId, p_FmSecYSc->sa[an].saId, TRUE)) != E_OK)
RETURN_ERROR(MINOR, err, NO_MSG);
p_FmSecYSc->sa[an].active = TRUE;
return err;
}
t_Error FM_MACSEC_SECY_RxSaDisableReceive(t_Handle h_FmMacsecSecY, t_Handle h_Sc, macsecAN_t an)
{
t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
t_SecYSc *p_FmSecYSc = (t_SecYSc *)h_Sc;
t_Error err = E_OK;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(an < MAX_NUM_OF_SA_PER_SC, E_INVALID_STATE);
if (p_FmSecYSc->sa[an].saId == SECY_AN_FREE_VALUE)
RETURN_ERROR(MINOR, E_INVALID_STATE, ("An %d is not configured",an));
if ((err = FmMacsecRxSaSetReceive(p_FmMacsecSecY->h_FmMacsec,p_FmSecYSc->scId, p_FmSecYSc->sa[an].saId, FALSE)) != E_OK)
RETURN_ERROR(MINOR, err, NO_MSG);
p_FmSecYSc->sa[an].active = FALSE;
return err;
}
t_Error FM_MACSEC_SECY_RxSaUpdateNextPn(t_Handle h_FmMacsecSecY, t_Handle h_Sc, macsecAN_t an, uint32_t updtNextPN)
{
t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
t_SecYSc *p_FmSecYSc = (t_SecYSc *)h_Sc;
t_Error err = E_OK;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(an < MAX_NUM_OF_SA_PER_SC, E_INVALID_STATE);
if (p_FmSecYSc->sa[an].saId == SECY_AN_FREE_VALUE)
RETURN_ERROR(MINOR, E_INVALID_STATE, ("An %d is not configured",an));
if ((err = FmMacsecRxSaUpdateNextPn(p_FmMacsecSecY->h_FmMacsec,p_FmSecYSc->scId, p_FmSecYSc->sa[an].saId, updtNextPN)) != E_OK)
RETURN_ERROR(MINOR, err, NO_MSG);
return err;
}
t_Error FM_MACSEC_SECY_RxSaUpdateLowestPn(t_Handle h_FmMacsecSecY, t_Handle h_Sc, macsecAN_t an, uint32_t updtLowestPN)
{
t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
t_SecYSc *p_FmSecYSc = (t_SecYSc *)h_Sc;
t_Error err = E_OK;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(an < MAX_NUM_OF_SA_PER_SC, E_INVALID_STATE);
if (p_FmSecYSc->sa[an].saId == SECY_AN_FREE_VALUE)
RETURN_ERROR(MINOR, E_INVALID_STATE, ("An %d is not configured",an));
if ((err = FmMacsecRxSaUpdateLowestPn(p_FmMacsecSecY->h_FmMacsec,p_FmSecYSc->scId, p_FmSecYSc->sa[an].saId, updtLowestPN)) != E_OK)
RETURN_ERROR(MINOR, err, NO_MSG);
return err;
}
t_Error FM_MACSEC_SECY_RxSaModifyKey(t_Handle h_FmMacsecSecY, t_Handle h_Sc, macsecAN_t an, macsecSAKey_t key)
{
t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
t_SecYSc *p_FmSecYSc = (t_SecYSc *)h_Sc;
t_Error err = E_OK;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(an < MAX_NUM_OF_SA_PER_SC, E_INVALID_STATE);
if (p_FmSecYSc->sa[an].saId == SECY_AN_FREE_VALUE)
RETURN_ERROR(MINOR, E_INVALID_STATE, ("An %d is not configured",an));
if (p_FmSecYSc->sa[an].active)
if ((err = FmMacsecRxSaSetReceive(p_FmMacsecSecY->h_FmMacsec, p_FmSecYSc->scId, p_FmSecYSc->sa[an].saId, FALSE)) != E_OK)
RETURN_ERROR(MINOR, err, NO_MSG);
/* TODO - statistics should be read */
if ((err = FmMacsecCreateRxSa(p_FmMacsecSecY->h_FmMacsec, p_FmSecYSc->scId, p_FmSecYSc->sa[an].saId, an, 1, key)) != E_OK)
RETURN_ERROR(MINOR, err, NO_MSG);
if (p_FmSecYSc->sa[an].active)
if ((err = FmMacsecRxSaSetReceive(p_FmMacsecSecY->h_FmMacsec, p_FmSecYSc->scId, p_FmSecYSc->sa[an].saId, TRUE)) != E_OK)
RETURN_ERROR(MINOR, err, NO_MSG);
return err;
}
t_Error FM_MACSEC_SECY_CreateTxSa(t_Handle h_FmMacsecSecY, macsecAN_t an, macsecSAKey_t key)
{
t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
t_SecYSc *p_FmSecYSc;
t_Error err = E_OK;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
p_FmSecYSc = &p_FmMacsecSecY->p_TxSc[0];
SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(an < MAX_NUM_OF_SA_PER_SC, E_INVALID_STATE);
if (p_FmSecYSc->sa[an].saId != SECY_AN_FREE_VALUE)
RETURN_ERROR(MINOR, err, ("An %d is already assigned",an));
if ((err = FmMacsecCreateTxSa(p_FmMacsecSecY->h_FmMacsec,p_FmSecYSc->scId, (e_ScSaId)p_FmSecYSc->numOfSa, key)) != E_OK)
RETURN_ERROR(MINOR, err, NO_MSG);
p_FmSecYSc->sa[an].saId = (e_ScSaId)p_FmSecYSc->numOfSa++;
return err;
}
t_Error FM_MACSEC_SECY_DeleteTxSa(t_Handle h_FmMacsecSecY, macsecAN_t an)
{
t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
t_SecYSc *p_FmSecYSc;
t_Error err = E_OK;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
p_FmSecYSc = &p_FmMacsecSecY->p_TxSc[0];
SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(an < MAX_NUM_OF_SA_PER_SC, E_INVALID_STATE);
if (p_FmSecYSc->sa[an].saId == SECY_AN_FREE_VALUE)
RETURN_ERROR(MINOR, E_INVALID_STATE, ("An %d is already deleted",an));
if ((err = FmMacsecDeleteTxSa(p_FmMacsecSecY->h_FmMacsec, p_FmSecYSc->scId, p_FmSecYSc->sa[an].saId)) != E_OK)
RETURN_ERROR(MINOR, err, NO_MSG);
p_FmSecYSc->numOfSa--;
p_FmSecYSc->sa[an].saId = (e_ScSaId)SECY_AN_FREE_VALUE;
/* TODO - check if statistics need to be read*/
return err;
}
t_Error FM_MACSEC_SECY_TxSaModifyKey(t_Handle h_FmMacsecSecY, macsecAN_t nextActiveAn, macsecSAKey_t key)
{
t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
t_SecYSc *p_FmSecYSc;
macsecAN_t currentAn;
t_Error err = E_OK;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
p_FmSecYSc = &p_FmMacsecSecY->p_TxSc[0];
SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(nextActiveAn < MAX_NUM_OF_SA_PER_SC, E_INVALID_STATE);
if ((err = FmMacsecTxSaGetActive(p_FmMacsecSecY->h_FmMacsec,
p_FmSecYSc->scId,
&currentAn)) != E_OK)
RETURN_ERROR(MINOR, err, NO_MSG);
if ((err = FmMacsecTxSaSetActive(p_FmMacsecSecY->h_FmMacsec,
p_FmSecYSc->scId,
p_FmSecYSc->sa[nextActiveAn].saId,
nextActiveAn)) != E_OK)
RETURN_ERROR(MINOR, err, NO_MSG);
/* TODO - statistics should be read */
if ((err = FmMacsecCreateTxSa(p_FmMacsecSecY->h_FmMacsec, p_FmSecYSc->scId, p_FmSecYSc->sa[currentAn].saId, key)) != E_OK)
RETURN_ERROR(MINOR, err, NO_MSG);
return err;
}
t_Error FM_MACSEC_SECY_TxSaSetActive(t_Handle h_FmMacsecSecY, macsecAN_t an)
{
t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
t_SecYSc *p_FmSecYSc;
t_Error err = E_OK;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
p_FmSecYSc = &p_FmMacsecSecY->p_TxSc[0];
SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(an < MAX_NUM_OF_SA_PER_SC, E_INVALID_STATE);
if (p_FmSecYSc->sa[an].saId == SECY_AN_FREE_VALUE)
RETURN_ERROR(MINOR, E_INVALID_STATE, ("An %d is not configured",an));
if ((err = FmMacsecTxSaSetActive(p_FmMacsecSecY->h_FmMacsec,
p_FmSecYSc->scId,
p_FmSecYSc->sa[an].saId,
an)) != E_OK)
RETURN_ERROR(MINOR, err, NO_MSG);
return err;
}
t_Error FM_MACSEC_SECY_TxSaGetActive(t_Handle h_FmMacsecSecY, macsecAN_t *p_An)
{
t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
t_SecYSc *p_FmSecYSc;
t_Error err = E_OK;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
p_FmSecYSc = &p_FmMacsecSecY->p_TxSc[0];
SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_An, E_INVALID_HANDLE);
if ((err = FmMacsecTxSaGetActive(p_FmMacsecSecY->h_FmMacsec,
p_FmSecYSc->scId,
p_An)) != E_OK)
RETURN_ERROR(MINOR, err, NO_MSG);
return err;
}
t_Error FM_MACSEC_SECY_GetRxScPhysId(t_Handle h_FmMacsecSecY, t_Handle h_Sc, uint32_t *p_ScPhysId)
{
t_SecYSc *p_FmSecYSc = (t_SecYSc *)h_Sc;
t_Error err = E_OK;
SANITY_CHECK_RETURN_ERROR(h_FmMacsecSecY, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(((t_FmMacsecSecY *)h_FmMacsecSecY)->h_FmMacsec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!((t_FmMacsecSecY *)h_FmMacsecSecY)->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE);
#ifdef DISABLE_SANITY_CHECKS
UNUSED(h_FmMacsecSecY);
#endif /* DISABLE_SANITY_CHECKS */
*p_ScPhysId = p_FmSecYSc->scId;
return err;
}
t_Error FM_MACSEC_SECY_GetTxScPhysId(t_Handle h_FmMacsecSecY, uint32_t *p_ScPhysId)
{
t_FmMacsecSecY *p_FmMacsecSecY = (t_FmMacsecSecY *)h_FmMacsecSecY;
t_SecYSc *p_FmSecYSc;
t_Error err = E_OK;
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmMacsecSecY->h_FmMacsec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_FmMacsecSecY->p_FmMacsecSecYDriverParam, E_INVALID_STATE);
p_FmSecYSc = &p_FmMacsecSecY->p_TxSc[0];
SANITY_CHECK_RETURN_ERROR(p_FmSecYSc, E_INVALID_HANDLE);
*p_ScPhysId = p_FmSecYSc->scId;
return err;
}
t_Error FM_MACSEC_SECY_SetException(t_Handle h_FmMacsecSecY, e_FmMacsecExceptions exception, bool enable)
{
UNUSED(h_FmMacsecSecY);UNUSED(exception);UNUSED(enable);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
t_Error FM_MACSEC_SECY_SetEvent(t_Handle h_FmMacsecSecY, e_FmMacsecSecYEvents event, bool enable)
{
UNUSED(h_FmMacsecSecY);UNUSED(event);UNUSED(enable);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
t_Error FM_MACSEC_SECY_GetStatistics(t_Handle h_FmMacsecSecY, t_FmMacsecSecYStatistics *p_Statistics)
{
UNUSED(h_FmMacsecSecY);UNUSED(p_Statistics);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
t_Error FM_MACSEC_SECY_RxScGetStatistics(t_Handle h_FmMacsecSecY, t_Handle h_Sc, t_FmMacsecSecYRxScStatistics *p_Statistics)
{
UNUSED(h_FmMacsecSecY);UNUSED(h_Sc);UNUSED(p_Statistics);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
t_Error FM_MACSEC_SECY_RxSaGetStatistics(t_Handle h_FmMacsecSecY, t_Handle h_Sc, macsecAN_t an, t_FmMacsecSecYRxSaStatistics *p_Statistics)
{
UNUSED(h_FmMacsecSecY);UNUSED(h_Sc);UNUSED(an);UNUSED(p_Statistics);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
t_Error FM_MACSEC_SECY_TxScGetStatistics(t_Handle h_FmMacsecSecY, t_FmMacsecSecYTxScStatistics *p_Statistics)
{
UNUSED(h_FmMacsecSecY);UNUSED(p_Statistics);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
t_Error FM_MACSEC_SECY_TxSaGetStatistics(t_Handle h_FmMacsecSecY, macsecAN_t an, t_FmMacsecSecYTxSaStatistics *p_Statistics)
{
UNUSED(h_FmMacsecSecY);UNUSED(an);UNUSED(p_Statistics);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}

144
drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MACSEC/fm_macsec_secy.h Normal file
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@ -0,0 +1,144 @@
/*
* Copyright 2008-2015 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_macsec_secy.h
@Description FM MACSEC SecY internal structures and definitions.
*//***************************************************************************/
#ifndef __FM_MACSEC_SECY_H
#define __FM_MACSEC_SECY_H
#include "error_ext.h"
#include "std_ext.h"
#include "fm_macsec.h"
/**************************************************************************//**
@Description Exceptions
*//***************************************************************************/
#define FM_MACSEC_SECY_EX_FRAME_DISCARDED 0x80000000
#define GET_EXCEPTION_FLAG(bitMask, exception) switch (exception){ \
case e_FM_MACSEC_SECY_EX_FRAME_DISCARDED: \
bitMask = FM_MACSEC_SECY_EX_FRAME_DISCARDED; break; \
default: bitMask = 0;break;}
/**************************************************************************//**
@Description Events
*//***************************************************************************/
#define FM_MACSEC_SECY_EV_NEXT_PN 0x80000000
#define GET_EVENT_FLAG(bitMask, event) switch (event){ \
case e_FM_MACSEC_SECY_EV_NEXT_PN: \
bitMask = FM_MACSEC_SECY_EV_NEXT_PN; break; \
default: bitMask = 0;break;}
/**************************************************************************//**
@Description Defaults
*//***************************************************************************/
#define DEFAULT_exceptions (FM_MACSEC_SECY_EX_FRAME_DISCARDED)
#define DEFAULT_events (FM_MACSEC_SECY_EV_NEXT_PN)
#define DEFAULT_numOfTxSc 1
#define DEFAULT_confidentialityEnable FALSE
#define DEFAULT_confidentialityOffset 0
#define DEFAULT_sciInsertionMode e_FM_MACSEC_SCI_INSERTION_MODE_EXPLICIT_SECTAG
#define DEFAULT_validateFrames e_FM_MACSEC_VALID_FRAME_BEHAVIOR_STRICT
#define DEFAULT_replayEnable FALSE
#define DEFAULT_replayWindow 0
#define DEFAULT_protectFrames TRUE
#define DEFAULT_ptp FALSE
/**************************************************************************//**
@Description General defines
*//***************************************************************************/
#define SECY_AN_FREE_VALUE MAX_NUM_OF_SA_PER_SC
typedef struct {
e_ScSaId saId;
bool active;
union {
t_FmMacsecSecYRxSaStatistics rxSaStatistics;
t_FmMacsecSecYTxSaStatistics txSaStatistics;
};
} t_SecYSa;
typedef struct {
bool inUse;
uint32_t scId;
e_ScType type;
uint8_t numOfSa;
t_SecYSa sa[MAX_NUM_OF_SA_PER_SC];
union {
t_FmMacsecSecYRxScStatistics rxScStatistics;
t_FmMacsecSecYTxScStatistics txScStatistics;
};
} t_SecYSc;
typedef struct {
t_FmMacsecSecYSCParams txScParams; /**< Tx SC Params */
} t_FmMacsecSecYDriverParam;
typedef struct {
t_Handle h_FmMacsec;
bool confidentialityEnable; /**< TRUE - confidentiality protection and integrity protection
FALSE - no confidentiality protection, only integrity protection*/
uint16_t confidentialityOffset; /**< The number of initial octets of each MSDU without confidentiality protection
common values are 0, 30, and 50 */
bool replayProtect; /**< replay protection function mode */
uint32_t replayWindow; /**< the size of the replay window */
e_FmMacsecValidFrameBehavior validateFrames; /**< validation function mode */
e_FmMacsecSciInsertionMode sciInsertionMode;
bool protectFrames;
bool isPointToPoint;
e_FmMacsecSecYCipherSuite cipherSuite; /**< Cipher suite to be used for this SecY */
uint32_t numOfRxSc; /**< Number of receive channels */
uint32_t numOfTxSc; /**< Number of transmit channels */
t_SecYSc *p_RxSc;
t_SecYSc *p_TxSc;
uint32_t events;
uint32_t exceptions;
t_FmMacsecSecYExceptionsCallback *f_Exception; /**< TODO */
t_FmMacsecSecYEventsCallback *f_Event; /**< TODO */
t_Handle h_App;
t_FmMacsecSecYStatistics statistics;
t_FmMacsecSecYDriverParam *p_FmMacsecSecYDriverParam;
} t_FmMacsecSecY;
#endif /* __FM_MACSEC_SECY_H */

23
drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Makefile Normal file
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@ -0,0 +1,23 @@
#
# Makefile for the Freescale Ethernet controllers
#
ccflags-y += -DVERSION=\"\"
#
#Include netcomm SW specific definitions
include $(srctree)/drivers/net/ethernet/freescale/sdk_fman/ncsw_config.mk
NCSW_FM_INC = $(srctree)/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/inc
ccflags-y += -I$(NCSW_FM_INC)
obj-y += fsl-ncsw-PFM1.o
fsl-ncsw-PFM1-objs := fm.o fm_muram.o fman.o
obj-y += MAC/
obj-y += Pcd/
obj-y += SP/
obj-y += Port/
obj-y += HC/
obj-y += Rtc/
obj-y += MACSEC/

26
drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/Makefile Normal file
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@ -0,0 +1,26 @@
#
# Makefile for the Freescale Ethernet controllers
#
ccflags-y += -DVERSION=\"\"
#
#Include netcomm SW specific definitions
include $(srctree)/drivers/net/ethernet/freescale/sdk_fman/ncsw_config.mk
NCSW_FM_INC = $(srctree)/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/inc
ccflags-y += -I$(NCSW_FM_INC)
obj-y += fsl-ncsw-Pcd.o
fsl-ncsw-Pcd-objs := fman_kg.o fman_prs.o fm_cc.o fm_kg.o fm_pcd.o fm_plcr.o fm_prs.o fm_manip.o
ifeq ($(CONFIG_FMAN_V3H),y)
fsl-ncsw-Pcd-objs += fm_replic.o
endif
ifeq ($(CONFIG_FMAN_V3L),y)
fsl-ncsw-Pcd-objs += fm_replic.o
endif
ifeq ($(CONFIG_FMAN_ARM),y)
fsl-ncsw-Pcd-objs += fm_replic.o
endif

360
drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/crc64.h Normal file
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@ -0,0 +1,360 @@
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**************************************************************************//**
@File crc64.h
@Description brief This file contains the CRC64 Table, and __inline__
functions used for calculating crc.
*//***************************************************************************/
#ifndef __CRC64_H
#define __CRC64_H
#include "std_ext.h"
#define BITS_PER_BYTE 8
#define CRC64_EXPON_ECMA_182 0xC96C5795D7870F42ULL
#define CRC64_DEFAULT_INITVAL 0xFFFFFFFFFFFFFFFFULL
#define CRC64_BYTE_MASK 0xFF
#define CRC64_TABLE_ENTRIES ( 1 << BITS_PER_BYTE )
#define CRC64_ODD_MASK 1
/**
\brief '64 bit crc' Table
*/
struct crc64_t {
uint64_t initial; /**< Initial seed */
uint64_t table[CRC64_TABLE_ENTRIES]; /**< CRC table entries */
};
static struct crc64_t CRC64_ECMA_182 = {
CRC64_DEFAULT_INITVAL,
{
0x0000000000000000ULL,
0xb32e4cbe03a75f6fULL,
0xf4843657a840a05bULL,
0x47aa7ae9abe7ff34ULL,
0x7bd0c384ff8f5e33ULL,
0xc8fe8f3afc28015cULL,
0x8f54f5d357cffe68ULL,
0x3c7ab96d5468a107ULL,
0xf7a18709ff1ebc66ULL,
0x448fcbb7fcb9e309ULL,
0x0325b15e575e1c3dULL,
0xb00bfde054f94352ULL,
0x8c71448d0091e255ULL,
0x3f5f08330336bd3aULL,
0x78f572daa8d1420eULL,
0xcbdb3e64ab761d61ULL,
0x7d9ba13851336649ULL,
0xceb5ed8652943926ULL,
0x891f976ff973c612ULL,
0x3a31dbd1fad4997dULL,
0x064b62bcaebc387aULL,
0xb5652e02ad1b6715ULL,
0xf2cf54eb06fc9821ULL,
0x41e11855055bc74eULL,
0x8a3a2631ae2dda2fULL,
0x39146a8fad8a8540ULL,
0x7ebe1066066d7a74ULL,
0xcd905cd805ca251bULL,
0xf1eae5b551a2841cULL,
0x42c4a90b5205db73ULL,
0x056ed3e2f9e22447ULL,
0xb6409f5cfa457b28ULL,
0xfb374270a266cc92ULL,
0x48190ecea1c193fdULL,
0x0fb374270a266cc9ULL,
0xbc9d3899098133a6ULL,
0x80e781f45de992a1ULL,
0x33c9cd4a5e4ecdceULL,
0x7463b7a3f5a932faULL,
0xc74dfb1df60e6d95ULL,
0x0c96c5795d7870f4ULL,
0xbfb889c75edf2f9bULL,
0xf812f32ef538d0afULL,
0x4b3cbf90f69f8fc0ULL,
0x774606fda2f72ec7ULL,
0xc4684a43a15071a8ULL,
0x83c230aa0ab78e9cULL,
0x30ec7c140910d1f3ULL,
0x86ace348f355aadbULL,
0x3582aff6f0f2f5b4ULL,
0x7228d51f5b150a80ULL,
0xc10699a158b255efULL,
0xfd7c20cc0cdaf4e8ULL,
0x4e526c720f7dab87ULL,
0x09f8169ba49a54b3ULL,
0xbad65a25a73d0bdcULL,
0x710d64410c4b16bdULL,
0xc22328ff0fec49d2ULL,
0x85895216a40bb6e6ULL,
0x36a71ea8a7ace989ULL,
0x0adda7c5f3c4488eULL,
0xb9f3eb7bf06317e1ULL,
0xfe5991925b84e8d5ULL,
0x4d77dd2c5823b7baULL,
0x64b62bcaebc387a1ULL,
0xd7986774e864d8ceULL,
0x90321d9d438327faULL,
0x231c512340247895ULL,
0x1f66e84e144cd992ULL,
0xac48a4f017eb86fdULL,
0xebe2de19bc0c79c9ULL,
0x58cc92a7bfab26a6ULL,
0x9317acc314dd3bc7ULL,
0x2039e07d177a64a8ULL,
0x67939a94bc9d9b9cULL,
0xd4bdd62abf3ac4f3ULL,
0xe8c76f47eb5265f4ULL,
0x5be923f9e8f53a9bULL,
0x1c4359104312c5afULL,
0xaf6d15ae40b59ac0ULL,
0x192d8af2baf0e1e8ULL,
0xaa03c64cb957be87ULL,
0xeda9bca512b041b3ULL,
0x5e87f01b11171edcULL,
0x62fd4976457fbfdbULL,
0xd1d305c846d8e0b4ULL,
0x96797f21ed3f1f80ULL,
0x2557339fee9840efULL,
0xee8c0dfb45ee5d8eULL,
0x5da24145464902e1ULL,
0x1a083bacedaefdd5ULL,
0xa9267712ee09a2baULL,
0x955cce7fba6103bdULL,
0x267282c1b9c65cd2ULL,
0x61d8f8281221a3e6ULL,
0xd2f6b4961186fc89ULL,
0x9f8169ba49a54b33ULL,
0x2caf25044a02145cULL,
0x6b055fede1e5eb68ULL,
0xd82b1353e242b407ULL,
0xe451aa3eb62a1500ULL,
0x577fe680b58d4a6fULL,
0x10d59c691e6ab55bULL,
0xa3fbd0d71dcdea34ULL,
0x6820eeb3b6bbf755ULL,
0xdb0ea20db51ca83aULL,
0x9ca4d8e41efb570eULL,
0x2f8a945a1d5c0861ULL,
0x13f02d374934a966ULL,
0xa0de61894a93f609ULL,
0xe7741b60e174093dULL,
0x545a57dee2d35652ULL,
0xe21ac88218962d7aULL,
0x5134843c1b317215ULL,
0x169efed5b0d68d21ULL,
0xa5b0b26bb371d24eULL,
0x99ca0b06e7197349ULL,
0x2ae447b8e4be2c26ULL,
0x6d4e3d514f59d312ULL,
0xde6071ef4cfe8c7dULL,
0x15bb4f8be788911cULL,
0xa6950335e42fce73ULL,
0xe13f79dc4fc83147ULL,
0x521135624c6f6e28ULL,
0x6e6b8c0f1807cf2fULL,
0xdd45c0b11ba09040ULL,
0x9aefba58b0476f74ULL,
0x29c1f6e6b3e0301bULL,
0xc96c5795d7870f42ULL,
0x7a421b2bd420502dULL,
0x3de861c27fc7af19ULL,
0x8ec62d7c7c60f076ULL,
0xb2bc941128085171ULL,
0x0192d8af2baf0e1eULL,
0x4638a2468048f12aULL,
0xf516eef883efae45ULL,
0x3ecdd09c2899b324ULL,
0x8de39c222b3eec4bULL,
0xca49e6cb80d9137fULL,
0x7967aa75837e4c10ULL,
0x451d1318d716ed17ULL,
0xf6335fa6d4b1b278ULL,
0xb199254f7f564d4cULL,
0x02b769f17cf11223ULL,
0xb4f7f6ad86b4690bULL,
0x07d9ba1385133664ULL,
0x4073c0fa2ef4c950ULL,
0xf35d8c442d53963fULL,
0xcf273529793b3738ULL,
0x7c0979977a9c6857ULL,
0x3ba3037ed17b9763ULL,
0x888d4fc0d2dcc80cULL,
0x435671a479aad56dULL,
0xf0783d1a7a0d8a02ULL,
0xb7d247f3d1ea7536ULL,
0x04fc0b4dd24d2a59ULL,
0x3886b22086258b5eULL,
0x8ba8fe9e8582d431ULL,
0xcc0284772e652b05ULL,
0x7f2cc8c92dc2746aULL,
0x325b15e575e1c3d0ULL,
0x8175595b76469cbfULL,
0xc6df23b2dda1638bULL,
0x75f16f0cde063ce4ULL,
0x498bd6618a6e9de3ULL,
0xfaa59adf89c9c28cULL,
0xbd0fe036222e3db8ULL,
0x0e21ac88218962d7ULL,
0xc5fa92ec8aff7fb6ULL,
0x76d4de52895820d9ULL,
0x317ea4bb22bfdfedULL,
0x8250e80521188082ULL,
0xbe2a516875702185ULL,
0x0d041dd676d77eeaULL,
0x4aae673fdd3081deULL,
0xf9802b81de97deb1ULL,
0x4fc0b4dd24d2a599ULL,
0xfceef8632775faf6ULL,
0xbb44828a8c9205c2ULL,
0x086ace348f355aadULL,
0x34107759db5dfbaaULL,
0x873e3be7d8faa4c5ULL,
0xc094410e731d5bf1ULL,
0x73ba0db070ba049eULL,
0xb86133d4dbcc19ffULL,
0x0b4f7f6ad86b4690ULL,
0x4ce50583738cb9a4ULL,
0xffcb493d702be6cbULL,
0xc3b1f050244347ccULL,
0x709fbcee27e418a3ULL,
0x3735c6078c03e797ULL,
0x841b8ab98fa4b8f8ULL,
0xadda7c5f3c4488e3ULL,
0x1ef430e13fe3d78cULL,
0x595e4a08940428b8ULL,
0xea7006b697a377d7ULL,
0xd60abfdbc3cbd6d0ULL,
0x6524f365c06c89bfULL,
0x228e898c6b8b768bULL,
0x91a0c532682c29e4ULL,
0x5a7bfb56c35a3485ULL,
0xe955b7e8c0fd6beaULL,
0xaeffcd016b1a94deULL,
0x1dd181bf68bdcbb1ULL,
0x21ab38d23cd56ab6ULL,
0x9285746c3f7235d9ULL,
0xd52f0e859495caedULL,
0x6601423b97329582ULL,
0xd041dd676d77eeaaULL,
0x636f91d96ed0b1c5ULL,
0x24c5eb30c5374ef1ULL,
0x97eba78ec690119eULL,
0xab911ee392f8b099ULL,
0x18bf525d915feff6ULL,
0x5f1528b43ab810c2ULL,
0xec3b640a391f4fadULL,
0x27e05a6e926952ccULL,
0x94ce16d091ce0da3ULL,
0xd3646c393a29f297ULL,
0x604a2087398eadf8ULL,
0x5c3099ea6de60cffULL,
0xef1ed5546e415390ULL,
0xa8b4afbdc5a6aca4ULL,
0x1b9ae303c601f3cbULL,
0x56ed3e2f9e224471ULL,
0xe5c372919d851b1eULL,
0xa26908783662e42aULL,
0x114744c635c5bb45ULL,
0x2d3dfdab61ad1a42ULL,
0x9e13b115620a452dULL,
0xd9b9cbfcc9edba19ULL,
0x6a978742ca4ae576ULL,
0xa14cb926613cf817ULL,
0x1262f598629ba778ULL,
0x55c88f71c97c584cULL,
0xe6e6c3cfcadb0723ULL,
0xda9c7aa29eb3a624ULL,
0x69b2361c9d14f94bULL,
0x2e184cf536f3067fULL,
0x9d36004b35545910ULL,
0x2b769f17cf112238ULL,
0x9858d3a9ccb67d57ULL,
0xdff2a94067518263ULL,
0x6cdce5fe64f6dd0cULL,
0x50a65c93309e7c0bULL,
0xe388102d33392364ULL,
0xa4226ac498dedc50ULL,
0x170c267a9b79833fULL,
0xdcd7181e300f9e5eULL,
0x6ff954a033a8c131ULL,
0x28532e49984f3e05ULL,
0x9b7d62f79be8616aULL,
0xa707db9acf80c06dULL,
0x14299724cc279f02ULL,
0x5383edcd67c06036ULL,
0xe0ada17364673f59ULL
}
};
/**
\brief Initializes the crc seed
*/
static __inline__ uint64_t crc64_init(void)
{
return CRC64_ECMA_182.initial;
}
/**
\brief Computes 64 bit the crc
\param[in] data Pointer to the Data in the frame
\param[in] len Length of the Data
\param[in] crc seed
\return calculated crc
*/
static __inline__ uint64_t crc64_compute(void const *data,
uint32_t len,
uint64_t seed)
{
uint32_t i;
uint64_t crc = seed;
uint8_t *bdata = (uint8_t *) data;
for (i = 0; i < len; i++)
crc =
CRC64_ECMA_182.
table[(crc ^ *bdata++) & CRC64_BYTE_MASK] ^ (crc >> 8);
return crc;
}
#endif /* __CRC64_H */

7582
drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_cc.c Normal file
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File diff suppressed because it is too large Load Diff

399
drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_cc.h Normal file
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@ -0,0 +1,399 @@
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_cc.h
@Description FM PCD CC ...
*//***************************************************************************/
#ifndef __FM_CC_H
#define __FM_CC_H
#include "std_ext.h"
#include "error_ext.h"
#include "list_ext.h"
#include "fm_pcd.h"
/***********************************************************************/
/* Coarse classification defines */
/***********************************************************************/
#define CC_MAX_NUM_OF_KEYS (FM_PCD_MAX_NUM_OF_KEYS + 1)
#define CC_PC_FF_MACDST 0x00
#define CC_PC_FF_MACSRC 0x01
#define CC_PC_FF_ETYPE 0x02
#define CC_PC_FF_TCI1 0x03
#define CC_PC_FF_TCI2 0x04
#define CC_PC_FF_MPLS1 0x06
#define CC_PC_FF_MPLS_LAST 0x07
#define CC_PC_FF_IPV4DST1 0x08
#define CC_PC_FF_IPV4DST2 0x16
#define CC_PC_FF_IPV4IPTOS_TC1 0x09
#define CC_PC_FF_IPV4IPTOS_TC2 0x17
#define CC_PC_FF_IPV4PTYPE1 0x0A
#define CC_PC_FF_IPV4PTYPE2 0x18
#define CC_PC_FF_IPV4SRC1 0x0b
#define CC_PC_FF_IPV4SRC2 0x19
#define CC_PC_FF_IPV4SRC1_IPV4DST1 0x0c
#define CC_PC_FF_IPV4SRC2_IPV4DST2 0x1a
#define CC_PC_FF_IPV4TTL 0x29
#define CC_PC_FF_IPTOS_IPV6TC1_IPV6FLOW1 0x0d /*TODO - CLASS - what is it? TOS*/
#define CC_PC_FF_IPTOS_IPV6TC2_IPV6FLOW2 0x1b
#define CC_PC_FF_IPV6PTYPE1 0x0e
#define CC_PC_FF_IPV6PTYPE2 0x1c
#define CC_PC_FF_IPV6DST1 0x0f
#define CC_PC_FF_IPV6DST2 0x1d
#define CC_PC_FF_IPV6SRC1 0x10
#define CC_PC_FF_IPV6SRC2 0x1e
#define CC_PC_FF_IPV6HOP_LIMIT 0x2a
#define CC_PC_FF_IPPID 0x24
#define CC_PC_FF_IPDSCP 0x76
#define CC_PC_FF_GREPTYPE 0x11
#define CC_PC_FF_MINENCAP_PTYPE 0x12
#define CC_PC_FF_MINENCAP_IPDST 0x13
#define CC_PC_FF_MINENCAP_IPSRC 0x14
#define CC_PC_FF_MINENCAP_IPSRC_IPDST 0x15
#define CC_PC_FF_L4PSRC 0x1f
#define CC_PC_FF_L4PDST 0x20
#define CC_PC_FF_L4PSRC_L4PDST 0x21
#define CC_PC_FF_PPPPID 0x05
#define CC_PC_PR_SHIM1 0x22
#define CC_PC_PR_SHIM2 0x23
#define CC_PC_GENERIC_WITHOUT_MASK 0x27
#define CC_PC_GENERIC_WITH_MASK 0x28
#define CC_PC_GENERIC_IC_GMASK 0x2B
#define CC_PC_GENERIC_IC_HASH_INDEXED 0x2C
#define CC_PC_GENERIC_IC_AGING_MASK 0x2D
#define CC_PR_OFFSET 0x25
#define CC_PR_WITHOUT_OFFSET 0x26
#define CC_PC_PR_ETH_OFFSET 19
#define CC_PC_PR_USER_DEFINED_SHIM1_OFFSET 16
#define CC_PC_PR_USER_DEFINED_SHIM2_OFFSET 17
#define CC_PC_PR_USER_LLC_SNAP_OFFSET 20
#define CC_PC_PR_VLAN1_OFFSET 21
#define CC_PC_PR_VLAN2_OFFSET 22
#define CC_PC_PR_PPPOE_OFFSET 24
#define CC_PC_PR_MPLS1_OFFSET 25
#define CC_PC_PR_MPLS_LAST_OFFSET 26
#define CC_PC_PR_IP1_OFFSET 27
#define CC_PC_PR_IP_LAST_OFFSET 28
#define CC_PC_PR_MINENC_OFFSET 28
#define CC_PC_PR_L4_OFFSET 30
#define CC_PC_PR_GRE_OFFSET 29
#define CC_PC_PR_ETYPE_LAST_OFFSET 23
#define CC_PC_PR_NEXT_HEADER_OFFSET 31
#define CC_PC_ILLEGAL 0xff
#define CC_SIZE_ILLEGAL 0
#define FM_PCD_CC_KEYS_MATCH_TABLE_ALIGN 16
#define FM_PCD_CC_AD_TABLE_ALIGN 16
#define FM_PCD_CC_AD_ENTRY_SIZE 16
#define FM_PCD_CC_NUM_OF_KEYS 255
#define FM_PCD_CC_TREE_ADDR_ALIGN 256
#define FM_PCD_AD_RESULT_CONTRL_FLOW_TYPE 0x00000000
#define FM_PCD_AD_RESULT_DATA_FLOW_TYPE 0x80000000
#define FM_PCD_AD_RESULT_PLCR_DIS 0x20000000
#define FM_PCD_AD_RESULT_EXTENDED_MODE 0x80000000
#define FM_PCD_AD_RESULT_NADEN 0x20000000
#define FM_PCD_AD_RESULT_STATISTICS_EN 0x40000000
#define FM_PCD_AD_CONT_LOOKUP_TYPE 0x40000000
#define FM_PCD_AD_CONT_LOOKUP_LCL_MASK 0x00800000
#define FM_PCD_AD_STATS_TYPE 0x40000000
#define FM_PCD_AD_STATS_FLR_ADDR_MASK 0x00FFFFFF
#define FM_PCD_AD_STATS_COUNTERS_ADDR_MASK 0x00FFFFFF
#define FM_PCD_AD_STATS_NEXT_ACTION_MASK 0xFFFF0000
#define FM_PCD_AD_STATS_NEXT_ACTION_SHIFT 12
#define FM_PCD_AD_STATS_NAD_EN 0x00008000
#define FM_PCD_AD_STATS_OP_CODE 0x00000036
#define FM_PCD_AD_STATS_FLR_EN 0x00004000
#define FM_PCD_AD_STATS_COND_EN 0x00002000
#define FM_PCD_AD_BYPASS_TYPE 0xc0000000
#define FM_PCD_AD_TYPE_MASK 0xc0000000
#define FM_PCD_AD_OPCODE_MASK 0x0000000f
#define FM_PCD_AD_PROFILEID_FOR_CNTRL_SHIFT 16
#if (DPAA_VERSION >= 11)
#define FM_PCD_AD_RESULT_VSP_SHIFT 24
#define FM_PCD_AD_RESULT_NO_OM_VSPE 0x02000000
#define FM_PCD_AD_RESULT_VSP_MASK 0x3f
#define FM_PCD_AD_NCSPFQIDM_MASK 0x80000000
#endif /* (DPAA_VERSION >= 11) */
#define GLBL_MASK_FOR_HASH_INDEXED 0xfff00000
#define CC_GLBL_MASK_SIZE 4
#define CC_AGING_MASK_SIZE 4
typedef uint32_t ccPrivateInfo_t; /**< private info of CC: */
#define CC_PRIVATE_INFO_NONE 0
#define CC_PRIVATE_INFO_IC_HASH_INDEX_LOOKUP 0x80000000
#define CC_PRIVATE_INFO_IC_HASH_EXACT_MATCH 0x40000000
#define CC_PRIVATE_INFO_IC_KEY_EXACT_MATCH 0x20000000
#define CC_PRIVATE_INFO_IC_DEQ_FQID_INDEX_LOOKUP 0x10000000
#define CC_BUILD_AGING_MASK(numOfKeys) ((((1LL << ((numOfKeys) + 1)) - 1)) << (31 - (numOfKeys)))
/***********************************************************************/
/* Memory map */
/***********************************************************************/
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(push,1)
#endif /* defined(__MWERKS__) && ... */
typedef struct
{
volatile uint32_t fqid;
volatile uint32_t plcrProfile;
volatile uint32_t nia;
volatile uint32_t res;
} t_AdOfTypeResult;
typedef struct
{
volatile uint32_t ccAdBase;
volatile uint32_t matchTblPtr;
volatile uint32_t pcAndOffsets;
volatile uint32_t gmask;
} t_AdOfTypeContLookup;
typedef struct
{
volatile uint32_t profileTableAddr;
volatile uint32_t reserved;
volatile uint32_t nextActionIndx;
volatile uint32_t statsTableAddr;
} t_AdOfTypeStats;
typedef union
{
volatile t_AdOfTypeResult adResult;
volatile t_AdOfTypeContLookup adContLookup;
} t_Ad;
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(pop)
#endif /* defined(__MWERKS__) && ... */
/***********************************************************************/
/* Driver's internal structures */
/***********************************************************************/
typedef struct t_FmPcdStatsObj
{
t_Handle h_StatsAd;
t_Handle h_StatsCounters;
t_List node;
} t_FmPcdStatsObj;
typedef struct
{
uint8_t key[FM_PCD_MAX_SIZE_OF_KEY];
uint8_t mask[FM_PCD_MAX_SIZE_OF_KEY];
t_FmPcdCcNextEngineParams nextEngineParams;
uint32_t requiredAction;
uint32_t shadowAction;
t_FmPcdStatsObj *p_StatsObj;
} t_FmPcdCcKeyAndNextEngineParams;
typedef struct
{
t_Handle p_Ad;
e_FmPcdEngine fmPcdEngine;
bool adAllocated;
bool isTree;
uint32_t myInfo;
t_List *h_CcNextNodesLst;
t_Handle h_AdditionalInfo;
t_Handle h_Node;
} t_FmPcdModifyCcAdditionalParams;
typedef struct
{
t_Handle p_AdTableNew;
t_Handle p_KeysMatchTableNew;
t_Handle p_AdTableOld;
t_Handle p_KeysMatchTableOld;
uint16_t numOfKeys;
t_Handle h_CurrentNode;
uint16_t savedKeyIndex;
t_Handle h_NodeForAdd;
t_Handle h_NodeForRmv;
t_Handle h_ManipForRmv;
t_Handle h_ManipForAdd;
t_FmPcdStatsObj *p_StatsObjForRmv;
#if (DPAA_VERSION >= 11)
t_Handle h_FrmReplicForAdd;
t_Handle h_FrmReplicForRmv;
#endif /* (DPAA_VERSION >= 11) */
bool tree;
t_FmPcdCcKeyAndNextEngineParams keyAndNextEngineParams[CC_MAX_NUM_OF_KEYS];
} t_FmPcdModifyCcKeyAdditionalParams;
typedef struct
{
t_Handle h_Manip;
t_Handle h_CcNode;
} t_CcNextEngineInfo;
typedef struct
{
uint16_t numOfKeys;
uint16_t maxNumOfKeys;
bool maskSupport;
uint32_t keysMatchTableMaxSize;
e_FmPcdCcStatsMode statisticsMode;
uint32_t numOfStatsFLRs;
uint32_t countersArraySize;
bool isHashBucket; /**< Valid for match table node that is a bucket of a hash table only */
t_Handle h_MissStatsCounters; /**< Valid for hash table node and match table that is a bucket;
Holds the statistics counters allocated by the hash table and
are shared by all hash table buckets; */
t_Handle h_PrivMissStatsCounters; /**< Valid for match table node that is a bucket of a hash table only;
Holds the statistics counters that were allocated for this node
and replaced by the shared counters (allocated by the hash table); */
bool statsEnForMiss; /**< Valid for hash table node only; TRUE is statistics are currently
enabled for hash 'miss', FALSE otherwise; This parameter effects the
returned statistics count to user, statistics AD always present for 'miss'
for all hash buckets; */
bool glblMaskUpdated;
t_Handle p_GlblMask;
bool lclMask;
uint8_t parseCode;
uint8_t offset;
uint8_t prsArrayOffset;
bool ctrlFlow;
uint16_t owners;
uint8_t ccKeySizeAccExtraction;
uint8_t sizeOfExtraction;
uint8_t glblMaskSize;
t_Handle h_KeysMatchTable;
t_Handle h_AdTable;
t_Handle h_StatsAds;
t_Handle h_TmpAd;
t_Handle h_Ad;
t_Handle h_StatsFLRs;
t_List availableStatsLst;
t_List ccPrevNodesLst;
t_List ccTreeIdLst;
t_List ccTreesLst;
t_Handle h_FmPcd;
uint32_t shadowAction;
uint8_t userSizeOfExtraction;
uint8_t userOffset;
uint8_t kgHashShift; /* used in hash-table */
t_Handle h_Spinlock;
t_FmPcdCcKeyAndNextEngineParams keyAndNextEngineParams[CC_MAX_NUM_OF_KEYS];
} t_FmPcdCcNode;
typedef struct
{
t_FmPcdCcNode *p_FmPcdCcNode;
bool occupied;
uint16_t owners;
volatile bool lock;
} t_FmPcdCcNodeArray;
typedef struct
{
uint8_t numOfEntriesInGroup;
uint32_t totalBitsMask;
uint8_t baseGroupEntry;
} t_FmPcdCcGroupParam;
typedef struct
{
t_Handle h_FmPcd;
uint8_t netEnvId;
uintptr_t ccTreeBaseAddr;
uint8_t numOfGrps;
t_FmPcdCcGroupParam fmPcdGroupParam[FM_PCD_MAX_NUM_OF_CC_GROUPS];
t_List fmPortsLst;
t_FmPcdLock *p_Lock;
uint8_t numOfEntries;
uint16_t owners;
t_Handle h_FmPcdCcSavedManipParams;
bool modifiedState;
uint32_t requiredAction;
t_Handle h_IpReassemblyManip;
t_Handle h_CapwapReassemblyManip;
t_FmPcdCcKeyAndNextEngineParams keyAndNextEngineParams[FM_PCD_MAX_NUM_OF_CC_GROUPS];
} t_FmPcdCcTree;
t_Error FmPcdCcNodeTreeTryLock(t_Handle h_FmPcd,t_Handle h_FmPcdCcNode, t_List *p_List);
void FmPcdCcNodeTreeReleaseLock(t_Handle h_FmPcd, t_List *p_List);
t_Error FmPcdUpdateCcShadow (t_FmPcd *p_FmPcd, uint32_t size, uint32_t align);
#endif /* __FM_CC_H */

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/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_kg.h
@Description FM KG private header
*//***************************************************************************/
#ifndef __FM_KG_H
#define __FM_KG_H
#include "std_ext.h"
/***********************************************************************/
/* Keygen defines */
/***********************************************************************/
/* maskes */
#if (DPAA_VERSION >= 11)
#define KG_SCH_VSP_SHIFT_MASK 0x0003f000
#define KG_SCH_OM_VSPE 0x00000001
#define KG_SCH_VSP_NO_KSP_EN 0x80000000
#define MAX_SP_SHIFT 23
#define KG_SCH_VSP_MASK_SHIFT 12
#define KG_SCH_VSP_SHIFT 24
#endif /* (DPAA_VERSION >= 11) */
typedef uint32_t t_KnownFieldsMasks;
#define KG_SCH_KN_PORT_ID 0x80000000
#define KG_SCH_KN_MACDST 0x40000000
#define KG_SCH_KN_MACSRC 0x20000000
#define KG_SCH_KN_TCI1 0x10000000
#define KG_SCH_KN_TCI2 0x08000000
#define KG_SCH_KN_ETYPE 0x04000000
#define KG_SCH_KN_PPPSID 0x02000000
#define KG_SCH_KN_PPPID 0x01000000
#define KG_SCH_KN_MPLS1 0x00800000
#define KG_SCH_KN_MPLS2 0x00400000
#define KG_SCH_KN_MPLS_LAST 0x00200000
#define KG_SCH_KN_IPSRC1 0x00100000
#define KG_SCH_KN_IPDST1 0x00080000
#define KG_SCH_KN_PTYPE1 0x00040000
#define KG_SCH_KN_IPTOS_TC1 0x00020000
#define KG_SCH_KN_IPV6FL1 0x00010000
#define KG_SCH_KN_IPSRC2 0x00008000
#define KG_SCH_KN_IPDST2 0x00004000
#define KG_SCH_KN_PTYPE2 0x00002000
#define KG_SCH_KN_IPTOS_TC2 0x00001000
#define KG_SCH_KN_IPV6FL2 0x00000800
#define KG_SCH_KN_GREPTYPE 0x00000400
#define KG_SCH_KN_IPSEC_SPI 0x00000200
#define KG_SCH_KN_IPSEC_NH 0x00000100
#define KG_SCH_KN_IPPID 0x00000080
#define KG_SCH_KN_L4PSRC 0x00000004
#define KG_SCH_KN_L4PDST 0x00000002
#define KG_SCH_KN_TFLG 0x00000001
typedef uint8_t t_GenericCodes;
#define KG_SCH_GEN_SHIM1 0x70
#define KG_SCH_GEN_DEFAULT 0x10
#define KG_SCH_GEN_PARSE_RESULT_N_FQID 0x20
#define KG_SCH_GEN_START_OF_FRM 0x40
#define KG_SCH_GEN_SHIM2 0x71
#define KG_SCH_GEN_IP_PID_NO_V 0x72
#define KG_SCH_GEN_ETH 0x03
#define KG_SCH_GEN_ETH_NO_V 0x73
#define KG_SCH_GEN_SNAP 0x04
#define KG_SCH_GEN_SNAP_NO_V 0x74
#define KG_SCH_GEN_VLAN1 0x05
#define KG_SCH_GEN_VLAN1_NO_V 0x75
#define KG_SCH_GEN_VLAN2 0x06
#define KG_SCH_GEN_VLAN2_NO_V 0x76
#define KG_SCH_GEN_ETH_TYPE 0x07
#define KG_SCH_GEN_ETH_TYPE_NO_V 0x77
#define KG_SCH_GEN_PPP 0x08
#define KG_SCH_GEN_PPP_NO_V 0x78
#define KG_SCH_GEN_MPLS1 0x09
#define KG_SCH_GEN_MPLS2 0x19
#define KG_SCH_GEN_MPLS3 0x29
#define KG_SCH_GEN_MPLS1_NO_V 0x79
#define KG_SCH_GEN_MPLS_LAST 0x0a
#define KG_SCH_GEN_MPLS_LAST_NO_V 0x7a
#define KG_SCH_GEN_IPV4 0x0b
#define KG_SCH_GEN_IPV6 0x1b
#define KG_SCH_GEN_L3_NO_V 0x7b
#define KG_SCH_GEN_IPV4_TUNNELED 0x0c
#define KG_SCH_GEN_IPV6_TUNNELED 0x1c
#define KG_SCH_GEN_MIN_ENCAP 0x2c
#define KG_SCH_GEN_IP2_NO_V 0x7c
#define KG_SCH_GEN_GRE 0x0d
#define KG_SCH_GEN_GRE_NO_V 0x7d
#define KG_SCH_GEN_TCP 0x0e
#define KG_SCH_GEN_UDP 0x1e
#define KG_SCH_GEN_IPSEC_AH 0x2e
#define KG_SCH_GEN_SCTP 0x3e
#define KG_SCH_GEN_DCCP 0x4e
#define KG_SCH_GEN_IPSEC_ESP 0x6e
#define KG_SCH_GEN_L4_NO_V 0x7e
#define KG_SCH_GEN_NEXTHDR 0x7f
/* shifts */
#define KG_SCH_PP_SHIFT_HIGH_SHIFT 27
#define KG_SCH_PP_SHIFT_LOW_SHIFT 12
#define KG_SCH_PP_MASK_SHIFT 16
#define KG_SCH_MODE_CCOBASE_SHIFT 24
#define KG_SCH_DEF_MAC_ADDR_SHIFT 30
#define KG_SCH_DEF_TCI_SHIFT 28
#define KG_SCH_DEF_ENET_TYPE_SHIFT 26
#define KG_SCH_DEF_PPP_SESSION_ID_SHIFT 24
#define KG_SCH_DEF_PPP_PROTOCOL_ID_SHIFT 22
#define KG_SCH_DEF_MPLS_LABEL_SHIFT 20
#define KG_SCH_DEF_IP_ADDR_SHIFT 18
#define KG_SCH_DEF_PROTOCOL_TYPE_SHIFT 16
#define KG_SCH_DEF_IP_TOS_TC_SHIFT 14
#define KG_SCH_DEF_IPV6_FLOW_LABEL_SHIFT 12
#define KG_SCH_DEF_IPSEC_SPI_SHIFT 10
#define KG_SCH_DEF_L4_PORT_SHIFT 8
#define KG_SCH_DEF_TCP_FLAG_SHIFT 6
#define KG_SCH_HASH_CONFIG_SHIFT_SHIFT 24
#define KG_SCH_GEN_MASK_SHIFT 16
#define KG_SCH_GEN_HT_SHIFT 8
#define KG_SCH_GEN_SIZE_SHIFT 24
#define KG_SCH_GEN_DEF_SHIFT 29
#define FM_PCD_KG_KGAR_NUM_SHIFT 16
/* others */
#define NUM_OF_SW_DEFAULTS 3
#define MAX_PP_SHIFT 23
#define MAX_KG_SCH_SIZE 16
#define MASK_FOR_GENERIC_BASE_ID 0x20
#define MAX_HASH_SHIFT 40
#define MAX_KG_SCH_FQID_BIT_OFFSET 31
#define MAX_KG_SCH_PP_BIT_OFFSET 15
#define MAX_DIST_FQID_SHIFT 23
#define GET_MASK_SEL_SHIFT(shift,i) \
switch (i) { \
case (0):shift = 26;break; \
case (1):shift = 20;break; \
case (2):shift = 10;break; \
case (3):shift = 4;break; \
default: \
RETURN_ERROR(MAJOR, E_INVALID_VALUE, NO_MSG); \
}
#define GET_MASK_OFFSET_SHIFT(shift,i) \
switch (i) { \
case (0):shift = 16;break; \
case (1):shift = 0;break; \
case (2):shift = 28;break; \
case (3):shift = 24;break; \
default: \
RETURN_ERROR(MAJOR, E_INVALID_VALUE, NO_MSG); \
}
#define GET_MASK_SHIFT(shift,i) \
switch (i) { \
case (0):shift = 24;break; \
case (1):shift = 16;break; \
case (2):shift = 8;break; \
case (3):shift = 0;break; \
default: \
RETURN_ERROR(MAJOR, E_INVALID_VALUE, NO_MSG); \
}
/***********************************************************************/
/* Keygen defines */
/***********************************************************************/
#define KG_DOUBLE_MEANING_REGS_OFFSET 0x100
#define NO_VALIDATION 0x70
#define KG_ACTION_REG_TO 1024
#define KG_MAX_PROFILE 255
#define SCHEME_ALWAYS_DIRECT 0xFFFFFFFF
#endif /* __FM_KG_H */

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/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_manip.h
@Description FM PCD manip...
*//***************************************************************************/
#ifndef __FM_MANIP_H
#define __FM_MANIP_H
#include "std_ext.h"
#include "error_ext.h"
#include "list_ext.h"
#include "fm_cc.h"
/***********************************************************************/
/* Header manipulations defines */
/***********************************************************************/
#define NUM_OF_SCRATCH_POOL_BUFFERS 1000 /*TODO - Change it!!*/
#if (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10))
#define HMAN_OC_RMV_N_OR_INSRT_INT_FRM_HDR 0x2e
#define HMAN_OC_INSRT_HDR_BY_TEMPL_N_OR_FRAG_AFTER 0x31
#define HMAN_OC_MV_INT_FRAME_HDR_FROM_FRM_TO_BUFFER_PREFFIX 0x2f
#define HMAN_OC_CAPWAP_RMV_DTLS_IF_EXIST 0x30
#define HMAN_OC_CAPWAP_REASSEMBLY 0x11 /* dummy */
#define HMAN_OC_CAPWAP_INDEXED_STATS 0x32 /* dummy */
#define HMAN_OC_CAPWAP_FRAGMENTATION 0x33
#else
#define HMAN_OC_CAPWAP_MANIP 0x2F
#define HMAN_OC_CAPWAP_FRAG_CHECK 0x2E
#define HMAN_OC_CAPWAP_FRAGMENTATION 0x33
#define HMAN_OC_CAPWAP_REASSEMBLY 0x30
#endif /* (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) */
#define HMAN_OC_IP_MANIP 0x34
#define HMAN_OC_IP_FRAGMENTATION 0x74
#define HMAN_OC_IP_REASSEMBLY 0xB4
#define HMAN_OC_IPSEC_MANIP 0xF4
#define HMAN_OC 0x35
#if (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10))
#define HMAN_RMV_HDR 0x80000000
#define HMAN_INSRT_INT_FRM_HDR 0x40000000
#define UDP_CHECKSUM_FIELD_OFFSET_FROM_UDP 6
#define UDP_CHECKSUM_FIELD_SIZE 2
#define UDP_LENGTH_FIELD_OFFSET_FROM_UDP 4
#define IPv4_DSCECN_FIELD_OFFSET_FROM_IP 1
#define IPv4_TOTALLENGTH_FIELD_OFFSET_FROM_IP 2
#define IPv4_HDRCHECKSUM_FIELD_OFFSET_FROM_IP 10
#define VLAN_TAG_FIELD_OFFSET_FROM_ETH 12
#define IPv4_ID_FIELD_OFFSET_FROM_IP 4
#define IPv6_PAYLOAD_LENGTH_OFFSET_FROM_IP 4
#define IPv6_NEXT_HEADER_OFFSET_FROM_IP 6
#define FM_PCD_MANIP_CAPWAP_REASM_TABLE_SIZE 0x80
#define FM_PCD_MANIP_CAPWAP_REASM_TABLE_ALIGN 8
#define FM_PCD_MANIP_CAPWAP_REASM_RFD_SIZE 32
#define FM_PCD_MANIP_CAPWAP_REASM_AUTO_LEARNING_HASH_ENTRY_SIZE 4
#define FM_PCD_MANIP_CAPWAP_REASM_TIME_OUT_ENTRY_SIZE 8
#define FM_PCD_MANIP_CAPWAP_REASM_TIME_OUT_BETWEEN_FRAMES 0x40000000
#define FM_PCD_MANIP_CAPWAP_REASM_HALT_ON_DUPLICATE_FRAG 0x10000000
#define FM_PCD_MANIP_CAPWAP_REASM_AUTOMATIC_LEARNIN_HASH_8_WAYS 0x08000000
#define FM_PCD_MANIP_CAPWAP_REASM_PR_COPY 0x00800000
#define FM_PCD_MANIP_CAPWAP_FRAG_COMPR_OPTION_FIELD_EN 0x80000000
#define FM_PCD_MANIP_INDEXED_STATS_ENTRY_SIZE 4
#define FM_PCD_MANIP_INDEXED_STATS_CNIA 0x20000000
#define FM_PCD_MANIP_INDEXED_STATS_DPD 0x10000000
#endif /* (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) */
#if (DPAA_VERSION >= 11)
#define FM_PCD_MANIP_CAPWAP_DTLS 0x00040000
#define FM_PCD_MANIP_CAPWAP_NADEN 0x20000000
#define FM_PCD_MANIP_CAPWAP_FRAG_CHECK_MTU_SHIFT 16
#define FM_PCD_MANIP_CAPWAP_FRAG_CHECK_NO_FRAGMENTATION 0xFFFF0000
#define FM_PCD_MANIP_CAPWAP_FRAG_CHECK_CNIA 0x20000000
#define FM_PCD_MANIP_CAPWAP_FRAG_COMPRESS_EN 0x04000000
#define FM_PCD_MANIP_CAPWAP_FRAG_SCRATCH_BPID 24
#define FM_PCD_MANIP_CAPWAP_FRAG_SG_BDID_EN 0x08000000
#define FM_PCD_MANIP_CAPWAP_FRAG_SG_BDID_MASK 0xFF000000
#define FM_PCD_MANIP_CAPWAP_FRAG_SG_BDID_SHIFT 24
#endif /* (DPAA_VERSION >= 11) */
#define FM_PCD_MANIP_REASM_TABLE_SIZE 0x40
#define FM_PCD_MANIP_REASM_TABLE_ALIGN 8
#define FM_PCD_MANIP_REASM_COMMON_PARAM_TABLE_SIZE 64
#define FM_PCD_MANIP_REASM_COMMON_PARAM_TABLE_ALIGN 8
#define FM_PCD_MANIP_REASM_TIME_OUT_BETWEEN_FRAMES 0x80000000
#define FM_PCD_MANIP_REASM_COUPLING_ENABLE 0x40000000
#define FM_PCD_MANIP_REASM_COUPLING_MASK 0xFF000000
#define FM_PCD_MANIP_REASM_COUPLING_SHIFT 24
#define FM_PCD_MANIP_REASM_LIODN_MASK 0x0000003F
#define FM_PCD_MANIP_REASM_LIODN_SHIFT 56
#define FM_PCD_MANIP_REASM_ELIODN_MASK 0x000003c0
#define FM_PCD_MANIP_REASM_ELIODN_SHIFT 38
#define FM_PCD_MANIP_REASM_COMMON_INT_BUFFER_IDX_MASK 0x000000FF
#define FM_PCD_MANIP_REASM_COMMON_INT_BUFFER_IDX_SHIFT 24
#define FM_PCD_MANIP_REASM_TIMEOUT_THREAD_THRESH 1024
#define FM_PCD_MANIP_IP_MTU_SHIFT 16
#define FM_PCD_MANIP_IP_NO_FRAGMENTATION 0xFFFF0000
#define FM_PCD_MANIP_IP_CNIA 0x20000000
#define FM_PCD_MANIP_IP_FRAG_DF_SHIFT 28
#define FM_PCD_MANIP_IP_FRAG_SCRATCH_BPID 24
#define FM_PCD_MANIP_IP_FRAG_SG_BDID_EN 0x08000000
#define FM_PCD_MANIP_IP_FRAG_SG_BDID_MASK 0xFF000000
#define FM_PCD_MANIP_IP_FRAG_SG_BDID_SHIFT 24
#define FM_PCD_MANIP_IPSEC_DEC 0x10000000
#define FM_PCD_MANIP_IPSEC_VIPV_EN 0x08000000
#define FM_PCD_MANIP_IPSEC_ECN_EN 0x04000000
#define FM_PCD_MANIP_IPSEC_DSCP_EN 0x02000000
#define FM_PCD_MANIP_IPSEC_VIPL_EN 0x01000000
#define FM_PCD_MANIP_IPSEC_NADEN 0x20000000
#define FM_PCD_MANIP_IPSEC_IP_HDR_LEN_MASK 0x00FF0000
#define FM_PCD_MANIP_IPSEC_IP_HDR_LEN_SHIFT 16
#define FM_PCD_MANIP_IPSEC_ARW_SIZE_MASK 0xFFFF0000
#define FM_PCD_MANIP_IPSEC_ARW_SIZE_SHIFT 16
#define e_FM_MANIP_IP_INDX 1
#define HMCD_OPCODE_GENERIC_RMV 0x01
#define HMCD_OPCODE_GENERIC_INSRT 0x02
#define HMCD_OPCODE_GENERIC_REPLACE 0x05
#define HMCD_OPCODE_L2_RMV 0x08
#define HMCD_OPCODE_L2_INSRT 0x09
#define HMCD_OPCODE_VLAN_PRI_UPDATE 0x0B
#define HMCD_OPCODE_IPV4_UPDATE 0x0C
#define HMCD_OPCODE_IPV6_UPDATE 0x10
#define HMCD_OPCODE_TCP_UDP_UPDATE 0x0E
#define HMCD_OPCODE_TCP_UDP_CHECKSUM 0x14
#define HMCD_OPCODE_REPLACE_IP 0x12
#define HMCD_OPCODE_RMV_TILL 0x15
#define HMCD_OPCODE_UDP_INSRT 0x16
#define HMCD_OPCODE_IP_INSRT 0x17
#define HMCD_OPCODE_CAPWAP_RMV 0x18
#define HMCD_OPCODE_CAPWAP_INSRT 0x18
#define HMCD_OPCODE_GEN_FIELD_REPLACE 0x19
#define HMCD_LAST 0x00800000
#define HMCD_DSCP_VALUES 64
#define HMCD_BASIC_SIZE 4
#define HMCD_PTR_SIZE 4
#define HMCD_PARAM_SIZE 4
#define HMCD_IPV4_ADDR_SIZE 4
#define HMCD_IPV6_ADDR_SIZE 0x10
#define HMCD_L4_HDR_SIZE 8
#define HMCD_CAPWAP_INSRT 0x00010000
#define HMCD_INSRT_UDP_LITE 0x00010000
#define HMCD_IP_ID_MASK 0x0000FFFF
#define HMCD_IP_SIZE_MASK 0x0000FF00
#define HMCD_IP_SIZE_SHIFT 8
#define HMCD_IP_LAST_PID_MASK 0x000000FF
#define HMCD_IP_OR_QOS 0x00010000
#define HMCD_IP_L4_CS_CALC 0x00040000
#define HMCD_IP_DF_MODE 0x00400000
#define HMCD_OC_SHIFT 24
#define HMCD_RMV_OFFSET_SHIFT 0
#define HMCD_RMV_SIZE_SHIFT 8
#define HMCD_INSRT_OFFSET_SHIFT 0
#define HMCD_INSRT_SIZE_SHIFT 8
#define HMTD_CFG_TYPE 0x4000
#define HMTD_CFG_EXT_HMCT 0x0080
#define HMTD_CFG_PRS_AFTER_HM 0x0040
#define HMTD_CFG_NEXT_AD_EN 0x0020
#define HMCD_RMV_L2_ETHERNET 0
#define HMCD_RMV_L2_STACKED_QTAGS 1
#define HMCD_RMV_L2_ETHERNET_AND_MPLS 2
#define HMCD_RMV_L2_MPLS 3
#define HMCD_RMV_L2_PPPOE 4
#define HMCD_INSRT_L2_MPLS 0
#define HMCD_INSRT_N_UPDATE_L2_MPLS 1
#define HMCD_INSRT_L2_PPPOE 2
#define HMCD_INSRT_L2_SIZE_SHIFT 24
#define HMCD_L2_MODE_SHIFT 16
#define HMCD_VLAN_PRI_REP_MODE_SHIFT 16
#define HMCD_VLAN_PRI_UPDATE 0
#define HMCD_VLAN_PRI_UPDATE_DSCP_TO_VPRI 1
#define HMCD_IPV4_UPDATE_TTL 0x00000001
#define HMCD_IPV4_UPDATE_TOS 0x00000002
#define HMCD_IPV4_UPDATE_DST 0x00000020
#define HMCD_IPV4_UPDATE_SRC 0x00000040
#define HMCD_IPV4_UPDATE_ID 0x00000080
#define HMCD_IPV4_UPDATE_TOS_SHIFT 8
#define HMCD_IPV6_UPDATE_HL 0x00000001
#define HMCD_IPV6_UPDATE_TC 0x00000002
#define HMCD_IPV6_UPDATE_DST 0x00000040
#define HMCD_IPV6_UPDATE_SRC 0x00000080
#define HMCD_IPV6_UPDATE_TC_SHIFT 8
#define HMCD_TCP_UDP_UPDATE_DST 0x00004000
#define HMCD_TCP_UDP_UPDATE_SRC 0x00008000
#define HMCD_TCP_UDP_UPDATE_SRC_SHIFT 16
#define HMCD_IP_REPLACE_REPLACE_IPV4 0x00000000
#define HMCD_IP_REPLACE_REPLACE_IPV6 0x00010000
#define HMCD_IP_REPLACE_TTL_HL 0x00200000
#define HMCD_IP_REPLACE_ID 0x00400000
#define HMCD_IP_REPLACE_L3HDRSIZE_SHIFT 24
#define HMCD_GEN_FIELD_SIZE_SHIFT 16
#define HMCD_GEN_FIELD_SRC_OFF_SHIFT 8
#define HMCD_GEN_FIELD_DST_OFF_SHIFT 0
#define HMCD_GEN_FIELD_MASK_EN 0x00400000
#define HMCD_GEN_FIELD_MASK_OFF_SHIFT 16
#define HMCD_GEN_FIELD_MASK_SHIFT 24
#define DSCP_TO_VLAN_TABLE_SIZE 32
#define MANIP_GET_HMCT_SIZE(h_Manip) (((t_FmPcdManip *)h_Manip)->tableSize)
#define MANIP_GET_DATA_SIZE(h_Manip) (((t_FmPcdManip *)h_Manip)->dataSize)
#define MANIP_GET_HMCT_PTR(h_Manip) (((t_FmPcdManip *)h_Manip)->p_Hmct)
#define MANIP_GET_DATA_PTR(h_Manip) (((t_FmPcdManip *)h_Manip)->p_Data)
#define MANIP_SET_HMCT_PTR(h_Manip, h_NewPtr) (((t_FmPcdManip *)h_Manip)->p_Hmct = h_NewPtr)
#define MANIP_SET_DATA_PTR(h_Manip, h_NewPtr) (((t_FmPcdManip *)h_Manip)->p_Data = h_NewPtr)
#define MANIP_GET_HMTD_PTR(h_Manip) (((t_FmPcdManip *)h_Manip)->h_Ad)
#define MANIP_DONT_REPARSE(h_Manip) (((t_FmPcdManip *)h_Manip)->dontParseAfterManip)
#define MANIP_SET_PREV(h_Manip, h_Prev) (((t_FmPcdManip *)h_Manip)->h_PrevManip = h_Prev)
#define MANIP_GET_OWNERS(h_Manip) (((t_FmPcdManip *)h_Manip)->owner)
#define MANIP_GET_TYPE(h_Manip) (((t_FmPcdManip *)h_Manip)->type)
#define MANIP_SET_UNIFIED_TBL_PTR_INDICATION(h_Manip) (((t_FmPcdManip *)h_Manip)->unifiedTablePtr = TRUE)
#define MANIP_GET_MURAM(h_Manip) (((t_FmPcd *)((t_FmPcdManip *)h_Manip)->h_FmPcd)->h_FmMuram)
#define MANIP_FREE_HMTD(h_Manip) \
{if (((t_FmPcdManip *)h_Manip)->muramAllocate) \
FM_MURAM_FreeMem(((t_FmPcd *)((t_FmPcdManip *)h_Manip)->h_FmPcd)->h_FmMuram, ((t_FmPcdManip *)h_Manip)->h_Ad);\
else \
XX_Free(((t_FmPcdManip *)h_Manip)->h_Ad); \
((t_FmPcdManip *)h_Manip)->h_Ad = NULL; \
}
/* position regarding Manip SW structure */
#define MANIP_IS_FIRST(h_Manip) (!(((t_FmPcdManip *)h_Manip)->h_PrevManip))
#define MANIP_IS_CASCADED(h_Manip) (((t_FmPcdManip *)h_Manip)->cascaded)
#define MANIP_IS_UNIFIED(h_Manip) (!(((t_FmPcdManip *)h_Manip)->unifiedPosition == e_MANIP_UNIFIED_NONE))
#define MANIP_IS_UNIFIED_NON_FIRST(h_Manip) ((((t_FmPcdManip *)h_Manip)->unifiedPosition == e_MANIP_UNIFIED_MID) || \
(((t_FmPcdManip *)h_Manip)->unifiedPosition == e_MANIP_UNIFIED_LAST))
#define MANIP_IS_UNIFIED_NON_LAST(h_Manip) ((((t_FmPcdManip *)h_Manip)->unifiedPosition == e_MANIP_UNIFIED_FIRST) ||\
(((t_FmPcdManip *)h_Manip)->unifiedPosition == e_MANIP_UNIFIED_MID))
#define MANIP_IS_UNIFIED_FIRST(h_Manip) (((t_FmPcdManip *)h_Manip)->unifiedPosition == e_MANIP_UNIFIED_FIRST)
#define MANIP_IS_UNIFIED_LAST(h_Manip) (((t_FmPcdManip *)h_Manip)->unifiedPosition == e_MANIP_UNIFIED_LAST)
#define MANIP_UPDATE_UNIFIED_POSITION(h_Manip) (((t_FmPcdManip *)h_Manip)->unifiedPosition = \
(((t_FmPcdManip *)h_Manip)->unifiedPosition == e_MANIP_UNIFIED_NONE)? \
e_MANIP_UNIFIED_LAST : e_MANIP_UNIFIED_MID)
typedef enum e_ManipUnifiedPosition {
e_MANIP_UNIFIED_NONE = 0,
e_MANIP_UNIFIED_FIRST,
e_MANIP_UNIFIED_MID,
e_MANIP_UNIFIED_LAST
} e_ManipUnifiedPosition;
typedef enum e_ManipInfo {
e_MANIP_HMTD,
e_MANIP_HMCT,
e_MANIP_HANDLER_TABLE_OWNER
}e_ManipInfo;
/***********************************************************************/
/* Memory map */
/***********************************************************************/
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(push,1)
#endif /* defined(__MWERKS__) && ... */
#if (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10))
typedef struct t_CapwapReasmPram {
volatile uint32_t mode;
volatile uint32_t autoLearnHashTblPtr;
volatile uint32_t intStatsTblPtr;
volatile uint32_t reasmFrmDescPoolTblPtr;
volatile uint32_t reasmFrmDescIndexPoolTblPtr;
volatile uint32_t timeOutTblPtr;
volatile uint32_t bufferPoolIdAndRisc1SetIndexes;
volatile uint32_t risc23SetIndexes;
volatile uint32_t risc4SetIndexesAndExtendedStatsTblPtr;
volatile uint32_t extendedStatsTblPtr;
volatile uint32_t expirationDelay;
volatile uint32_t totalProcessedFragCounter;
volatile uint32_t totalUnsuccessfulReasmFramesCounter;
volatile uint32_t totalDuplicatedFragCounter;
volatile uint32_t totalMalformdFragCounter;
volatile uint32_t totalTimeOutCounter;
volatile uint32_t totalSetBusyCounter;
volatile uint32_t totalRfdPoolBusyCounter;
volatile uint32_t totalDiscardedFragsCounter;
volatile uint32_t totalMoreThan16FramesCounter;
volatile uint32_t internalBufferBusy;
volatile uint32_t externalBufferBusy;
volatile uint32_t reserved1[4];
} t_CapwapReasmPram;
#endif /* (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) */
typedef _Packed struct t_ReassTbl {
volatile uint16_t waysNumAndSetSize;
volatile uint16_t autoLearnHashKeyMask;
volatile uint32_t reassCommonPrmTblPtr;
volatile uint32_t liodnAlAndAutoLearnHashTblPtrHi;
volatile uint32_t autoLearnHashTblPtrLow;
volatile uint32_t liodnSlAndAutoLearnSetLockTblPtrHi;
volatile uint32_t autoLearnSetLockTblPtrLow;
volatile uint16_t minFragSize; /* Not relevant for CAPWAP*/
volatile uint16_t maxReassemblySize; /* Only relevant for CAPWAP*/
volatile uint32_t totalSuccessfullyReasmFramesCounter;
volatile uint32_t totalValidFragmentCounter;
volatile uint32_t totalProcessedFragCounter;
volatile uint32_t totalMalformdFragCounter;
volatile uint32_t totalSetBusyCounter;
volatile uint32_t totalDiscardedFragsCounter;
volatile uint32_t totalMoreThan16FramesCounter;
volatile uint32_t reserved2[2];
} _PackedType t_ReassTbl;
typedef struct t_ReassCommonTbl {
volatile uint32_t timeoutModeAndFqid;
volatile uint32_t reassFrmDescIndexPoolTblPtr;
volatile uint32_t liodnAndReassFrmDescPoolPtrHi;
volatile uint32_t reassFrmDescPoolPtrLow;
volatile uint32_t timeOutTblPtr;
volatile uint32_t expirationDelay;
volatile uint32_t internalBufferManagement;
volatile uint32_t reserved2;
volatile uint32_t totalTimeOutCounter;
volatile uint32_t totalRfdPoolBusyCounter;
volatile uint32_t totalInternalBufferBusy;
volatile uint32_t totalExternalBufferBusy;
volatile uint32_t totalSgFragmentCounter;
volatile uint32_t totalDmaSemaphoreDepletionCounter;
volatile uint32_t totalNCSPCounter;
volatile uint32_t discardMask;
} t_ReassCommonTbl;
typedef _Packed struct t_Hmtd {
volatile uint16_t cfg;
volatile uint8_t eliodnOffset;
volatile uint8_t extHmcdBasePtrHi;
volatile uint32_t hmcdBasePtr;
volatile uint16_t nextAdIdx;
volatile uint8_t res1;
volatile uint8_t opCode;
volatile uint32_t res2;
} _PackedType t_Hmtd;
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(pop)
#endif /* defined(__MWERKS__) && ... */
/***********************************************************************/
/* Driver's internal structures */
/***********************************************************************/
#if (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10))
typedef struct
{
t_Handle p_AutoLearnHashTbl;
t_Handle p_ReassmFrmDescrPoolTbl;
t_Handle p_ReassmFrmDescrIndxPoolTbl;
t_Handle p_TimeOutTbl;
uint16_t maxNumFramesInProcess;
uint8_t numOfTasks;
//uint8_t poolId;
uint8_t prOffset;
uint16_t dataOffset;
uint8_t sgBpid;
uint8_t hwPortId;
uint32_t fqidForTimeOutFrames;
uint32_t timeoutRoutineRequestTime;
uint32_t bitFor1Micro;
} t_CapwapFragParams;
#endif /* (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) */
typedef struct
{
t_AdOfTypeContLookup *p_Frag;
#if (DPAA_VERSION == 10)
uint8_t scratchBpid;
#endif /* (DPAA_VERSION == 10) */
} t_FragParams;
typedef struct t_ReassmParams
{
e_NetHeaderType hdr; /* Header selection */
t_ReassCommonTbl *p_ReassCommonTbl;
uintptr_t reassFrmDescrIndxPoolTblAddr;
uintptr_t reassFrmDescrPoolTblAddr;
uintptr_t timeOutTblAddr;
uintptr_t internalBufferPoolManagementIndexAddr;
uintptr_t internalBufferPoolAddr;
uint32_t maxNumFramesInProcess;
uint8_t sgBpid;
uint8_t dataMemId;
uint16_t dataLiodnOffset;
uint32_t fqidForTimeOutFrames;
e_FmPcdManipReassemTimeOutMode timeOutMode;
uint32_t timeoutThresholdForReassmProcess;
union {
struct {
t_Handle h_Ipv4Ad;
t_Handle h_Ipv6Ad;
bool ipv6Assigned;
t_ReassTbl *p_Ipv4ReassTbl;
t_ReassTbl *p_Ipv6ReassTbl;
uintptr_t ipv4AutoLearnHashTblAddr;
uintptr_t ipv6AutoLearnHashTblAddr;
uintptr_t ipv4AutoLearnSetLockTblAddr;
uintptr_t ipv6AutoLearnSetLockTblAddr;
uint16_t minFragSize[2];
e_FmPcdManipReassemWaysNumber numOfFramesPerHashEntry[2];
uint8_t relativeSchemeId[2];
t_Handle h_Ipv4Scheme;
t_Handle h_Ipv6Scheme;
uint32_t nonConsistentSpFqid;
} ip;
struct {
t_Handle h_Ad;
t_ReassTbl *p_ReassTbl;
uintptr_t autoLearnHashTblAddr;
uintptr_t autoLearnSetLockTblAddr;
uint16_t maxRessembledsSize;
e_FmPcdManipReassemWaysNumber numOfFramesPerHashEntry;
uint8_t relativeSchemeId;
t_Handle h_Scheme;
} capwap;
};
} t_ReassmParams;
typedef struct{
e_FmPcdManipType type;
t_FmPcdManipParams manipParams;
bool muramAllocate;
t_Handle h_Ad;
uint32_t opcode;
bool rmv;
bool insrt;
t_Handle h_NextManip;
t_Handle h_PrevManip;
e_FmPcdManipType nextManipType;
/* HdrManip parameters*/
uint8_t *p_Hmct;
uint8_t *p_Data;
bool dontParseAfterManip;
bool fieldUpdate;
bool custom;
uint16_t tableSize;
uint8_t dataSize;
bool cascaded;
e_ManipUnifiedPosition unifiedPosition;
/* end HdrManip */
uint8_t *p_Template;
uint16_t owner;
uint32_t updateParams;
uint32_t shadowUpdateParams;
bool frag;
bool reassm;
uint16_t sizeForFragmentation;
#if (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10))
t_Handle h_Frag;
t_CapwapFragParams capwapFragParams;
#endif /* (defined(FM_CAPWAP_SUPPORT) && (DPAA_VERSION == 10)) */
union {
t_ReassmParams reassmParams;
t_FragParams fragParams;
};
uint8_t icOffset;
uint16_t ownerTmp;
bool cnia;
t_Handle p_StatsTbl;
t_Handle h_FmPcd;
t_List nodesLst;
t_Handle h_Spinlock;
} t_FmPcdManip;
typedef struct t_FmPcdCcSavedManipParams
{
union
{
struct
{
uint16_t dataOffset;
//uint8_t poolId;
}capwapParams;
struct
{
uint16_t dataOffset;
uint8_t poolId;
}ipParams;
};
} t_FmPcdCcSavedManipParams;
#endif /* __FM_MANIP_H */

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/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_pcd.h
@Description FM PCD ...
*//***************************************************************************/
#ifndef __FM_PCD_H
#define __FM_PCD_H
#include "std_ext.h"
#include "error_ext.h"
#include "list_ext.h"
#include "fm_pcd_ext.h"
#include "fm_common.h"
#include "fsl_fman_prs.h"
#include "fsl_fman_kg.h"
#define __ERR_MODULE__ MODULE_FM_PCD
/****************************/
/* Defaults */
/****************************/
#define DEFAULT_plcrAutoRefresh FALSE
#define DEFAULT_fmPcdKgErrorExceptions (FM_EX_KG_DOUBLE_ECC | FM_EX_KG_KEYSIZE_OVERFLOW)
#define DEFAULT_fmPcdPlcrErrorExceptions (FM_PCD_EX_PLCR_DOUBLE_ECC | FM_PCD_EX_PLCR_INIT_ENTRY_ERROR)
#define DEFAULT_fmPcdPlcrExceptions 0
#define DEFAULT_fmPcdPrsErrorExceptions (FM_PCD_EX_PRS_DOUBLE_ECC)
#define DEFAULT_fmPcdPrsExceptions FM_PCD_EX_PRS_SINGLE_ECC
#define DEFAULT_numOfUsedProfilesPerWindow 16
#define DEFAULT_numOfSharedPlcrProfiles 4
/****************************/
/* Network defines */
/****************************/
#define UDP_HEADER_SIZE 8
#define ESP_SPI_OFFSET 0
#define ESP_SPI_SIZE 4
#define ESP_SEQ_NUM_OFFSET ESP_SPI_SIZE
#define ESP_SEQ_NUM_SIZE 4
/****************************/
/* General defines */
/****************************/
#define ILLEGAL_CLS_PLAN 0xff
#define ILLEGAL_NETENV 0xff
#define FM_PCD_MAX_NUM_OF_ALIAS_HDRS 3
/****************************/
/* Error defines */
/****************************/
#define FM_PCD_EX_PLCR_DOUBLE_ECC 0x20000000
#define FM_PCD_EX_PLCR_INIT_ENTRY_ERROR 0x10000000
#define FM_PCD_EX_PLCR_PRAM_SELF_INIT_COMPLETE 0x08000000
#define FM_PCD_EX_PLCR_ATOMIC_ACTION_COMPLETE 0x04000000
#define GET_FM_PCD_EXCEPTION_FLAG(bitMask, exception) \
switch (exception){ \
case e_FM_PCD_KG_EXCEPTION_DOUBLE_ECC: \
bitMask = FM_EX_KG_DOUBLE_ECC; break; \
case e_FM_PCD_PLCR_EXCEPTION_DOUBLE_ECC: \
bitMask = FM_PCD_EX_PLCR_DOUBLE_ECC; break; \
case e_FM_PCD_KG_EXCEPTION_KEYSIZE_OVERFLOW: \
bitMask = FM_EX_KG_KEYSIZE_OVERFLOW; break; \
case e_FM_PCD_PLCR_EXCEPTION_INIT_ENTRY_ERROR: \
bitMask = FM_PCD_EX_PLCR_INIT_ENTRY_ERROR; break; \
case e_FM_PCD_PLCR_EXCEPTION_PRAM_SELF_INIT_COMPLETE: \
bitMask = FM_PCD_EX_PLCR_PRAM_SELF_INIT_COMPLETE; break; \
case e_FM_PCD_PLCR_EXCEPTION_ATOMIC_ACTION_COMPLETE: \
bitMask = FM_PCD_EX_PLCR_ATOMIC_ACTION_COMPLETE; break; \
case e_FM_PCD_PRS_EXCEPTION_DOUBLE_ECC: \
bitMask = FM_PCD_EX_PRS_DOUBLE_ECC; break; \
case e_FM_PCD_PRS_EXCEPTION_SINGLE_ECC: \
bitMask = FM_PCD_EX_PRS_SINGLE_ECC; break; \
default: bitMask = 0;break;}
/***********************************************************************/
/* Policer defines */
/***********************************************************************/
#define FM_PCD_PLCR_GCR_STEN 0x40000000
#define FM_PCD_PLCR_DOUBLE_ECC 0x80000000
#define FM_PCD_PLCR_INIT_ENTRY_ERROR 0x40000000
#define FM_PCD_PLCR_PRAM_SELF_INIT_COMPLETE 0x80000000
#define FM_PCD_PLCR_ATOMIC_ACTION_COMPLETE 0x40000000
/***********************************************************************/
/* Memory map */
/***********************************************************************/
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(push,1)
#endif /* defined(__MWERKS__) && ... */
typedef struct {
/* General Configuration and Status Registers */
volatile uint32_t fmpl_gcr; /* 0x000 FMPL_GCR - FM Policer General Configuration */
volatile uint32_t fmpl_gsr; /* 0x004 FMPL_GSR - FM Policer Global Status Register */
volatile uint32_t fmpl_evr; /* 0x008 FMPL_EVR - FM Policer Event Register */
volatile uint32_t fmpl_ier; /* 0x00C FMPL_IER - FM Policer Interrupt Enable Register */
volatile uint32_t fmpl_ifr; /* 0x010 FMPL_IFR - FM Policer Interrupt Force Register */
volatile uint32_t fmpl_eevr; /* 0x014 FMPL_EEVR - FM Policer Error Event Register */
volatile uint32_t fmpl_eier; /* 0x018 FMPL_EIER - FM Policer Error Interrupt Enable Register */
volatile uint32_t fmpl_eifr; /* 0x01C FMPL_EIFR - FM Policer Error Interrupt Force Register */
/* Global Statistic Counters */
volatile uint32_t fmpl_rpcnt; /* 0x020 FMPL_RPC - FM Policer RED Packets Counter */
volatile uint32_t fmpl_ypcnt; /* 0x024 FMPL_YPC - FM Policer YELLOW Packets Counter */
volatile uint32_t fmpl_rrpcnt; /* 0x028 FMPL_RRPC - FM Policer Recolored RED Packet Counter */
volatile uint32_t fmpl_rypcnt; /* 0x02C FMPL_RYPC - FM Policer Recolored YELLOW Packet Counter */
volatile uint32_t fmpl_tpcnt; /* 0x030 FMPL_TPC - FM Policer Total Packet Counter */
volatile uint32_t fmpl_flmcnt; /* 0x034 FMPL_FLMC - FM Policer Frame Length Mismatch Counter */
volatile uint32_t fmpl_res0[21]; /* 0x038 - 0x08B Reserved */
/* Profile RAM Access Registers */
volatile uint32_t fmpl_par; /* 0x08C FMPL_PAR - FM Policer Profile Action Register*/
t_FmPcdPlcrProfileRegs profileRegs;
/* Error Capture Registers */
volatile uint32_t fmpl_serc; /* 0x100 FMPL_SERC - FM Policer Soft Error Capture */
volatile uint32_t fmpl_upcr; /* 0x104 FMPL_UPCR - FM Policer Uninitialized Profile Capture Register */
volatile uint32_t fmpl_res2; /* 0x108 Reserved */
/* Debug Registers */
volatile uint32_t fmpl_res3[61]; /* 0x10C-0x200 Reserved Debug*/
/* Profile Selection Mapping Registers Per Port-ID (n=1-11, 16) */
volatile uint32_t fmpl_dpmr; /* 0x200 FMPL_DPMR - FM Policer Default Mapping Register */
volatile uint32_t fmpl_pmr[63]; /*+default 0x204-0x2FF FMPL_PMR1 - FMPL_PMR63, - FM Policer Profile Mapping Registers.
(for port-ID 1-11, only for supported Port-ID registers) */
} t_FmPcdPlcrRegs;
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(pop)
#endif /* defined(__MWERKS__) && ... */
/***********************************************************************/
/* Driver's internal structures */
/***********************************************************************/
typedef struct {
bool known;
uint8_t id;
} t_FmPcdKgSchemesExtractsEntry;
typedef struct {
t_FmPcdKgSchemesExtractsEntry extractsArray[FM_PCD_KG_MAX_NUM_OF_EXTRACTS_PER_KEY];
} t_FmPcdKgSchemesExtracts;
typedef struct {
t_Handle h_Manip;
bool keepRes;
e_FmPcdEngine nextEngine;
uint8_t parseCode;
} t_FmPcdInfoForManip;
/**************************************************************************//**
@Description A structure of parameters to communicate
between the port and PCD regarding the KG scheme.
*//***************************************************************************/
typedef struct {
uint8_t netEnvId; /* in */
uint8_t numOfDistinctionUnits; /* in */
uint8_t unitIds[FM_PCD_MAX_NUM_OF_DISTINCTION_UNITS]; /* in */
uint32_t vector; /* out */
} t_NetEnvParams;
typedef struct {
bool allocated;
uint8_t ownerId; /* guestId for KG in multi-partition only.
portId for PLCR in any environment */
} t_FmPcdAllocMng;
typedef struct {
volatile bool lock;
bool used;
uint8_t owners;
uint8_t netEnvId;
uint8_t guestId;
uint8_t baseEntry;
uint16_t sizeOfGrp;
protocolOpt_t optArray[FM_PCD_MAX_NUM_OF_OPTIONS(FM_PCD_MAX_NUM_OF_CLS_PLANS)];
} t_FmPcdKgClsPlanGrp;
typedef struct {
t_Handle h_FmPcd;
uint8_t schemeId;
t_FmPcdLock *p_Lock;
bool valid;
uint8_t netEnvId;
uint8_t owners;
uint32_t matchVector;
uint32_t ccUnits;
bool nextRelativePlcrProfile;
uint16_t relativeProfileId;
uint16_t numOfProfiles;
t_FmPcdKgKeyOrder orderedArray;
e_FmPcdEngine nextEngine;
e_FmPcdDoneAction doneAction;
bool requiredActionFlag;
uint32_t requiredAction;
bool extractedOrs;
uint8_t bitOffsetInPlcrProfile;
bool directPlcr;
#if (DPAA_VERSION >= 11)
bool vspe;
#endif
} t_FmPcdKgScheme;
typedef union {
struct fman_kg_scheme_regs schemeRegs;
struct fman_kg_pe_regs portRegs;
struct fman_kg_cp_regs clsPlanRegs;
} u_FmPcdKgIndirectAccessRegs;
typedef struct {
struct fman_kg_regs *p_FmPcdKgRegs;
uint32_t schemeExceptionsBitMask;
uint8_t numOfSchemes;
t_Handle h_HwSpinlock;
uint8_t schemesIds[FM_PCD_KG_NUM_OF_SCHEMES];
t_FmPcdKgScheme schemes[FM_PCD_KG_NUM_OF_SCHEMES];
t_FmPcdKgClsPlanGrp clsPlanGrps[FM_MAX_NUM_OF_PORTS];
uint8_t emptyClsPlanGrpId;
t_FmPcdAllocMng schemesMng[FM_PCD_KG_NUM_OF_SCHEMES]; /* only for MASTER ! */
t_FmPcdAllocMng clsPlanBlocksMng[FM_PCD_MAX_NUM_OF_CLS_PLANS/CLS_PLAN_NUM_PER_GRP];
u_FmPcdKgIndirectAccessRegs *p_IndirectAccessRegs;
} t_FmPcdKg;
typedef struct {
uint16_t profilesBase;
uint16_t numOfProfiles;
t_Handle h_FmPort;
} t_FmPcdPlcrMapParam;
typedef struct {
uint16_t absoluteProfileId;
t_Handle h_FmPcd;
bool valid;
t_FmPcdLock *p_Lock;
t_FmPcdAllocMng profilesMng;
bool requiredActionFlag;
uint32_t requiredAction;
e_FmPcdEngine nextEngineOnGreen; /**< Green next engine type */
u_FmPcdPlcrNextEngineParams paramsOnGreen; /**< Green next engine params */
e_FmPcdEngine nextEngineOnYellow; /**< Yellow next engine type */
u_FmPcdPlcrNextEngineParams paramsOnYellow; /**< Yellow next engine params */
e_FmPcdEngine nextEngineOnRed; /**< Red next engine type */
u_FmPcdPlcrNextEngineParams paramsOnRed; /**< Red next engine params */
} t_FmPcdPlcrProfile;
typedef struct {
t_FmPcdPlcrRegs *p_FmPcdPlcrRegs;
uint16_t partPlcrProfilesBase;
uint16_t partNumOfPlcrProfiles;
t_FmPcdPlcrProfile profiles[FM_PCD_PLCR_NUM_ENTRIES];
uint16_t numOfSharedProfiles;
uint16_t sharedProfilesIds[FM_PCD_PLCR_NUM_ENTRIES];
t_FmPcdPlcrMapParam portsMapping[FM_MAX_NUM_OF_PORTS];
t_Handle h_HwSpinlock;
t_Handle h_SwSpinlock;
} t_FmPcdPlcr;
typedef struct {
uint32_t *p_SwPrsCode;
uint32_t *p_CurrSwPrs;
uint8_t currLabel;
struct fman_prs_regs *p_FmPcdPrsRegs;
t_FmPcdPrsLabelParams labelsTable[FM_PCD_PRS_NUM_OF_LABELS];
uint32_t fmPcdPrsPortIdStatistics;
} t_FmPcdPrs;
typedef struct {
struct {
e_NetHeaderType hdr;
protocolOpt_t opt; /* only one option !! */
} hdrs[FM_PCD_MAX_NUM_OF_INTERCHANGEABLE_HDRS];
} t_FmPcdIntDistinctionUnit;
typedef struct {
e_NetHeaderType hdr;
protocolOpt_t opt; /* only one option !! */
e_NetHeaderType aliasHdr;
} t_FmPcdNetEnvAliases;
typedef struct {
uint8_t netEnvId;
t_Handle h_FmPcd;
t_Handle h_Spinlock;
bool used;
uint8_t owners;
uint8_t clsPlanGrpId;
t_FmPcdIntDistinctionUnit units[FM_PCD_MAX_NUM_OF_DISTINCTION_UNITS];
uint32_t unitsVectors[FM_PCD_MAX_NUM_OF_DISTINCTION_UNITS];
uint32_t lcvs[FM_PCD_PRS_NUM_OF_HDRS];
uint32_t macsecVector;
t_FmPcdNetEnvAliases aliasHdrs[FM_PCD_MAX_NUM_OF_ALIAS_HDRS];
} t_FmPcdNetEnv;
typedef struct {
struct fman_prs_cfg dfltCfg;
bool plcrAutoRefresh;
uint16_t prsMaxParseCycleLimit;
} t_FmPcdDriverParam;
typedef struct {
t_Handle h_Fm;
t_Handle h_FmMuram;
t_FmRevisionInfo fmRevInfo;
uint64_t physicalMuramBase;
t_Handle h_Spinlock;
t_List freeLocksLst;
t_List acquiredLocksLst;
t_Handle h_IpcSession; /* relevant for guest only */
bool enabled;
uint8_t guestId; /**< Guest Partition Id */
uint8_t numOfEnabledGuestPartitionsPcds;
char fmPcdModuleName[MODULE_NAME_SIZE];
char fmPcdIpcHandlerModuleName[MODULE_NAME_SIZE]; /* relevant for guest only - this is the master's name */
t_FmPcdNetEnv netEnvs[FM_MAX_NUM_OF_PORTS];
t_FmPcdKg *p_FmPcdKg;
t_FmPcdPlcr *p_FmPcdPlcr;
t_FmPcdPrs *p_FmPcdPrs;
void *p_CcShadow; /**< CC MURAM shadow */
uint32_t ccShadowSize;
uint32_t ccShadowAlign;
volatile bool shadowLock;
t_Handle h_ShadowSpinlock;
t_Handle h_Hc;
uint32_t exceptions;
t_FmPcdExceptionCallback *f_Exception;
t_FmPcdIdExceptionCallback *f_FmPcdIndexedException;
t_Handle h_App;
uintptr_t ipv6FrameIdAddr;
uintptr_t capwapFrameIdAddr;
bool advancedOffloadSupport;
t_FmPcdDriverParam *p_FmPcdDriverParam;
} t_FmPcd;
#if (DPAA_VERSION >= 11)
typedef uint8_t t_FmPcdFrmReplicUpdateType;
#define FRM_REPLIC_UPDATE_COUNTER 0x01
#define FRM_REPLIC_UPDATE_INFO 0x02
#endif /* (DPAA_VERSION >= 11) */
/***********************************************************************/
/* PCD internal routines */
/***********************************************************************/
t_Error PcdGetVectorForOpt(t_FmPcd *p_FmPcd, uint8_t netEnvId, protocolOpt_t opt, uint32_t *p_Vector);
t_Error PcdGetUnitsVector(t_FmPcd *p_FmPcd, t_NetEnvParams *p_Params);
bool PcdNetEnvIsUnitWithoutOpts(t_FmPcd *p_FmPcd, uint8_t netEnvId, uint32_t unitVector);
t_Error PcdGetClsPlanGrpParams(t_FmPcd *p_FmPcd, t_FmPcdKgInterModuleClsPlanGrpParams *p_GrpParams);
void FmPcdSetClsPlanGrpId(t_FmPcd *p_FmPcd, uint8_t netEnvId, uint8_t clsPlanGrpId);
e_NetHeaderType FmPcdGetAliasHdr(t_FmPcd *p_FmPcd, uint8_t netEnvId, e_NetHeaderType hdr);
uint8_t FmPcdNetEnvGetUnitIdForSingleHdr(t_FmPcd *p_FmPcd, uint8_t netEnvId, e_NetHeaderType hdr);
uint8_t FmPcdNetEnvGetUnitId(t_FmPcd *p_FmPcd, uint8_t netEnvId, e_NetHeaderType hdr, bool interchangeable, protocolOpt_t opt);
t_Error FmPcdManipBuildIpReassmScheme(t_FmPcd *p_FmPcd, t_Handle h_NetEnv, t_Handle h_CcTree, t_Handle h_Manip, bool isIpv4, uint8_t groupId);
t_Error FmPcdManipDeleteIpReassmSchemes(t_Handle h_Manip);
t_Error FmPcdManipBuildCapwapReassmScheme(t_FmPcd *p_FmPcd, t_Handle h_NetEnv, t_Handle h_CcTree, t_Handle h_Manip, uint8_t groupId);
t_Error FmPcdManipDeleteCapwapReassmSchemes(t_Handle h_Manip);
bool FmPcdManipIpReassmIsIpv6Hdr(t_Handle h_Manip);
t_Handle KgConfig( t_FmPcd *p_FmPcd, t_FmPcdParams *p_FmPcdParams);
t_Error KgInit(t_FmPcd *p_FmPcd);
t_Error KgFree(t_FmPcd *p_FmPcd);
void KgSetClsPlan(t_Handle h_FmPcd, t_FmPcdKgInterModuleClsPlanSet *p_Set);
bool KgIsSchemeAlwaysDirect(t_Handle h_FmPcd, uint8_t schemeId);
void KgEnable(t_FmPcd *p_FmPcd);
void KgDisable(t_FmPcd *p_FmPcd);
t_Error KgAllocClsPlanEntries(t_Handle h_FmPcd, uint16_t numOfClsPlanEntries, uint8_t guestId, uint8_t *p_First);
void KgFreeClsPlanEntries(t_Handle h_FmPcd, uint16_t numOfClsPlanEntries, uint8_t guestId, uint8_t base);
/* only for MULTI partittion */
t_Error FmPcdKgAllocSchemes(t_Handle h_FmPcd, uint8_t numOfSchemes, uint8_t guestId, uint8_t *p_SchemesIds);
t_Error FmPcdKgFreeSchemes(t_Handle h_FmPcd, uint8_t numOfSchemes, uint8_t guestId, uint8_t *p_SchemesIds);
/* only for SINGLE partittion */
t_Error KgBindPortToSchemes(t_Handle h_FmPcd , uint8_t hardwarePortId, uint32_t spReg);
t_FmPcdLock *FmPcdAcquireLock(t_Handle h_FmPcd);
void FmPcdReleaseLock(t_Handle h_FmPcd, t_FmPcdLock *p_Lock);
t_Handle PlcrConfig(t_FmPcd *p_FmPcd, t_FmPcdParams *p_FmPcdParams);
t_Error PlcrInit(t_FmPcd *p_FmPcd);
t_Error PlcrFree(t_FmPcd *p_FmPcd);
void PlcrEnable(t_FmPcd *p_FmPcd);
void PlcrDisable(t_FmPcd *p_FmPcd);
uint16_t PlcrAllocProfilesForPartition(t_FmPcd *p_FmPcd, uint16_t base, uint16_t numOfProfiles, uint8_t guestId);
void PlcrFreeProfilesForPartition(t_FmPcd *p_FmPcd, uint16_t base, uint16_t numOfProfiles, uint8_t guestId);
t_Error PlcrSetPortProfiles(t_FmPcd *p_FmPcd,
uint8_t hardwarePortId,
uint16_t numOfProfiles,
uint16_t base);
t_Error PlcrClearPortProfiles(t_FmPcd *p_FmPcd, uint8_t hardwarePortId);
t_Handle PrsConfig(t_FmPcd *p_FmPcd,t_FmPcdParams *p_FmPcdParams);
t_Error PrsInit(t_FmPcd *p_FmPcd);
void PrsEnable(t_FmPcd *p_FmPcd);
void PrsDisable(t_FmPcd *p_FmPcd);
void PrsFree(t_FmPcd *p_FmPcd );
t_Error PrsIncludePortInStatistics(t_FmPcd *p_FmPcd, uint8_t hardwarePortId, bool include);
t_Error FmPcdCcGetGrpParams(t_Handle treeId, uint8_t grpId, uint32_t *p_GrpBits, uint8_t *p_GrpBase);
uint8_t FmPcdCcGetOffset(t_Handle h_CcNode);
uint8_t FmPcdCcGetParseCode(t_Handle h_CcNode);
uint16_t FmPcdCcGetNumOfKeys(t_Handle h_CcNode);
t_Error ValidateNextEngineParams(t_Handle h_FmPcd, t_FmPcdCcNextEngineParams *p_FmPcdCcNextEngineParams, e_FmPcdCcStatsMode supportedStatsMode);
void FmPcdManipUpdateOwner(t_Handle h_Manip, bool add);
t_Error FmPcdManipCheckParamsForCcNextEngine(t_FmPcdCcNextEngineParams *p_InfoForManip, uint32_t *requiredAction);
void FmPcdManipUpdateAdResultForCc(t_Handle h_Manip,
t_FmPcdCcNextEngineParams *p_CcNextEngineParams,
t_Handle p_Ad,
t_Handle *p_AdNewPtr);
void FmPcdManipUpdateAdContLookupForCc(t_Handle h_Manip, t_Handle p_Ad, t_Handle *p_AdNew, uint32_t adTableOffset);
void FmPcdManipUpdateOwner(t_Handle h_Manip, bool add);
t_Error FmPcdManipCheckParamsWithCcNodeParams(t_Handle h_Manip, t_Handle h_FmPcdCcNode);
#ifdef FM_CAPWAP_SUPPORT
t_Handle FmPcdManipApplSpecificBuild(void);
bool FmPcdManipIsCapwapApplSpecific(t_Handle h_Manip);
#endif /* FM_CAPWAP_SUPPORT */
#if (DPAA_VERSION >= 11)
void * FrmReplicGroupGetSourceTableDescriptor(t_Handle h_ReplicGroup);
void FrmReplicGroupUpdateOwner(t_Handle h_ReplicGroup, bool add);
void FrmReplicGroupUpdateAd(t_Handle h_ReplicGroup, void *p_Ad, t_Handle *h_AdNew);
void FmPcdCcGetAdTablesThatPointOnReplicGroup(t_Handle h_Node,
t_Handle h_ReplicGroup,
t_List *p_AdTables,
uint32_t *p_NumOfAdTables);
#endif /* (DPAA_VERSION >= 11) */
void EnqueueNodeInfoToRelevantLst(t_List *p_List, t_CcNodeInformation *p_CcInfo, t_Handle h_Spinlock);
void DequeueNodeInfoFromRelevantLst(t_List *p_List, t_Handle h_Info, t_Handle h_Spinlock);
t_CcNodeInformation* FindNodeInfoInReleventLst(t_List *p_List, t_Handle h_Info, t_Handle h_Spinlock);
t_List *FmPcdManipGetSpinlock(t_Handle h_Manip);
t_List *FmPcdManipGetNodeLstPointedOnThisManip(t_Handle h_Manip);
typedef struct
{
t_Handle h_StatsAd;
t_Handle h_StatsCounters;
#if (DPAA_VERSION >= 11)
t_Handle h_StatsFLRs;
#endif /* (DPAA_VERSION >= 11) */
} t_FmPcdCcStatsParams;
void NextStepAd(t_Handle h_Ad,
t_FmPcdCcStatsParams *p_FmPcdCcStatsParams,
t_FmPcdCcNextEngineParams *p_FmPcdCcNextEngineParams,
t_FmPcd *p_FmPcd);
void ReleaseLst(t_List *p_List);
static __inline__ t_Handle FmPcdGetMuramHandle(t_Handle h_FmPcd)
{
t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd;
ASSERT_COND(p_FmPcd);
return p_FmPcd->h_FmMuram;
}
static __inline__ uint64_t FmPcdGetMuramPhysBase(t_Handle h_FmPcd)
{
t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd;
ASSERT_COND(p_FmPcd);
return p_FmPcd->physicalMuramBase;
}
static __inline__ uint32_t FmPcdLockSpinlock(t_FmPcdLock *p_Lock)
{
ASSERT_COND(p_Lock);
return XX_LockIntrSpinlock(p_Lock->h_Spinlock);
}
static __inline__ void FmPcdUnlockSpinlock(t_FmPcdLock *p_Lock, uint32_t flags)
{
ASSERT_COND(p_Lock);
XX_UnlockIntrSpinlock(p_Lock->h_Spinlock, flags);
}
static __inline__ bool FmPcdLockTryLock(t_FmPcdLock *p_Lock)
{
uint32_t intFlags;
ASSERT_COND(p_Lock);
intFlags = XX_LockIntrSpinlock(p_Lock->h_Spinlock);
if (p_Lock->flag)
{
XX_UnlockIntrSpinlock(p_Lock->h_Spinlock, intFlags);
return FALSE;
}
p_Lock->flag = TRUE;
XX_UnlockIntrSpinlock(p_Lock->h_Spinlock, intFlags);
return TRUE;
}
static __inline__ void FmPcdLockUnlock(t_FmPcdLock *p_Lock)
{
ASSERT_COND(p_Lock);
p_Lock->flag = FALSE;
}
#endif /* __FM_PCD_H */

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drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_pcd_ipc.h Normal file
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@ -0,0 +1,280 @@
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**************************************************************************//**
@File fm_pcd_ipc.h
@Description FM PCD Inter-Partition prototypes, structures and definitions.
*//***************************************************************************/
#ifndef __FM_PCD_IPC_H
#define __FM_PCD_IPC_H
#include "std_ext.h"
/**************************************************************************//**
@Group FM_grp Frame Manager API
@Description FM API functions, definitions and enums
@{
*//***************************************************************************/
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(push,1)
#endif /* defined(__MWERKS__) && ... */
/**************************************************************************//**
@Description Structure for getting a sw parser address according to a label
Fields commented 'IN' are passed by the port module to be used
by the FM module.
Fields commented 'OUT' will be filled by FM before returning to port.
*//***************************************************************************/
typedef _Packed struct t_FmPcdIpcSwPrsLable
{
uint32_t enumHdr; /**< IN. The existence of this header will invoke
the sw parser code. */
uint8_t indexPerHdr; /**< IN. Normally 0, if more than one sw parser
attachments for the same header, use this
index to distinguish between them. */
} _PackedType t_FmPcdIpcSwPrsLable;
/**************************************************************************//**
@Description Structure for port-PCD communication.
Fields commented 'IN' are passed by the port module to be used
by the FM module.
Fields commented 'OUT' will be filled by FM before returning to port.
Some fields are optional (depending on configuration) and
will be analized by the port and FM modules accordingly.
*//***************************************************************************/
typedef struct t_FmPcdIpcKgSchemesParams
{
uint8_t guestId;
uint8_t numOfSchemes;
uint8_t schemesIds[FM_PCD_KG_NUM_OF_SCHEMES];
} _PackedType t_FmPcdIpcKgSchemesParams;
typedef struct t_FmPcdIpcKgClsPlanParams
{
uint8_t guestId;
uint16_t numOfClsPlanEntries;
uint8_t clsPlanBase;
} _PackedType t_FmPcdIpcKgClsPlanParams;
typedef _Packed struct t_FmPcdIpcPrsIncludePort
{
uint8_t hardwarePortId;
bool include;
} _PackedType t_FmPcdIpcPrsIncludePort;
#define FM_PCD_MAX_REPLY_SIZE 16
#define FM_PCD_MAX_MSG_SIZE 36
#define FM_PCD_MAX_REPLY_BODY_SIZE 36
typedef _Packed struct {
uint32_t msgId;
uint8_t msgBody[FM_PCD_MAX_MSG_SIZE];
} _PackedType t_FmPcdIpcMsg;
typedef _Packed struct t_FmPcdIpcReply {
uint32_t error;
uint8_t replyBody[FM_PCD_MAX_REPLY_BODY_SIZE];
} _PackedType t_FmPcdIpcReply;
typedef _Packed struct t_FmIpcResourceAllocParams {
uint8_t guestId;
uint16_t base;
uint16_t num;
}_PackedType t_FmIpcResourceAllocParams;
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(pop)
#endif /* defined(__MWERKS__) && ... */
/**************************************************************************//**
@Function FM_PCD_ALLOC_KG_SCHEMES
@Description Used by FM PCD front-end in order to allocate KG resources
@Param[in/out] t_FmPcdIpcKgAllocParams Pointer
*//***************************************************************************/
#define FM_PCD_ALLOC_KG_SCHEMES 3
/**************************************************************************//**
@Function FM_PCD_FREE_KG_SCHEMES
@Description Used by FM PCD front-end in order to Free KG resources
@Param[in/out] t_FmPcdIpcKgSchemesParams Pointer
*//***************************************************************************/
#define FM_PCD_FREE_KG_SCHEMES 4
/**************************************************************************//**
@Function FM_PCD_ALLOC_PROFILES
@Description Used by FM PCD front-end in order to allocate Policer profiles
@Param[in/out] t_FmIpcResourceAllocParams Pointer
*//***************************************************************************/
#define FM_PCD_ALLOC_PROFILES 5
/**************************************************************************//**
@Function FM_PCD_FREE_PROFILES
@Description Used by FM PCD front-end in order to Free Policer profiles
@Param[in/out] t_FmIpcResourceAllocParams Pointer
*//***************************************************************************/
#define FM_PCD_FREE_PROFILES 6
/**************************************************************************//**
@Function FM_PCD_SET_PORT_PROFILES
@Description Used by FM PCD front-end in order to allocate Policer profiles
for specific port
@Param[in/out] t_FmIpcResourceAllocParams Pointer
*//***************************************************************************/
#define FM_PCD_SET_PORT_PROFILES 7
/**************************************************************************//**
@Function FM_PCD_CLEAR_PORT_PROFILES
@Description Used by FM PCD front-end in order to allocate Policer profiles
for specific port
@Param[in/out] t_FmIpcResourceAllocParams Pointer
*//***************************************************************************/
#define FM_PCD_CLEAR_PORT_PROFILES 8
/**************************************************************************//**
@Function FM_PCD_GET_PHYS_MURAM_BASE
@Description Used by FM PCD front-end in order to get MURAM base address
@Param[in/out] t_FmPcdIcPhysAddr Pointer
*//***************************************************************************/
#define FM_PCD_GET_PHYS_MURAM_BASE 9
/**************************************************************************//**
@Function FM_PCD_GET_SW_PRS_OFFSET
@Description Used by FM front-end to get the SW parser offset of the start of
code relevant to a given label.
@Param[in/out] t_FmPcdIpcSwPrsLable Pointer
*//***************************************************************************/
#define FM_PCD_GET_SW_PRS_OFFSET 10
/**************************************************************************//**
@Function FM_PCD_MASTER_IS_ENABLED
@Description Used by FM front-end in order to verify
PCD enablement.
@Param[in] bool Pointer
*//***************************************************************************/
#define FM_PCD_MASTER_IS_ENABLED 15
/**************************************************************************//**
@Function FM_PCD_GUEST_DISABLE
@Description Used by FM front-end to inform back-end when
front-end PCD is disabled
@Param[in] None
*//***************************************************************************/
#define FM_PCD_GUEST_DISABLE 16
/**************************************************************************//**
@Function FM_PCD_FREE_KG_CLSPLAN
@Description Used by FM PCD front-end in order to Free KG classification plan entries
@Param[in/out] t_FmPcdIpcKgClsPlanParams Pointer
*//***************************************************************************/
#define FM_PCD_FREE_KG_CLSPLAN 22
/**************************************************************************//**
@Function FM_PCD_ALLOC_KG_CLSPLAN
@Description Used by FM PCD front-end in order to allocate KG classification plan entries
@Param[in/out] t_FmPcdIpcKgClsPlanParams Pointer
*//***************************************************************************/
#define FM_PCD_ALLOC_KG_CLSPLAN 23
/**************************************************************************//**
@Function FM_PCD_MASTER_IS_ALIVE
@Description Used by FM front-end to check that back-end exists
@Param[in] None
*//***************************************************************************/
#define FM_PCD_MASTER_IS_ALIVE 24
/**************************************************************************//**
@Function FM_PCD_GET_COUNTER
@Description Used by FM front-end to read PCD counters
@Param[in/out] t_FmPcdIpcGetCounter Pointer
*//***************************************************************************/
#define FM_PCD_GET_COUNTER 25
/**************************************************************************//**
@Function FM_PCD_PRS_INC_PORT_STATS
@Description Used by FM front-end to set/clear statistics for port
@Param[in/out] t_FmPcdIpcPrsIncludePort Pointer
*//***************************************************************************/
#define FM_PCD_PRS_INC_PORT_STATS 26
#if (DPAA_VERSION >= 11)
/* TODO - doc */
#define FM_PCD_ALLOC_SP 27
#endif /* (DPAA_VERSION >= 11) */
/** @} */ /* end of FM_PCD_IPC_grp group */
/** @} */ /* end of FM_grp group */
#endif /* __FM_PCD_IPC_H */

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/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_plcr.h
@Description FM Policer private header
*//***************************************************************************/
#ifndef __FM_PLCR_H
#define __FM_PLCR_H
#include "std_ext.h"
/***********************************************************************/
/* Policer defines */
/***********************************************************************/
#define FM_PCD_PLCR_PAR_GO 0x80000000
#define FM_PCD_PLCR_PAR_PWSEL_MASK 0x0000FFFF
#define FM_PCD_PLCR_PAR_R 0x40000000
/* shifts */
#define FM_PCD_PLCR_PAR_PNUM_SHIFT 16
/* masks */
#define FM_PCD_PLCR_PEMODE_PI 0x80000000
#define FM_PCD_PLCR_PEMODE_CBLND 0x40000000
#define FM_PCD_PLCR_PEMODE_ALG_MASK 0x30000000
#define FM_PCD_PLCR_PEMODE_ALG_RFC2698 0x10000000
#define FM_PCD_PLCR_PEMODE_ALG_RFC4115 0x20000000
#define FM_PCD_PLCR_PEMODE_DEFC_MASK 0x0C000000
#define FM_PCD_PLCR_PEMODE_DEFC_Y 0x04000000
#define FM_PCD_PLCR_PEMODE_DEFC_R 0x08000000
#define FM_PCD_PLCR_PEMODE_DEFC_OVERRIDE 0x0C000000
#define FM_PCD_PLCR_PEMODE_OVCLR_MASK 0x03000000
#define FM_PCD_PLCR_PEMODE_OVCLR_Y 0x01000000
#define FM_PCD_PLCR_PEMODE_OVCLR_R 0x02000000
#define FM_PCD_PLCR_PEMODE_OVCLR_G_NC 0x03000000
#define FM_PCD_PLCR_PEMODE_PKT 0x00800000
#define FM_PCD_PLCR_PEMODE_FPP_MASK 0x001F0000
#define FM_PCD_PLCR_PEMODE_FPP_SHIFT 16
#define FM_PCD_PLCR_PEMODE_FLS_MASK 0x0000F000
#define FM_PCD_PLCR_PEMODE_FLS_L2 0x00003000
#define FM_PCD_PLCR_PEMODE_FLS_L3 0x0000B000
#define FM_PCD_PLCR_PEMODE_FLS_L4 0x0000E000
#define FM_PCD_PLCR_PEMODE_FLS_FULL 0x0000F000
#define FM_PCD_PLCR_PEMODE_RBFLS 0x00000800
#define FM_PCD_PLCR_PEMODE_TRA 0x00000004
#define FM_PCD_PLCR_PEMODE_TRB 0x00000002
#define FM_PCD_PLCR_PEMODE_TRC 0x00000001
#define FM_PCD_PLCR_DOUBLE_ECC 0x80000000
#define FM_PCD_PLCR_INIT_ENTRY_ERROR 0x40000000
#define FM_PCD_PLCR_PRAM_SELF_INIT_COMPLETE 0x80000000
#define FM_PCD_PLCR_ATOMIC_ACTION_COMPLETE 0x40000000
#define FM_PCD_PLCR_NIA_VALID 0x80000000
#define FM_PCD_PLCR_GCR_EN 0x80000000
#define FM_PCD_PLCR_GCR_STEN 0x40000000
#define FM_PCD_PLCR_GCR_DAR 0x20000000
#define FM_PCD_PLCR_GCR_DEFNIA 0x00FFFFFF
#define FM_PCD_PLCR_NIA_ABS 0x00000100
#define FM_PCD_PLCR_GSR_BSY 0x80000000
#define FM_PCD_PLCR_GSR_DQS 0x60000000
#define FM_PCD_PLCR_GSR_RPB 0x20000000
#define FM_PCD_PLCR_GSR_FQS 0x0C000000
#define FM_PCD_PLCR_GSR_LPALG 0x0000C000
#define FM_PCD_PLCR_GSR_LPCA 0x00003000
#define FM_PCD_PLCR_GSR_LPNUM 0x000000FF
#define FM_PCD_PLCR_EVR_PSIC 0x80000000
#define FM_PCD_PLCR_EVR_AAC 0x40000000
#define FM_PCD_PLCR_PAR_PSI 0x20000000
#define FM_PCD_PLCR_PAR_PNUM 0x00FF0000
/* PWSEL Selctive select options */
#define FM_PCD_PLCR_PAR_PWSEL_PEMODE 0x00008000 /* 0 */
#define FM_PCD_PLCR_PAR_PWSEL_PEGNIA 0x00004000 /* 1 */
#define FM_PCD_PLCR_PAR_PWSEL_PEYNIA 0x00002000 /* 2 */
#define FM_PCD_PLCR_PAR_PWSEL_PERNIA 0x00001000 /* 3 */
#define FM_PCD_PLCR_PAR_PWSEL_PECIR 0x00000800 /* 4 */
#define FM_PCD_PLCR_PAR_PWSEL_PECBS 0x00000400 /* 5 */
#define FM_PCD_PLCR_PAR_PWSEL_PEPIR_EIR 0x00000200 /* 6 */
#define FM_PCD_PLCR_PAR_PWSEL_PEPBS_EBS 0x00000100 /* 7 */
#define FM_PCD_PLCR_PAR_PWSEL_PELTS 0x00000080 /* 8 */
#define FM_PCD_PLCR_PAR_PWSEL_PECTS 0x00000040 /* 9 */
#define FM_PCD_PLCR_PAR_PWSEL_PEPTS_ETS 0x00000020 /* 10 */
#define FM_PCD_PLCR_PAR_PWSEL_PEGPC 0x00000010 /* 11 */
#define FM_PCD_PLCR_PAR_PWSEL_PEYPC 0x00000008 /* 12 */
#define FM_PCD_PLCR_PAR_PWSEL_PERPC 0x00000004 /* 13 */
#define FM_PCD_PLCR_PAR_PWSEL_PERYPC 0x00000002 /* 14 */
#define FM_PCD_PLCR_PAR_PWSEL_PERRPC 0x00000001 /* 15 */
#define FM_PCD_PLCR_PAR_PMR_BRN_1TO1 0x0000 /* - Full bit replacement. {PBNUM[0:N-1]
1-> 2^N specific locations. */
#define FM_PCD_PLCR_PAR_PMR_BRN_2TO2 0x1 /* - {PBNUM[0:N-2],PNUM[N-1]}.
2-> 2^(N-1) base locations. */
#define FM_PCD_PLCR_PAR_PMR_BRN_4TO4 0x2 /* - {PBNUM[0:N-3],PNUM[N-2:N-1]}.
4-> 2^(N-2) base locations. */
#define FM_PCD_PLCR_PAR_PMR_BRN_8TO8 0x3 /* - {PBNUM[0:N-4],PNUM[N-3:N-1]}.
8->2^(N-3) base locations. */
#define FM_PCD_PLCR_PAR_PMR_BRN_16TO16 0x4 /* - {PBNUM[0:N-5],PNUM[N-4:N-1]}.
16-> 2^(N-4) base locations. */
#define FM_PCD_PLCR_PAR_PMR_BRN_32TO32 0x5 /* {PBNUM[0:N-6],PNUM[N-5:N-1]}.
32-> 2^(N-5) base locations. */
#define FM_PCD_PLCR_PAR_PMR_BRN_64TO64 0x6 /* {PBNUM[0:N-7],PNUM[N-6:N-1]}.
64-> 2^(N-6) base locations. */
#define FM_PCD_PLCR_PAR_PMR_BRN_128TO128 0x7 /* {PBNUM[0:N-8],PNUM[N-7:N-1]}.
128-> 2^(N-7) base locations. */
#define FM_PCD_PLCR_PAR_PMR_BRN_256TO256 0x8 /* - No bit replacement for N=8. {PNUM[N-8:N-1]}.
When N=8 this option maps all 256 profiles by the DISPATCH bus into one group. */
#define FM_PCD_PLCR_PMR_V 0x80000000
#define PLCR_ERR_ECC_CAP 0x80000000
#define PLCR_ERR_ECC_TYPE_DOUBLE 0x40000000
#define PLCR_ERR_ECC_PNUM_MASK 0x00000FF0
#define PLCR_ERR_ECC_OFFSET_MASK 0x0000000F
#define PLCR_ERR_UNINIT_CAP 0x80000000
#define PLCR_ERR_UNINIT_NUM_MASK 0x000000FF
#define PLCR_ERR_UNINIT_PID_MASK 0x003f0000
#define PLCR_ERR_UNINIT_ABSOLUTE_MASK 0x00008000
/* shifts */
#define PLCR_ERR_ECC_PNUM_SHIFT 4
#define PLCR_ERR_UNINIT_PID_SHIFT 16
#define FM_PCD_PLCR_PMR_BRN_SHIFT 16
#define PLCR_PORT_WINDOW_SIZE(hardwarePortId)
#endif /* __FM_PLCR_H */

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/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_pcd.c
@Description FM PCD ...
*//***************************************************************************/
#include <linux/math64.h>
#include "std_ext.h"
#include "error_ext.h"
#include "string_ext.h"
#include "debug_ext.h"
#include "net_ext.h"
#include "fm_common.h"
#include "fm_pcd.h"
#include "fm_pcd_ipc.h"
#include "fm_prs.h"
#include "fsl_fman_prs.h"
static void PcdPrsErrorException(t_Handle h_FmPcd)
{
t_FmPcd *p_FmPcd = (t_FmPcd *)h_FmPcd;
uint32_t event, ev_mask;
struct fman_prs_regs *PrsRegs = (struct fman_prs_regs *)p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs;
ASSERT_COND(p_FmPcd->guestId == NCSW_MASTER_ID);
ev_mask = fman_prs_get_err_ev_mask(PrsRegs);
event = fman_prs_get_err_event(PrsRegs, ev_mask);
fman_prs_ack_err_event(PrsRegs, event);
DBG(TRACE, ("parser error - 0x%08x\n",event));
if(event & FM_PCD_PRS_DOUBLE_ECC)
p_FmPcd->f_Exception(p_FmPcd->h_App,e_FM_PCD_PRS_EXCEPTION_DOUBLE_ECC);
}
static void PcdPrsException(t_Handle h_FmPcd)
{
t_FmPcd *p_FmPcd = (t_FmPcd *)h_FmPcd;
uint32_t event, ev_mask;
struct fman_prs_regs *PrsRegs = (struct fman_prs_regs *)p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs;
ASSERT_COND(p_FmPcd->guestId == NCSW_MASTER_ID);
ev_mask = fman_prs_get_expt_ev_mask(PrsRegs);
event = fman_prs_get_expt_event(PrsRegs, ev_mask);
ASSERT_COND(event & FM_PCD_PRS_SINGLE_ECC);
DBG(TRACE, ("parser event - 0x%08x\n",event));
fman_prs_ack_expt_event(PrsRegs, event);
p_FmPcd->f_Exception(p_FmPcd->h_App,e_FM_PCD_PRS_EXCEPTION_SINGLE_ECC);
}
t_Handle PrsConfig(t_FmPcd *p_FmPcd,t_FmPcdParams *p_FmPcdParams)
{
t_FmPcdPrs *p_FmPcdPrs;
uintptr_t baseAddr;
UNUSED(p_FmPcd);
UNUSED(p_FmPcdParams);
p_FmPcdPrs = (t_FmPcdPrs *) XX_Malloc(sizeof(t_FmPcdPrs));
if (!p_FmPcdPrs)
{
REPORT_ERROR(MAJOR, E_NO_MEMORY, ("FM Parser structure allocation FAILED"));
return NULL;
}
memset(p_FmPcdPrs, 0, sizeof(t_FmPcdPrs));
fman_prs_defconfig(&p_FmPcd->p_FmPcdDriverParam->dfltCfg);
if (p_FmPcd->guestId == NCSW_MASTER_ID)
{
baseAddr = FmGetPcdPrsBaseAddr(p_FmPcdParams->h_Fm);
p_FmPcdPrs->p_SwPrsCode = (uint32_t *)UINT_TO_PTR(baseAddr);
p_FmPcdPrs->p_FmPcdPrsRegs = (struct fman_prs_regs *)UINT_TO_PTR(baseAddr + PRS_REGS_OFFSET);
}
p_FmPcdPrs->fmPcdPrsPortIdStatistics = p_FmPcd->p_FmPcdDriverParam->dfltCfg.port_id_stat;
p_FmPcd->p_FmPcdDriverParam->prsMaxParseCycleLimit = p_FmPcd->p_FmPcdDriverParam->dfltCfg.max_prs_cyc_lim;
p_FmPcd->exceptions |= p_FmPcd->p_FmPcdDriverParam->dfltCfg.prs_exceptions;
return p_FmPcdPrs;
}
#if ((DPAA_VERSION == 10) && defined(FM_CAPWAP_SUPPORT))
static uint8_t swPrsPatch[] = SW_PRS_UDP_LITE_PATCH;
#else
static uint8_t swPrsPatch[] = SW_PRS_OFFLOAD_PATCH;
#endif /* FM_CAPWAP_SUPPORT */
t_Error PrsInit(t_FmPcd *p_FmPcd)
{
t_FmPcdDriverParam *p_Param = p_FmPcd->p_FmPcdDriverParam;
uint32_t *p_TmpCode;
uint32_t *p_LoadTarget = (uint32_t *)PTR_MOVE(p_FmPcd->p_FmPcdPrs->p_SwPrsCode,
FM_PCD_SW_PRS_SIZE-FM_PCD_PRS_SW_PATCHES_SIZE);
struct fman_prs_regs *PrsRegs = (struct fman_prs_regs *)p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs;
uint32_t i;
ASSERT_COND(sizeof(swPrsPatch) <= (FM_PCD_PRS_SW_PATCHES_SIZE-FM_PCD_PRS_SW_TAIL_SIZE));
/* nothing to do in guest-partition */
if (p_FmPcd->guestId != NCSW_MASTER_ID)
return E_OK;
p_TmpCode = (uint32_t *)XX_MallocSmart(ROUND_UP(sizeof(swPrsPatch),4), 0, sizeof(uint32_t));
if (!p_TmpCode)
RETURN_ERROR(MAJOR, E_NO_MEMORY, ("Tmp Sw-Parser code allocation FAILED"));
memset((uint8_t *)p_TmpCode, 0, ROUND_UP(sizeof(swPrsPatch),4));
memcpy((uint8_t *)p_TmpCode, (uint8_t *)swPrsPatch, sizeof(swPrsPatch));
fman_prs_init(PrsRegs, &p_Param->dfltCfg);
/* register even if no interrupts enabled, to allow future enablement */
FmRegisterIntr(p_FmPcd->h_Fm, e_FM_MOD_PRS, 0, e_FM_INTR_TYPE_ERR, PcdPrsErrorException, p_FmPcd);
/* register even if no interrupts enabled, to allow future enablement */
FmRegisterIntr(p_FmPcd->h_Fm, e_FM_MOD_PRS, 0, e_FM_INTR_TYPE_NORMAL, PcdPrsException, p_FmPcd);
if(p_FmPcd->exceptions & FM_PCD_EX_PRS_SINGLE_ECC)
FmEnableRamsEcc(p_FmPcd->h_Fm);
if(p_FmPcd->exceptions & FM_PCD_EX_PRS_DOUBLE_ECC)
FmEnableRamsEcc(p_FmPcd->h_Fm);
/* load sw parser Ip-Frag patch */
for (i=0; i<DIV_CEIL(sizeof(swPrsPatch), 4); i++)
WRITE_UINT32(p_LoadTarget[i], GET_UINT32(p_TmpCode[i]));
XX_FreeSmart(p_TmpCode);
return E_OK;
}
void PrsFree(t_FmPcd *p_FmPcd)
{
ASSERT_COND(p_FmPcd->guestId == NCSW_MASTER_ID);
FmUnregisterIntr(p_FmPcd->h_Fm, e_FM_MOD_PRS, 0, e_FM_INTR_TYPE_ERR);
/* register even if no interrupts enabled, to allow future enablement */
FmUnregisterIntr(p_FmPcd->h_Fm, e_FM_MOD_PRS, 0, e_FM_INTR_TYPE_NORMAL);
}
void PrsEnable(t_FmPcd *p_FmPcd)
{
struct fman_prs_regs *PrsRegs = (struct fman_prs_regs *)p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs;
ASSERT_COND(p_FmPcd->guestId == NCSW_MASTER_ID);
fman_prs_enable(PrsRegs);
}
void PrsDisable(t_FmPcd *p_FmPcd)
{
struct fman_prs_regs *PrsRegs = (struct fman_prs_regs *)p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs;
ASSERT_COND(p_FmPcd->guestId == NCSW_MASTER_ID);
fman_prs_disable(PrsRegs);
}
int PrsIsEnabled(t_FmPcd *p_FmPcd)
{
struct fman_prs_regs *PrsRegs = (struct fman_prs_regs *)p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs;
ASSERT_COND(p_FmPcd->guestId == NCSW_MASTER_ID);
return fman_prs_is_enabled(PrsRegs);
}
t_Error PrsIncludePortInStatistics(t_FmPcd *p_FmPcd, uint8_t hardwarePortId, bool include)
{
struct fman_prs_regs *PrsRegs;
uint32_t bitMask = 0;
uint8_t prsPortId;
SANITY_CHECK_RETURN_ERROR((hardwarePortId >=1 && hardwarePortId <= 16), E_INVALID_VALUE);
SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmPcd->p_FmPcdPrs, E_INVALID_HANDLE);
PrsRegs = (struct fman_prs_regs *)p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs;
GET_FM_PCD_PRS_PORT_ID(prsPortId, hardwarePortId);
GET_FM_PCD_INDEX_FLAG(bitMask, prsPortId);
if (include)
p_FmPcd->p_FmPcdPrs->fmPcdPrsPortIdStatistics |= bitMask;
else
p_FmPcd->p_FmPcdPrs->fmPcdPrsPortIdStatistics &= ~bitMask;
fman_prs_set_stst_port_msk(PrsRegs,
p_FmPcd->p_FmPcdPrs->fmPcdPrsPortIdStatistics);
return E_OK;
}
t_Error FmPcdPrsIncludePortInStatistics(t_Handle h_FmPcd, uint8_t hardwarePortId, bool include)
{
t_FmPcd *p_FmPcd = (t_FmPcd *)h_FmPcd;
t_Error err;
SANITY_CHECK_RETURN_ERROR((hardwarePortId >=1 && hardwarePortId <= 16), E_INVALID_VALUE);
SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmPcd->p_FmPcdPrs, E_INVALID_HANDLE);
if ((p_FmPcd->guestId != NCSW_MASTER_ID) &&
p_FmPcd->h_IpcSession)
{
t_FmPcdIpcPrsIncludePort prsIncludePortParams;
t_FmPcdIpcMsg msg;
prsIncludePortParams.hardwarePortId = hardwarePortId;
prsIncludePortParams.include = include;
memset(&msg, 0, sizeof(msg));
msg.msgId = FM_PCD_PRS_INC_PORT_STATS;
memcpy(msg.msgBody, &prsIncludePortParams, sizeof(prsIncludePortParams));
err = XX_IpcSendMessage(p_FmPcd->h_IpcSession,
(uint8_t*)&msg,
sizeof(msg.msgId) +sizeof(prsIncludePortParams),
NULL,
NULL,
NULL,
NULL);
if (err != E_OK)
RETURN_ERROR(MAJOR, err, NO_MSG);
return E_OK;
}
else if (p_FmPcd->guestId != NCSW_MASTER_ID)
RETURN_ERROR(MINOR, E_NOT_SUPPORTED,
("running in guest-mode without IPC!"));
return PrsIncludePortInStatistics(p_FmPcd, hardwarePortId, include);
}
uint32_t FmPcdGetSwPrsOffset(t_Handle h_FmPcd, e_NetHeaderType hdr, uint8_t indexPerHdr)
{
t_FmPcd *p_FmPcd = (t_FmPcd *)h_FmPcd;
t_FmPcdPrsLabelParams *p_Label;
int i;
SANITY_CHECK_RETURN_VALUE(p_FmPcd, E_INVALID_HANDLE, 0);
SANITY_CHECK_RETURN_VALUE(!p_FmPcd->p_FmPcdDriverParam, E_INVALID_HANDLE, 0);
if ((p_FmPcd->guestId != NCSW_MASTER_ID) &&
p_FmPcd->h_IpcSession)
{
t_Error err = E_OK;
t_FmPcdIpcSwPrsLable labelParams;
t_FmPcdIpcMsg msg;
uint32_t prsOffset = 0;
t_FmPcdIpcReply reply;
uint32_t replyLength;
memset(&reply, 0, sizeof(reply));
memset(&msg, 0, sizeof(msg));
labelParams.enumHdr = (uint32_t)hdr;
labelParams.indexPerHdr = indexPerHdr;
msg.msgId = FM_PCD_GET_SW_PRS_OFFSET;
memcpy(msg.msgBody, &labelParams, sizeof(labelParams));
replyLength = sizeof(uint32_t) + sizeof(uint32_t);
err = XX_IpcSendMessage(p_FmPcd->h_IpcSession,
(uint8_t*)&msg,
sizeof(msg.msgId) +sizeof(labelParams),
(uint8_t*)&reply,
&replyLength,
NULL,
NULL);
if (err != E_OK)
RETURN_ERROR(MAJOR, err, NO_MSG);
if (replyLength != sizeof(uint32_t) + sizeof(uint32_t))
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("IPC reply length mismatch"));
memcpy((uint8_t*)&prsOffset, reply.replyBody, sizeof(uint32_t));
return prsOffset;
}
else if (p_FmPcd->guestId != NCSW_MASTER_ID)
RETURN_ERROR(MINOR, E_NOT_SUPPORTED,
("running in guest-mode without IPC!"));
ASSERT_COND(p_FmPcd->p_FmPcdPrs->currLabel < FM_PCD_PRS_NUM_OF_LABELS);
for (i=0; i<p_FmPcd->p_FmPcdPrs->currLabel; i++)
{
p_Label = &p_FmPcd->p_FmPcdPrs->labelsTable[i];
if ((hdr == p_Label->hdr) && (indexPerHdr == p_Label->indexPerHdr))
return p_Label->instructionOffset;
}
REPORT_ERROR(MAJOR, E_NOT_FOUND, ("Sw Parser attachment Not found"));
return (uint32_t)ILLEGAL_BASE;
}
void FM_PCD_SetPrsStatistics(t_Handle h_FmPcd, bool enable)
{
t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd;
struct fman_prs_regs *PrsRegs;
SANITY_CHECK_RETURN(p_FmPcd, E_INVALID_HANDLE);
SANITY_CHECK_RETURN(p_FmPcd->p_FmPcdPrs, E_INVALID_HANDLE);
PrsRegs = (struct fman_prs_regs *)p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs;
if(p_FmPcd->guestId != NCSW_MASTER_ID)
{
REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("FM_PCD_SetPrsStatistics - guest mode!"));
return;
}
fman_prs_set_stst(PrsRegs, enable);
}
t_Error FM_PCD_PrsLoadSw(t_Handle h_FmPcd, t_FmPcdPrsSwParams *p_SwPrs)
{
t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd;
uint32_t *p_LoadTarget;
uint32_t *p_TmpCode;
int i;
SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_FmPcd->p_FmPcdDriverParam, E_INVALID_STATE);
SANITY_CHECK_RETURN_ERROR(p_FmPcd->p_FmPcdPrs, E_INVALID_STATE);
SANITY_CHECK_RETURN_ERROR(p_SwPrs, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_FmPcd->enabled, E_INVALID_HANDLE);
if (p_FmPcd->guestId != NCSW_MASTER_ID)
RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, ("FM in guest-mode!"));
if (!p_SwPrs->override)
{
if(p_FmPcd->p_FmPcdPrs->p_CurrSwPrs > p_FmPcd->p_FmPcdPrs->p_SwPrsCode + p_SwPrs->base*2/4)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("SW parser base must be larger than current loaded code"));
}
else
p_FmPcd->p_FmPcdPrs->currLabel = 0;
if (p_SwPrs->size > FM_PCD_SW_PRS_SIZE - FM_PCD_PRS_SW_TAIL_SIZE - p_SwPrs->base*2)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("p_SwPrs->size may not be larger than MAX_SW_PRS_CODE_SIZE"));
if (p_FmPcd->p_FmPcdPrs->currLabel + p_SwPrs->numOfLabels > FM_PCD_PRS_NUM_OF_LABELS)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Exceeded number of labels allowed "));
p_TmpCode = (uint32_t *)XX_MallocSmart(ROUND_UP(p_SwPrs->size,4), 0, sizeof(uint32_t));
if (!p_TmpCode)
RETURN_ERROR(MAJOR, E_NO_MEMORY, ("Tmp Sw-Parser code allocation FAILED"));
memset((uint8_t *)p_TmpCode, 0, ROUND_UP(p_SwPrs->size,4));
memcpy((uint8_t *)p_TmpCode, p_SwPrs->p_Code, p_SwPrs->size);
/* save sw parser labels */
memcpy(&p_FmPcd->p_FmPcdPrs->labelsTable[p_FmPcd->p_FmPcdPrs->currLabel],
p_SwPrs->labelsTable,
p_SwPrs->numOfLabels*sizeof(t_FmPcdPrsLabelParams));
p_FmPcd->p_FmPcdPrs->currLabel += p_SwPrs->numOfLabels;
/* load sw parser code */
p_LoadTarget = p_FmPcd->p_FmPcdPrs->p_SwPrsCode + p_SwPrs->base*2/4;
for(i=0; i<DIV_CEIL(p_SwPrs->size, 4); i++)
WRITE_UINT32(p_LoadTarget[i], GET_UINT32(p_TmpCode[i]));
p_FmPcd->p_FmPcdPrs->p_CurrSwPrs =
p_FmPcd->p_FmPcdPrs->p_SwPrsCode + p_SwPrs->base*2/4 + ROUND_UP(p_SwPrs->size,4);
/* copy data parameters */
for (i=0;i<FM_PCD_PRS_NUM_OF_HDRS;i++)
WRITE_UINT32(*(p_FmPcd->p_FmPcdPrs->p_SwPrsCode+PRS_SW_DATA/4+i), p_SwPrs->swPrsDataParams[i]);
/* Clear last 4 bytes */
WRITE_UINT32(*(p_FmPcd->p_FmPcdPrs->p_SwPrsCode+(PRS_SW_DATA-FM_PCD_PRS_SW_TAIL_SIZE)/4), 0);
XX_FreeSmart(p_TmpCode);
return E_OK;
}
t_Error FM_PCD_ConfigPrsMaxCycleLimit(t_Handle h_FmPcd,uint16_t value)
{
t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd;
SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmPcd->p_FmPcdDriverParam, E_INVALID_HANDLE);
if(p_FmPcd->guestId != NCSW_MASTER_ID)
RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, ("FM_PCD_ConfigPrsMaxCycleLimit - guest mode!"));
p_FmPcd->p_FmPcdDriverParam->prsMaxParseCycleLimit = value;
return E_OK;
}

316
drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_prs.h Normal file
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@ -0,0 +1,316 @@
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_prs.h
@Description FM Parser private header
*//***************************************************************************/
#ifndef __FM_PRS_H
#define __FM_PRS_H
#include "std_ext.h"
/***********************************************************************/
/* SW parser IP_FRAG patch */
/***********************************************************************/
#if ((DPAA_VERSION == 10) && defined(FM_CAPWAP_SUPPORT))
#define SW_PRS_UDP_LITE_PATCH \
{\
0x31,0x52,0x00,0xDA,0xFC,0x00,0x00,0x00,0x00,0x00, \
0x00,0x00,0x50,0x2C,0x40,0x00,0x31,0x92,0x50,0x2C, \
0x00,0x88,0x18,0x2F,0x00,0x01,0x1B,0xFE,0x18,0x71, \
0x02,0x1F,0x00,0x08,0x00,0x83,0x02,0x1F,0x00,0x20, \
0x28,0x1B,0x00,0x05,0x29,0x1F,0x30,0xD0,0x60,0x4F, \
0x00,0x07,0x00,0x05,0x00,0x00,0xC3,0x8F,0x00,0x52, \
0x00,0x01,0x07,0x01,0x60,0x3B,0x00,0x00,0x30,0xD0, \
0x00,0xDA,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00, \
0x40,0x4C,0x00,0x00,0x02,0x8F,0x00,0x00,0x30,0xF2, \
0x00,0x06,0x18,0x5D,0x00,0x00,0x9F,0xFF,0x30,0xF2, \
0x00,0x06,0x29,0x1E,0x07,0x08,0x30,0xD0,0x00,0x52, \
0x00,0x08,0x28,0x1A,0x60,0x37,0x00,0x00,0x30,0xF2, \
0x18,0x5D,0x06,0x00,0x29,0x1E,0x30,0xF2,0x2F,0x0E, \
0x30,0x72,0x00,0x00,0x9B,0x8F,0x00,0x06,0x2F,0x0E, \
0x32,0xF1,0x32,0xB0,0x00,0x4F,0x00,0x57,0x00,0x28, \
0x00,0x00,0x97,0x9E,0x00,0x4E,0x30,0x72,0x00,0x06, \
0x2F,0x0E,0x32,0xC1,0x32,0xF0,0x00,0x4A,0x00,0x80, \
0x00,0x02,0x00,0x00,0x97,0x9E,0x40,0x7E,0x00,0x08, \
0x08,0x16,0x00,0x54,0x00,0x01,0x1B,0xFE,0x00,0x00, \
0x9F,0x9E,0x40,0xB3,0x00,0x00,0x02,0x1F,0x00,0x08, \
0x28,0x1B,0x30,0x73,0x29,0x1F,0x30,0xD0,0x60,0x9F, \
0x00,0x07,0x00,0x05,0x00,0x00,0xC3,0x8F,0x00,0x52, \
0x00,0x01,0x07,0x01,0x60,0x8B,0x00,0x00,0x30,0xD0, \
0x00,0xDA,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00, \
0x40,0x9C,0x00,0x00,0x02,0x8F,0x00,0x00,0x30,0xF2, \
0x00,0x06,0x18,0xAD,0x00,0x00,0x9F,0xFF,0x30,0xF2, \
0x00,0x06,0x29,0x1E,0x07,0x08,0x30,0xD0,0x00,0x52, \
0x00,0x08,0x28,0x1A,0x60,0x87,0x00,0x00,0x30,0xF2, \
0x18,0xAD,0x06,0x00,0x29,0x1E,0x30,0xF2,0x50,0xB3, \
0xFF,0xFF,0x18,0xB8,0x08,0x16,0x00,0x54,0x00,0x01, \
0x1B,0xFE,0x18,0xC5,0x32,0xF1,0x28,0x5D,0x32,0xF1, \
0x00,0x55,0x00,0x08,0x28,0x5F,0x00,0x00,0x8F,0x9F, \
0x29,0x33,0x08,0x16,0x00,0x49,0x00,0x01,0x1B,0xFF, \
0x00,0x01,0x1B,0xFF \
}
#endif /* ((DPAA_VERSION == 10) && defined(FM_CAPWAP_SUPPORT)) */
#if (DPAA_VERSION == 10)
/* Version: 106.1.9 */
#define SW_PRS_OFFLOAD_PATCH \
{ \
0x31,0x52,0x00,0xDA,0x0A,0x00,0x00,0x00,0x00,0x00, \
0x00,0x00,0x43,0x0A,0x00,0x00,0x00,0x01,0x1B,0xFE, \
0x00,0x00,0x99,0x00,0x53,0x13,0x00,0x00,0x00,0x00, \
0x9F,0x98,0x53,0x13,0x00,0x00,0x1B,0x23,0x33,0xF1, \
0x00,0xF9,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00, \
0x28,0x7F,0x00,0x03,0x00,0x02,0x00,0x00,0x00,0x01, \
0x32,0xC1,0x32,0xF0,0x00,0x4A,0x00,0x80,0x1F,0xFF, \
0x00,0x01,0x1B,0xFE,0x31,0x52,0x00,0xDA,0x06,0x00, \
0x00,0x00,0x00,0x00,0x00,0x00,0x43,0x2F,0x00,0x00, \
0x00,0x01,0x1B,0xFE,0x31,0x52,0x00,0xDA,0x00,0x40, \
0x00,0x00,0x00,0x00,0x00,0x00,0x53,0x95,0x00,0x00, \
0x00,0x00,0x9B,0x8F,0x2F,0x0F,0x32,0xC1,0x00,0x55, \
0x00,0x28,0x28,0x43,0x30,0x7E,0x43,0x45,0x00,0x00, \
0x30,0x7E,0x43,0x45,0x00,0x3C,0x1B,0x5D,0x32,0x11, \
0x32,0xC0,0x00,0x4F,0x00,0x81,0x00,0x00,0x83,0x8F, \
0x2F,0x0F,0x06,0x00,0x32,0x11,0x32,0xC0,0x00,0x4F, \
0x00,0x55,0x00,0x01,0x00,0x81,0x32,0x11,0x00,0x00, \
0x83,0x8E,0x00,0x50,0x00,0x01,0x01,0x04,0x00,0x4D, \
0x28,0x43,0x06,0x00,0x1B,0x3E,0x30,0x7E,0x53,0x79, \
0x00,0x2B,0x32,0x11,0x32,0xC0,0x00,0x4F,0x00,0x81, \
0x00,0x00,0x87,0x8F,0x28,0x23,0x06,0x00,0x32,0x11, \
0x32,0xC0,0x00,0x4F,0x00,0x55,0x00,0x01,0x00,0x81, \
0x32,0x11,0x00,0x00,0x83,0x8E,0x00,0x50,0x00,0x01, \
0x01,0x04,0x00,0x4D,0x28,0x43,0x06,0x00,0x00,0x01, \
0x1B,0xFE,0x00,0x00,0x9B,0x8E,0x53,0x90,0x00,0x00, \
0x06,0x29,0x00,0x00,0x83,0x8F,0x28,0x23,0x06,0x00, \
0x06,0x29,0x32,0xC1,0x00,0x55,0x00,0x28,0x00,0x00, \
0x83,0x8E,0x00,0x50,0x00,0x01,0x01,0x04,0x00,0x4D, \
0x28,0x43,0x06,0x00,0x00,0x01,0x1B,0xFE,0x32,0xC1, \
0x00,0x55,0x00,0x28,0x28,0x43,0x1B,0xCF,0x00,0x00, \
0x9B,0x8F,0x2F,0x0F,0x32,0xC1,0x00,0x55,0x00,0x28, \
0x28,0x43,0x30,0x7E,0x43,0xBF,0x00,0x2C,0x32,0x11, \
0x32,0xC0,0x00,0x4F,0x00,0x81,0x00,0x00,0x87,0x8F, \
0x28,0x23,0x06,0x00,0x32,0x11,0x32,0xC0,0x00,0x4F, \
0x00,0x81,0x00,0x00,0x83,0x8F,0x2F,0x0F,0x06,0x00, \
0x32,0x11,0x32,0xC0,0x00,0x4F,0x00,0x55,0x00,0x01, \
0x00,0x81,0x32,0x11,0x00,0x00,0x83,0x8E,0x00,0x50, \
0x00,0x01,0x01,0x04,0x00,0x4D,0x28,0x43,0x06,0x00, \
0x1B,0x9C,0x33,0xF1,0x00,0xF9,0x00,0x01,0x00,0x00, \
0x00,0x00,0x00,0x00,0x28,0x7F,0x00,0x03,0x00,0x02, \
0x00,0x00,0x00,0x01,0x32,0xC1,0x32,0xF0,0x00,0x4A, \
0x00,0x80,0x1F,0xFF,0x00,0x01,0x1B,0xFE, \
}
#else
#define SW_PRS_OFFLOAD_PATCH \
{ \
0x31,0x52,0x00,0xDA,0x0E,0x4F,0x00,0x00,0x00,0x00, \
0x00,0x00,0x51,0x16,0x08,0x4B,0x31,0x53,0x00,0xFB, \
0xFF,0xF0,0x00,0x00,0x00,0x00,0x00,0x00,0x29,0x2B, \
0x33,0xF1,0x00,0xFB,0x00,0xDF,0x00,0x00,0x00,0x00, \
0x00,0x00,0x28,0x7F,0x31,0x52,0x00,0xDA,0x0A,0x00, \
0x00,0x00,0x00,0x00,0x00,0x00,0x41,0x20,0x00,0x00, \
0x00,0x01,0x1B,0xFE,0x00,0x00,0x99,0x00,0x51,0x29, \
0x00,0x00,0x00,0x00,0x9F,0x98,0x51,0x29,0x00,0x00, \
0x19,0x44,0x09,0x5F,0x00,0x20,0x00,0x00,0x09,0x4F, \
0x00,0x20,0x00,0x00,0x34,0xB7,0x00,0xF9,0x00,0x00, \
0x01,0x00,0x00,0x00,0x00,0x00,0x2B,0x97,0x31,0xB3, \
0x29,0x8F,0x33,0xF1,0x00,0xF9,0x00,0x01,0x00,0x00, \
0x00,0x00,0x00,0x00,0x28,0x7F,0x00,0x03,0x00,0x02, \
0x00,0x00,0x00,0x01,0x1B,0xFE,0x00,0x01,0x1B,0xFE, \
0x31,0x52,0x00,0xDA,0xFC,0x00,0x00,0x00,0x00,0x00, \
0x00,0x00,0x51,0x52,0x40,0x00,0x31,0x92,0x51,0x52, \
0x00,0x88,0x19,0x55,0x08,0x05,0x00,0x00,0x19,0x99, \
0x02,0x1F,0x00,0x08,0x00,0x83,0x02,0x1F,0x00,0x20, \
0x28,0x1B,0x00,0x05,0x29,0x1F,0x30,0xD0,0x61,0x75, \
0x00,0x07,0x00,0x05,0x00,0x00,0xC3,0x8F,0x00,0x52, \
0x00,0x01,0x07,0x01,0x61,0x61,0x00,0x00,0x30,0xD0, \
0x00,0xDA,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00, \
0x41,0x72,0x00,0x00,0x02,0x8F,0x00,0x00,0x30,0xF2, \
0x00,0x06,0x19,0x83,0x00,0x00,0x9F,0xFF,0x30,0xF2, \
0x00,0x06,0x29,0x1E,0x07,0x08,0x30,0xD0,0x00,0x52, \
0x00,0x08,0x28,0x1A,0x61,0x5D,0x00,0x00,0x30,0xF2, \
0x19,0x83,0x06,0x00,0x29,0x1E,0x30,0xF2,0x29,0x0E, \
0x30,0x72,0x00,0x00,0x9B,0x8F,0x00,0x06,0x29,0x0E, \
0x32,0xF1,0x32,0xB0,0x00,0x4F,0x00,0x57,0x00,0x28, \
0x00,0x00,0x97,0x9E,0x00,0x4E,0x30,0x72,0x00,0x06, \
0x29,0x0E,0x08,0x05,0x00,0x01,0x31,0x52,0x00,0xDA, \
0x0E,0x4F,0x00,0x00,0x00,0x00,0x00,0x00,0x51,0xAF, \
0x04,0x4B,0x31,0x53,0x00,0xFB,0xFF,0xF0,0x00,0x00, \
0x00,0x00,0x00,0x00,0x29,0x2B,0x33,0xF1,0x00,0xFB, \
0x00,0xDF,0x00,0x00,0x00,0x00,0x00,0x00,0x28,0x7F, \
0x31,0x52,0x00,0xDA,0x06,0x00,0x00,0x00,0x00,0x00, \
0x00,0x00,0x41,0xB9,0x00,0x00,0x00,0x01,0x1B,0xFE, \
0x31,0x52,0x00,0xDA,0x00,0x40,0x00,0x00,0x00,0x00, \
0x00,0x00,0x42,0x06,0x00,0x00,0x00,0x00,0x9B,0x8F, \
0x28,0x01,0x32,0xC1,0x00,0x55,0x00,0x28,0x28,0x43, \
0x30,0x00,0x41,0xEB,0x00,0x2C,0x32,0x11,0x32,0xC0, \
0x00,0x4F,0x00,0x81,0x00,0x00,0x87,0x8F,0x28,0x23, \
0x06,0x00,0x32,0x11,0x32,0xC0,0x00,0x4F,0x00,0x81, \
0x00,0x00,0x83,0x8F,0x28,0x01,0x06,0x00,0x32,0x11, \
0x32,0xC0,0x00,0x4F,0x00,0x55,0x00,0x01,0x00,0x81, \
0x32,0x11,0x00,0x00,0x83,0x8E,0x00,0x50,0x00,0x01, \
0x01,0x04,0x00,0x4D,0x28,0x43,0x06,0x00,0x19,0xC8, \
0x09,0x5F,0x00,0x20,0x00,0x00,0x09,0x4F,0x00,0x20, \
0x00,0x00,0x34,0xB7,0x00,0xF9,0x00,0x00,0x01,0x00, \
0x00,0x00,0x00,0x00,0x2B,0x97,0x31,0xB3,0x29,0x8F, \
0x33,0xF1,0x00,0xF9,0x00,0x01,0x00,0x00,0x00,0x00, \
0x00,0x00,0x28,0x7F,0x00,0x03,0x00,0x02,0x00,0x00, \
0x00,0x01,0x1B,0xFE,0x30,0x50,0x52,0x0B,0x00,0x00, \
0x00,0x01,0x1B,0xFE,0x32,0xF1,0x32,0xC0,0x00,0x4F, \
0x00,0x81,0x00,0x02,0x00,0x00,0x97,0x9E,0x42,0x18, \
0x00,0x08,0x08,0x16,0x00,0x54,0x00,0x01,0x1B,0xFE, \
0x00,0x00,0x9F,0x9E,0x42,0x4D,0x00,0x00,0x02,0x1F, \
0x00,0x08,0x28,0x1B,0x30,0x73,0x29,0x1F,0x30,0xD0, \
0x62,0x39,0x00,0x07,0x00,0x05,0x00,0x00,0xC3,0x8F, \
0x00,0x52,0x00,0x01,0x07,0x01,0x62,0x25,0x00,0x00, \
0x30,0xD0,0x00,0xDA,0x00,0x01,0x00,0x00,0x00,0x00, \
0x00,0x00,0x42,0x36,0x00,0x00,0x02,0x8F,0x00,0x00, \
0x30,0xF2,0x00,0x06,0x1A,0x47,0x00,0x00,0x9F,0xFF, \
0x30,0xF2,0x00,0x06,0x29,0x1E,0x07,0x08,0x30,0xD0, \
0x00,0x52,0x00,0x08,0x28,0x1A,0x62,0x21,0x00,0x00, \
0x30,0xF2,0x1A,0x47,0x06,0x00,0x29,0x1E,0x30,0xF2, \
0x52,0x4D,0xFF,0xFF,0x1A,0x52,0x08,0x16,0x00,0x54, \
0x00,0x01,0x1B,0xFE,0x1A,0x5F,0x32,0xF1,0x28,0x5D, \
0x32,0xF1,0x00,0x55,0x00,0x08,0x28,0x5F,0x00,0x00, \
0x8F,0x9F,0x29,0x33,0x08,0x16,0x00,0x49,0x00,0x01, \
0x1B,0xFF,0x00,0x01,0x1B,0xFF,0x31,0x52,0x00,0xDA, \
0xFC,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x52,0x6D, \
0x40,0x00,0x31,0x92,0x52,0x6D,0x00,0x88,0x1A,0x70, \
0x08,0x05,0x00,0x00,0x1A,0xB4,0x02,0x1F,0x00,0x08, \
0x00,0x83,0x02,0x1F,0x00,0x20,0x28,0x1B,0x00,0x05, \
0x29,0x1F,0x30,0xD0,0x62,0x90,0x00,0x07,0x00,0x05, \
0x00,0x00,0xC3,0x8F,0x00,0x52,0x00,0x01,0x07,0x01, \
0x62,0x7C,0x00,0x00,0x30,0xD0,0x00,0xDA,0x00,0x01, \
0x00,0x00,0x00,0x00,0x00,0x00,0x42,0x8D,0x00,0x00, \
0x02,0x8F,0x00,0x00,0x30,0xF2,0x00,0x06,0x1A,0x9E, \
0x00,0x00,0x9F,0xFF,0x30,0xF2,0x00,0x06,0x29,0x1E, \
0x07,0x08,0x30,0xD0,0x00,0x52,0x00,0x08,0x28,0x1A, \
0x62,0x78,0x00,0x00,0x30,0xF2,0x1A,0x9E,0x06,0x00, \
0x29,0x1E,0x30,0xF2,0x29,0x0E,0x30,0x72,0x00,0x00, \
0x9B,0x8F,0x00,0x06,0x29,0x0E,0x32,0xF1,0x32,0xB0, \
0x00,0x4F,0x00,0x57,0x00,0x28,0x00,0x00,0x97,0x9E, \
0x00,0x4E,0x30,0x72,0x00,0x06,0x29,0x0E,0x08,0x05, \
0x00,0x01,0x31,0x52,0x00,0xDA,0x0E,0x4F,0x00,0x00, \
0x00,0x00,0x00,0x00,0x52,0xCA,0x04,0x4B,0x31,0x53, \
0x00,0xFB,0xFF,0xF0,0x00,0x00,0x00,0x00,0x00,0x00, \
0x29,0x2B,0x33,0xF1,0x00,0xFB,0x00,0xDF,0x00,0x00, \
0x00,0x00,0x00,0x00,0x28,0x7F,0x31,0x52,0x00,0xDA, \
0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x42,0xD4, \
0x00,0x00,0x00,0x01,0x1B,0xFE,0x31,0x52,0x00,0xDA, \
0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x53,0x37, \
0x00,0x00,0x00,0x00,0x9B,0x8F,0x28,0x01,0x32,0xC1, \
0x00,0x55,0x00,0x28,0x28,0x43,0x30,0x00,0x42,0xEA, \
0x00,0x00,0x30,0x00,0x42,0xEA,0x00,0x3C,0x1B,0x02, \
0x32,0x11,0x32,0xC0,0x00,0x4F,0x00,0x81,0x00,0x00, \
0x83,0x8F,0x28,0x01,0x06,0x00,0x32,0x11,0x32,0xC0, \
0x00,0x4F,0x00,0x55,0x00,0x01,0x00,0x81,0x32,0x11, \
0x00,0x00,0x83,0x8E,0x00,0x50,0x00,0x01,0x01,0x04, \
0x00,0x4D,0x28,0x43,0x06,0x00,0x1A,0xE3,0x30,0x00, \
0x43,0x20,0x00,0x2B,0x00,0x00,0x9B,0x8E,0x43,0x0E, \
0x00,0x00,0x32,0xC1,0x00,0x55,0x00,0x28,0x28,0x43, \
0x1B,0x1F,0x06,0x29,0x00,0x00,0x83,0x8F,0x28,0x23, \
0x06,0x00,0x06,0x29,0x32,0xC1,0x00,0x55,0x00,0x28, \
0x00,0x00,0x83,0x8E,0x00,0x50,0x00,0x01,0x01,0x04, \
0x00,0x4D,0x28,0x43,0x06,0x00,0x1B,0x37,0x32,0x11, \
0x32,0xC0,0x00,0x4F,0x00,0x81,0x00,0x00,0x87,0x8F, \
0x28,0x23,0x06,0x00,0x32,0x11,0x32,0xC0,0x00,0x4F, \
0x00,0x55,0x00,0x01,0x00,0x81,0x32,0x11,0x00,0x00, \
0x83,0x8E,0x00,0x50,0x00,0x01,0x01,0x04,0x00,0x4D, \
0x28,0x43,0x06,0x00,0x30,0x50,0x53,0x3C,0x00,0x00, \
0x00,0x01,0x1B,0xFE,0x32,0xF1,0x32,0xC0,0x00,0x4F, \
0x00,0x81,0x00,0x02,0x00,0x00,0x97,0x9E,0x43,0x49, \
0x00,0x08,0x08,0x16,0x00,0x54,0x00,0x01,0x1B,0xFE, \
0x00,0x00,0x9F,0x9E,0x43,0x7E,0x00,0x00,0x02,0x1F, \
0x00,0x08,0x28,0x1B,0x30,0x73,0x29,0x1F,0x30,0xD0, \
0x63,0x6A,0x00,0x07,0x00,0x05,0x00,0x00,0xC3,0x8F, \
0x00,0x52,0x00,0x01,0x07,0x01,0x63,0x56,0x00,0x00, \
0x30,0xD0,0x00,0xDA,0x00,0x01,0x00,0x00,0x00,0x00, \
0x00,0x00,0x43,0x67,0x00,0x00,0x02,0x8F,0x00,0x00, \
0x30,0xF2,0x00,0x06,0x1B,0x78,0x00,0x00,0x9F,0xFF, \
0x30,0xF2,0x00,0x06,0x29,0x1E,0x07,0x08,0x30,0xD0, \
0x00,0x52,0x00,0x08,0x28,0x1A,0x63,0x52,0x00,0x00, \
0x30,0xF2,0x1B,0x78,0x06,0x00,0x29,0x1E,0x30,0xF2, \
0x53,0x7E,0xFF,0xFF,0x1B,0x83,0x08,0x16,0x00,0x54, \
0x00,0x01,0x1B,0xFE,0x1B,0x90,0x32,0xF1,0x28,0x5D, \
0x32,0xF1,0x00,0x55,0x00,0x08,0x28,0x5F,0x00,0x00, \
0x8F,0x9F,0x29,0x33,0x08,0x16,0x00,0x49,0x00,0x01, \
0x1B,0xFF,0x00,0x01,0x1B,0xFF,0x08,0x07,0x00,0x02, \
0x00,0x00,0x8D,0x80,0x53,0x9C,0x00,0x01,0x30,0x71, \
0x00,0x55,0x00,0x01,0x28,0x0F,0x00,0x00,0x8D,0x00, \
0x53,0xA4,0x00,0x01,0x30,0x71,0x00,0x55,0x00,0x01, \
0x28,0x0F,0x00,0x00,0x83,0x8E,0x53,0xB9,0x00,0x00, \
0x00,0x00,0x86,0x08,0x30,0x71,0x00,0x7B,0x03,0xB9, \
0x33,0xB4,0x00,0xDA,0xFF,0xFF,0x00,0x0F,0x00,0x00, \
0x00,0x00,0x00,0x00,0x86,0x09,0x01,0x03,0x00,0x7D, \
0x03,0xB9,0x1B,0xC8,0x33,0xD1,0x00,0xF9,0x00,0x10, \
0x00,0x00,0x00,0x00,0x00,0x00,0x28,0x7B,0x09,0x5F, \
0x00,0x1A,0x00,0x00,0x09,0x4F,0x00,0x1A,0x00,0x00, \
0x00,0x01,0x1B,0xFF,0x00,0x00,0x8C,0x00,0x53,0xF0, \
0x00,0x01,0x34,0xF5,0x00,0xFB,0xFF,0xFF,0x00,0x7F, \
0x00,0x00,0x00,0x00,0x2A,0x9F,0x00,0x00,0x93,0x8F, \
0x28,0x49,0x00,0x00,0x97,0x8F,0x28,0x4B,0x34,0x61, \
0x28,0x4D,0x34,0x71,0x28,0x4F,0x34,0xB7,0x00,0xF9, \
0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x2B,0x97, \
0x33,0xF1,0x00,0xF9,0x00,0x01,0x00,0x00,0x00,0x00, \
0x00,0x00,0x28,0x7F,0x00,0x03,0x00,0x02,0x00,0x00, \
0x00,0x01,0x1B,0xFF,0x00,0x01,0x1B,0xFF, \
}
#endif /* (DPAA_VERSION == 10) */
/****************************/
/* Parser defines */
/****************************/
#define FM_PCD_PRS_SW_TAIL_SIZE 4 /**< Number of bytes that must be cleared at
the end of the SW parser area */
/* masks */
#define PRS_ERR_CAP 0x80000000
#define PRS_ERR_TYPE_DOUBLE 0x40000000
#define PRS_ERR_SINGLE_ECC_CNT_MASK 0x00FF0000
#define PRS_ERR_ADDR_MASK 0x000001FF
/* others */
#define PRS_MAX_CYCLE_LIMIT 8191
#define PRS_SW_DATA 0x00000800
#define PRS_REGS_OFFSET 0x00000840
#define GET_FM_PCD_PRS_PORT_ID(prsPortId,hardwarePortId) \
prsPortId = (uint8_t)(hardwarePortId & 0x0f)
#define GET_FM_PCD_INDEX_FLAG(bitMask, prsPortId) \
bitMask = 0x80000000>>prsPortId
#endif /* __FM_PRS_H */

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@ -0,0 +1,984 @@
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_replic.c
@Description FM frame replicator
*//***************************************************************************/
#include "std_ext.h"
#include "error_ext.h"
#include "string_ext.h"
#include "debug_ext.h"
#include "fm_pcd_ext.h"
#include "fm_muram_ext.h"
#include "fm_common.h"
#include "fm_hc.h"
#include "fm_replic.h"
#include "fm_cc.h"
#include "list_ext.h"
/****************************************/
/* static functions */
/****************************************/
static uint8_t GetMemberPosition(t_FmPcdFrmReplicGroup *p_ReplicGroup,
uint32_t memberIndex,
bool isAddOperation)
{
uint8_t memberPosition;
uint32_t lastMemberIndex;
ASSERT_COND(p_ReplicGroup);
/* the last member index is different between add and remove operation -
in case of remove - this is exactly the last member index
in case of add - this is the last member index + 1 - e.g.
if we have 4 members, the index of the actual last member is 3(because the
index starts from 0) therefore in order to add a new member as the last
member we shall use memberIndex = 4 and not 3
*/
if (isAddOperation)
lastMemberIndex = p_ReplicGroup->numOfEntries;
else
lastMemberIndex = p_ReplicGroup->numOfEntries-1;
/* last */
if (memberIndex == lastMemberIndex)
memberPosition = FRM_REPLIC_LAST_MEMBER_INDEX;
else
{
/* first */
if (memberIndex == 0)
memberPosition = FRM_REPLIC_FIRST_MEMBER_INDEX;
else
{
/* middle */
ASSERT_COND(memberIndex < lastMemberIndex);
memberPosition = FRM_REPLIC_MIDDLE_MEMBER_INDEX;
}
}
return memberPosition;
}
static t_Error MemberCheckParams(t_Handle h_FmPcd,
t_FmPcdCcNextEngineParams *p_MemberParams)
{
t_Error err;
if ((p_MemberParams->nextEngine != e_FM_PCD_DONE) &&
(p_MemberParams->nextEngine != e_FM_PCD_KG) &&
(p_MemberParams->nextEngine != e_FM_PCD_PLCR))
RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, ("Next engine of a member should be MatchTable(cc) or Done or Policer"));
/* check the regular parameters of the next engine */
err = ValidateNextEngineParams(h_FmPcd, p_MemberParams, e_FM_PCD_CC_STATS_MODE_NONE);
if (err)
RETURN_ERROR(MAJOR, err, ("member next engine parameters"));
return E_OK;
}
static t_Error CheckParams(t_Handle h_FmPcd,
t_FmPcdFrmReplicGroupParams *p_ReplicGroupParam)
{
int i;
t_Error err;
/* check that max num of entries is at least 2 */
if (!IN_RANGE(2, p_ReplicGroupParam->maxNumOfEntries, FM_PCD_FRM_REPLIC_MAX_NUM_OF_ENTRIES))
RETURN_ERROR(MAJOR, E_NOT_IN_RANGE, ("maxNumOfEntries in the frame replicator parameters should be 2-%d",FM_PCD_FRM_REPLIC_MAX_NUM_OF_ENTRIES));
/* check that number of entries is greater than zero */
if (!p_ReplicGroupParam->numOfEntries)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("numOFEntries in the frame replicator group should be greater than zero"));
/* check that max num of entries is equal or greater than number of entries */
if (p_ReplicGroupParam->maxNumOfEntries < p_ReplicGroupParam->numOfEntries)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("maxNumOfEntries should be equal or greater than numOfEntries"));
for (i=0; i<p_ReplicGroupParam->numOfEntries; i++)
{
err = MemberCheckParams(h_FmPcd, &p_ReplicGroupParam->nextEngineParams[i]);
if (err)
RETURN_ERROR(MAJOR, err, ("member check parameters"));
}
return E_OK;
}
static t_FmPcdFrmReplicMember *GetAvailableMember(t_FmPcdFrmReplicGroup *p_ReplicGroup)
{
t_FmPcdFrmReplicMember *p_ReplicMember = NULL;
t_List *p_Next;
if (!LIST_IsEmpty(&p_ReplicGroup->availableMembersList))
{
p_Next = LIST_FIRST(&p_ReplicGroup->availableMembersList);
p_ReplicMember = LIST_OBJECT(p_Next, t_FmPcdFrmReplicMember, node);
ASSERT_COND(p_ReplicMember);
LIST_DelAndInit(p_Next);
}
return p_ReplicMember;
}
static void PutAvailableMember(t_FmPcdFrmReplicGroup *p_ReplicGroup,
t_FmPcdFrmReplicMember *p_ReplicMember)
{
LIST_AddToTail(&p_ReplicMember->node, &p_ReplicGroup->availableMembersList);
}
static void AddMemberToList(t_FmPcdFrmReplicGroup *p_ReplicGroup,
t_FmPcdFrmReplicMember *p_CurrentMember,
t_List *p_ListHead)
{
LIST_Add(&p_CurrentMember->node, p_ListHead);
p_ReplicGroup->numOfEntries++;
}
static void RemoveMemberFromList(t_FmPcdFrmReplicGroup *p_ReplicGroup,
t_FmPcdFrmReplicMember *p_CurrentMember)
{
ASSERT_COND(p_ReplicGroup->numOfEntries);
LIST_DelAndInit(&p_CurrentMember->node);
p_ReplicGroup->numOfEntries--;
}
static void LinkSourceToMember(t_FmPcdFrmReplicGroup *p_ReplicGroup,
t_AdOfTypeContLookup *p_SourceTd,
t_FmPcdFrmReplicMember *p_ReplicMember)
{
t_FmPcd *p_FmPcd;
ASSERT_COND(p_SourceTd);
ASSERT_COND(p_ReplicMember);
ASSERT_COND(p_ReplicGroup);
ASSERT_COND(p_ReplicGroup->h_FmPcd);
/* Link the first member in the group to the source TD */
p_FmPcd = p_ReplicGroup->h_FmPcd;
WRITE_UINT32(p_SourceTd->matchTblPtr,
(uint32_t)(XX_VirtToPhys(p_ReplicMember->p_MemberAd) -
p_FmPcd->physicalMuramBase));
}
static void LinkMemberToMember(t_FmPcdFrmReplicGroup *p_ReplicGroup,
t_FmPcdFrmReplicMember *p_CurrentMember,
t_FmPcdFrmReplicMember *p_NextMember)
{
t_AdOfTypeResult *p_CurrReplicAd = (t_AdOfTypeResult*)p_CurrentMember->p_MemberAd;
t_AdOfTypeResult *p_NextReplicAd = NULL;
t_FmPcd *p_FmPcd;
uint32_t offset = 0;
/* Check if the next member exists or it's NULL (- means that this is the last member) */
if (p_NextMember)
{
p_NextReplicAd = (t_AdOfTypeResult*)p_NextMember->p_MemberAd;
p_FmPcd = p_ReplicGroup->h_FmPcd;
offset = (XX_VirtToPhys(p_NextReplicAd) - (p_FmPcd->physicalMuramBase));
offset = ((offset>>NEXT_FRM_REPLIC_ADDR_SHIFT)<< NEXT_FRM_REPLIC_MEMBER_INDEX_SHIFT);
}
/* link the current AD to point to the AD of the next member */
WRITE_UINT32(p_CurrReplicAd->res, offset);
}
static t_Error ModifyDescriptor(t_FmPcdFrmReplicGroup *p_ReplicGroup,
void *p_OldDescriptor,
void *p_NewDescriptor)
{
t_Handle h_Hc;
t_Error err;
t_FmPcd *p_FmPcd;
ASSERT_COND(p_ReplicGroup);
ASSERT_COND(p_ReplicGroup->h_FmPcd);
ASSERT_COND(p_OldDescriptor);
ASSERT_COND(p_NewDescriptor);
p_FmPcd = p_ReplicGroup->h_FmPcd;
h_Hc = FmPcdGetHcHandle(p_FmPcd);
if (!h_Hc)
RETURN_ERROR(MAJOR, E_INVALID_HANDLE, ("Host command"));
err = FmHcPcdCcDoDynamicChange(h_Hc,
(uint32_t)(XX_VirtToPhys(p_OldDescriptor) - p_FmPcd->physicalMuramBase),
(uint32_t)(XX_VirtToPhys(p_NewDescriptor) - p_FmPcd->physicalMuramBase));
if (err)
RETURN_ERROR(MAJOR, err, ("Dynamic change host command"));
return E_OK;
}
static void FillReplicAdOfTypeResult(void *p_ReplicAd, bool last)
{
t_AdOfTypeResult *p_CurrReplicAd = (t_AdOfTypeResult*)p_ReplicAd;
uint32_t tmp;
tmp = GET_UINT32(p_CurrReplicAd->plcrProfile);
if (last)
/* clear the NL bit in case it's the last member in the group*/
WRITE_UINT32(p_CurrReplicAd->plcrProfile,(tmp & ~FRM_REPLIC_NL_BIT));
else
/* set the NL bit in case it's not the last member in the group */
WRITE_UINT32(p_CurrReplicAd->plcrProfile, (tmp |FRM_REPLIC_NL_BIT));
/* set FR bit in the action descriptor */
tmp = GET_UINT32(p_CurrReplicAd->nia);
WRITE_UINT32(p_CurrReplicAd->nia,
(tmp | FRM_REPLIC_FR_BIT | FM_PCD_AD_RESULT_EXTENDED_MODE ));
}
static void BuildSourceTd(void *p_Ad)
{
t_AdOfTypeContLookup *p_SourceTd;
ASSERT_COND(p_Ad);
p_SourceTd = (t_AdOfTypeContLookup *)p_Ad;
IOMemSet32((uint8_t*)p_SourceTd, 0, FM_PCD_CC_AD_ENTRY_SIZE);
/* initialize the source table descriptor */
WRITE_UINT32(p_SourceTd->ccAdBase, FM_PCD_AD_CONT_LOOKUP_TYPE);
WRITE_UINT32(p_SourceTd->pcAndOffsets, FRM_REPLIC_SOURCE_TD_OPCODE);
}
static t_Error BuildShadowAndModifyDescriptor(t_FmPcdFrmReplicGroup *p_ReplicGroup,
t_FmPcdFrmReplicMember *p_NextMember,
t_FmPcdFrmReplicMember *p_CurrentMember,
bool sourceDescriptor,
bool last)
{
t_FmPcd *p_FmPcd;
t_FmPcdFrmReplicMember shadowMember;
t_Error err;
ASSERT_COND(p_ReplicGroup);
ASSERT_COND(p_ReplicGroup->h_FmPcd);
p_FmPcd = p_ReplicGroup->h_FmPcd;
ASSERT_COND(p_FmPcd->p_CcShadow);
if (!TRY_LOCK(p_FmPcd->h_ShadowSpinlock, &p_FmPcd->shadowLock))
return ERROR_CODE(E_BUSY);
if (sourceDescriptor)
{
BuildSourceTd(p_FmPcd->p_CcShadow);
LinkSourceToMember(p_ReplicGroup, p_FmPcd->p_CcShadow, p_NextMember);
/* Modify the source table descriptor according to the prepared shadow descriptor */
err = ModifyDescriptor(p_ReplicGroup,
p_ReplicGroup->p_SourceTd,
p_FmPcd->p_CcShadow/* new prepared source td */);
RELEASE_LOCK(p_FmPcd->shadowLock);
if (err)
RETURN_ERROR(MAJOR, err, ("Modify source Descriptor in BuildShadowAndModifyDescriptor"));
}
else
{
IO2IOCpy32(p_FmPcd->p_CcShadow,
p_CurrentMember->p_MemberAd,
FM_PCD_CC_AD_ENTRY_SIZE);
/* update the last bit in the shadow ad */
FillReplicAdOfTypeResult(p_FmPcd->p_CcShadow, last);
shadowMember.p_MemberAd = p_FmPcd->p_CcShadow;
/* update the next FR member index */
LinkMemberToMember(p_ReplicGroup, &shadowMember, p_NextMember);
/* Modify the next member according to the prepared shadow descriptor */
err = ModifyDescriptor(p_ReplicGroup,
p_CurrentMember->p_MemberAd,
p_FmPcd->p_CcShadow);
RELEASE_LOCK(p_FmPcd->shadowLock);
if (err)
RETURN_ERROR(MAJOR, err, ("Modify Descriptor in BuildShadowAndModifyDescriptor"));
}
return E_OK;
}
static t_FmPcdFrmReplicMember* GetMemberByIndex(t_FmPcdFrmReplicGroup *p_ReplicGroup,
uint16_t memberIndex)
{
int i=0;
t_List *p_Pos;
t_FmPcdFrmReplicMember *p_Member = NULL;
LIST_FOR_EACH(p_Pos, &p_ReplicGroup->membersList)
{
if (i == memberIndex)
{
p_Member = LIST_OBJECT(p_Pos, t_FmPcdFrmReplicMember, node);
return p_Member;
}
i++;
}
return p_Member;
}
static t_Error AllocMember(t_FmPcdFrmReplicGroup *p_ReplicGroup)
{
t_FmPcdFrmReplicMember *p_CurrentMember;
t_Handle h_Muram;
ASSERT_COND(p_ReplicGroup);
h_Muram = FmPcdGetMuramHandle(p_ReplicGroup->h_FmPcd);
ASSERT_COND(h_Muram);
/* Initialize an internal structure of a member to add to the available members list */
p_CurrentMember = (t_FmPcdFrmReplicMember *)XX_Malloc(sizeof(t_FmPcdFrmReplicMember));
if (!p_CurrentMember)
RETURN_ERROR(MAJOR, E_NO_MEMORY, ("Frame replicator member"));
memset(p_CurrentMember, 0 ,sizeof(t_FmPcdFrmReplicMember));
/* Allocate the member AD */
p_CurrentMember->p_MemberAd =
(t_AdOfTypeResult*)FM_MURAM_AllocMem(h_Muram,
FM_PCD_CC_AD_ENTRY_SIZE,
FM_PCD_CC_AD_TABLE_ALIGN);
if (!p_CurrentMember->p_MemberAd)
{
XX_Free(p_CurrentMember);
RETURN_ERROR(MAJOR, E_NO_MEMORY, ("member AD table"));
}
IOMemSet32((uint8_t*)p_CurrentMember->p_MemberAd, 0, FM_PCD_CC_AD_ENTRY_SIZE);
/* Add the new member to the available members list */
LIST_AddToTail(&p_CurrentMember->node, &(p_ReplicGroup->availableMembersList));
return E_OK;
}
static t_FmPcdFrmReplicMember* InitMember(t_FmPcdFrmReplicGroup *p_ReplicGroup,
t_FmPcdCcNextEngineParams *p_MemberParams,
bool last)
{
t_FmPcdFrmReplicMember *p_CurrentMember = NULL;
ASSERT_COND(p_ReplicGroup);
/* Get an available member from the internal members list */
p_CurrentMember = GetAvailableMember(p_ReplicGroup);
if (!p_CurrentMember)
{
REPORT_ERROR(MAJOR, E_NOT_FOUND, ("Available member"));
return NULL;
}
p_CurrentMember->h_Manip = NULL;
/* clear the Ad of the new member */
IOMemSet32((uint8_t*)p_CurrentMember->p_MemberAd, 0, FM_PCD_CC_AD_ENTRY_SIZE);
INIT_LIST(&p_CurrentMember->node);
/* Initialize the Ad of the member */
NextStepAd(p_CurrentMember->p_MemberAd,
NULL,
p_MemberParams,
p_ReplicGroup->h_FmPcd);
/* save Manip handle (for free needs) */
if (p_MemberParams->h_Manip)
p_CurrentMember->h_Manip = p_MemberParams->h_Manip;
/* Initialize the relevant frame replicator fields in the AD */
FillReplicAdOfTypeResult(p_CurrentMember->p_MemberAd, last);
return p_CurrentMember;
}
static void FreeMember(t_FmPcdFrmReplicGroup *p_ReplicGroup,
t_FmPcdFrmReplicMember *p_Member)
{
/* Note: Can't free the member AD just returns the member to the available
member list - therefore only memset the AD */
/* zero the AD */
IOMemSet32(p_Member->p_MemberAd, 0, FM_PCD_CC_AD_ENTRY_SIZE);
/* return the member to the available members list */
PutAvailableMember(p_ReplicGroup, p_Member);
}
static t_Error RemoveMember(t_FmPcdFrmReplicGroup *p_ReplicGroup,
uint16_t memberIndex)
{
t_FmPcd *p_FmPcd = NULL;
t_FmPcdFrmReplicMember *p_CurrentMember = NULL, *p_PreviousMember = NULL, *p_NextMember = NULL;
t_Error err;
uint8_t memberPosition;
p_FmPcd = p_ReplicGroup->h_FmPcd;
ASSERT_COND(p_FmPcd);
UNUSED(p_FmPcd);
p_CurrentMember = GetMemberByIndex(p_ReplicGroup, memberIndex);
ASSERT_COND(p_CurrentMember);
/* determine the member position in the group */
memberPosition = GetMemberPosition(p_ReplicGroup,
memberIndex,
FALSE/*remove operation*/);
switch (memberPosition)
{
case FRM_REPLIC_FIRST_MEMBER_INDEX:
p_NextMember = GetMemberByIndex(p_ReplicGroup, (uint16_t)(memberIndex+1));
ASSERT_COND(p_NextMember);
/* update the source td itself by using a host command */
err = BuildShadowAndModifyDescriptor(p_ReplicGroup,
p_NextMember,
NULL,
TRUE/*sourceDescriptor*/,
FALSE/*last*/);
break;
case FRM_REPLIC_MIDDLE_MEMBER_INDEX:
p_PreviousMember = GetMemberByIndex(p_ReplicGroup, (uint16_t)(memberIndex-1));
ASSERT_COND(p_PreviousMember);
p_NextMember = GetMemberByIndex(p_ReplicGroup, (uint16_t)(memberIndex+1));
ASSERT_COND(p_NextMember);
err = BuildShadowAndModifyDescriptor(p_ReplicGroup,
p_NextMember,
p_PreviousMember,
FALSE/*sourceDescriptor*/,
FALSE/*last*/);
break;
case FRM_REPLIC_LAST_MEMBER_INDEX:
p_PreviousMember = GetMemberByIndex(p_ReplicGroup, (uint16_t)(memberIndex-1));
ASSERT_COND(p_PreviousMember);
err = BuildShadowAndModifyDescriptor(p_ReplicGroup,
NULL,
p_PreviousMember,
FALSE/*sourceDescriptor*/,
TRUE/*last*/);
break;
default:
RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("member position in remove member"));
}
if (err)
RETURN_ERROR(MAJOR, err, NO_MSG);
if (p_CurrentMember->h_Manip)
{
FmPcdManipUpdateOwner(p_CurrentMember->h_Manip, FALSE);
p_CurrentMember->h_Manip = NULL;
}
/* remove the member from the driver internal members list */
RemoveMemberFromList(p_ReplicGroup, p_CurrentMember);
/* return the member to the available members list */
FreeMember(p_ReplicGroup, p_CurrentMember);
return E_OK;
}
static void DeleteGroup(t_FmPcdFrmReplicGroup *p_ReplicGroup)
{
int i, j;
t_Handle h_Muram;
t_FmPcdFrmReplicMember *p_Member, *p_CurrentMember;
if (p_ReplicGroup)
{
ASSERT_COND(p_ReplicGroup->h_FmPcd);
h_Muram = FmPcdGetMuramHandle(p_ReplicGroup->h_FmPcd);
ASSERT_COND(h_Muram);
/* free the source table descriptor */
if (p_ReplicGroup->p_SourceTd)
{
FM_MURAM_FreeMem(h_Muram, p_ReplicGroup->p_SourceTd);
p_ReplicGroup->p_SourceTd = NULL;
}
/* Remove all members from the members linked list (hw and sw) and
return the members to the available members list */
if (p_ReplicGroup->numOfEntries)
{
j = p_ReplicGroup->numOfEntries-1;
/* manually removal of the member because there are no owners of
this group */
for (i=j; i>=0; i--)
{
p_CurrentMember = GetMemberByIndex(p_ReplicGroup, (uint16_t)i/*memberIndex*/);
ASSERT_COND(p_CurrentMember);
if (p_CurrentMember->h_Manip)
{
FmPcdManipUpdateOwner(p_CurrentMember->h_Manip, FALSE);
p_CurrentMember->h_Manip = NULL;
}
/* remove the member from the internal driver members list */
RemoveMemberFromList(p_ReplicGroup, p_CurrentMember);
/* return the member to the available members list */
FreeMember(p_ReplicGroup, p_CurrentMember);
}
}
/* Free members AD */
for (i=0; i<p_ReplicGroup->maxNumOfEntries; i++)
{
p_Member = GetAvailableMember(p_ReplicGroup);
ASSERT_COND(p_Member);
if (p_Member->p_MemberAd)
{
FM_MURAM_FreeMem(h_Muram, p_Member->p_MemberAd);
p_Member->p_MemberAd = NULL;
}
XX_Free(p_Member);
}
/* release the group lock */
if (p_ReplicGroup->p_Lock)
FmPcdReleaseLock(p_ReplicGroup->h_FmPcd, p_ReplicGroup->p_Lock);
/* free the replicator group */
XX_Free(p_ReplicGroup);
}
}
/*****************************************************************************/
/* Inter-module API routines */
/*****************************************************************************/
/* NOTE: the inter-module routines are locked by cc in case of using them */
void * FrmReplicGroupGetSourceTableDescriptor(t_Handle h_ReplicGroup)
{
t_FmPcdFrmReplicGroup *p_ReplicGroup = (t_FmPcdFrmReplicGroup *)h_ReplicGroup;
ASSERT_COND(p_ReplicGroup);
return (p_ReplicGroup->p_SourceTd);
}
void FrmReplicGroupUpdateAd(t_Handle h_ReplicGroup,
void *p_Ad,
t_Handle *h_AdNew)
{
t_FmPcdFrmReplicGroup *p_ReplicGroup = (t_FmPcdFrmReplicGroup *)h_ReplicGroup;
t_AdOfTypeResult *p_AdResult = (t_AdOfTypeResult*)p_Ad;
t_FmPcd *p_FmPcd;
ASSERT_COND(p_ReplicGroup);
p_FmPcd = p_ReplicGroup->h_FmPcd;
/* build a bypass ad */
WRITE_UINT32(p_AdResult->fqid, FM_PCD_AD_BYPASS_TYPE |
(uint32_t)((XX_VirtToPhys(p_ReplicGroup->p_SourceTd)) - p_FmPcd->physicalMuramBase));
*h_AdNew = NULL;
}
void FrmReplicGroupUpdateOwner(t_Handle h_ReplicGroup,
bool add)
{
t_FmPcdFrmReplicGroup *p_ReplicGroup = (t_FmPcdFrmReplicGroup *)h_ReplicGroup;
ASSERT_COND(p_ReplicGroup);
/* update the group owner counter */
if (add)
p_ReplicGroup->owners++;
else
{
ASSERT_COND(p_ReplicGroup->owners);
p_ReplicGroup->owners--;
}
}
t_Error FrmReplicGroupTryLock(t_Handle h_ReplicGroup)
{
t_FmPcdFrmReplicGroup *p_ReplicGroup = (t_FmPcdFrmReplicGroup *)h_ReplicGroup;
ASSERT_COND(h_ReplicGroup);
if (FmPcdLockTryLock(p_ReplicGroup->p_Lock))
return E_OK;
return ERROR_CODE(E_BUSY);
}
void FrmReplicGroupUnlock(t_Handle h_ReplicGroup)
{
t_FmPcdFrmReplicGroup *p_ReplicGroup = (t_FmPcdFrmReplicGroup *)h_ReplicGroup;
ASSERT_COND(h_ReplicGroup);
FmPcdLockUnlock(p_ReplicGroup->p_Lock);
}
/*********************** End of inter-module routines ************************/
/****************************************/
/* API Init unit functions */
/****************************************/
t_Handle FM_PCD_FrmReplicSetGroup(t_Handle h_FmPcd,
t_FmPcdFrmReplicGroupParams *p_ReplicGroupParam)
{
t_FmPcdFrmReplicGroup *p_ReplicGroup;
t_FmPcdFrmReplicMember *p_CurrentMember, *p_NextMember = NULL;
int i;
t_Error err;
bool last = FALSE;
t_Handle h_Muram;
SANITY_CHECK_RETURN_VALUE(h_FmPcd, E_INVALID_HANDLE, NULL);
SANITY_CHECK_RETURN_VALUE(p_ReplicGroupParam, E_INVALID_HANDLE, NULL);
if (!FmPcdIsAdvancedOffloadSupported(h_FmPcd))
{
REPORT_ERROR(MAJOR, E_INVALID_STATE, ("Advanced-offload must be enabled"));
return NULL;
}
err = CheckParams(h_FmPcd, p_ReplicGroupParam);
if (err)
{
REPORT_ERROR(MAJOR, err, (NO_MSG));
return NULL;
}
p_ReplicGroup = (t_FmPcdFrmReplicGroup*)XX_Malloc(sizeof(t_FmPcdFrmReplicGroup));
if (!p_ReplicGroup)
{
REPORT_ERROR(MAJOR, E_NO_MEMORY, ("No memory"));
return NULL;
}
memset(p_ReplicGroup, 0, sizeof(t_FmPcdFrmReplicGroup));
/* initialize lists for internal driver use */
INIT_LIST(&p_ReplicGroup->availableMembersList);
INIT_LIST(&p_ReplicGroup->membersList);
p_ReplicGroup->h_FmPcd = h_FmPcd;
h_Muram = FmPcdGetMuramHandle(p_ReplicGroup->h_FmPcd);
ASSERT_COND(h_Muram);
/* initialize the group lock */
p_ReplicGroup->p_Lock = FmPcdAcquireLock(p_ReplicGroup->h_FmPcd);
if (!p_ReplicGroup->p_Lock)
{
REPORT_ERROR(MAJOR, E_NO_MEMORY, ("Replic group lock"));
DeleteGroup(p_ReplicGroup);
return NULL;
}
/* Allocate the frame replicator source table descriptor */
p_ReplicGroup->p_SourceTd =
(t_Handle)FM_MURAM_AllocMem(h_Muram,
FM_PCD_CC_AD_ENTRY_SIZE,
FM_PCD_CC_AD_TABLE_ALIGN);
if (!p_ReplicGroup->p_SourceTd)
{
REPORT_ERROR(MAJOR, E_NO_MEMORY, ("frame replicator source table descriptor"));
DeleteGroup(p_ReplicGroup);
return NULL;
}
/* update the shadow size - required for the host commands */
err = FmPcdUpdateCcShadow(p_ReplicGroup->h_FmPcd,
FM_PCD_CC_AD_ENTRY_SIZE,
FM_PCD_CC_AD_TABLE_ALIGN);
if (err)
{
REPORT_ERROR(MAJOR, err, ("Update CC shadow"));
DeleteGroup(p_ReplicGroup);
return NULL;
}
p_ReplicGroup->maxNumOfEntries = p_ReplicGroupParam->maxNumOfEntries;
/* Allocate the maximal number of members ADs and Statistics AD for the group
It prevents allocation of Muram in run-time */
for (i=0; i<p_ReplicGroup->maxNumOfEntries; i++)
{
err = AllocMember(p_ReplicGroup);
if (err)
{
REPORT_ERROR(MAJOR, err, ("allocate a new member"));
DeleteGroup(p_ReplicGroup);
return NULL;
}
}
/* Initialize the members linked lists:
(hw - the one that is used by the FMan controller and
sw - the one that is managed by the driver internally) */
for (i=(p_ReplicGroupParam->numOfEntries-1); i>=0; i--)
{
/* check if this is the last member in the group */
if (i == (p_ReplicGroupParam->numOfEntries-1))
last = TRUE;
else
last = FALSE;
/* Initialize a new member */
p_CurrentMember = InitMember(p_ReplicGroup,
&(p_ReplicGroupParam->nextEngineParams[i]),
last);
if (!p_CurrentMember)
{
REPORT_ERROR(MAJOR, E_INVALID_HANDLE, ("No available member"));
DeleteGroup(p_ReplicGroup);
return NULL;
}
/* Build the members group - link two consecutive members in the hw linked list */
LinkMemberToMember(p_ReplicGroup, p_CurrentMember, p_NextMember);
/* update the driver internal members list to be compatible to the hw members linked list */
AddMemberToList(p_ReplicGroup, p_CurrentMember, &p_ReplicGroup->membersList);
p_NextMember = p_CurrentMember;
}
/* initialize the source table descriptor */
BuildSourceTd(p_ReplicGroup->p_SourceTd);
/* link the source table descriptor to point to the first member in the group */
LinkSourceToMember(p_ReplicGroup, p_ReplicGroup->p_SourceTd, p_NextMember);
return p_ReplicGroup;
}
t_Error FM_PCD_FrmReplicDeleteGroup(t_Handle h_ReplicGroup)
{
t_FmPcdFrmReplicGroup *p_ReplicGroup = (t_FmPcdFrmReplicGroup *)h_ReplicGroup;
SANITY_CHECK_RETURN_ERROR(p_ReplicGroup, E_INVALID_HANDLE);
if (p_ReplicGroup->owners)
RETURN_ERROR(MAJOR,
E_INVALID_STATE,
("the group has owners and can't be deleted"));
DeleteGroup(p_ReplicGroup);
return E_OK;
}
/*****************************************************************************/
/* API Run-time Frame replicator Control unit functions */
/*****************************************************************************/
t_Error FM_PCD_FrmReplicAddMember(t_Handle h_ReplicGroup,
uint16_t memberIndex,
t_FmPcdCcNextEngineParams *p_MemberParams)
{
t_FmPcdFrmReplicGroup *p_ReplicGroup = (t_FmPcdFrmReplicGroup*) h_ReplicGroup;
t_FmPcdFrmReplicMember *p_NewMember, *p_CurrentMember = NULL, *p_PreviousMember = NULL;
t_Error err;
uint8_t memberPosition;
SANITY_CHECK_RETURN_ERROR(p_ReplicGroup, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_MemberParams, E_INVALID_HANDLE);
/* group lock */
err = FrmReplicGroupTryLock(p_ReplicGroup);
if (GET_ERROR_TYPE(err) == E_BUSY)
return ERROR_CODE(E_BUSY);
if (memberIndex > p_ReplicGroup->numOfEntries)
{
/* unlock */
FrmReplicGroupUnlock(p_ReplicGroup);
RETURN_ERROR(MAJOR, E_INVALID_SELECTION,
("memberIndex is greater than the members in the list"));
}
if (memberIndex >= p_ReplicGroup->maxNumOfEntries)
{
/* unlock */
FrmReplicGroupUnlock(p_ReplicGroup);
RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("memberIndex is greater than the allowed number of members in the group"));
}
if ((p_ReplicGroup->numOfEntries + 1) > FM_PCD_FRM_REPLIC_MAX_NUM_OF_ENTRIES)
{
/* unlock */
FrmReplicGroupUnlock(p_ReplicGroup);
RETURN_ERROR(MAJOR, E_INVALID_VALUE,
("numOfEntries with new entry can not be larger than %d\n",
FM_PCD_FRM_REPLIC_MAX_NUM_OF_ENTRIES));
}
err = MemberCheckParams(p_ReplicGroup->h_FmPcd, p_MemberParams);
if (err)
{
/* unlock */
FrmReplicGroupUnlock(p_ReplicGroup);
RETURN_ERROR(MAJOR, err, ("member check parameters in add operation"));
}
/* determine the member position in the group */
memberPosition = GetMemberPosition(p_ReplicGroup,
memberIndex,
TRUE/* add operation */);
/* Initialize a new member */
p_NewMember = InitMember(p_ReplicGroup,
p_MemberParams,
(memberPosition == FRM_REPLIC_LAST_MEMBER_INDEX ? TRUE : FALSE));
if (!p_NewMember)
{
/* unlock */
FrmReplicGroupUnlock(p_ReplicGroup);
RETURN_ERROR(MAJOR, E_INVALID_HANDLE, ("No available member"));
}
switch (memberPosition)
{
case FRM_REPLIC_FIRST_MEMBER_INDEX:
p_CurrentMember = GetMemberByIndex(p_ReplicGroup, memberIndex);
ASSERT_COND(p_CurrentMember);
LinkMemberToMember(p_ReplicGroup, p_NewMember, p_CurrentMember);
/* update the internal group source TD */
LinkSourceToMember(p_ReplicGroup,
p_ReplicGroup->p_SourceTd,
p_NewMember);
/* add member to the internal sw member list */
AddMemberToList(p_ReplicGroup,
p_NewMember,
&p_ReplicGroup->membersList);
break;
case FRM_REPLIC_MIDDLE_MEMBER_INDEX:
p_CurrentMember = GetMemberByIndex(p_ReplicGroup, memberIndex);
ASSERT_COND(p_CurrentMember);
p_PreviousMember = GetMemberByIndex(p_ReplicGroup, (uint16_t)(memberIndex-1));
ASSERT_COND(p_PreviousMember);
LinkMemberToMember(p_ReplicGroup, p_NewMember, p_CurrentMember);
LinkMemberToMember(p_ReplicGroup, p_PreviousMember, p_NewMember);
AddMemberToList(p_ReplicGroup, p_NewMember, &p_PreviousMember->node);
break;
case FRM_REPLIC_LAST_MEMBER_INDEX:
p_PreviousMember = GetMemberByIndex(p_ReplicGroup, (uint16_t)(memberIndex-1));
ASSERT_COND(p_PreviousMember);
LinkMemberToMember(p_ReplicGroup, p_PreviousMember, p_NewMember);
FillReplicAdOfTypeResult(p_PreviousMember->p_MemberAd, FALSE/*last*/);
/* add the new member to the internal sw member list */
AddMemberToList(p_ReplicGroup, p_NewMember, &p_PreviousMember->node);
break;
default:
/* unlock */
FrmReplicGroupUnlock(p_ReplicGroup);
RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("member position in add member"));
}
/* unlock */
FrmReplicGroupUnlock(p_ReplicGroup);
return E_OK;
}
t_Error FM_PCD_FrmReplicRemoveMember(t_Handle h_ReplicGroup,
uint16_t memberIndex)
{
t_FmPcdFrmReplicGroup *p_ReplicGroup = (t_FmPcdFrmReplicGroup*) h_ReplicGroup;
t_Error err;
SANITY_CHECK_RETURN_ERROR(p_ReplicGroup, E_INVALID_HANDLE);
/* lock */
err = FrmReplicGroupTryLock(p_ReplicGroup);
if (GET_ERROR_TYPE(err) == E_BUSY)
return ERROR_CODE(E_BUSY);
if (memberIndex >= p_ReplicGroup->numOfEntries)
RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("member index to remove"));
/* Design decision: group must contain at least one member
No possibility to remove the last member from the group */
if (p_ReplicGroup->numOfEntries == 1)
RETURN_ERROR(MAJOR, E_CONFLICT, ("Can't remove the last member. At least one member should be related to a group."));
err = RemoveMember(p_ReplicGroup, memberIndex);
/* unlock */
FrmReplicGroupUnlock(p_ReplicGroup);
switch (GET_ERROR_TYPE(err))
{
case E_OK:
return E_OK;
case E_BUSY:
DBG(TRACE, ("E_BUSY error"));
return ERROR_CODE(E_BUSY);
default:
RETURN_ERROR(MAJOR, err, NO_MSG);
}
}
/*********************** End of API routines ************************/

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/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_replic.h
@Description FM frame replicator
*//***************************************************************************/
#ifndef __FM_REPLIC_H
#define __FM_REPLIC_H
#include "std_ext.h"
#include "error_ext.h"
#define FRM_REPLIC_SOURCE_TD_OPCODE 0x75
#define NEXT_FRM_REPLIC_ADDR_SHIFT 4
#define NEXT_FRM_REPLIC_MEMBER_INDEX_SHIFT 16
#define FRM_REPLIC_FR_BIT 0x08000000
#define FRM_REPLIC_NL_BIT 0x10000000
#define FRM_REPLIC_INVALID_MEMBER_INDEX 0xffff
#define FRM_REPLIC_FIRST_MEMBER_INDEX 0
#define FRM_REPLIC_MIDDLE_MEMBER_INDEX 1
#define FRM_REPLIC_LAST_MEMBER_INDEX 2
#define SOURCE_TD_ITSELF_OPTION 0x01
#define SOURCE_TD_COPY_OPTION 0x02
#define SOURCE_TD_ITSELF_AND_COPY_OPTION SOURCE_TD_ITSELF_OPTION | SOURCE_TD_COPY_OPTION
#define SOURCE_TD_NONE 0x04
/*typedef enum e_SourceTdOption
{
e_SOURCE_TD_NONE = 0,
e_SOURCE_TD_ITSELF_OPTION = 1,
e_SOURCE_TD_COPY_OPTION = 2,
e_SOURCE_TD_ITSELF_AND_COPY_OPTION = e_SOURCE_TD_ITSELF_OPTION | e_SOURCE_TD_COPY_OPTION
} e_SourceTdOption;
*/
typedef struct
{
volatile uint32_t type;
volatile uint32_t frGroupPointer;
volatile uint32_t operationCode;
volatile uint32_t reserved;
} t_FrmReplicGroupSourceAd;
typedef struct t_FmPcdFrmReplicMember
{
void *p_MemberAd; /**< pointer to the member AD */
void *p_StatisticsAd;/**< pointer to the statistics AD of the member */
t_Handle h_Manip; /**< manip handle - need for free routines */
t_List node;
} t_FmPcdFrmReplicMember;
typedef struct t_FmPcdFrmReplicGroup
{
t_Handle h_FmPcd;
uint8_t maxNumOfEntries;/**< maximal number of members in the group */
uint8_t numOfEntries; /**< actual number of members in the group */
uint16_t owners; /**< how many keys share this frame replicator group */
void *p_SourceTd; /**< pointer to the frame replicator source table descriptor */
t_List membersList; /**< the members list - should reflect the order of the members as in the hw linked list*/
t_List availableMembersList;/**< list of all the available members in the group */
t_FmPcdLock *p_Lock;
} t_FmPcdFrmReplicGroup;
#endif /* __FM_REPLIC_H */

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/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_fman_kg.h"
/****************************************/
/* static functions */
/****************************************/
static uint32_t build_ar_bind_scheme(uint8_t hwport_id, bool write)
{
uint32_t rw;
rw = write ? (uint32_t)FM_KG_KGAR_WRITE : (uint32_t)FM_KG_KGAR_READ;
return (uint32_t)(FM_KG_KGAR_GO |
rw |
FM_PCD_KG_KGAR_SEL_PORT_ENTRY |
hwport_id |
FM_PCD_KG_KGAR_SEL_PORT_WSEL_SP);
}
static void clear_pe_all_scheme(struct fman_kg_regs *regs, uint8_t hwport_id)
{
uint32_t ar;
fman_kg_write_sp(regs, 0xffffffff, 0);
ar = build_ar_bind_scheme(hwport_id, TRUE);
fman_kg_write_ar_wait(regs, ar);
}
static uint32_t build_ar_bind_cls_plan(uint8_t hwport_id, bool write)
{
uint32_t rw;
rw = write ? (uint32_t)FM_KG_KGAR_WRITE : (uint32_t)FM_KG_KGAR_READ;
return (uint32_t)(FM_KG_KGAR_GO |
rw |
FM_PCD_KG_KGAR_SEL_PORT_ENTRY |
hwport_id |
FM_PCD_KG_KGAR_SEL_PORT_WSEL_CPP);
}
static void clear_pe_all_cls_plan(struct fman_kg_regs *regs, uint8_t hwport_id)
{
uint32_t ar;
fman_kg_write_cpp(regs, 0);
ar = build_ar_bind_cls_plan(hwport_id, TRUE);
fman_kg_write_ar_wait(regs, ar);
}
static uint8_t get_gen_ht_code(enum fman_kg_gen_extract_src src,
bool no_validation,
uint8_t *offset)
{
int code;
switch (src) {
case E_FMAN_KG_GEN_EXTRACT_ETH:
code = no_validation ? 0x73 : 0x3;
break;
case E_FMAN_KG_GEN_EXTRACT_ETYPE:
code = no_validation ? 0x77 : 0x7;
break;
case E_FMAN_KG_GEN_EXTRACT_SNAP:
code = no_validation ? 0x74 : 0x4;
break;
case E_FMAN_KG_GEN_EXTRACT_VLAN_TCI_1:
code = no_validation ? 0x75 : 0x5;
break;
case E_FMAN_KG_GEN_EXTRACT_VLAN_TCI_N:
code = no_validation ? 0x76 : 0x6;
break;
case E_FMAN_KG_GEN_EXTRACT_PPPoE:
code = no_validation ? 0x78 : 0x8;
break;
case E_FMAN_KG_GEN_EXTRACT_MPLS_1:
code = no_validation ? 0x79 : 0x9;
break;
case E_FMAN_KG_GEN_EXTRACT_MPLS_2:
code = no_validation ? FM_KG_SCH_GEN_HT_INVALID : 0x19;
break;
case E_FMAN_KG_GEN_EXTRACT_MPLS_3:
code = no_validation ? FM_KG_SCH_GEN_HT_INVALID : 0x29;
break;
case E_FMAN_KG_GEN_EXTRACT_MPLS_N:
code = no_validation ? 0x7a : 0xa;
break;
case E_FMAN_KG_GEN_EXTRACT_IPv4_1:
code = no_validation ? 0x7b : 0xb;
break;
case E_FMAN_KG_GEN_EXTRACT_IPv6_1:
code = no_validation ? 0x7b : 0x1b;
break;
case E_FMAN_KG_GEN_EXTRACT_IPv4_2:
code = no_validation ? 0x7c : 0xc;
break;
case E_FMAN_KG_GEN_EXTRACT_IPv6_2:
code = no_validation ? 0x7c : 0x1c;
break;
case E_FMAN_KG_GEN_EXTRACT_MINENCAP:
code = no_validation ? 0x7c : 0x2c;
break;
case E_FMAN_KG_GEN_EXTRACT_IP_PID:
code = no_validation ? 0x72 : 0x2;
break;
case E_FMAN_KG_GEN_EXTRACT_GRE:
code = no_validation ? 0x7d : 0xd;
break;
case E_FMAN_KG_GEN_EXTRACT_TCP:
code = no_validation ? 0x7e : 0xe;
break;
case E_FMAN_KG_GEN_EXTRACT_UDP:
code = no_validation ? 0x7e : 0x1e;
break;
case E_FMAN_KG_GEN_EXTRACT_SCTP:
code = no_validation ? 0x7e : 0x3e;
break;
case E_FMAN_KG_GEN_EXTRACT_DCCP:
code = no_validation ? 0x7e : 0x4e;
break;
case E_FMAN_KG_GEN_EXTRACT_IPSEC_AH:
code = no_validation ? 0x7e : 0x2e;
break;
case E_FMAN_KG_GEN_EXTRACT_IPSEC_ESP:
code = no_validation ? 0x7e : 0x6e;
break;
case E_FMAN_KG_GEN_EXTRACT_SHIM_1:
code = 0x70;
break;
case E_FMAN_KG_GEN_EXTRACT_SHIM_2:
code = 0x71;
break;
case E_FMAN_KG_GEN_EXTRACT_FROM_DFLT:
code = 0x10;
break;
case E_FMAN_KG_GEN_EXTRACT_FROM_FRAME_START:
code = 0x40;
break;
case E_FMAN_KG_GEN_EXTRACT_FROM_PARSE_RESULT:
code = 0x20;
break;
case E_FMAN_KG_GEN_EXTRACT_FROM_END_OF_PARSE:
code = 0x7f;
break;
case E_FMAN_KG_GEN_EXTRACT_FROM_FQID:
code = 0x20;
*offset += 0x20;
break;
default:
code = FM_KG_SCH_GEN_HT_INVALID;
}
return (uint8_t)code;
}
static uint32_t build_ar_scheme(uint8_t scheme,
uint8_t hwport_id,
bool update_counter,
bool write)
{
uint32_t rw;
rw = (uint32_t)(write ? FM_KG_KGAR_WRITE : FM_KG_KGAR_READ);
return (uint32_t)(FM_KG_KGAR_GO |
rw |
FM_KG_KGAR_SEL_SCHEME_ENTRY |
hwport_id |
((uint32_t)scheme << FM_KG_KGAR_NUM_SHIFT) |
(update_counter ? FM_KG_KGAR_SCM_WSEL_UPDATE_CNT : 0));
}
static uint32_t build_ar_cls_plan(uint8_t grp,
uint8_t entries_mask,
uint8_t hwport_id,
bool write)
{
uint32_t rw;
rw = (uint32_t)(write ? FM_KG_KGAR_WRITE : FM_KG_KGAR_READ);
return (uint32_t)(FM_KG_KGAR_GO |
rw |
FM_PCD_KG_KGAR_SEL_CLS_PLAN_ENTRY |
hwport_id |
((uint32_t)grp << FM_KG_KGAR_NUM_SHIFT) |
((uint32_t)entries_mask << FM_KG_KGAR_WSEL_SHIFT));
}
int fman_kg_write_ar_wait(struct fman_kg_regs *regs, uint32_t fmkg_ar)
{
iowrite32be(fmkg_ar, &regs->fmkg_ar);
/* Wait for GO to be idle and read error */
while ((fmkg_ar = ioread32be(&regs->fmkg_ar)) & FM_KG_KGAR_GO) ;
if (fmkg_ar & FM_PCD_KG_KGAR_ERR)
return -EINVAL;
return 0;
}
void fman_kg_write_sp(struct fman_kg_regs *regs, uint32_t sp, bool add)
{
struct fman_kg_pe_regs *kgpe_regs;
uint32_t tmp;
kgpe_regs = (struct fman_kg_pe_regs *)&(regs->fmkg_indirect[0]);
tmp = ioread32be(&kgpe_regs->fmkg_pe_sp);
if (add)
tmp |= sp;
else /* clear */
tmp &= ~sp;
iowrite32be(tmp, &kgpe_regs->fmkg_pe_sp);
}
void fman_kg_write_cpp(struct fman_kg_regs *regs, uint32_t cpp)
{
struct fman_kg_pe_regs *kgpe_regs;
kgpe_regs = (struct fman_kg_pe_regs *)&(regs->fmkg_indirect[0]);
iowrite32be(cpp, &kgpe_regs->fmkg_pe_cpp);
}
void fman_kg_get_event(struct fman_kg_regs *regs,
uint32_t *event,
uint32_t *scheme_idx)
{
uint32_t mask, force;
*event = ioread32be(&regs->fmkg_eer);
mask = ioread32be(&regs->fmkg_eeer);
*scheme_idx = ioread32be(&regs->fmkg_seer);
*scheme_idx &= ioread32be(&regs->fmkg_seeer);
*event &= mask;
/* clear the forced events */
force = ioread32be(&regs->fmkg_feer);
if (force & *event)
iowrite32be(force & ~*event ,&regs->fmkg_feer);
iowrite32be(*event, &regs->fmkg_eer);
iowrite32be(*scheme_idx, &regs->fmkg_seer);
}
void fman_kg_init(struct fman_kg_regs *regs,
uint32_t exceptions,
uint32_t dflt_nia)
{
uint32_t tmp;
int i;
iowrite32be(FM_EX_KG_DOUBLE_ECC | FM_EX_KG_KEYSIZE_OVERFLOW,
&regs->fmkg_eer);
tmp = 0;
if (exceptions & FM_EX_KG_DOUBLE_ECC)
tmp |= FM_EX_KG_DOUBLE_ECC;
if (exceptions & FM_EX_KG_KEYSIZE_OVERFLOW)
tmp |= FM_EX_KG_KEYSIZE_OVERFLOW;
iowrite32be(tmp, &regs->fmkg_eeer);
iowrite32be(0, &regs->fmkg_fdor);
iowrite32be(0, &regs->fmkg_gdv0r);
iowrite32be(0, &regs->fmkg_gdv1r);
iowrite32be(dflt_nia, &regs->fmkg_gcr);
/* Clear binding between ports to schemes and classification plans
* so that all ports are not bound to any scheme/classification plan */
for (i = 0; i < FMAN_MAX_NUM_OF_HW_PORTS; i++) {
clear_pe_all_scheme(regs, (uint8_t)i);
clear_pe_all_cls_plan(regs, (uint8_t)i);
}
}
void fman_kg_enable_scheme_interrupts(struct fman_kg_regs *regs)
{
/* enable and enable all scheme interrupts */
iowrite32be(0xFFFFFFFF, &regs->fmkg_seer);
iowrite32be(0xFFFFFFFF, &regs->fmkg_seeer);
}
void fman_kg_enable(struct fman_kg_regs *regs)
{
iowrite32be(ioread32be(&regs->fmkg_gcr) | FM_KG_KGGCR_EN,
&regs->fmkg_gcr);
}
void fman_kg_disable(struct fman_kg_regs *regs)
{
iowrite32be(ioread32be(&regs->fmkg_gcr) & ~FM_KG_KGGCR_EN,
&regs->fmkg_gcr);
}
void fman_kg_set_data_after_prs(struct fman_kg_regs *regs, uint8_t offset)
{
iowrite32be(offset, &regs->fmkg_fdor);
}
void fman_kg_set_dflt_val(struct fman_kg_regs *regs,
uint8_t def_id,
uint32_t val)
{
if(def_id == 0)
iowrite32be(val, &regs->fmkg_gdv0r);
else
iowrite32be(val, &regs->fmkg_gdv1r);
}
void fman_kg_set_exception(struct fman_kg_regs *regs,
uint32_t exception,
bool enable)
{
uint32_t tmp;
tmp = ioread32be(&regs->fmkg_eeer);
if (enable) {
tmp |= exception;
} else {
tmp &= ~exception;
}
iowrite32be(tmp, &regs->fmkg_eeer);
}
void fman_kg_get_exception(struct fman_kg_regs *regs,
uint32_t *events,
uint32_t *scheme_ids,
bool clear)
{
uint32_t mask;
*events = ioread32be(&regs->fmkg_eer);
mask = ioread32be(&regs->fmkg_eeer);
*events &= mask;
*scheme_ids = 0;
if (*events & FM_EX_KG_KEYSIZE_OVERFLOW) {
*scheme_ids = ioread32be(&regs->fmkg_seer);
mask = ioread32be(&regs->fmkg_seeer);
*scheme_ids &= mask;
}
if (clear) {
iowrite32be(*scheme_ids, &regs->fmkg_seer);
iowrite32be(*events, &regs->fmkg_eer);
}
}
void fman_kg_get_capture(struct fman_kg_regs *regs,
struct fman_kg_ex_ecc_attr *ecc_attr,
bool clear)
{
uint32_t tmp;
tmp = ioread32be(&regs->fmkg_serc);
if (tmp & KG_FMKG_SERC_CAP) {
/* Captured data is valid */
ecc_attr->valid = TRUE;
ecc_attr->double_ecc =
(bool)((tmp & KG_FMKG_SERC_CET) ? TRUE : FALSE);
ecc_attr->single_ecc_count =
(uint8_t)((tmp & KG_FMKG_SERC_CNT_MSK) >>
KG_FMKG_SERC_CNT_SHIFT);
ecc_attr->addr = (uint16_t)(tmp & KG_FMKG_SERC_ADDR_MSK);
if (clear)
iowrite32be(KG_FMKG_SERC_CAP, &regs->fmkg_serc);
} else {
/* No ECC error is captured */
ecc_attr->valid = FALSE;
}
}
int fman_kg_build_scheme(struct fman_kg_scheme_params *params,
struct fman_kg_scheme_regs *scheme_regs)
{
struct fman_kg_extract_params *extract_params;
struct fman_kg_gen_extract_params *gen_params;
uint32_t tmp_reg, i, select, mask, fqb;
uint8_t offset, shift, ht;
/* Zero out all registers so no need to care about unused ones */
memset(scheme_regs, 0, sizeof(struct fman_kg_scheme_regs));
/* Mode register */
tmp_reg = fm_kg_build_nia(params->next_engine,
params->next_engine_action);
if (tmp_reg == KG_NIA_INVALID) {
return -EINVAL;
}
if (params->next_engine == E_FMAN_PCD_PLCR) {
tmp_reg |= FMAN_KG_SCH_MODE_NIA_PLCR;
}
else if (params->next_engine == E_FMAN_PCD_CC) {
tmp_reg |= (uint32_t)params->cc_params.base_offset <<
FMAN_KG_SCH_MODE_CCOBASE_SHIFT;
}
tmp_reg |= FMAN_KG_SCH_MODE_EN;
scheme_regs->kgse_mode = tmp_reg;
/* Match vector */
scheme_regs->kgse_mv = params->match_vector;
extract_params = &params->extract_params;
/* Scheme default values registers */
scheme_regs->kgse_dv0 = extract_params->def_scheme_0;
scheme_regs->kgse_dv1 = extract_params->def_scheme_1;
/* Extract Known Fields Command register */
scheme_regs->kgse_ekfc = extract_params->known_fields;
/* Entry Extract Known Default Value register */
tmp_reg = 0;
tmp_reg |= extract_params->known_fields_def.mac_addr <<
FMAN_KG_SCH_DEF_MAC_ADDR_SHIFT;
tmp_reg |= extract_params->known_fields_def.vlan_tci <<
FMAN_KG_SCH_DEF_VLAN_TCI_SHIFT;
tmp_reg |= extract_params->known_fields_def.etype <<
FMAN_KG_SCH_DEF_ETYPE_SHIFT;
tmp_reg |= extract_params->known_fields_def.ppp_sid <<
FMAN_KG_SCH_DEF_PPP_SID_SHIFT;
tmp_reg |= extract_params->known_fields_def.ppp_pid <<
FMAN_KG_SCH_DEF_PPP_PID_SHIFT;
tmp_reg |= extract_params->known_fields_def.mpls <<
FMAN_KG_SCH_DEF_MPLS_SHIFT;
tmp_reg |= extract_params->known_fields_def.ip_addr <<
FMAN_KG_SCH_DEF_IP_ADDR_SHIFT;
tmp_reg |= extract_params->known_fields_def.ptype <<
FMAN_KG_SCH_DEF_PTYPE_SHIFT;
tmp_reg |= extract_params->known_fields_def.ip_tos_tc <<
FMAN_KG_SCH_DEF_IP_TOS_TC_SHIFT;
tmp_reg |= extract_params->known_fields_def.ipv6_fl <<
FMAN_KG_SCH_DEF_IPv6_FL_SHIFT;
tmp_reg |= extract_params->known_fields_def.ipsec_spi <<
FMAN_KG_SCH_DEF_IPSEC_SPI_SHIFT;
tmp_reg |= extract_params->known_fields_def.l4_port <<
FMAN_KG_SCH_DEF_L4_PORT_SHIFT;
tmp_reg |= extract_params->known_fields_def.tcp_flg <<
FMAN_KG_SCH_DEF_TCP_FLG_SHIFT;
scheme_regs->kgse_ekdv = tmp_reg;
/* Generic extract registers */
if (extract_params->gen_extract_num > FM_KG_NUM_OF_GENERIC_REGS) {
return -EINVAL;
}
for (i = 0; i < extract_params->gen_extract_num; i++) {
gen_params = extract_params->gen_extract + i;
tmp_reg = FMAN_KG_SCH_GEN_VALID;
tmp_reg |= (uint32_t)gen_params->def_val <<
FMAN_KG_SCH_GEN_DEF_SHIFT;
if (gen_params->type == E_FMAN_KG_HASH_EXTRACT) {
if ((gen_params->extract > FMAN_KG_SCH_GEN_SIZE_MAX) ||
(gen_params->extract == 0)) {
return -EINVAL;
}
} else {
tmp_reg |= FMAN_KG_SCH_GEN_OR;
}
tmp_reg |= (uint32_t)gen_params->extract <<
FMAN_KG_SCH_GEN_SIZE_SHIFT;
tmp_reg |= (uint32_t)gen_params->mask <<
FMAN_KG_SCH_GEN_MASK_SHIFT;
offset = gen_params->offset;
ht = get_gen_ht_code(gen_params->src,
gen_params->no_validation,
&offset);
tmp_reg |= (uint32_t)ht << FMAN_KG_SCH_GEN_HT_SHIFT;
tmp_reg |= offset;
scheme_regs->kgse_gec[i] = tmp_reg;
}
/* Masks registers */
if (extract_params->masks_num > FM_KG_EXTRACT_MASKS_NUM) {
return -EINVAL;
}
select = 0;
mask = 0;
fqb = 0;
for (i = 0; i < extract_params->masks_num; i++) {
/* MCSx fields */
KG_GET_MASK_SEL_SHIFT(shift, i);
if (extract_params->masks[i].is_known) {
/* Mask known field */
select |= extract_params->masks[i].field_or_gen_idx <<
shift;
} else {
/* Mask generic extract */
select |= (extract_params->masks[i].field_or_gen_idx +
FM_KG_MASK_SEL_GEN_BASE) << shift;
}
/* MOx fields - spread between se_bmch and se_fqb registers */
KG_GET_MASK_OFFSET_SHIFT(shift, i);
if (i < 2) {
select |= (uint32_t)extract_params->masks[i].offset <<
shift;
} else {
fqb |= (uint32_t)extract_params->masks[i].offset <<
shift;
}
/* BMx fields */
KG_GET_MASK_SHIFT(shift, i);
mask |= (uint32_t)extract_params->masks[i].mask << shift;
}
/* Finish with rest of BMx fileds -
* don't mask bits for unused masks by setting
* corresponding BMx field = 0xFF */
for (i = extract_params->masks_num; i < FM_KG_EXTRACT_MASKS_NUM; i++) {
KG_GET_MASK_SHIFT(shift, i);
mask |= 0xFF << shift;
}
scheme_regs->kgse_bmch = select;
scheme_regs->kgse_bmcl = mask;
/* Finish with FQB register initialization.
* Check fqid is 24-bit value. */
if (params->base_fqid & ~0x00FFFFFF) {
return -EINVAL;
}
fqb |= params->base_fqid;
scheme_regs->kgse_fqb = fqb;
/* Hash Configuration register */
tmp_reg = 0;
if (params->hash_params.use_hash) {
/* Check hash mask is 24-bit value */
if (params->hash_params.mask & ~0x00FFFFFF) {
return -EINVAL;
}
/* Hash function produces 64-bit value, 24 bits of that
* are used to generate fq_id and policer profile.
* Thus, maximal shift is 40 bits to allow 24 bits out of 64.
*/
if (params->hash_params.shift_r > FMAN_KG_SCH_HASH_HSHIFT_MAX) {
return -EINVAL;
}
tmp_reg |= params->hash_params.mask;
tmp_reg |= (uint32_t)params->hash_params.shift_r <<
FMAN_KG_SCH_HASH_HSHIFT_SHIFT;
if (params->hash_params.sym) {
tmp_reg |= FMAN_KG_SCH_HASH_SYM;
}
}
if (params->bypass_fqid_gen) {
tmp_reg |= FMAN_KG_SCH_HASH_NO_FQID_GEN;
}
scheme_regs->kgse_hc = tmp_reg;
/* Policer Profile register */
if (params->policer_params.bypass_pp_gen) {
tmp_reg = 0;
} else {
/* Lower 8 bits of 24-bits extracted from hash result
* are used for policer profile generation.
* That leaves maximum shift value = 23. */
if (params->policer_params.shift > FMAN_KG_SCH_PP_SHIFT_MAX) {
return -EINVAL;
}
tmp_reg = params->policer_params.base;
tmp_reg |= ((uint32_t)params->policer_params.shift <<
FMAN_KG_SCH_PP_SH_SHIFT) &
FMAN_KG_SCH_PP_SH_MASK;
tmp_reg |= ((uint32_t)params->policer_params.shift <<
FMAN_KG_SCH_PP_SL_SHIFT) &
FMAN_KG_SCH_PP_SL_MASK;
tmp_reg |= (uint32_t)params->policer_params.mask <<
FMAN_KG_SCH_PP_MASK_SHIFT;
}
scheme_regs->kgse_ppc = tmp_reg;
/* Coarse Classification Bit Select register */
if (params->next_engine == E_FMAN_PCD_CC) {
scheme_regs->kgse_ccbs = params->cc_params.qlcv_bits_sel;
}
/* Packets Counter register */
if (params->update_counter) {
scheme_regs->kgse_spc = params->counter_value;
}
return 0;
}
int fman_kg_write_scheme(struct fman_kg_regs *regs,
uint8_t scheme_id,
uint8_t hwport_id,
struct fman_kg_scheme_regs *scheme_regs,
bool update_counter)
{
struct fman_kg_scheme_regs *kgse_regs;
uint32_t tmp_reg;
int err, i;
/* Write indirect scheme registers */
kgse_regs = (struct fman_kg_scheme_regs *)&(regs->fmkg_indirect[0]);
iowrite32be(scheme_regs->kgse_mode, &kgse_regs->kgse_mode);
iowrite32be(scheme_regs->kgse_ekfc, &kgse_regs->kgse_ekfc);
iowrite32be(scheme_regs->kgse_ekdv, &kgse_regs->kgse_ekdv);
iowrite32be(scheme_regs->kgse_bmch, &kgse_regs->kgse_bmch);
iowrite32be(scheme_regs->kgse_bmcl, &kgse_regs->kgse_bmcl);
iowrite32be(scheme_regs->kgse_fqb, &kgse_regs->kgse_fqb);
iowrite32be(scheme_regs->kgse_hc, &kgse_regs->kgse_hc);
iowrite32be(scheme_regs->kgse_ppc, &kgse_regs->kgse_ppc);
iowrite32be(scheme_regs->kgse_spc, &kgse_regs->kgse_spc);
iowrite32be(scheme_regs->kgse_dv0, &kgse_regs->kgse_dv0);
iowrite32be(scheme_regs->kgse_dv1, &kgse_regs->kgse_dv1);
iowrite32be(scheme_regs->kgse_ccbs, &kgse_regs->kgse_ccbs);
iowrite32be(scheme_regs->kgse_mv, &kgse_regs->kgse_mv);
for (i = 0 ; i < FM_KG_NUM_OF_GENERIC_REGS ; i++)
iowrite32be(scheme_regs->kgse_gec[i], &kgse_regs->kgse_gec[i]);
/* Write AR (Action register) */
tmp_reg = build_ar_scheme(scheme_id, hwport_id, update_counter, TRUE);
err = fman_kg_write_ar_wait(regs, tmp_reg);
return err;
}
int fman_kg_delete_scheme(struct fman_kg_regs *regs,
uint8_t scheme_id,
uint8_t hwport_id)
{
struct fman_kg_scheme_regs *kgse_regs;
uint32_t tmp_reg;
int err, i;
kgse_regs = (struct fman_kg_scheme_regs *)&(regs->fmkg_indirect[0]);
/* Clear all registers including enable bit in mode register */
for (i = 0; i < (sizeof(struct fman_kg_scheme_regs)) / 4; ++i) {
iowrite32be(0, ((uint32_t *)kgse_regs + i));
}
/* Write AR (Action register) */
tmp_reg = build_ar_scheme(scheme_id, hwport_id, FALSE, TRUE);
err = fman_kg_write_ar_wait(regs, tmp_reg);
return err;
}
int fman_kg_get_scheme_counter(struct fman_kg_regs *regs,
uint8_t scheme_id,
uint8_t hwport_id,
uint32_t *counter)
{
struct fman_kg_scheme_regs *kgse_regs;
uint32_t tmp_reg;
int err;
kgse_regs = (struct fman_kg_scheme_regs *)&(regs->fmkg_indirect[0]);
tmp_reg = build_ar_scheme(scheme_id, hwport_id, TRUE, FALSE);
err = fman_kg_write_ar_wait(regs, tmp_reg);
if (err != 0)
return err;
*counter = ioread32be(&kgse_regs->kgse_spc);
return 0;
}
int fman_kg_set_scheme_counter(struct fman_kg_regs *regs,
uint8_t scheme_id,
uint8_t hwport_id,
uint32_t counter)
{
struct fman_kg_scheme_regs *kgse_regs;
uint32_t tmp_reg;
int err;
kgse_regs = (struct fman_kg_scheme_regs *)&(regs->fmkg_indirect[0]);
tmp_reg = build_ar_scheme(scheme_id, hwport_id, TRUE, FALSE);
err = fman_kg_write_ar_wait(regs, tmp_reg);
if (err != 0)
return err;
/* Keygen indirect access memory contains all scheme_id registers
* by now. Change only counter value. */
iowrite32be(counter, &kgse_regs->kgse_spc);
/* Write back scheme registers */
tmp_reg = build_ar_scheme(scheme_id, hwport_id, TRUE, TRUE);
err = fman_kg_write_ar_wait(regs, tmp_reg);
return err;
}
uint32_t fman_kg_get_schemes_total_counter(struct fman_kg_regs *regs)
{
return ioread32be(&regs->fmkg_tpc);
}
int fman_kg_build_cls_plan(struct fman_kg_cls_plan_params *params,
struct fman_kg_cp_regs *cls_plan_regs)
{
uint8_t entries_set, entry_bit;
int i;
/* Zero out all group's register */
memset(cls_plan_regs, 0, sizeof(struct fman_kg_cp_regs));
/* Go over all classification entries in params->entries_mask and
* configure the corresponding cpe register */
entries_set = params->entries_mask;
for (i = 0; entries_set; i++) {
entry_bit = (uint8_t)(0x80 >> i);
if ((entry_bit & entries_set) == 0)
continue;
entries_set ^= entry_bit;
cls_plan_regs->kgcpe[i] = params->mask_vector[i];
}
return 0;
}
int fman_kg_write_cls_plan(struct fman_kg_regs *regs,
uint8_t grp_id,
uint8_t entries_mask,
uint8_t hwport_id,
struct fman_kg_cp_regs *cls_plan_regs)
{
struct fman_kg_cp_regs *kgcpe_regs;
uint32_t tmp_reg;
int i, err;
/* Check group index is valid and the group isn't empty */
if (grp_id >= FM_KG_CLS_PLAN_GRPS_NUM)
return -EINVAL;
/* Write indirect classification plan registers */
kgcpe_regs = (struct fman_kg_cp_regs *)&(regs->fmkg_indirect[0]);
for (i = 0; i < FM_KG_NUM_CLS_PLAN_ENTR; i++) {
iowrite32be(cls_plan_regs->kgcpe[i], &kgcpe_regs->kgcpe[i]);
}
tmp_reg = build_ar_cls_plan(grp_id, entries_mask, hwport_id, TRUE);
err = fman_kg_write_ar_wait(regs, tmp_reg);
return err;
}
int fman_kg_write_bind_schemes(struct fman_kg_regs *regs,
uint8_t hwport_id,
uint32_t schemes)
{
struct fman_kg_pe_regs *kg_pe_regs;
uint32_t tmp_reg;
int err;
kg_pe_regs = (struct fman_kg_pe_regs *)&(regs->fmkg_indirect[0]);
iowrite32be(schemes, &kg_pe_regs->fmkg_pe_sp);
tmp_reg = build_ar_bind_scheme(hwport_id, TRUE);
err = fman_kg_write_ar_wait(regs, tmp_reg);
return err;
}
int fman_kg_build_bind_cls_plans(uint8_t grp_base,
uint8_t grp_mask,
uint32_t *bind_cls_plans)
{
/* Check grp_base and grp_mask are 5-bits values */
if ((grp_base & ~0x0000001F) || (grp_mask & ~0x0000001F))
return -EINVAL;
*bind_cls_plans = (uint32_t) ((grp_mask << FMAN_KG_PE_CPP_MASK_SHIFT) | grp_base);
return 0;
}
int fman_kg_write_bind_cls_plans(struct fman_kg_regs *regs,
uint8_t hwport_id,
uint32_t bind_cls_plans)
{
struct fman_kg_pe_regs *kg_pe_regs;
uint32_t tmp_reg;
int err;
kg_pe_regs = (struct fman_kg_pe_regs *)&(regs->fmkg_indirect[0]);
iowrite32be(bind_cls_plans, &kg_pe_regs->fmkg_pe_cpp);
tmp_reg = build_ar_bind_cls_plan(hwport_id, TRUE);
err = fman_kg_write_ar_wait(regs, tmp_reg);
return err;
}

129
drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fman_prs.c Normal file
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/*
* Copyright 2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_fman_prs.h"
uint32_t fman_prs_get_err_event(struct fman_prs_regs *regs, uint32_t ev_mask)
{
return ioread32be(&regs->fmpr_perr) & ev_mask;
}
uint32_t fman_prs_get_err_ev_mask(struct fman_prs_regs *regs)
{
return ioread32be(&regs->fmpr_perer);
}
void fman_prs_ack_err_event(struct fman_prs_regs *regs, uint32_t event)
{
iowrite32be(event, &regs->fmpr_perr);
}
uint32_t fman_prs_get_expt_event(struct fman_prs_regs *regs, uint32_t ev_mask)
{
return ioread32be(&regs->fmpr_pevr) & ev_mask;
}
uint32_t fman_prs_get_expt_ev_mask(struct fman_prs_regs *regs)
{
return ioread32be(&regs->fmpr_pever);
}
void fman_prs_ack_expt_event(struct fman_prs_regs *regs, uint32_t event)
{
iowrite32be(event, &regs->fmpr_pevr);
}
void fman_prs_defconfig(struct fman_prs_cfg *cfg)
{
cfg->port_id_stat = 0;
cfg->max_prs_cyc_lim = DEFAULT_MAX_PRS_CYC_LIM;
cfg->prs_exceptions = 0x03000000;
}
int fman_prs_init(struct fman_prs_regs *regs, struct fman_prs_cfg *cfg)
{
uint32_t tmp;
iowrite32be(cfg->max_prs_cyc_lim, &regs->fmpr_rpclim);
iowrite32be((FM_PCD_PRS_SINGLE_ECC | FM_PCD_PRS_PORT_IDLE_STS),
&regs->fmpr_pevr);
if (cfg->prs_exceptions & FM_PCD_EX_PRS_SINGLE_ECC)
iowrite32be(FM_PCD_PRS_SINGLE_ECC, &regs->fmpr_pever);
else
iowrite32be(0, &regs->fmpr_pever);
iowrite32be(FM_PCD_PRS_DOUBLE_ECC, &regs->fmpr_perr);
tmp = 0;
if (cfg->prs_exceptions & FM_PCD_EX_PRS_DOUBLE_ECC)
tmp |= FM_PCD_PRS_DOUBLE_ECC;
iowrite32be(tmp, &regs->fmpr_perer);
iowrite32be(cfg->port_id_stat, &regs->fmpr_ppsc);
return 0;
}
void fman_prs_enable(struct fman_prs_regs *regs)
{
uint32_t tmp;
tmp = ioread32be(&regs->fmpr_rpimac) | FM_PCD_PRS_RPIMAC_EN;
iowrite32be(tmp, &regs->fmpr_rpimac);
}
void fman_prs_disable(struct fman_prs_regs *regs)
{
uint32_t tmp;
tmp = ioread32be(&regs->fmpr_rpimac) & ~FM_PCD_PRS_RPIMAC_EN;
iowrite32be(tmp, &regs->fmpr_rpimac);
}
int fman_prs_is_enabled(struct fman_prs_regs *regs)
{
return ioread32be(&regs->fmpr_rpimac) & FM_PCD_PRS_RPIMAC_EN;
}
void fman_prs_set_stst_port_msk(struct fman_prs_regs *regs, uint32_t pid_msk)
{
iowrite32be(pid_msk, &regs->fmpr_ppsc);
}
void fman_prs_set_stst(struct fman_prs_regs *regs, bool enable)
{
if (enable)
iowrite32be(FM_PCD_PRS_PPSC_ALL_PORTS, &regs->fmpr_ppsc);
else
iowrite32be(0, &regs->fmpr_ppsc);
}

15
drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Port/Makefile Normal file
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#
# Makefile for the Freescale Ethernet controllers
#
ccflags-y += -DVERSION=\"\"
#
#Include netcomm SW specific definitions
include $(srctree)/drivers/net/ethernet/freescale/sdk_fman/ncsw_config.mk
NCSW_FM_INC = $(srctree)/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/inc
ccflags-y += -I$(NCSW_FM_INC)
obj-y += fsl-ncsw-Pcd.o
fsl-ncsw-Pcd-objs := fm_port.o fm_port_im.o fman_port.o

6436
drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Port/fm_port.c Normal file
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File diff suppressed because it is too large Load Diff

999
drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Port/fm_port.h Normal file
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@ -0,0 +1,999 @@
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_port.h
@Description FM Port internal structures and definitions.
*//***************************************************************************/
#ifndef __FM_PORT_H
#define __FM_PORT_H
#include "error_ext.h"
#include "std_ext.h"
#include "fm_port_ext.h"
#include "fm_common.h"
#include "fm_sp_common.h"
#include "fsl_fman_sp.h"
#include "fm_port_ext.h"
#include "fsl_fman_port.h"
#define __ERR_MODULE__ MODULE_FM_PORT
#define MIN_EXT_BUF_SIZE 64
#define DATA_ALIGNMENT 64
#define MAX_LIODN_OFFSET 64
#define MAX_PORT_FIFO_SIZE MIN(BMI_MAX_FIFO_SIZE, 1024*BMI_FIFO_UNITS)
/**************************************************************************//**
@Description Memory Map defines
*//***************************************************************************/
#define BMI_PORT_REGS_OFFSET 0
#define QMI_PORT_REGS_OFFSET 0x400
#define PRS_PORT_REGS_OFFSET 0x800
/**************************************************************************//**
@Description defaults
*//***************************************************************************/
#define DEFAULT_PORT_deqHighPriority_1G FALSE
#define DEFAULT_PORT_deqHighPriority_10G TRUE
#define DEFAULT_PORT_deqType e_FM_PORT_DEQ_TYPE1
#define DEFAULT_PORT_deqPrefetchOption e_FM_PORT_DEQ_FULL_PREFETCH
#define DEFAULT_PORT_deqPrefetchOption_HC e_FM_PORT_DEQ_NO_PREFETCH
#define DEFAULT_PORT_deqByteCnt_10G 0x1400
#define DEFAULT_PORT_deqByteCnt_1G 0x400
#define DEFAULT_PORT_bufferPrefixContent_privDataSize DEFAULT_FM_SP_bufferPrefixContent_privDataSize
#define DEFAULT_PORT_bufferPrefixContent_passPrsResult DEFAULT_FM_SP_bufferPrefixContent_passPrsResult
#define DEFAULT_PORT_bufferPrefixContent_passTimeStamp DEFAULT_FM_SP_bufferPrefixContent_passTimeStamp
#define DEFAULT_PORT_bufferPrefixContent_allOtherPCDInfo DEFAULT_FM_SP_bufferPrefixContent_allOtherPCDInfo
#define DEFAULT_PORT_bufferPrefixContent_dataAlign DEFAULT_FM_SP_bufferPrefixContent_dataAlign
#define DEFAULT_PORT_cheksumLastBytesIgnore 0
#define DEFAULT_PORT_cutBytesFromEnd 4
#define DEFAULT_PORT_fifoDeqPipelineDepth_IM 2
#define DEFAULT_PORT_frmDiscardOverride FALSE
#define DEFAULT_PORT_dmaSwapData (e_FmDmaSwapOption)DEFAULT_FMAN_SP_DMA_SWAP_DATA
#define DEFAULT_PORT_dmaIntContextCacheAttr (e_FmDmaCacheOption)DEFAULT_FMAN_SP_DMA_INT_CONTEXT_CACHE_ATTR
#define DEFAULT_PORT_dmaHeaderCacheAttr (e_FmDmaCacheOption)DEFAULT_FMAN_SP_DMA_HEADER_CACHE_ATTR
#define DEFAULT_PORT_dmaScatterGatherCacheAttr (e_FmDmaCacheOption)DEFAULT_FMAN_SP_DMA_SCATTER_GATHER_CACHE_ATTR
#define DEFAULT_PORT_dmaWriteOptimize DEFAULT_FMAN_SP_DMA_WRITE_OPTIMIZE
#define DEFAULT_PORT_noScatherGather DEFAULT_FMAN_SP_NO_SCATTER_GATHER
#define DEFAULT_PORT_forwardIntContextReuse FALSE
#define DEFAULT_PORT_BufMargins_startMargins 32
#define DEFAULT_PORT_BufMargins_endMargins 0
#define DEFAULT_PORT_syncReq TRUE
#define DEFAULT_PORT_syncReqForHc FALSE
#define DEFAULT_PORT_color e_FM_PORT_COLOR_GREEN
#define DEFAULT_PORT_errorsToDiscard FM_PORT_FRM_ERR_CLS_DISCARD
/* #define DEFAULT_PORT_dualRateLimitScaleDown e_FM_PORT_DUAL_RATE_LIMITER_NONE */
/* #define DEFAULT_PORT_rateLimitBurstSizeHighGranularity FALSE */
#define DEFAULT_PORT_exception IM_EV_BSY
#define DEFAULT_PORT_maxFrameLength 9600
#define DEFAULT_notSupported 0xff
#if (DPAA_VERSION < 11)
#define DEFAULT_PORT_rxFifoPriElevationLevel MAX_PORT_FIFO_SIZE
#define DEFAULT_PORT_rxFifoThreshold (MAX_PORT_FIFO_SIZE*3/4)
#define DEFAULT_PORT_txFifoMinFillLevel 0
#define DEFAULT_PORT_txFifoLowComfLevel (5*KILOBYTE)
#define DEFAULT_PORT_fifoDeqPipelineDepth_1G 1
#define DEFAULT_PORT_fifoDeqPipelineDepth_10G 4
#define DEFAULT_PORT_fifoDeqPipelineDepth_OH 2
/* Host command port MUST NOT be changed to more than 1 !!! */
#define DEFAULT_PORT_numOfTasks(type) \
(uint32_t)((((type) == e_FM_PORT_TYPE_RX_10G) || \
((type) == e_FM_PORT_TYPE_TX_10G)) ? 16 : \
((((type) == e_FM_PORT_TYPE_RX) || \
((type) == e_FM_PORT_TYPE_TX) || \
((type) == e_FM_PORT_TYPE_OH_OFFLINE_PARSING)) ? 3 : 1))
#define DEFAULT_PORT_extraNumOfTasks(type) \
(uint32_t)(((type) == e_FM_PORT_TYPE_RX_10G) ? 8 : \
(((type) == e_FM_PORT_TYPE_RX) ? 2 : 0))
#define DEFAULT_PORT_numOfOpenDmas(type) \
(uint32_t)((((type) == e_FM_PORT_TYPE_TX_10G) || \
((type) == e_FM_PORT_TYPE_RX_10G)) ? 8 : 1 )
#define DEFAULT_PORT_extraNumOfOpenDmas(type) \
(uint32_t)(((type) == e_FM_PORT_TYPE_RX_10G) ? 8 : \
(((type) == e_FM_PORT_TYPE_RX) ? 1 : 0))
#define DEFAULT_PORT_numOfFifoBufs(type) \
(uint32_t)((((type) == e_FM_PORT_TYPE_RX_10G) || \
((type) == e_FM_PORT_TYPE_TX_10G)) ? 48 : \
((type) == e_FM_PORT_TYPE_RX) ? 45 : \
((type) == e_FM_PORT_TYPE_TX) ? 44 : 8)
#define DEFAULT_PORT_extraNumOfFifoBufs 0
#else /* (DPAA_VERSION < 11) */
/* Defaults are registers' reset values */
#define DEFAULT_PORT_rxFifoPriElevationLevel MAX_PORT_FIFO_SIZE
#define DEFAULT_PORT_rxFifoThreshold MAX_PORT_FIFO_SIZE
#define DEFAULT_PORT_txFifoMinFillLevel 0
#define DEFAULT_PORT_txFifoLowComfLevel (5 * KILOBYTE)
#define DEFAULT_PORT_fifoDeqPipelineDepth_1G 2
#define DEFAULT_PORT_fifoDeqPipelineDepth_10G 4
#define DEFAULT_PORT_fifoDeqPipelineDepth_OH 2
#define DEFAULT_PORT_numOfTasks(type) \
(uint32_t)((((type) == e_FM_PORT_TYPE_RX_10G) || \
((type) == e_FM_PORT_TYPE_TX_10G)) ? 14 : \
(((type) == e_FM_PORT_TYPE_RX) || \
((type) == e_FM_PORT_TYPE_TX)) ? 4 : \
((type) == e_FM_PORT_TYPE_OH_OFFLINE_PARSING) ? 6 : 1)
#define DEFAULT_PORT_extraNumOfTasks(type) 0
#define DEFAULT_PORT_numOfOpenDmas(type) \
(uint32_t)(((type) == e_FM_PORT_TYPE_RX_10G) ? 8 : \
((type) == e_FM_PORT_TYPE_TX_10G) ? 12 : \
((type) == e_FM_PORT_TYPE_RX) ? 2 : \
((type) == e_FM_PORT_TYPE_TX) ? 3 : \
((type) == e_FM_PORT_TYPE_OH_HOST_COMMAND) ? 2 : 4)
#define DEFAULT_PORT_extraNumOfOpenDmas(type) 0
#define DEFAULT_PORT_numOfFifoBufs(type) \
(uint32_t) (((type) == e_FM_PORT_TYPE_RX_10G) ? 96 : \
((type) == e_FM_PORT_TYPE_TX_10G) ? 64 : \
((type) == e_FM_PORT_TYPE_OH_HOST_COMMAND) ? 10 : 50)
#define DEFAULT_PORT_extraNumOfFifoBufs 0
#endif /* (DPAA_VERSION < 11) */
#define DEFAULT_PORT_txBdRingLength 16
#define DEFAULT_PORT_rxBdRingLength 128
#define DEFAULT_PORT_ImfwExtStructsMemId 0
#define DEFAULT_PORT_ImfwExtStructsMemAttr MEMORY_ATTR_CACHEABLE
#define FM_PORT_CG_REG_NUM(_cgId) (((FM_PORT_NUM_OF_CONGESTION_GRPS/32)-1)-_cgId/32)
/**************************************************************************//**
@Collection PCD Engines
*//***************************************************************************/
typedef uint32_t fmPcdEngines_t; /**< options as defined below: */
#define FM_PCD_NONE 0 /**< No PCD Engine indicated */
#define FM_PCD_PRS 0x80000000 /**< Parser indicated */
#define FM_PCD_KG 0x40000000 /**< Keygen indicated */
#define FM_PCD_CC 0x20000000 /**< Coarse classification indicated */
#define FM_PCD_PLCR 0x10000000 /**< Policer indicated */
#define FM_PCD_MANIP 0x08000000 /**< Manipulation indicated */
/* @} */
#define FM_PORT_MAX_NUM_OF_EXT_POOLS_ALL_INTEGRATIONS 8
#define FM_PORT_MAX_NUM_OF_CONGESTION_GRPS_ALL_INTEGRATIONS 256
#define FM_PORT_CG_REG_NUM(_cgId) (((FM_PORT_NUM_OF_CONGESTION_GRPS/32)-1)-_cgId/32)
#define FM_OH_PORT_ID 0
/***********************************************************************/
/* SW parser OFFLOAD labels (offsets) */
/***********************************************************************/
#if (DPAA_VERSION == 10)
#define OFFLOAD_SW_PATCH_IPv4_IPR_LABEL 0x300
#define OFFLOAD_SW_PATCH_IPv6_IPR_LABEL 0x325
#define OFFLOAD_SW_PATCH_IPv6_IPF_LABEL 0x325
#else
#define OFFLOAD_SW_PATCH_IPv4_IPR_LABEL 0x100
/* Will be used for:
* 1. identify fragments
* 2. udp-lite
*/
#define OFFLOAD_SW_PATCH_IPv6_IPR_LABEL 0x146
/* Will be used for:
* 1. will identify the fragmentable area
* 2. udp-lite
*/
#define OFFLOAD_SW_PATCH_IPv6_IPF_LABEL 0x261
#define OFFLOAD_SW_PATCH_CAPWAP_LABEL 0x38d
#endif /* (DPAA_VERSION == 10) */
#if ((DPAA_VERSION == 10) && defined(FM_CAPWAP_SUPPORT))
#define UDP_LITE_SW_PATCH_LABEL 0x2E0
#endif /* ((DPAA_VERSION == 10) && defined(FM_CAPWAP_SUPPORT)) */
/**************************************************************************//**
@Description Memory Mapped Registers
*//***************************************************************************/
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(push,1)
#endif /* defined(__MWERKS__) && ... */
typedef struct
{
volatile uint32_t fmbm_rcfg; /**< Rx Configuration */
volatile uint32_t fmbm_rst; /**< Rx Status */
volatile uint32_t fmbm_rda; /**< Rx DMA attributes*/
volatile uint32_t fmbm_rfp; /**< Rx FIFO Parameters*/
volatile uint32_t fmbm_rfed; /**< Rx Frame End Data*/
volatile uint32_t fmbm_ricp; /**< Rx Internal Context Parameters*/
volatile uint32_t fmbm_rim; /**< Rx Internal Buffer Margins*/
volatile uint32_t fmbm_rebm; /**< Rx External Buffer Margins*/
volatile uint32_t fmbm_rfne; /**< Rx Frame Next Engine*/
volatile uint32_t fmbm_rfca; /**< Rx Frame Command Attributes.*/
volatile uint32_t fmbm_rfpne; /**< Rx Frame Parser Next Engine*/
volatile uint32_t fmbm_rpso; /**< Rx Parse Start Offset*/
volatile uint32_t fmbm_rpp; /**< Rx Policer Profile */
volatile uint32_t fmbm_rccb; /**< Rx Coarse Classification Base */
volatile uint32_t fmbm_reth; /**< Rx Excessive Threshold */
volatile uint32_t reserved1[0x01];/**< (0x03C) */
volatile uint32_t fmbm_rprai[FM_PORT_PRS_RESULT_NUM_OF_WORDS];
/**< Rx Parse Results Array Initialization*/
volatile uint32_t fmbm_rfqid; /**< Rx Frame Queue ID*/
volatile uint32_t fmbm_refqid; /**< Rx Error Frame Queue ID*/
volatile uint32_t fmbm_rfsdm; /**< Rx Frame Status Discard Mask*/
volatile uint32_t fmbm_rfsem; /**< Rx Frame Status Error Mask*/
volatile uint32_t fmbm_rfene; /**< Rx Frame Enqueue Next Engine */
volatile uint32_t reserved2[0x02];/**< (0x074-0x078) */
volatile uint32_t fmbm_rcmne; /**< Rx Frame Continuous Mode Next Engine */
volatile uint32_t reserved3[0x20];/**< (0x080 0x0FF) */
volatile uint32_t fmbm_ebmpi[FM_PORT_MAX_NUM_OF_EXT_POOLS_ALL_INTEGRATIONS];
/**< Buffer Manager pool Information-*/
volatile uint32_t fmbm_acnt[FM_PORT_MAX_NUM_OF_EXT_POOLS_ALL_INTEGRATIONS];
/**< Allocate Counter-*/
volatile uint32_t reserved4[0x08];
/**< 0x130/0x140 - 0x15F reserved -*/
volatile uint32_t fmbm_rcgm[FM_PORT_MAX_NUM_OF_CONGESTION_GRPS_ALL_INTEGRATIONS/32];
/**< Congestion Group Map*/
volatile uint32_t fmbm_rmpd; /**< BM Pool Depletion */
volatile uint32_t reserved5[0x1F];/**< (0x184 0x1FF) */
volatile uint32_t fmbm_rstc; /**< Rx Statistics Counters*/
volatile uint32_t fmbm_rfrc; /**< Rx Frame Counter*/
volatile uint32_t fmbm_rfbc; /**< Rx Bad Frames Counter*/
volatile uint32_t fmbm_rlfc; /**< Rx Large Frames Counter*/
volatile uint32_t fmbm_rffc; /**< Rx Filter Frames Counter*/
volatile uint32_t fmbm_rfcd; /**< Rx Frame Discard Counter*/
volatile uint32_t fmbm_rfldec; /**< Rx Frames List DMA Error Counter*/
volatile uint32_t fmbm_rodc; /**< Rx Out of Buffers Discard Counter-*/
volatile uint32_t fmbm_rbdc; /**< Rx Buffers Deallocate Counter-*/
volatile uint32_t fmbm_rpec; /**< Rx RX Prepare to enqueue Counter-*/
volatile uint32_t reserved6[0x16];/**< (0x228 0x27F) */
volatile uint32_t fmbm_rpc; /**< Rx Performance Counters*/
volatile uint32_t fmbm_rpcp; /**< Rx Performance Count Parameters*/
volatile uint32_t fmbm_rccn; /**< Rx Cycle Counter*/
volatile uint32_t fmbm_rtuc; /**< Rx Tasks Utilization Counter*/
volatile uint32_t fmbm_rrquc; /**< Rx Receive Queue Utilization Counter*/
volatile uint32_t fmbm_rduc; /**< Rx DMA Utilization Counter*/
volatile uint32_t fmbm_rfuc; /**< Rx FIFO Utilization Counter*/
volatile uint32_t fmbm_rpac; /**< Rx Pause Activation Counter*/
volatile uint32_t reserved7[0x18];/**< (0x2A0-0x2FF) */
volatile uint32_t fmbm_rdcfg[0x3];/**< Rx Debug-*/
volatile uint32_t fmbm_rgpr; /**< Rx General Purpose Register. */
volatile uint32_t reserved8[0x3a];/**< (0x310-0x3FF) */
} t_FmPortRxBmiRegs;
typedef struct
{
volatile uint32_t fmbm_tcfg; /**< Tx Configuration */
volatile uint32_t fmbm_tst; /**< Tx Status */
volatile uint32_t fmbm_tda; /**< Tx DMA attributes */
volatile uint32_t fmbm_tfp; /**< Tx FIFO Parameters */
volatile uint32_t fmbm_tfed; /**< Tx Frame End Data */
volatile uint32_t fmbm_ticp; /**< Tx Internal Context Parameters */
volatile uint32_t fmbm_tfdne; /**< Tx Frame Dequeue Next Engine. */
volatile uint32_t fmbm_tfca; /**< Tx Frame Command attribute. */
volatile uint32_t fmbm_tcfqid; /**< Tx Confirmation Frame Queue ID. */
volatile uint32_t fmbm_tfeqid; /**< Tx Frame Error Queue ID */
volatile uint32_t fmbm_tfene; /**< Tx Frame Enqueue Next Engine */
volatile uint32_t fmbm_trlmts; /**< Tx Rate Limiter Scale */
volatile uint32_t fmbm_trlmt; /**< Tx Rate Limiter */
volatile uint32_t fmbm_tccb; /**< Tx Coarse Classification Base */
volatile uint32_t reserved0[0x0e];/**< (0x038-0x070) */
volatile uint32_t fmbm_tfne; /**< Tx Frame Next Engine */
volatile uint32_t fmbm_tpfcm[0x02];/**< Tx Priority based Flow Control (PFC) Mapping */
volatile uint32_t fmbm_tcmne; /**< Tx Frame Continuous Mode Next Engine */
volatile uint32_t reserved2[0x60];/**< (0x080-0x200) */
volatile uint32_t fmbm_tstc; /**< Tx Statistics Counters */
volatile uint32_t fmbm_tfrc; /**< Tx Frame Counter */
volatile uint32_t fmbm_tfdc; /**< Tx Frames Discard Counter */
volatile uint32_t fmbm_tfledc; /**< Tx Frame Length error discard counter */
volatile uint32_t fmbm_tfufdc; /**< Tx Frame unsupported format discard Counter */
volatile uint32_t fmbm_tbdc; /**< Tx Buffers Deallocate Counter */
volatile uint32_t reserved3[0x1A];/**< (0x218-0x280) */
volatile uint32_t fmbm_tpc; /**< Tx Performance Counters*/
volatile uint32_t fmbm_tpcp; /**< Tx Performance Count Parameters*/
volatile uint32_t fmbm_tccn; /**< Tx Cycle Counter*/
volatile uint32_t fmbm_ttuc; /**< Tx Tasks Utilization Counter*/
volatile uint32_t fmbm_ttcquc; /**< Tx Transmit Confirm Queue Utilization Counter*/
volatile uint32_t fmbm_tduc; /**< Tx DMA Utilization Counter*/
volatile uint32_t fmbm_tfuc; /**< Tx FIFO Utilization Counter*/
volatile uint32_t reserved4[16]; /**< (0x29C-0x2FF) */
volatile uint32_t fmbm_tdcfg[0x3];/**< Tx Debug-*/
volatile uint32_t fmbm_tgpr; /**< O/H General Purpose Register */
volatile uint32_t reserved5[0x3a];/**< (0x310-0x3FF) */
} t_FmPortTxBmiRegs;
typedef struct
{
volatile uint32_t fmbm_ocfg; /**< O/H Configuration */
volatile uint32_t fmbm_ost; /**< O/H Status */
volatile uint32_t fmbm_oda; /**< O/H DMA attributes */
volatile uint32_t fmbm_oicp; /**< O/H Internal Context Parameters */
volatile uint32_t fmbm_ofdne; /**< O/H Frame Dequeue Next Engine */
volatile uint32_t fmbm_ofne; /**< O/H Frame Next Engine */
volatile uint32_t fmbm_ofca; /**< O/H Frame Command Attributes. */
volatile uint32_t fmbm_ofpne; /**< O/H Frame Parser Next Engine */
volatile uint32_t fmbm_opso; /**< O/H Parse Start Offset */
volatile uint32_t fmbm_opp; /**< O/H Policer Profile */
volatile uint32_t fmbm_occb; /**< O/H Coarse Classification base */
volatile uint32_t fmbm_oim; /**< O/H Internal margins*/
volatile uint32_t fmbm_ofp; /**< O/H Fifo Parameters*/
volatile uint32_t fmbm_ofed; /**< O/H Frame End Data*/
volatile uint32_t reserved0[2]; /**< (0x038 - 0x03F) */
volatile uint32_t fmbm_oprai[FM_PORT_PRS_RESULT_NUM_OF_WORDS];
/**< O/H Parse Results Array Initialization */
volatile uint32_t fmbm_ofqid; /**< O/H Frame Queue ID */
volatile uint32_t fmbm_oefqid; /**< O/H Error Frame Queue ID */
volatile uint32_t fmbm_ofsdm; /**< O/H Frame Status Discard Mask */
volatile uint32_t fmbm_ofsem; /**< O/H Frame Status Error Mask */
volatile uint32_t fmbm_ofene; /**< O/H Frame Enqueue Next Engine */
volatile uint32_t fmbm_orlmts; /**< O/H Rate Limiter Scale */
volatile uint32_t fmbm_orlmt; /**< O/H Rate Limiter */
volatile uint32_t fmbm_ocmne; /**< O/H Continuous Mode Next Engine */
volatile uint32_t reserved1[0x20];/**< (0x080 - 0x0FF) */
volatile uint32_t fmbm_oebmpi[2]; /**< Buffer Manager Observed Pool Information */
volatile uint32_t reserved2[0x16];/**< (0x108 - 0x15F) */
volatile uint32_t fmbm_ocgm; /**< Observed Congestion Group Map */
volatile uint32_t reserved3[0x7]; /**< (0x164 - 0x17F) */
volatile uint32_t fmbm_ompd; /**< Observed BMan Pool Depletion */
volatile uint32_t reserved4[0x1F];/**< (0x184 - 0x1FF) */
volatile uint32_t fmbm_ostc; /**< O/H Statistics Counters */
volatile uint32_t fmbm_ofrc; /**< O/H Frame Counter */
volatile uint32_t fmbm_ofdc; /**< O/H Frames Discard Counter */
volatile uint32_t fmbm_ofledc; /**< O/H Frames Length Error Discard Counter */
volatile uint32_t fmbm_ofufdc; /**< O/H Frames Unsupported Format Discard Counter */
volatile uint32_t fmbm_offc; /**< O/H Filter Frames Counter */
volatile uint32_t fmbm_ofwdc; /**< - Rx Frames WRED Discard Counter */
volatile uint32_t fmbm_ofldec; /**< O/H Frames List DMA Error Counter */
volatile uint32_t fmbm_obdc; /**< O/H Buffers Deallocate Counter */
volatile uint32_t fmbm_oodc; /**< O/H Out of Buffers Discard Counter */
volatile uint32_t fmbm_opec; /**< O/H Prepare to enqueue Counter */
volatile uint32_t reserved5[0x15];/**< ( - 0x27F) */
volatile uint32_t fmbm_opc; /**< O/H Performance Counters */
volatile uint32_t fmbm_opcp; /**< O/H Performance Count Parameters */
volatile uint32_t fmbm_occn; /**< O/H Cycle Counter */
volatile uint32_t fmbm_otuc; /**< O/H Tasks Utilization Counter */
volatile uint32_t fmbm_oduc; /**< O/H DMA Utilization Counter */
volatile uint32_t fmbm_ofuc; /**< O/H FIFO Utilization Counter */
volatile uint32_t reserved6[26]; /**< (0x298-0x2FF) */
volatile uint32_t fmbm_odcfg[0x3];/**< O/H Debug (only 1 in P1023) */
volatile uint32_t fmbm_ogpr; /**< O/H General Purpose Register. */
volatile uint32_t reserved7[0x3a];/**< (0x310 0x3FF) */
} t_FmPortOhBmiRegs;
typedef union
{
t_FmPortRxBmiRegs rxPortBmiRegs;
t_FmPortTxBmiRegs txPortBmiRegs;
t_FmPortOhBmiRegs ohPortBmiRegs;
} u_FmPortBmiRegs;
typedef struct
{
volatile uint32_t reserved1[2]; /**< 0xn024 - 0x02B */
volatile uint32_t fmqm_pndn; /**< PortID n Dequeue NIA Register */
volatile uint32_t fmqm_pndc; /**< PortID n Dequeue Config Register */
volatile uint32_t fmqm_pndtfc; /**< PortID n Dequeue Total Frame Counter */
volatile uint32_t fmqm_pndfdc; /**< PortID n Dequeue FQID from Default Counter */
volatile uint32_t fmqm_pndcc; /**< PortID n Dequeue Confirm Counter */
} t_FmPortNonRxQmiRegs;
typedef struct
{
volatile uint32_t fmqm_pnc; /**< PortID n Configuration Register */
volatile uint32_t fmqm_pns; /**< PortID n Status Register */
volatile uint32_t fmqm_pnts; /**< PortID n Task Status Register */
volatile uint32_t reserved0[4]; /**< 0xn00C - 0xn01B */
volatile uint32_t fmqm_pnen; /**< PortID n Enqueue NIA Register */
volatile uint32_t fmqm_pnetfc; /**< PortID n Enqueue Total Frame Counter */
t_FmPortNonRxQmiRegs nonRxQmiRegs; /**< Registers for Tx Hc & Op ports */
} t_FmPortQmiRegs;
typedef struct
{
struct
{
volatile uint32_t softSeqAttach; /**< Soft Sequence Attachment */
volatile uint32_t lcv; /**< Line-up Enable Confirmation Mask */
} hdrs[FM_PCD_PRS_NUM_OF_HDRS];
volatile uint32_t reserved0[0xde];
volatile uint32_t pcac; /**< Parse Internal Memory Configuration Access Control Register */
volatile uint32_t pctpid; /**< Parse Internal Memory Configured TPID Register */
} t_FmPortPrsRegs;
/**************************************************************************//*
@Description Basic buffer descriptor (BD) structure
*//***************************************************************************/
typedef _Packed struct
{
volatile uint16_t status;
volatile uint16_t length;
volatile uint8_t reserved0[0x6];
volatile uint8_t reserved1[0x1];
volatile t_FmPhysAddr buff;
} _PackedType t_FmImBd;
typedef _Packed struct
{
volatile uint16_t gen; /**< tbd */
volatile uint8_t reserved0[0x1];
volatile t_FmPhysAddr bdRingBase; /**< tbd */
volatile uint16_t bdRingSize; /**< tbd */
volatile uint16_t offsetIn; /**< tbd */
volatile uint16_t offsetOut; /**< tbd */
volatile uint8_t reserved1[0x12]; /**< 0x0e - 0x1f */
} _PackedType t_FmPortImQd;
typedef _Packed struct
{
volatile uint32_t mode; /**< Mode register */
volatile uint32_t rxQdPtr; /**< tbd */
volatile uint32_t txQdPtr; /**< tbd */
volatile uint16_t mrblr; /**< tbd */
volatile uint16_t rxQdBsyCnt; /**< tbd */
volatile uint8_t reserved0[0x10]; /**< 0x10 - 0x1f */
t_FmPortImQd rxQd;
t_FmPortImQd txQd;
volatile uint8_t reserved1[0xa0]; /**< 0x60 - 0xff */
} _PackedType t_FmPortImPram;
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(pop)
#endif /* defined(__MWERKS__) && ... */
/**************************************************************************//**
@Description Registers bit fields
*//***************************************************************************/
/**************************************************************************//**
@Description BMI defines
*//***************************************************************************/
#if (DPAA_VERSION >= 11)
#define BMI_SP_ID_MASK 0xff000000
#define BMI_SP_ID_SHIFT 24
#define BMI_SP_EN 0x01000000
#endif /* (DPAA_VERSION >= 11) */
#define BMI_PORT_CFG_EN 0x80000000
#define BMI_PORT_CFG_EN_MACSEC 0x00800000
#define BMI_PORT_CFG_FDOVR 0x02000000
#define BMI_PORT_CFG_IM 0x01000000
#define BMI_PORT_CFG_AM 0x00000040
#define BMI_PORT_STATUS_BSY 0x80000000
#define BMI_COUNTERS_EN 0x80000000
#define BMI_PORT_RFNE_FRWD_DCL4C 0x10000000
#define BMI_PORT_RFNE_FRWD_RPD 0x40000000
#define BMI_RFNE_FDCS_MASK 0xFF000000
#define BMI_RFNE_HXS_MASK 0x000000FF
#define BMI_CMD_MR_LEAC 0x00200000
#define BMI_CMD_MR_SLEAC 0x00100000
#define BMI_CMD_MR_MA 0x00080000
#define BMI_CMD_MR_DEAS 0x00040000
#define BMI_CMD_RX_MR_DEF (BMI_CMD_MR_LEAC | \
BMI_CMD_MR_SLEAC | \
BMI_CMD_MR_MA | \
BMI_CMD_MR_DEAS)
#define BMI_CMD_ATTR_ORDER 0x80000000
#define BMI_CMD_ATTR_SYNC 0x02000000
#define BMI_CMD_ATTR_MODE_MISS_ALLIGN_ADDR_EN 0x00080000
#define BMI_CMD_ATTR_MACCMD_MASK 0x0000ff00
#define BMI_CMD_ATTR_MACCMD_OVERRIDE 0x00008000
#define BMI_CMD_ATTR_MACCMD_SECURED 0x00001000
#define BMI_CMD_ATTR_MACCMD_SC_MASK 0x00000f00
#define BMI_EXT_BUF_POOL_ID_MASK 0x003F0000
#define BMI_STATUS_RX_MASK_UNUSED (uint32_t)(~(FM_PORT_FRM_ERR_DMA | \
FM_PORT_FRM_ERR_PHYSICAL | \
FM_PORT_FRM_ERR_SIZE | \
FM_PORT_FRM_ERR_CLS_DISCARD | \
FM_PORT_FRM_ERR_EXTRACTION | \
FM_PORT_FRM_ERR_NO_SCHEME | \
FM_PORT_FRM_ERR_COLOR_RED | \
FM_PORT_FRM_ERR_COLOR_YELLOW | \
FM_PORT_FRM_ERR_ILL_PLCR | \
FM_PORT_FRM_ERR_PLCR_FRAME_LEN | \
FM_PORT_FRM_ERR_PRS_TIMEOUT | \
FM_PORT_FRM_ERR_PRS_ILL_INSTRUCT | \
FM_PORT_FRM_ERR_BLOCK_LIMIT_EXCEEDED | \
FM_PORT_FRM_ERR_PRS_HDR_ERR | \
FM_PORT_FRM_ERR_IPRE | \
FM_PORT_FRM_ERR_IPR_NCSP | \
FM_PORT_FRM_ERR_KEYSIZE_OVERFLOW))
#define BMI_STATUS_OP_MASK_UNUSED (uint32_t)(BMI_STATUS_RX_MASK_UNUSED & \
~(FM_PORT_FRM_ERR_LENGTH | \
FM_PORT_FRM_ERR_NON_FM | \
FM_PORT_FRM_ERR_UNSUPPORTED_FORMAT))
#define BMI_RATE_LIMIT_EN 0x80000000
#define BMI_RATE_LIMIT_BURST_SIZE_GRAN 0x80000000
#define BMI_RATE_LIMIT_SCALE_BY_2 0x00000001
#define BMI_RATE_LIMIT_SCALE_BY_4 0x00000002
#define BMI_RATE_LIMIT_SCALE_BY_8 0x00000003
#define BMI_RX_FIFO_THRESHOLD_BC 0x80000000
#define BMI_PRS_RESULT_HIGH 0x00000000
#define BMI_PRS_RESULT_LOW 0xFFFFFFFF
#define RX_ERRS_TO_ENQ (FM_PORT_FRM_ERR_DMA | \
FM_PORT_FRM_ERR_PHYSICAL | \
FM_PORT_FRM_ERR_SIZE | \
FM_PORT_FRM_ERR_EXTRACTION | \
FM_PORT_FRM_ERR_NO_SCHEME | \
FM_PORT_FRM_ERR_ILL_PLCR | \
FM_PORT_FRM_ERR_PLCR_FRAME_LEN | \
FM_PORT_FRM_ERR_PRS_TIMEOUT | \
FM_PORT_FRM_ERR_PRS_ILL_INSTRUCT | \
FM_PORT_FRM_ERR_BLOCK_LIMIT_EXCEEDED | \
FM_PORT_FRM_ERR_PRS_HDR_ERR | \
FM_PORT_FRM_ERR_KEYSIZE_OVERFLOW | \
FM_PORT_FRM_ERR_IPRE)
#define OP_ERRS_TO_ENQ (RX_ERRS_TO_ENQ | \
FM_PORT_FRM_ERR_LENGTH | \
FM_PORT_FRM_ERR_NON_FM | \
FM_PORT_FRM_ERR_UNSUPPORTED_FORMAT)
#define BMI_RX_FIFO_PRI_ELEVATION_MASK 0x03FF0000
#define BMI_RX_FIFO_THRESHOLD_MASK 0x000003FF
#define BMI_TX_FIFO_MIN_FILL_MASK 0x03FF0000
#define BMI_FIFO_PIPELINE_DEPTH_MASK 0x0000F000
#define BMI_TX_LOW_COMF_MASK 0x000003FF
/* shifts */
#define BMI_PORT_CFG_MS_SEL_SHIFT 16
#define BMI_DMA_ATTR_IC_CACHE_SHIFT FMAN_SP_DMA_ATTR_IC_CACHE_SHIFT
#define BMI_DMA_ATTR_HDR_CACHE_SHIFT FMAN_SP_DMA_ATTR_HDR_CACHE_SHIFT
#define BMI_DMA_ATTR_SG_CACHE_SHIFT FMAN_SP_DMA_ATTR_SG_CACHE_SHIFT
#define BMI_IM_FOF_SHIFT 28
#define BMI_PR_PORTID_SHIFT 24
#define BMI_RX_FIFO_PRI_ELEVATION_SHIFT 16
#define BMI_RX_FIFO_THRESHOLD_SHIFT 0
#define BMI_RX_FRAME_END_CS_IGNORE_SHIFT 24
#define BMI_RX_FRAME_END_CUT_SHIFT 16
#define BMI_IC_SIZE_SHIFT FMAN_SP_IC_SIZE_SHIFT
#define BMI_INT_BUF_MARG_SHIFT 28
#define BMI_EXT_BUF_MARG_END_SHIFT FMAN_SP_EXT_BUF_MARG_END_SHIFT
#define BMI_CMD_ATTR_COLOR_SHIFT 26
#define BMI_CMD_ATTR_COM_MODE_SHIFT 16
#define BMI_CMD_ATTR_MACCMD_SHIFT 8
#define BMI_CMD_ATTR_MACCMD_OVERRIDE_SHIFT 15
#define BMI_CMD_ATTR_MACCMD_SECURED_SHIFT 12
#define BMI_CMD_ATTR_MACCMD_SC_SHIFT 8
#define BMI_POOL_DEP_NUM_OF_POOLS_VECTOR_SHIFT 24
#define BMI_TX_FIFO_MIN_FILL_SHIFT 16
#define BMI_TX_LOW_COMF_SHIFT 0
#define BMI_PERFORMANCE_TASK_COMP_SHIFT 24
#define BMI_PERFORMANCE_PORT_COMP_SHIFT 16
#define BMI_PERFORMANCE_DMA_COMP_SHIFT 12
#define BMI_PERFORMANCE_FIFO_COMP_SHIFT 0
#define BMI_MAX_BURST_SHIFT 16
#define BMI_COUNT_RATE_UNIT_SHIFT 16
/* sizes */
#define FRAME_END_DATA_SIZE 16
#define FRAME_OFFSET_UNITS 16
#define MIN_TX_INT_OFFSET 16
#define MAX_FRAME_OFFSET 64
#define MAX_FIFO_PIPELINE_DEPTH 8
#define MAX_PERFORMANCE_TASK_COMP 64
#define MAX_PERFORMANCE_TX_QUEUE_COMP 8
#define MAX_PERFORMANCE_RX_QUEUE_COMP 64
#define MAX_PERFORMANCE_DMA_COMP 16
#define MAX_NUM_OF_TASKS 64
#define MAX_NUM_OF_EXTRA_TASKS 8
#define MAX_NUM_OF_DMAS 16
#define MAX_NUM_OF_EXTRA_DMAS 8
#define MAX_BURST_SIZE 1024
#define MIN_NUM_OF_OP_DMAS 2
/**************************************************************************//**
@Description QMI defines
*//***************************************************************************/
/* masks */
#define QMI_PORT_CFG_EN 0x80000000
#define QMI_PORT_CFG_EN_COUNTERS 0x10000000
#define QMI_PORT_STATUS_DEQ_TNUM_BSY 0x80000000
#define QMI_PORT_STATUS_DEQ_FD_BSY 0x20000000
#define QMI_DEQ_CFG_PREFETCH_NO_TNUM 0x02000000
#define QMI_DEQ_CFG_PREFETCH_WAITING_TNUM 0
#define QMI_DEQ_CFG_PREFETCH_1_FRAME 0
#define QMI_DEQ_CFG_PREFETCH_3_FRAMES 0x01000000
#define QMI_DEQ_CFG_PRI 0x80000000
#define QMI_DEQ_CFG_TYPE1 0x10000000
#define QMI_DEQ_CFG_TYPE2 0x20000000
#define QMI_DEQ_CFG_TYPE3 0x30000000
#define QMI_DEQ_CFG_SUBPORTAL_MASK 0x1f
#define QMI_DEQ_CFG_SUBPORTAL_SHIFT 20
/**************************************************************************//**
@Description PARSER defines
*//***************************************************************************/
/* masks */
#define PRS_HDR_ERROR_DIS 0x00000800
#define PRS_HDR_SW_PRS_EN 0x00000400
#define PRS_CP_OFFSET_MASK 0x0000000F
#define PRS_TPID1_MASK 0xFFFF0000
#define PRS_TPID2_MASK 0x0000FFFF
#define PRS_TPID_DFLT 0x91009100
#define PRS_HDR_MPLS_LBL_INTER_EN 0x00200000
#define PRS_HDR_IPV6_ROUTE_HDR_EN 0x00008000
#define PRS_HDR_PPPOE_MTU_CHECK_EN 0x80000000
#define PRS_HDR_UDP_PAD_REMOVAL 0x80000000
#define PRS_HDR_TCP_PAD_REMOVAL 0x80000000
#define PRS_CAC_STOP 0x00000001
#define PRS_CAC_ACTIVE 0x00000100
/* shifts */
#define PRS_PCTPID_SHIFT 16
#define PRS_HDR_MPLS_NEXT_HDR_SHIFT 22
#define PRS_HDR_ETH_BC_SHIFT 28
#define PRS_HDR_ETH_MC_SHIFT 24
#define PRS_HDR_VLAN_STACKED_SHIFT 16
#define PRS_HDR_MPLS_STACKED_SHIFT 16
#define PRS_HDR_IPV4_1_BC_SHIFT 28
#define PRS_HDR_IPV4_1_MC_SHIFT 24
#define PRS_HDR_IPV4_2_UC_SHIFT 20
#define PRS_HDR_IPV4_2_MC_BC_SHIFT 16
#define PRS_HDR_IPV6_1_MC_SHIFT 24
#define PRS_HDR_IPV6_2_UC_SHIFT 20
#define PRS_HDR_IPV6_2_MC_SHIFT 16
#define PRS_HDR_ETH_BC_MASK 0x0fffffff
#define PRS_HDR_ETH_MC_MASK 0xf0ffffff
#define PRS_HDR_VLAN_STACKED_MASK 0xfff0ffff
#define PRS_HDR_MPLS_STACKED_MASK 0xfff0ffff
#define PRS_HDR_IPV4_1_BC_MASK 0x0fffffff
#define PRS_HDR_IPV4_1_MC_MASK 0xf0ffffff
#define PRS_HDR_IPV4_2_UC_MASK 0xff0fffff
#define PRS_HDR_IPV4_2_MC_BC_MASK 0xfff0ffff
#define PRS_HDR_IPV6_1_MC_MASK 0xf0ffffff
#define PRS_HDR_IPV6_2_UC_MASK 0xff0fffff
#define PRS_HDR_IPV6_2_MC_MASK 0xfff0ffff
/* others */
#define PRS_HDR_ENTRY_SIZE 8
#define DEFAULT_CLS_PLAN_VECTOR 0xFFFFFFFF
#define IPSEC_SW_PATCH_START 0x20
#define SCTP_SW_PATCH_START 0x4D
#define DCCP_SW_PATCH_START 0x41
/**************************************************************************//**
@Description IM defines
*//***************************************************************************/
#define BD_R_E 0x80000000
#define BD_L 0x08000000
#define BD_RX_CRE 0x00080000
#define BD_RX_FTL 0x00040000
#define BD_RX_FTS 0x00020000
#define BD_RX_OV 0x00010000
#define BD_RX_ERRORS (BD_RX_CRE | BD_RX_FTL | BD_RX_FTS | BD_RX_OV)
#define FM_IM_SIZEOF_BD sizeof(t_FmImBd)
#define BD_STATUS_MASK 0xffff0000
#define BD_LENGTH_MASK 0x0000ffff
#define BD_STATUS_AND_LENGTH_SET(bd, val) WRITE_UINT32(*(volatile uint32_t*)(bd), (val))
#define BD_STATUS_AND_LENGTH(bd) GET_UINT32(*(volatile uint32_t*)(bd))
#define BD_GET(id) &p_FmPort->im.p_BdRing[id]
#define IM_ILEGAL_BD_ID 0xffff
/* others */
#define IM_PRAM_ALIGN 0x100
/* masks */
#define IM_MODE_GBL 0x20000000
#define IM_MODE_BO_MASK 0x18000000
#define IM_MODE_BO_SHIFT 3
#define IM_MODE_GRC_STP 0x00800000
#define IM_MODE_SET_BO(val) (uint32_t)((val << (31-IM_MODE_BO_SHIFT)) & IM_MODE_BO_MASK)
#define IM_RXQD_BSYINTM 0x0008
#define IM_RXQD_RXFINTM 0x0010
#define IM_RXQD_FPMEVT_SEL_MASK 0x0003
#define IM_EV_BSY 0x40000000
#define IM_EV_RX 0x80000000
/**************************************************************************//**
@Description Additional defines
*//***************************************************************************/
typedef struct {
t_Handle h_FmMuram;
t_FmPortImPram *p_FmPortImPram;
uint8_t fwExtStructsMemId;
uint32_t fwExtStructsMemAttr;
uint16_t bdRingSize;
t_FmImBd *p_BdRing;
t_Handle *p_BdShadow;
uint16_t currBdId;
uint16_t firstBdOfFrameId;
/* Rx port parameters */
uint8_t dataMemId; /**< Memory partition ID for data buffers */
uint32_t dataMemAttributes; /**< Memory attributes for data buffers */
t_BufferPoolInfo rxPool;
uint16_t mrblr;
uint16_t rxFrameAccumLength;
t_FmPortImRxStoreCallback *f_RxStore;
/* Tx port parameters */
uint32_t txFirstBdStatus;
t_FmPortImTxConfCallback *f_TxConf;
} t_FmMacIm;
typedef struct {
struct fman_port_cfg dfltCfg;
uint32_t dfltFqid;
uint32_t confFqid;
uint32_t errFqid;
uintptr_t baseAddr;
uint8_t deqSubPortal;
bool deqHighPriority;
e_FmPortDeqType deqType;
e_FmPortDeqPrefetchOption deqPrefetchOption;
uint16_t deqByteCnt;
uint8_t cheksumLastBytesIgnore;
uint8_t cutBytesFromEnd;
t_FmBufPoolDepletion bufPoolDepletion;
uint8_t pipelineDepth;
uint16_t fifoLowComfLevel;
bool frmDiscardOverride;
bool enRateLimit;
t_FmPortRateLimit rateLimit;
e_FmPortDualRateLimiterScaleDown rateLimitDivider;
bool enBufPoolDepletion;
uint16_t liodnOffset;
uint16_t liodnBase;
t_FmExtPools extBufPools;
e_FmDmaSwapOption dmaSwapData;
e_FmDmaCacheOption dmaIntContextCacheAttr;
e_FmDmaCacheOption dmaHeaderCacheAttr;
e_FmDmaCacheOption dmaScatterGatherCacheAttr;
bool dmaReadOptimize;
bool dmaWriteOptimize;
uint32_t txFifoMinFillLevel;
uint32_t txFifoLowComfLevel;
uint32_t rxFifoPriElevationLevel;
uint32_t rxFifoThreshold;
t_FmSpBufMargins bufMargins;
t_FmSpIntContextDataCopy intContext;
bool syncReq;
e_FmPortColor color;
fmPortFrameErrSelect_t errorsToDiscard;
fmPortFrameErrSelect_t errorsToEnq;
bool forwardReuseIntContext;
t_FmBufferPrefixContent bufferPrefixContent;
t_FmBackupBmPools *p_BackupBmPools;
bool dontReleaseBuf;
bool setNumOfTasks;
bool setNumOfOpenDmas;
bool setSizeOfFifo;
#if (DPAA_VERSION >= 11)
bool noScatherGather;
#endif /* (DPAA_VERSION >= 11) */
#ifdef FM_HEAVY_TRAFFIC_HANG_ERRATA_FMAN_A005669
bool bcbWorkaround;
#endif /* FM_HEAVY_TRAFFIC_HANG_ERRATA_FMAN_A005669 */
} t_FmPortDriverParam;
typedef struct t_FmPortRxPoolsParams
{
uint8_t numOfPools;
uint16_t secondLargestBufSize;
uint16_t largestBufSize;
} t_FmPortRxPoolsParams;
typedef struct t_FmPortDsarVars {
t_Handle *autoResOffsets;
t_FmPortDsarTablesSizes *autoResMaxSizes;
uint32_t fmbm_tcfg;
uint32_t fmbm_tcmne;
uint32_t fmbm_rfne;
uint32_t fmbm_rfpne;
uint32_t fmbm_rcfg;
bool dsarEnabledParser;
} t_FmPortDsarVars;
typedef struct {
struct fman_port port;
t_Handle h_Fm;
t_Handle h_FmPcd;
t_Handle h_FmMuram;
t_FmRevisionInfo fmRevInfo;
uint8_t portId;
e_FmPortType portType;
int enabled;
char name[MODULE_NAME_SIZE];
uint8_t hardwarePortId;
uint16_t fmClkFreq;
t_FmPortQmiRegs *p_FmPortQmiRegs;
u_FmPortBmiRegs *p_FmPortBmiRegs;
t_FmPortPrsRegs *p_FmPortPrsRegs;
fmPcdEngines_t pcdEngines;
uint32_t savedBmiNia;
uint8_t netEnvId;
uint32_t optArray[FM_PCD_MAX_NUM_OF_OPTIONS(FM_PCD_MAX_NUM_OF_CLS_PLANS)];
uint32_t lcvs[FM_PCD_PRS_NUM_OF_HDRS];
uint8_t privateInfo;
uint32_t schemesPerPortVector;
bool useClsPlan;
uint8_t clsPlanGrpId;
t_Handle ccTreeId;
t_Handle completeArg;
void (*f_Complete)(t_Handle arg);
t_FmSpBufferOffsets bufferOffsets;
/* Independent-Mode parameters support */
bool imEn;
t_FmMacIm im;
volatile bool lock;
t_Handle h_Spinlock;
t_FmPortExceptionCallback *f_Exception;
t_Handle h_App;
uint8_t internalBufferOffset;
uint8_t fmanCtrlEventId;
uint32_t exceptions;
bool polling;
t_FmExtPools extBufPools;
uint32_t requiredAction;
uint32_t savedQmiPnen;
uint32_t savedBmiFene;
uint32_t savedBmiFpne;
uint32_t savedBmiCmne;
uint32_t savedBmiOfp;
uint32_t savedNonRxQmiRegsPndn;
uint32_t origNonRxQmiRegsPndn;
int savedPrsStartOffset;
bool includeInPrsStatistics;
uint16_t maxFrameLength;
t_FmFmanCtrl orFmanCtrl;
t_FmPortRsrc openDmas;
t_FmPortRsrc tasks;
t_FmPortRsrc fifoBufs;
t_FmPortRxPoolsParams rxPoolsParams;
// bool explicitUserSizeOfFifo;
t_Handle h_IpReassemblyManip;
t_Handle h_CapwapReassemblyManip;
t_Handle h_ReassemblyTree;
uint64_t fmMuramPhysBaseAddr;
#if (DPAA_VERSION >= 11)
bool vspe;
uint8_t dfltRelativeId;
e_FmPortGprFuncType gprFunc;
t_FmPcdCtrlParamsPage *p_ParamsPage;
#endif /* (DPAA_VERSION >= 11) */
t_FmPortDsarVars deepSleepVars;
t_FmPortDriverParam *p_FmPortDriverParam;
} t_FmPort;
void FmPortConfigIM (t_FmPort *p_FmPort, t_FmPortParams *p_FmPortParams);
t_Error FmPortImCheckInitParameters(t_FmPort *p_FmPort);
t_Error FmPortImInit(t_FmPort *p_FmPort);
void FmPortImFree(t_FmPort *p_FmPort);
t_Error FmPortImEnable (t_FmPort *p_FmPort);
t_Error FmPortImDisable (t_FmPort *p_FmPort);
t_Error FmPortImRx (t_FmPort *p_FmPort);
void FmPortSetMacsecLcv(t_Handle h_FmPort);
void FmPortSetMacsecCmd(t_Handle h_FmPort, uint8_t dfltSci);
t_Error FM_PORT_SetNumOfOpenDmas(t_Handle h_FmPort, t_FmPortRsrc *p_NumOfOpenDmas);
t_Error FM_PORT_SetNumOfTasks(t_Handle h_FmPort, t_FmPortRsrc *p_NumOfTasks);
t_Error FM_PORT_SetSizeOfFifo(t_Handle h_FmPort, t_FmPortRsrc *p_SizeOfFifo);
static __inline__ uint8_t * BdBufferGet (t_PhysToVirt *f_PhysToVirt, t_FmImBd *p_Bd)
{
uint64_t physAddr = (uint64_t)((uint64_t)GET_UINT8(p_Bd->buff.high) << 32);
physAddr |= GET_UINT32(p_Bd->buff.low);
return (uint8_t *)f_PhysToVirt((physAddress_t)(physAddr));
}
static __inline__ void SET_ADDR(volatile t_FmPhysAddr *fmPhysAddr, uint64_t value)
{
WRITE_UINT8(fmPhysAddr->high,(uint8_t)((value & 0x000000ff00000000LL) >> 32));
WRITE_UINT32(fmPhysAddr->low,(uint32_t)value);
}
static __inline__ void BdBufferSet(t_VirtToPhys *f_VirtToPhys, t_FmImBd *p_Bd, uint8_t *p_Buffer)
{
uint64_t physAddr = (uint64_t)(f_VirtToPhys(p_Buffer));
SET_ADDR(&p_Bd->buff, physAddr);
}
static __inline__ uint16_t GetNextBdId(t_FmPort *p_FmPort, uint16_t id)
{
if (id < p_FmPort->im.bdRingSize-1)
return (uint16_t)(id+1);
else
return 0;
}
void FM_PORT_Dsar_DumpRegs(void);
#endif /* __FM_PORT_H */

494
drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Port/fm_port_dsar.h Executable file
View File

@ -0,0 +1,494 @@
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**************************************************************************//**
@File fm_port_dsar.h
@Description Deep Sleep Auto Response project - common module header file.
Author - Eyal Harari
@Cautions See the FMan Controller spec and design document for more information.
*//***************************************************************************/
#ifndef __FM_PORT_DSAR_H_
#define __FM_PORT_DSAR_H_
#define DSAR_GETSER_MASK 0xFF0000FF
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(push,1)
#endif /* defined(__MWERKS__) && ... */
/**************************************************************************//**
@Description Deep Sleep Auto Response VLAN-IPv4 Binding Table (for ARP/ICMPv4)
Refer to the FMan Controller spec for more details.
*//***************************************************************************/
typedef _Packed struct
{
uint32_t ipv4Addr; /*!< 32 bit IPv4 Address. */
uint16_t vlanId; /*!< 12 bits VLAN ID. The 4 left-most bits should be cleared */
/*!< This field should be 0x0000 for an entry with no VLAN tag or a null VLAN ID. */
uint16_t reserved;
} _PackedType t_DsarArpBindingEntry;
/**************************************************************************//**
@Description Deep Sleep Auto Response Address Resolution Protocol Statistics Descriptor
Refer to the FMan Controller spec for more details.
0x00 INVAL_CNT Invalid ARP IPv4-Ethernet counter
0x04 ECHO_CNT Echo counter
0x08 CD_CNT Conflict Detection counter
0x0C AR_CNT Auto-Response counter
0x10 RATM_CNT Replies Addressed To Me counter
0x14 UKOP_CNT Unknown Operation counter
0x18 NMTP_CNT Not my TPA counter
0x1C NMVLAN_CNT Not My VLAN counter
*//***************************************************************************/
typedef _Packed struct
{
uint32_t invalCnt; /**< Invalid ARP IPv4-Ethernet counter. */
uint32_t echoCnt; /**< Echo counter. */
uint32_t cdCnt; /**< Conflict Detection counter. */
uint32_t arCnt; /**< Auto-Response counter. */
uint32_t ratmCnt; /**< Replies Addressed To Me counter. */
uint32_t ukopCnt; /**< Unknown Operation counter. */
uint32_t nmtpCnt; /**< Not my TPA counter. */
uint32_t nmVlanCnt; /**< Not My VLAN counter */
} _PackedType t_DsarArpStatistics;
/**************************************************************************//**
@Description Deep Sleep Auto Response Address Resolution Protocol Descriptor
0x0 0-15 Control bits [0-15]. Bit 15 = CDEN.
0x2 0-15 NumOfBindings Number of entries in the binding list.
0x4 0-15 BindingsPointer Bindings Pointer. This points to an IPv4-MAC Addresses Bindings list.
0x6 0-15
0x8 0-15 StatisticsPointer Statistics Pointer. This field points to the ARP Descriptors statistics data structure.
0xA 0-15
0xC 0-15 Reserved Reserved. Must be cleared.
0xE 015
*//***************************************************************************/
typedef _Packed struct
{
uint16_t control; /** Control bits [0-15]. Bit 15 = CDEN */
uint16_t numOfBindings; /**< Number of VLAN-IPv4 */
uint32_t p_Bindings; /**< VLAN-IPv4 Bindings table pointer. */
uint32_t p_Statistics; /**< Statistics Data Structure pointer. */
uint32_t reserved1; /**< Reserved. */
} _PackedType t_DsarArpDescriptor;
/**************************************************************************//**
@Description Deep Sleep Auto Response VLAN-IPv4 Binding Table (for ARP/ICMPv4)
Refer to the FMan Controller spec for more details.
*//***************************************************************************/
typedef _Packed struct
{
uint32_t ipv4Addr; /*!< 32 bit IPv4 Address. */
uint16_t vlanId; /*!< 12 bits VLAN ID. The 4 left-most bits should be cleared */
/*!< This field should be 0x0000 for an entry with no VLAN tag or a null VLAN ID. */
uint16_t reserved;
} _PackedType t_DsarIcmpV4BindingEntry;
/**************************************************************************//**
@Description Deep Sleep Auto Response ICMPv4 Statistics Descriptor
Refer to the FMan Controller spec for more details.
0x00 INVAL_CNT Invalid ICMPv4 header counter
0x04 NMVLAN_CNT Not My VLAN counter
0x08 NMIP_CNT Not My IP counter
0x0C AR_CNT Auto-Response counter
0x10 CSERR_CNT Checksum Error counter
0x14 Reserved Reserved
0x18 Reserved Reserved
0x1C Reserved Reserved
*//***************************************************************************/
typedef _Packed struct
{
uint32_t invalCnt; /**< Invalid ICMPv4 Echo counter. */
uint32_t nmVlanCnt; /**< Not My VLAN counter */
uint32_t nmIpCnt; /**< Not My IP counter */
uint32_t arCnt; /**< Auto-Response counter */
uint32_t cserrCnt; /**< Checksum Error counter */
uint32_t reserved0; /**< Reserved */
uint32_t reserved1; /**< Reserved */
uint32_t reserved2; /**< Reserved */
} _PackedType t_DsarIcmpV4Statistics;
/**************************************************************************//**
@Description Deep Sleep Auto Response ICMPv4 Descriptor
0x0 0-15 Control bits [0-15]
0x2 0-15 NumOfBindings Number of entries in the binding list.
0x4 0-15 BindingsPointer Bindings Pointer. This points to an VLAN-IPv4 Addresses Bindings list.
0x6 0-15
0x8 0-15 StatisticsPointer Statistics Pointer. This field points to the ICMPv4 statistics data structure.
0xA 0-15
0xC 0-15 Reserved Reserved. Must be cleared.
0xE 015
*//***************************************************************************/
typedef _Packed struct
{
uint16_t control; /** Control bits [0-15]. */
uint16_t numOfBindings; /**< Number of VLAN-IPv4 */
uint32_t p_Bindings; /**< VLAN-IPv4 Bindings table pointer. */
uint32_t p_Statistics; /**< Statistics Data Structure pointer. */
uint32_t reserved1; /**< Reserved. */
} _PackedType t_DsarIcmpV4Descriptor;
/**************************************************************************//**
@Description Deep Sleep Auto Response VLAN-IPv4 Binding Table (for ARP/ICMPv4)
The 4 left-most bits (15:12) of the VlanId parameter are control flags.
Flags[3:1] (VlanId[15:13]): Reserved, should be cleared.
Flags[0] (VlanId[12]): Temporary address.
• 0 - Assigned IP address.
• 1- Temporary (tentative) IP address.
Refer to the FMan Controller spec for more details.
*//***************************************************************************/
typedef _Packed struct
{
uint32_t ipv6Addr[4]; /*!< 3 * 32 bit IPv4 Address. */
uint16_t resFlags:4; /*!< reserved flags. should be cleared */
uint16_t vlanId:12; /*!< 12 bits VLAN ID. */
/*!< This field should be 0x000 for an entry with no VLAN tag or a null VLAN ID. */
uint16_t reserved;
} _PackedType t_DsarIcmpV6BindingEntry;
/**************************************************************************//**
@Description Deep Sleep Auto Response ICMPv4 Statistics Descriptor
Refer to the FMan Controller spec for more details.
0x00 INVAL_CNT Invalid ICMPv4 header counter
0x04 NMVLAN_CNT Not My VLAN counter
0x08 NMIP_CNT Not My IP counter
0x0C AR_CNT Auto-Response counter
0x10 CSERR_CNT Checksum Error counter
0x14 MCAST_CNT Multicast counter
0x18 Reserved Reserved
0x1C Reserved Reserved
*//***************************************************************************/
typedef _Packed struct
{
uint32_t invalCnt; /**< Invalid ICMPv4 Echo counter. */
uint32_t nmVlanCnt; /**< Not My VLAN counter */
uint32_t nmIpCnt; /**< Not My IP counter */
uint32_t arCnt; /**< Auto-Response counter */
uint32_t reserved1; /**< Reserved */
uint32_t reserved2; /**< Reserved */
uint32_t reserved3; /**< Reserved */
uint32_t reserved4; /**< Reserved */
} _PackedType t_DsarIcmpV6Statistics;
/**************************************************************************//**
@Description Deep Sleep Auto Response Neighbor Discovery Statistics Descriptor
0x00 INVAL_CNT Invalid Neighbor Discovery message counter
0x04 NMVLAN_CNT Not My VLAN counter
0x08 NMIP_CNT Not My IP counter
0x0C AR_CNT Auto-Response counter
0x10 CSERR_CNT Checksum Error counter
0x14 USADVERT_CNT Unsolicited Neighbor Advertisements counter
0x18 NMMCAST_CNT Not My Multicast group counter
0x1C NSLLA_CNT No Source Link-Layer Address counter. Indicates that there was a match on a Target
Address of a packet that its source IP address is a unicast address, but the ICMPv6
Source Link-layer Address option is omitted
*//***************************************************************************/
typedef _Packed struct
{
uint32_t invalCnt; /**< Invalid ICMPv4 Echo counter. */
uint32_t nmVlanCnt; /**< Not My VLAN counter */
uint32_t nmIpCnt; /**< Not My IP counter */
uint32_t arCnt; /**< Auto-Response counter */
uint32_t reserved1; /**< Reserved */
uint32_t usadvertCnt; /**< Unsolicited Neighbor Advertisements counter */
uint32_t nmmcastCnt; /**< Not My Multicast group counter */
uint32_t nsllaCnt; /**< No Source Link-Layer Address counter */
} _PackedType t_NdStatistics;
/**************************************************************************//**
@Description Deep Sleep Auto Response ICMPv6 Descriptor
0x0 0-15 Control bits [0-15]
0x2 0-15 NumOfBindings Number of entries in the binding list.
0x4 0-15 BindingsPointer Bindings Pointer. This points to an VLAN-IPv4 Addresses Bindings list.
0x6 0-15
0x8 0-15 StatisticsPointer Statistics Pointer. This field points to the ICMPv4 statistics data structure.
0xA 0-15
0xC 0-15 Reserved Reserved. Must be cleared.
0xE 015
*//***************************************************************************/
typedef _Packed struct
{
uint16_t control; /** Control bits [0-15]. */
uint16_t numOfBindings; /**< Number of VLAN-IPv6 */
uint32_t p_Bindings; /**< VLAN-IPv4 Bindings table pointer. */
uint32_t p_Statistics; /**< Statistics Data Structure pointer. */
uint32_t reserved1; /**< Reserved. */
} _PackedType t_DsarIcmpV6Descriptor;
/**************************************************************************//**
@Description Internet Control Message Protocol (ICMPv6) Echo message header
The fields names are taken from RFC 4443.
*//***************************************************************************/
/* 0 1 2 3 */
/* 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 */
/* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */
/* | Type | Code | Checksum | */
/* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */
/* | Identifier | Sequence Number | */
/* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */
/* | Data ... */
/* +-+-+-+-+- */
typedef _Packed struct
{
uint8_t type;
uint8_t code;
uint16_t checksum;
uint16_t identifier;
uint16_t sequenceNumber;
} _PackedType t_IcmpV6EchoHdr;
/**************************************************************************//**
@Description Internet Control Message Protocol (ICMPv6)
Neighbor Solicitation/Advertisement header
The fields names are taken from RFC 4861.
The R/S/O fields are valid for Neighbor Advertisement only
*//***************************************************************************/
/* 0 1 2 3
* 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | Type | Code | Checksum |
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* |R|S|O| Reserved |
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | |
* + +
* | |
* + Target Address +
* | |
* + +
* | |
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | Options ...
* +-+-+-+-+-+-+-+-+-+-+-+-
*
* Options Format:
* 0 1 2 3
* 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | Type | Length | Link-Layer Address ... |
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | Link-Layer Address |
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
typedef _Packed struct
{
uint8_t type;
uint8_t code;
uint16_t checksum;
uint32_t router:1;
uint32_t solicited:1;
uint32_t override:1;
uint32_t reserved:29;
uint32_t targetAddr[4];
uint8_t optionType;
uint8_t optionLength;
uint8_t linkLayerAddr[6];
} _PackedType t_IcmpV6NdHdr;
/**************************************************************************//**
@Description Deep Sleep Auto Response ICMPv6 Descriptor
0x0 0-15 Control bits [0-15]
0x2 0-15 NumOfBindings Number of entries in the binding list.
0x4 0-15 BindingsPointer Bindings Pointer. This points to an VLAN-IPv4 Addresses Bindings list.
0x6 0-15
0x8 0-15 StatisticsPointer Statistics Pointer. This field points to the ICMPv4 statistics data structure.
0xA 0-15
0xC 0-15 Reserved Reserved. Must be cleared.
0xE 015
*//***************************************************************************/
typedef _Packed struct
{
uint16_t control; /** Control bits [0-15]. */
uint16_t numOfBindings; /**< Number of VLAN-IPv6 */
uint32_t p_Bindings; /**< VLAN-IPv4 Bindings table pointer. */
uint32_t p_Statistics; /**< Statistics Data Structure pointer. */
uint32_t solicitedAddr; /**< Solicited Node Multicast Group Address */
} _PackedType t_DsarNdDescriptor;
/**************************************************************************//**
@Description Deep Sleep Auto Response SNMP OIDs table entry
*//***************************************************************************/
typedef struct {
uint16_t oidSize; /**< Size in octets of the OID. */
uint16_t resSize; /**< Size in octets of the value that is attached to the OID. */
uint32_t p_Oid; /**< Pointer to the OID. OID is encoded in BER but type and length are excluded. */
uint32_t resValOrPtr; /**< Value (for up to 4 octets) or pointer to the Value. Encoded in BER. */
uint32_t reserved;
} t_OidsTblEntry;
/**************************************************************************//**
@Description Deep Sleep Auto Response SNMP IPv4 Addresses Table Entry
Refer to the FMan Controller spec for more details.
*//***************************************************************************/
typedef struct
{
uint32_t ipv4Addr; /*!< 32 bit IPv4 Address. */
uint16_t vlanId; /*!< 12 bits VLAN ID. The 4 left-most bits should be cleared */
/*!< This field should be 0x0000 for an entry with no VLAN tag or a null VLAN ID. */
uint16_t reserved;
} t_DsarSnmpIpv4AddrTblEntry;
/**************************************************************************//**
@Description Deep Sleep Auto Response SNMP IPv6 Addresses Table Entry
Refer to the FMan Controller spec for more details.
*//***************************************************************************/
#pragma pack(push,1)
typedef struct
{
uint32_t ipv6Addr[4]; /*!< 4 * 32 bit IPv6 Address. */
uint16_t vlanId; /*!< 12 bits VLAN ID. The 4 left-most bits should be cleared */
/*!< This field should be 0x0000 for an entry with no VLAN tag or a null VLAN ID. */
uint16_t reserved;
} t_DsarSnmpIpv6AddrTblEntry;
#pragma pack(pop)
/**************************************************************************//**
@Description Deep Sleep Auto Response SNMP statistics table
*//***************************************************************************/
typedef struct {
uint32_t snmpErrCnt; /**< Counts SNMP errors (wrong version, BER encoding, format). */
uint32_t snmpCommunityErrCnt; /**< Counts messages that were dropped due to insufficient permission. */
uint32_t snmpTotalDiscardCnt; /**< Counts any message that was dropped. */
uint32_t snmpGetReqCnt; /**< Counts the number of get-request messages */
uint32_t snmpGetNextReqCnt; /**< Counts the number of get-next-request messages */
} t_DsarSnmpStatistics;
/**************************************************************************//**
@Description Deep Sleep Auto Response SNMP Descriptor
*//***************************************************************************/
typedef struct
{
uint16_t control; /**< Control bits [0-15]. */
uint16_t maxSnmpMsgLength; /**< Maximal allowed SNMP message length. */
uint16_t numOfIpv4Addresses; /**< Number of entries in IPv4 addresses table. */
uint16_t numOfIpv6Addresses; /**< Number of entries in IPv6 addresses table. */
uint32_t p_Ipv4AddrTbl; /**< Pointer to IPv4 addresses table. */
uint32_t p_Ipv6AddrTbl; /**< Pointer to IPv6 addresses table. */
uint32_t p_RdOnlyCommunityStr; /**< Pointer to the Read Only Community String. */
uint32_t p_RdWrCommunityStr; /**< Pointer to the Read Write Community String. */
uint32_t p_OidsTbl; /**< Pointer to OIDs table. */
uint32_t oidsTblSize; /**< Number of entries in OIDs table. */
uint32_t p_Statistics; /**< Pointer to SNMP statistics table. */
} t_DsarSnmpDescriptor;
/**************************************************************************//**
@Description Deep Sleep Auto Response (Common) Statistics
*//***************************************************************************/
typedef _Packed struct {
uint32_t dsarDiscarded;
uint32_t dsarErrDiscarded;
uint32_t dsarFragDiscarded;
uint32_t dsarTunnelDiscarded;
uint32_t dsarArpDiscarded;
uint32_t dsarIpDiscarded;
uint32_t dsarTcpDiscarded;
uint32_t dsarUdpDiscarded;
uint32_t dsarIcmpV6ChecksumErr; /* ICMPv6 Checksum Error counter */
uint32_t dsarIcmpV6OtherType; /* ICMPv6 'Other' type (not Echo or Neighbor Solicitaion/Advertisement counter */
uint32_t dsarIcmpV4OtherType; /* ICMPv4 'Other' type (not Echo) counter */
} _PackedType t_ArStatistics;
/**************************************************************************//**
@Description Deep Sleep Auto Response TCP/UDP port filter table entry
*//***************************************************************************/
typedef _Packed struct {
uint32_t Ports;
uint32_t PortsMask;
} _PackedType t_PortTblEntry;
/**************************************************************************//**
@Description Deep Sleep Auto Response Common Parameters Descriptor
*//***************************************************************************/
typedef _Packed struct {
uint8_t arTxPort; /* 0x00 0-7 Auto Response Transmit Port number */
uint8_t controlBits; /* 0x00 8-15 Auto Response control bits */
uint16_t res1; /* 0x00 16-31 Reserved */
uint32_t activeHPNIA; /* 0x04 0-31 Active mode Hardware Parser NIA */
uint16_t snmpPort; /* 0x08 0-15 SNMP Port. */
uint8_t macStationAddr[6]; /* 0x08 16-31 and 0x0C 0-31 MAC Station Address */
uint8_t res2; /* 0x10 0-7 Reserved */
uint8_t filterControl; /* 0x10 8-15 Filtering Control Bits. */
uint16_t tcpControlPass; /* 0x10 16-31 TCP control pass flags */
uint8_t ipProtocolTblSize; /* 0x14 0-7 IP Protocol Table Size. */
uint8_t udpPortTblSize; /* 0x14 8-15 UDP Port Table Size. */
uint8_t tcpPortTblSize; /* 0x14 16-23 TCP Port Table Size. */
uint8_t res3; /* 0x14 24-31 Reserved */
uint32_t p_IpProtocolFiltTbl; /* 0x18 0-31 Pointer to IP Protocol Filter Table */
uint32_t p_UdpPortFiltTbl; /* 0x1C 0-31 Pointer to UDP Port Filter Table */
uint32_t p_TcpPortFiltTbl; /* 0x20 0-31 Pointer to TCP Port Filter Table */
uint32_t res4; /* 0x24 Reserved */
uint32_t p_ArpDescriptor; /* 0x28 0-31 ARP Descriptor Pointer. */
uint32_t p_NdDescriptor; /* 0x2C 0-31 Neighbor Discovery Descriptor. */
uint32_t p_IcmpV4Descriptor; /* 0x30 0-31 ICMPv4 Descriptor pointer. */
uint32_t p_IcmpV6Descriptor; /* 0x34 0-31 ICMPv6 Descriptor pointer. */
uint32_t p_SnmpDescriptor; /* 0x38 0-31 SNMP Descriptor pointer. */
uint32_t p_ArStats; /* 0x3C 0-31 Pointer to Auto Response Statistics */
} _PackedType t_ArCommonDesc;
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(pop)
#endif /* defined(__MWERKS__) && ... */
/* t_ArCommonDesc.filterControl bits */
#define IP_PROT_TBL_PASS_MASK 0x08
#define UDP_PORT_TBL_PASS_MASK 0x04
#define TCP_PORT_TBL_PASS_MASK 0x02
/* Offset of TCF flags within TCP packet */
#define TCP_FLAGS_OFFSET 12
#endif /* __FM_PORT_DSAR_H_ */

753
drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Port/fm_port_im.c Normal file
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@ -0,0 +1,753 @@
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_port_im.c
@Description FM Port Independent-Mode ...
*//***************************************************************************/
#include "std_ext.h"
#include "string_ext.h"
#include "error_ext.h"
#include "memcpy_ext.h"
#include "fm_muram_ext.h"
#include "fm_port.h"
#define TX_CONF_STATUS_UNSENT 0x1
typedef enum e_TxConfType
{
e_TX_CONF_TYPE_CHECK = 0 /**< check if all the buffers were touched by the muxator, no confirmation callback */
,e_TX_CONF_TYPE_CALLBACK = 1 /**< confirm to user all the available sent buffers */
,e_TX_CONF_TYPE_FLUSH = 3 /**< confirm all buffers plus the unsent one with an appropriate status */
} e_TxConfType;
static void ImException(t_Handle h_FmPort, uint32_t event)
{
t_FmPort *p_FmPort = (t_FmPort*)h_FmPort;
ASSERT_COND(((event & (IM_EV_RX | IM_EV_BSY)) && FmIsMaster(p_FmPort->h_Fm)) ||
!FmIsMaster(p_FmPort->h_Fm));
if (event & IM_EV_RX)
FmPortImRx(p_FmPort);
if ((event & IM_EV_BSY) && p_FmPort->f_Exception)
p_FmPort->f_Exception(p_FmPort->h_App, e_FM_PORT_EXCEPTION_IM_BUSY);
}
static t_Error TxConf(t_FmPort *p_FmPort, e_TxConfType confType)
{
t_Error retVal = E_BUSY;
uint32_t bdStatus;
uint16_t savedStartBdId, confBdId;
ASSERT_COND(p_FmPort);
/*
if (confType==e_TX_CONF_TYPE_CHECK)
return (WfqEntryIsQueueEmpty(p_FmPort->im.h_WfqEntry) ? E_OK : E_BUSY);
*/
confBdId = savedStartBdId = p_FmPort->im.currBdId;
bdStatus = BD_STATUS_AND_LENGTH(BD_GET(confBdId));
/* If R bit is set, we don't enter, or we break.
we run till we get to R, or complete the loop */
while ((!(bdStatus & BD_R_E) || (confType == e_TX_CONF_TYPE_FLUSH)) && (retVal != E_OK))
{
if (confType & e_TX_CONF_TYPE_CALLBACK) /* if it is confirmation with user callbacks */
BD_STATUS_AND_LENGTH_SET(BD_GET(confBdId), 0);
/* case 1: R bit is 0 and Length is set -> confirm! */
if ((confType & e_TX_CONF_TYPE_CALLBACK) && (bdStatus & BD_LENGTH_MASK))
{
if (p_FmPort->im.f_TxConf)
{
if ((confType == e_TX_CONF_TYPE_FLUSH) && (bdStatus & BD_R_E))
p_FmPort->im.f_TxConf(p_FmPort->h_App,
BdBufferGet(XX_PhysToVirt, BD_GET(confBdId)),
TX_CONF_STATUS_UNSENT,
p_FmPort->im.p_BdShadow[confBdId]);
else
p_FmPort->im.f_TxConf(p_FmPort->h_App,
BdBufferGet(XX_PhysToVirt, BD_GET(confBdId)),
0,
p_FmPort->im.p_BdShadow[confBdId]);
}
}
/* case 2: R bit is 0 and Length is 0 -> not used yet, nop! */
confBdId = GetNextBdId(p_FmPort, confBdId);
if (confBdId == savedStartBdId)
retVal = E_OK;
bdStatus = BD_STATUS_AND_LENGTH(BD_GET(confBdId));
}
return retVal;
}
t_Error FmPortImEnable(t_FmPort *p_FmPort)
{
uint32_t tmpReg = GET_UINT32(p_FmPort->im.p_FmPortImPram->mode);
WRITE_UINT32(p_FmPort->im.p_FmPortImPram->mode, (uint32_t)(tmpReg & ~IM_MODE_GRC_STP));
return E_OK;
}
t_Error FmPortImDisable(t_FmPort *p_FmPort)
{
uint32_t tmpReg = GET_UINT32(p_FmPort->im.p_FmPortImPram->mode);
WRITE_UINT32(p_FmPort->im.p_FmPortImPram->mode, (uint32_t)(tmpReg | IM_MODE_GRC_STP));
return E_OK;
}
t_Error FmPortImRx(t_FmPort *p_FmPort)
{
t_Handle h_CurrUserPriv, h_NewUserPriv;
uint32_t bdStatus;
volatile uint8_t buffPos;
uint16_t length;
uint16_t errors;
uint8_t *p_CurData, *p_Data;
uint32_t flags;
ASSERT_COND(p_FmPort);
flags = XX_LockIntrSpinlock(p_FmPort->h_Spinlock);
if (p_FmPort->lock)
{
XX_UnlockIntrSpinlock(p_FmPort->h_Spinlock, flags);
return E_OK;
}
p_FmPort->lock = TRUE;
XX_UnlockIntrSpinlock(p_FmPort->h_Spinlock, flags);
bdStatus = BD_STATUS_AND_LENGTH(BD_GET(p_FmPort->im.currBdId));
while (!(bdStatus & BD_R_E)) /* while there is data in the Rx BD */
{
if ((p_Data = p_FmPort->im.rxPool.f_GetBuf(p_FmPort->im.rxPool.h_BufferPool, &h_NewUserPriv)) == NULL)
{
p_FmPort->lock = FALSE;
RETURN_ERROR(MAJOR, E_NOT_AVAILABLE, ("Data buffer"));
}
if (p_FmPort->im.firstBdOfFrameId == IM_ILEGAL_BD_ID)
p_FmPort->im.firstBdOfFrameId = p_FmPort->im.currBdId;
p_CurData = BdBufferGet(p_FmPort->im.rxPool.f_PhysToVirt, BD_GET(p_FmPort->im.currBdId));
h_CurrUserPriv = p_FmPort->im.p_BdShadow[p_FmPort->im.currBdId];
length = (uint16_t)((bdStatus & BD_L) ?
((bdStatus & BD_LENGTH_MASK) - p_FmPort->im.rxFrameAccumLength):
(bdStatus & BD_LENGTH_MASK));
p_FmPort->im.rxFrameAccumLength += length;
/* determine whether buffer is first, last, first and last (single */
/* buffer frame) or middle (not first and not last) */
buffPos = (uint8_t)((p_FmPort->im.currBdId == p_FmPort->im.firstBdOfFrameId) ?
((bdStatus & BD_L) ? SINGLE_BUF : FIRST_BUF) :
((bdStatus & BD_L) ? LAST_BUF : MIDDLE_BUF));
if (bdStatus & BD_L)
{
p_FmPort->im.rxFrameAccumLength = 0;
p_FmPort->im.firstBdOfFrameId = IM_ILEGAL_BD_ID;
}
BdBufferSet(p_FmPort->im.rxPool.f_VirtToPhys, BD_GET(p_FmPort->im.currBdId), p_Data);
BD_STATUS_AND_LENGTH_SET(BD_GET(p_FmPort->im.currBdId), BD_R_E);
errors = (uint16_t)((bdStatus & BD_RX_ERRORS) >> 16);
p_FmPort->im.p_BdShadow[p_FmPort->im.currBdId] = h_NewUserPriv;
p_FmPort->im.currBdId = GetNextBdId(p_FmPort, p_FmPort->im.currBdId);
WRITE_UINT16(p_FmPort->im.p_FmPortImPram->rxQd.offsetOut, (uint16_t)(p_FmPort->im.currBdId<<4));
/* Pass the buffer if one of the conditions is true:
- There are no errors
- This is a part of a larger frame ( the application has already received some buffers ) */
if ((buffPos != SINGLE_BUF) || !errors)
{
if (p_FmPort->im.f_RxStore(p_FmPort->h_App,
p_CurData,
length,
errors,
buffPos,
h_CurrUserPriv) == e_RX_STORE_RESPONSE_PAUSE)
break;
}
else if (p_FmPort->im.rxPool.f_PutBuf(p_FmPort->im.rxPool.h_BufferPool,
p_CurData,
h_CurrUserPriv))
{
p_FmPort->lock = FALSE;
RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Failed freeing data buffer"));
}
bdStatus = BD_STATUS_AND_LENGTH(BD_GET(p_FmPort->im.currBdId));
}
p_FmPort->lock = FALSE;
return E_OK;
}
void FmPortConfigIM (t_FmPort *p_FmPort, t_FmPortParams *p_FmPortParams)
{
ASSERT_COND(p_FmPort);
SANITY_CHECK_RETURN(p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE);
p_FmPort->im.h_FmMuram = p_FmPortParams->specificParams.imRxTxParams.h_FmMuram;
p_FmPort->p_FmPortDriverParam->liodnOffset = p_FmPortParams->specificParams.imRxTxParams.liodnOffset;
p_FmPort->im.dataMemId = p_FmPortParams->specificParams.imRxTxParams.dataMemId;
p_FmPort->im.dataMemAttributes = p_FmPortParams->specificParams.imRxTxParams.dataMemAttributes;
p_FmPort->im.fwExtStructsMemId = DEFAULT_PORT_ImfwExtStructsMemId;
p_FmPort->im.fwExtStructsMemAttr = DEFAULT_PORT_ImfwExtStructsMemAttr;
if ((p_FmPort->portType == e_FM_PORT_TYPE_RX) ||
(p_FmPort->portType == e_FM_PORT_TYPE_RX_10G))
{
p_FmPort->im.rxPool.h_BufferPool = p_FmPortParams->specificParams.imRxTxParams.rxPoolParams.h_BufferPool;
p_FmPort->im.rxPool.f_GetBuf = p_FmPortParams->specificParams.imRxTxParams.rxPoolParams.f_GetBuf;
p_FmPort->im.rxPool.f_PutBuf = p_FmPortParams->specificParams.imRxTxParams.rxPoolParams.f_PutBuf;
p_FmPort->im.rxPool.bufferSize = p_FmPortParams->specificParams.imRxTxParams.rxPoolParams.bufferSize;
p_FmPort->im.rxPool.f_PhysToVirt = p_FmPortParams->specificParams.imRxTxParams.rxPoolParams.f_PhysToVirt;
if (!p_FmPort->im.rxPool.f_PhysToVirt)
p_FmPort->im.rxPool.f_PhysToVirt = XX_PhysToVirt;
p_FmPort->im.rxPool.f_VirtToPhys = p_FmPortParams->specificParams.imRxTxParams.rxPoolParams.f_VirtToPhys;
if (!p_FmPort->im.rxPool.f_VirtToPhys)
p_FmPort->im.rxPool.f_VirtToPhys = XX_VirtToPhys;
p_FmPort->im.f_RxStore = p_FmPortParams->specificParams.imRxTxParams.f_RxStore;
p_FmPort->im.mrblr = 0x8000;
while (p_FmPort->im.mrblr)
{
if (p_FmPort->im.rxPool.bufferSize & p_FmPort->im.mrblr)
break;
p_FmPort->im.mrblr >>= 1;
}
if (p_FmPort->im.mrblr != p_FmPort->im.rxPool.bufferSize)
DBG(WARNING, ("Max-Rx-Buffer-Length set to %d", p_FmPort->im.mrblr));
p_FmPort->im.bdRingSize = DEFAULT_PORT_rxBdRingLength;
p_FmPort->exceptions = DEFAULT_PORT_exception;
if (FmIsMaster(p_FmPort->h_Fm))
p_FmPort->polling = FALSE;
else
p_FmPort->polling = TRUE;
p_FmPort->fmanCtrlEventId = (uint8_t)NO_IRQ;
}
else
{
p_FmPort->im.f_TxConf = p_FmPortParams->specificParams.imRxTxParams.f_TxConf;
p_FmPort->im.bdRingSize = DEFAULT_PORT_txBdRingLength;
}
}
t_Error FmPortImCheckInitParameters(t_FmPort *p_FmPort)
{
if ((p_FmPort->portType != e_FM_PORT_TYPE_RX) &&
(p_FmPort->portType != e_FM_PORT_TYPE_RX_10G) &&
(p_FmPort->portType != e_FM_PORT_TYPE_TX) &&
(p_FmPort->portType != e_FM_PORT_TYPE_TX_10G))
RETURN_ERROR(MAJOR, E_INVALID_VALUE, NO_MSG);
if ((p_FmPort->portType == e_FM_PORT_TYPE_RX) ||
(p_FmPort->portType == e_FM_PORT_TYPE_RX_10G))
{
if (!POWER_OF_2(p_FmPort->im.mrblr))
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("max Rx buffer length must be power of 2!!!"));
if (p_FmPort->im.mrblr < 256)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("max Rx buffer length must at least 256!!!"));
if (p_FmPort->p_FmPortDriverParam->liodnOffset & ~FM_LIODN_OFFSET_MASK)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("liodnOffset is larger than %d", FM_LIODN_OFFSET_MASK+1));
}
return E_OK;
}
t_Error FmPortImInit(t_FmPort *p_FmPort)
{
t_FmImBd *p_Bd=NULL;
t_Handle h_BufContext;
uint64_t tmpPhysBase;
uint16_t log2Num;
uint8_t *p_Data/*, *p_Tmp*/;
int i;
t_Error err;
uint16_t tmpReg16;
uint32_t tmpReg32;
ASSERT_COND(p_FmPort);
p_FmPort->im.p_FmPortImPram =
(t_FmPortImPram *)FM_MURAM_AllocMem(p_FmPort->im.h_FmMuram, sizeof(t_FmPortImPram), IM_PRAM_ALIGN);
if (!p_FmPort->im.p_FmPortImPram)
RETURN_ERROR(MAJOR, E_NO_MEMORY, ("Independent-Mode Parameter-RAM!!!"));
WRITE_BLOCK(p_FmPort->im.p_FmPortImPram, 0, sizeof(t_FmPortImPram));
if ((p_FmPort->portType == e_FM_PORT_TYPE_RX) ||
(p_FmPort->portType == e_FM_PORT_TYPE_RX_10G))
{
p_FmPort->im.p_BdRing =
(t_FmImBd *)XX_MallocSmart((uint32_t)(sizeof(t_FmImBd)*p_FmPort->im.bdRingSize),
p_FmPort->im.fwExtStructsMemId,
4);
if (!p_FmPort->im.p_BdRing)
RETURN_ERROR(MAJOR, E_NO_MEMORY, ("Independent-Mode Rx BD ring!!!"));
IOMemSet32(p_FmPort->im.p_BdRing, 0, (uint32_t)(sizeof(t_FmImBd)*p_FmPort->im.bdRingSize));
p_FmPort->im.p_BdShadow = (t_Handle *)XX_Malloc((uint32_t)(sizeof(t_Handle)*p_FmPort->im.bdRingSize));
if (!p_FmPort->im.p_BdShadow)
RETURN_ERROR(MAJOR, E_NO_MEMORY, ("Independent-Mode Rx BD shadow!!!"));
memset(p_FmPort->im.p_BdShadow, 0, (uint32_t)(sizeof(t_Handle)*p_FmPort->im.bdRingSize));
/* Initialize the Rx-BD ring */
for (i=0; i<p_FmPort->im.bdRingSize; i++)
{
p_Bd = BD_GET(i);
BD_STATUS_AND_LENGTH_SET (p_Bd, BD_R_E);
if ((p_Data = p_FmPort->im.rxPool.f_GetBuf(p_FmPort->im.rxPool.h_BufferPool, &h_BufContext)) == NULL)
RETURN_ERROR(MAJOR, E_NOT_AVAILABLE, ("Data buffer"));
BdBufferSet(p_FmPort->im.rxPool.f_VirtToPhys, p_Bd, p_Data);
p_FmPort->im.p_BdShadow[i] = h_BufContext;
}
if ((p_FmPort->im.dataMemAttributes & MEMORY_ATTR_CACHEABLE) ||
(p_FmPort->im.fwExtStructsMemAttr & MEMORY_ATTR_CACHEABLE))
WRITE_UINT32(p_FmPort->im.p_FmPortImPram->mode, IM_MODE_GBL | IM_MODE_SET_BO(2));
else
WRITE_UINT32(p_FmPort->im.p_FmPortImPram->mode, IM_MODE_SET_BO(2));
WRITE_UINT32(p_FmPort->im.p_FmPortImPram->rxQdPtr,
(uint32_t)((uint64_t)(XX_VirtToPhys(p_FmPort->im.p_FmPortImPram)) -
p_FmPort->fmMuramPhysBaseAddr + 0x20));
LOG2((uint64_t)p_FmPort->im.mrblr, log2Num);
WRITE_UINT16(p_FmPort->im.p_FmPortImPram->mrblr, log2Num);
/* Initialize Rx QD */
tmpPhysBase = (uint64_t)(XX_VirtToPhys(p_FmPort->im.p_BdRing));
SET_ADDR(&p_FmPort->im.p_FmPortImPram->rxQd.bdRingBase, tmpPhysBase);
WRITE_UINT16(p_FmPort->im.p_FmPortImPram->rxQd.bdRingSize, (uint16_t)(sizeof(t_FmImBd)*p_FmPort->im.bdRingSize));
/* Update the IM PRAM address in the BMI */
WRITE_UINT32(p_FmPort->p_FmPortBmiRegs->rxPortBmiRegs.fmbm_rfqid,
(uint32_t)((uint64_t)(XX_VirtToPhys(p_FmPort->im.p_FmPortImPram)) -
p_FmPort->fmMuramPhysBaseAddr));
if (!p_FmPort->polling || p_FmPort->exceptions)
{
/* Allocate, configure and register interrupts */
err = FmAllocFmanCtrlEventReg(p_FmPort->h_Fm, &p_FmPort->fmanCtrlEventId);
if (err)
RETURN_ERROR(MAJOR, err, NO_MSG);
ASSERT_COND(!(p_FmPort->fmanCtrlEventId & ~IM_RXQD_FPMEVT_SEL_MASK));
tmpReg16 = (uint16_t)(p_FmPort->fmanCtrlEventId & IM_RXQD_FPMEVT_SEL_MASK);
tmpReg32 = 0;
if (p_FmPort->exceptions & IM_EV_BSY)
{
tmpReg16 |= IM_RXQD_BSYINTM;
tmpReg32 |= IM_EV_BSY;
}
if (!p_FmPort->polling)
{
tmpReg16 |= IM_RXQD_RXFINTM;
tmpReg32 |= IM_EV_RX;
}
WRITE_UINT16(p_FmPort->im.p_FmPortImPram->rxQd.gen, tmpReg16);
FmRegisterFmanCtrlIntr(p_FmPort->h_Fm, p_FmPort->fmanCtrlEventId, ImException , (t_Handle)p_FmPort);
FmSetFmanCtrlIntr(p_FmPort->h_Fm, p_FmPort->fmanCtrlEventId, tmpReg32);
}
else
p_FmPort->fmanCtrlEventId = (uint8_t)NO_IRQ;
}
else
{
p_FmPort->im.p_BdRing = (t_FmImBd *)XX_MallocSmart((uint32_t)(sizeof(t_FmImBd)*p_FmPort->im.bdRingSize), p_FmPort->im.fwExtStructsMemId, 4);
if (!p_FmPort->im.p_BdRing)
RETURN_ERROR(MAJOR, E_NO_MEMORY, ("Independent-Mode Tx BD ring!!!"));
IOMemSet32(p_FmPort->im.p_BdRing, 0, (uint32_t)(sizeof(t_FmImBd)*p_FmPort->im.bdRingSize));
p_FmPort->im.p_BdShadow = (t_Handle *)XX_Malloc((uint32_t)(sizeof(t_Handle)*p_FmPort->im.bdRingSize));
if (!p_FmPort->im.p_BdShadow)
RETURN_ERROR(MAJOR, E_NO_MEMORY, ("Independent-Mode Rx BD shadow!!!"));
memset(p_FmPort->im.p_BdShadow, 0, (uint32_t)(sizeof(t_Handle)*p_FmPort->im.bdRingSize));
p_FmPort->im.firstBdOfFrameId = IM_ILEGAL_BD_ID;
if ((p_FmPort->im.dataMemAttributes & MEMORY_ATTR_CACHEABLE) ||
(p_FmPort->im.fwExtStructsMemAttr & MEMORY_ATTR_CACHEABLE))
WRITE_UINT32(p_FmPort->im.p_FmPortImPram->mode, IM_MODE_GBL | IM_MODE_SET_BO(2));
else
WRITE_UINT32(p_FmPort->im.p_FmPortImPram->mode, IM_MODE_SET_BO(2));
WRITE_UINT32(p_FmPort->im.p_FmPortImPram->txQdPtr,
(uint32_t)((uint64_t)(XX_VirtToPhys(p_FmPort->im.p_FmPortImPram)) -
p_FmPort->fmMuramPhysBaseAddr + 0x40));
/* Initialize Tx QD */
tmpPhysBase = (uint64_t)(XX_VirtToPhys(p_FmPort->im.p_BdRing));
SET_ADDR(&p_FmPort->im.p_FmPortImPram->txQd.bdRingBase, tmpPhysBase);
WRITE_UINT16(p_FmPort->im.p_FmPortImPram->txQd.bdRingSize, (uint16_t)(sizeof(t_FmImBd)*p_FmPort->im.bdRingSize));
/* Update the IM PRAM address in the BMI */
WRITE_UINT32(p_FmPort->p_FmPortBmiRegs->txPortBmiRegs.fmbm_tcfqid,
(uint32_t)((uint64_t)(XX_VirtToPhys(p_FmPort->im.p_FmPortImPram)) -
p_FmPort->fmMuramPhysBaseAddr));
}
return E_OK;
}
void FmPortImFree(t_FmPort *p_FmPort)
{
uint32_t bdStatus;
uint8_t *p_CurData;
ASSERT_COND(p_FmPort);
ASSERT_COND(p_FmPort->im.p_FmPortImPram);
if ((p_FmPort->portType == e_FM_PORT_TYPE_RX) ||
(p_FmPort->portType == e_FM_PORT_TYPE_RX_10G))
{
if (!p_FmPort->polling || p_FmPort->exceptions)
{
/* Deallocate and unregister interrupts */
FmSetFmanCtrlIntr(p_FmPort->h_Fm, p_FmPort->fmanCtrlEventId, 0);
FmFreeFmanCtrlEventReg(p_FmPort->h_Fm, p_FmPort->fmanCtrlEventId);
WRITE_UINT16(p_FmPort->im.p_FmPortImPram->rxQd.gen, 0);
FmUnregisterFmanCtrlIntr(p_FmPort->h_Fm, p_FmPort->fmanCtrlEventId);
}
/* Try first clean what has received */
FmPortImRx(p_FmPort);
/* Now, get rid of the the empty buffer! */
bdStatus = BD_STATUS_AND_LENGTH(BD_GET(p_FmPort->im.currBdId));
while (bdStatus & BD_R_E) /* while there is data in the Rx BD */
{
p_CurData = BdBufferGet(p_FmPort->im.rxPool.f_PhysToVirt, BD_GET(p_FmPort->im.currBdId));
BdBufferSet(p_FmPort->im.rxPool.f_VirtToPhys, BD_GET(p_FmPort->im.currBdId), NULL);
BD_STATUS_AND_LENGTH_SET(BD_GET(p_FmPort->im.currBdId), 0);
p_FmPort->im.rxPool.f_PutBuf(p_FmPort->im.rxPool.h_BufferPool,
p_CurData,
p_FmPort->im.p_BdShadow[p_FmPort->im.currBdId]);
p_FmPort->im.currBdId = GetNextBdId(p_FmPort, p_FmPort->im.currBdId);
bdStatus = BD_STATUS_AND_LENGTH(BD_GET(p_FmPort->im.currBdId));
}
}
else
TxConf(p_FmPort, e_TX_CONF_TYPE_FLUSH);
FM_MURAM_FreeMem(p_FmPort->im.h_FmMuram, p_FmPort->im.p_FmPortImPram);
if (p_FmPort->im.p_BdShadow)
XX_Free(p_FmPort->im.p_BdShadow);
if (p_FmPort->im.p_BdRing)
XX_FreeSmart(p_FmPort->im.p_BdRing);
}
t_Error FM_PORT_ConfigIMMaxRxBufLength(t_Handle h_FmPort, uint16_t newVal)
{
t_FmPort *p_FmPort = (t_FmPort*)h_FmPort;
SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmPort->imEn, E_INVALID_STATE);
SANITY_CHECK_RETURN_ERROR(p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE);
p_FmPort->im.mrblr = newVal;
return E_OK;
}
t_Error FM_PORT_ConfigIMRxBdRingLength(t_Handle h_FmPort, uint16_t newVal)
{
t_FmPort *p_FmPort = (t_FmPort*)h_FmPort;
SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmPort->imEn, E_INVALID_STATE);
SANITY_CHECK_RETURN_ERROR(p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE);
p_FmPort->im.bdRingSize = newVal;
return E_OK;
}
t_Error FM_PORT_ConfigIMTxBdRingLength(t_Handle h_FmPort, uint16_t newVal)
{
t_FmPort *p_FmPort = (t_FmPort*)h_FmPort;
SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmPort->imEn, E_INVALID_STATE);
SANITY_CHECK_RETURN_ERROR(p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE);
p_FmPort->im.bdRingSize = newVal;
return E_OK;
}
t_Error FM_PORT_ConfigIMFmanCtrlExternalStructsMemory(t_Handle h_FmPort,
uint8_t memId,
uint32_t memAttributes)
{
t_FmPort *p_FmPort = (t_FmPort*)h_FmPort;
SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmPort->imEn, E_INVALID_STATE);
SANITY_CHECK_RETURN_ERROR(p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE);
p_FmPort->im.fwExtStructsMemId = memId;
p_FmPort->im.fwExtStructsMemAttr = memAttributes;
return E_OK;
}
t_Error FM_PORT_ConfigIMPolling(t_Handle h_FmPort)
{
t_FmPort *p_FmPort = (t_FmPort*)h_FmPort;
SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmPort->imEn, E_INVALID_STATE);
SANITY_CHECK_RETURN_ERROR(p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE);
if ((p_FmPort->portType != e_FM_PORT_TYPE_RX_10G) && (p_FmPort->portType != e_FM_PORT_TYPE_RX))
RETURN_ERROR(MAJOR, E_INVALID_OPERATION, ("Available for Rx ports only"));
if (!FmIsMaster(p_FmPort->h_Fm))
RETURN_ERROR(MAJOR, E_INVALID_OPERATION, ("Available on master-partition only;"
"in guest-partitions, IM is always in polling!"));
p_FmPort->polling = TRUE;
return E_OK;
}
t_Error FM_PORT_SetIMExceptions(t_Handle h_FmPort, e_FmPortExceptions exception, bool enable)
{
t_FmPort *p_FmPort = (t_FmPort*)h_FmPort;
t_Error err;
uint16_t tmpReg16;
uint32_t tmpReg32;
SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmPort->imEn, E_INVALID_STATE);
SANITY_CHECK_RETURN_ERROR(!p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE);
if (exception == e_FM_PORT_EXCEPTION_IM_BUSY)
{
if (enable)
{
p_FmPort->exceptions |= IM_EV_BSY;
if (p_FmPort->fmanCtrlEventId == (uint8_t)NO_IRQ)
{
/* Allocate, configure and register interrupts */
err = FmAllocFmanCtrlEventReg(p_FmPort->h_Fm, &p_FmPort->fmanCtrlEventId);
if (err)
RETURN_ERROR(MAJOR, err, NO_MSG);
ASSERT_COND(!(p_FmPort->fmanCtrlEventId & ~IM_RXQD_FPMEVT_SEL_MASK));
FmRegisterFmanCtrlIntr(p_FmPort->h_Fm, p_FmPort->fmanCtrlEventId, ImException, (t_Handle)p_FmPort);
tmpReg16 = (uint16_t)((p_FmPort->fmanCtrlEventId & IM_RXQD_FPMEVT_SEL_MASK) | IM_RXQD_BSYINTM);
tmpReg32 = IM_EV_BSY;
}
else
{
tmpReg16 = (uint16_t)(GET_UINT16(p_FmPort->im.p_FmPortImPram->rxQd.gen) | IM_RXQD_BSYINTM);
tmpReg32 = FmGetFmanCtrlIntr(p_FmPort->h_Fm, p_FmPort->fmanCtrlEventId) | IM_EV_BSY;
}
WRITE_UINT16(p_FmPort->im.p_FmPortImPram->rxQd.gen, tmpReg16);
FmSetFmanCtrlIntr(p_FmPort->h_Fm, p_FmPort->fmanCtrlEventId, tmpReg32);
}
else
{
p_FmPort->exceptions &= ~IM_EV_BSY;
if (!p_FmPort->exceptions && p_FmPort->polling)
{
FmFreeFmanCtrlEventReg(p_FmPort->h_Fm, p_FmPort->fmanCtrlEventId);
FmUnregisterFmanCtrlIntr(p_FmPort->h_Fm, p_FmPort->fmanCtrlEventId);
FmSetFmanCtrlIntr(p_FmPort->h_Fm, p_FmPort->fmanCtrlEventId, 0);
WRITE_UINT16(p_FmPort->im.p_FmPortImPram->rxQd.gen, 0);
p_FmPort->fmanCtrlEventId = (uint8_t)NO_IRQ;
}
else
{
tmpReg16 = (uint16_t)(GET_UINT16(p_FmPort->im.p_FmPortImPram->rxQd.gen) & ~IM_RXQD_BSYINTM);
WRITE_UINT16(p_FmPort->im.p_FmPortImPram->rxQd.gen, tmpReg16);
tmpReg32 = FmGetFmanCtrlIntr(p_FmPort->h_Fm, p_FmPort->fmanCtrlEventId) & ~IM_EV_BSY;
FmSetFmanCtrlIntr(p_FmPort->h_Fm, p_FmPort->fmanCtrlEventId, tmpReg32);
}
}
}
else
RETURN_ERROR(MINOR, E_INVALID_SELECTION, ("Invalid exception."));
return E_OK;
}
t_Error FM_PORT_ImTx( t_Handle h_FmPort,
uint8_t *p_Data,
uint16_t length,
bool lastBuffer,
t_Handle h_BufContext)
{
t_FmPort *p_FmPort = (t_FmPort*)h_FmPort;
uint16_t nextBdId;
uint32_t bdStatus, nextBdStatus;
bool firstBuffer;
SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmPort->imEn, E_INVALID_STATE);
SANITY_CHECK_RETURN_ERROR(!p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE);
bdStatus = BD_STATUS_AND_LENGTH(BD_GET(p_FmPort->im.currBdId));
nextBdId = GetNextBdId(p_FmPort, p_FmPort->im.currBdId);
nextBdStatus = BD_STATUS_AND_LENGTH(BD_GET(nextBdId));
if (!(bdStatus & BD_R_E) && !(nextBdStatus & BD_R_E))
{
/* Confirm the current BD - BD is available */
if ((bdStatus & BD_LENGTH_MASK) && (p_FmPort->im.f_TxConf))
p_FmPort->im.f_TxConf (p_FmPort->h_App,
BdBufferGet(XX_PhysToVirt, BD_GET(p_FmPort->im.currBdId)),
0,
p_FmPort->im.p_BdShadow[p_FmPort->im.currBdId]);
bdStatus = length;
/* if this is the first BD of a frame */
if (p_FmPort->im.firstBdOfFrameId == IM_ILEGAL_BD_ID)
{
firstBuffer = TRUE;
p_FmPort->im.txFirstBdStatus = (bdStatus | BD_R_E);
if (!lastBuffer)
p_FmPort->im.firstBdOfFrameId = p_FmPort->im.currBdId;
}
else
firstBuffer = FALSE;
BdBufferSet(XX_VirtToPhys, BD_GET(p_FmPort->im.currBdId), p_Data);
p_FmPort->im.p_BdShadow[p_FmPort->im.currBdId] = h_BufContext;
/* deal with last */
if (lastBuffer)
{
/* if single buffer frame */
if (firstBuffer)
BD_STATUS_AND_LENGTH_SET(BD_GET(p_FmPort->im.currBdId), p_FmPort->im.txFirstBdStatus | BD_L);
else
{
/* Set the last BD of the frame */
BD_STATUS_AND_LENGTH_SET (BD_GET(p_FmPort->im.currBdId), (bdStatus | BD_R_E | BD_L));
/* Set the first BD of the frame */
BD_STATUS_AND_LENGTH_SET(BD_GET(p_FmPort->im.firstBdOfFrameId), p_FmPort->im.txFirstBdStatus);
p_FmPort->im.firstBdOfFrameId = IM_ILEGAL_BD_ID;
}
WRITE_UINT16(p_FmPort->im.p_FmPortImPram->txQd.offsetIn, (uint16_t)(GetNextBdId(p_FmPort, p_FmPort->im.currBdId)<<4));
}
else if (!firstBuffer) /* mid frame buffer */
BD_STATUS_AND_LENGTH_SET (BD_GET(p_FmPort->im.currBdId), bdStatus | BD_R_E);
p_FmPort->im.currBdId = GetNextBdId(p_FmPort, p_FmPort->im.currBdId);
}
else
{
/* Discard current frame. Return error. */
if (p_FmPort->im.firstBdOfFrameId != IM_ILEGAL_BD_ID)
{
/* Error: No free BD */
/* Response: Discard current frame. Return error. */
uint16_t cleanBdId = p_FmPort->im.firstBdOfFrameId;
ASSERT_COND(p_FmPort->im.firstBdOfFrameId != p_FmPort->im.currBdId);
/* Since firstInFrame is not NULL, one buffer at least has already been
inserted into the BD ring. Using do-while covers the situation of a
frame spanned throughout the whole Tx BD ring (p_CleanBd is incremented
prior to testing whether or not it's equal to TxBd). */
do
{
BD_STATUS_AND_LENGTH_SET(BD_GET(cleanBdId), 0);
/* Advance BD pointer */
cleanBdId = GetNextBdId(p_FmPort, cleanBdId);
} while (cleanBdId != p_FmPort->im.currBdId);
p_FmPort->im.currBdId = cleanBdId;
p_FmPort->im.firstBdOfFrameId = IM_ILEGAL_BD_ID;
}
return ERROR_CODE(E_FULL);
}
return E_OK;
}
void FM_PORT_ImTxConf(t_Handle h_FmPort)
{
t_FmPort *p_FmPort = (t_FmPort*)h_FmPort;
SANITY_CHECK_RETURN(p_FmPort, E_INVALID_HANDLE);
SANITY_CHECK_RETURN(p_FmPort->imEn, E_INVALID_STATE);
SANITY_CHECK_RETURN(!p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE);
TxConf(p_FmPort, e_TX_CONF_TYPE_CALLBACK);
}
t_Error FM_PORT_ImRx(t_Handle h_FmPort)
{
t_FmPort *p_FmPort = (t_FmPort*)h_FmPort;
SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmPort->imEn, E_INVALID_STATE);
SANITY_CHECK_RETURN_ERROR(!p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE);
return FmPortImRx(p_FmPort);
}

1568
drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Port/fman_port.c Executable file
View File

File diff suppressed because it is too large Load Diff

15
drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Rtc/Makefile Normal file
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@ -0,0 +1,15 @@
#
# Makefile for the Freescale Ethernet controllers
#
ccflags-y += -DVERSION=\"\"
#
#Include netcomm SW specific definitions
include $(srctree)/drivers/net/ethernet/freescale/sdk_fman/ncsw_config.mk
NCSW_FM_INC = $(srctree)/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/inc
ccflags-y += -I$(NCSW_FM_INC)
obj-y += fsl-ncsw-RTC.o
fsl-ncsw-RTC-objs := fm_rtc.o fman_rtc.o

692
drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Rtc/fm_rtc.c Normal file
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@ -0,0 +1,692 @@
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_rtc.c
@Description FM RTC driver implementation.
@Cautions None
*//***************************************************************************/
#include <linux/math64.h>
#include "error_ext.h"
#include "debug_ext.h"
#include "string_ext.h"
#include "part_ext.h"
#include "xx_ext.h"
#include "ncsw_ext.h"
#include "fm_rtc.h"
#include "fm_common.h"
/*****************************************************************************/
static t_Error CheckInitParameters(t_FmRtc *p_Rtc)
{
struct rtc_cfg *p_RtcDriverParam = p_Rtc->p_RtcDriverParam;
int i;
if ((p_RtcDriverParam->src_clk != E_FMAN_RTC_SOURCE_CLOCK_EXTERNAL) &&
(p_RtcDriverParam->src_clk != E_FMAN_RTC_SOURCE_CLOCK_SYSTEM) &&
(p_RtcDriverParam->src_clk != E_FMAN_RTC_SOURCE_CLOCK_OSCILATOR))
RETURN_ERROR(MAJOR, E_INVALID_CLOCK, ("Source clock undefined"));
if (p_Rtc->outputClockDivisor == 0)
{
RETURN_ERROR(MAJOR, E_INVALID_VALUE,
("Divisor for output clock (should be positive)"));
}
for (i=0; i < FM_RTC_NUM_OF_ALARMS; i++)
{
if ((p_RtcDriverParam->alarm_polarity[i] != E_FMAN_RTC_ALARM_POLARITY_ACTIVE_LOW) &&
(p_RtcDriverParam->alarm_polarity[i] != E_FMAN_RTC_ALARM_POLARITY_ACTIVE_HIGH))
{
RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("Alarm %d signal polarity", i));
}
}
for (i=0; i < FM_RTC_NUM_OF_EXT_TRIGGERS; i++)
{
if ((p_RtcDriverParam->trigger_polarity[i] != E_FMAN_RTC_TRIGGER_ON_FALLING_EDGE) &&
(p_RtcDriverParam->trigger_polarity[i] != E_FMAN_RTC_TRIGGER_ON_RISING_EDGE))
{
RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("Trigger %d signal polarity", i));
}
}
return E_OK;
}
/*****************************************************************************/
static void RtcExceptions(t_Handle h_FmRtc)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
struct rtc_regs *p_MemMap;
register uint32_t events;
ASSERT_COND(p_Rtc);
p_MemMap = p_Rtc->p_MemMap;
events = fman_rtc_check_and_clear_event(p_MemMap);
if (events & FMAN_RTC_TMR_TEVENT_ALM1)
{
if (p_Rtc->alarmParams[0].clearOnExpiration)
{
fman_rtc_set_timer_alarm_l(p_MemMap, 0, 0);
fman_rtc_disable_interupt(p_MemMap, FMAN_RTC_TMR_TEVENT_ALM1);
}
ASSERT_COND(p_Rtc->alarmParams[0].f_AlarmCallback);
p_Rtc->alarmParams[0].f_AlarmCallback(p_Rtc->h_App, 0);
}
if (events & FMAN_RTC_TMR_TEVENT_ALM2)
{
if (p_Rtc->alarmParams[1].clearOnExpiration)
{
fman_rtc_set_timer_alarm_l(p_MemMap, 1, 0);
fman_rtc_disable_interupt(p_MemMap, FMAN_RTC_TMR_TEVENT_ALM2);
}
ASSERT_COND(p_Rtc->alarmParams[1].f_AlarmCallback);
p_Rtc->alarmParams[1].f_AlarmCallback(p_Rtc->h_App, 1);
}
if (events & FMAN_RTC_TMR_TEVENT_PP1)
{
ASSERT_COND(p_Rtc->periodicPulseParams[0].f_PeriodicPulseCallback);
p_Rtc->periodicPulseParams[0].f_PeriodicPulseCallback(p_Rtc->h_App, 0);
}
if (events & FMAN_RTC_TMR_TEVENT_PP2)
{
ASSERT_COND(p_Rtc->periodicPulseParams[1].f_PeriodicPulseCallback);
p_Rtc->periodicPulseParams[1].f_PeriodicPulseCallback(p_Rtc->h_App, 1);
}
if (events & FMAN_RTC_TMR_TEVENT_ETS1)
{
ASSERT_COND(p_Rtc->externalTriggerParams[0].f_ExternalTriggerCallback);
p_Rtc->externalTriggerParams[0].f_ExternalTriggerCallback(p_Rtc->h_App, 0);
}
if (events & FMAN_RTC_TMR_TEVENT_ETS2)
{
ASSERT_COND(p_Rtc->externalTriggerParams[1].f_ExternalTriggerCallback);
p_Rtc->externalTriggerParams[1].f_ExternalTriggerCallback(p_Rtc->h_App, 1);
}
}
/*****************************************************************************/
t_Handle FM_RTC_Config(t_FmRtcParams *p_FmRtcParam)
{
t_FmRtc *p_Rtc;
SANITY_CHECK_RETURN_VALUE(p_FmRtcParam, E_NULL_POINTER, NULL);
/* Allocate memory for the FM RTC driver parameters */
p_Rtc = (t_FmRtc *)XX_Malloc(sizeof(t_FmRtc));
if (!p_Rtc)
{
REPORT_ERROR(MAJOR, E_NO_MEMORY, ("FM RTC driver structure"));
return NULL;
}
memset(p_Rtc, 0, sizeof(t_FmRtc));
/* Allocate memory for the FM RTC driver parameters */
p_Rtc->p_RtcDriverParam = (struct rtc_cfg *)XX_Malloc(sizeof(struct rtc_cfg));
if (!p_Rtc->p_RtcDriverParam)
{
REPORT_ERROR(MAJOR, E_NO_MEMORY, ("FM RTC driver parameters"));
XX_Free(p_Rtc);
return NULL;
}
memset(p_Rtc->p_RtcDriverParam, 0, sizeof(struct rtc_cfg));
/* Store RTC configuration parameters */
p_Rtc->h_Fm = p_FmRtcParam->h_Fm;
/* Set default RTC configuration parameters */
fman_rtc_defconfig(p_Rtc->p_RtcDriverParam);
p_Rtc->outputClockDivisor = DEFAULT_OUTPUT_CLOCK_DIVISOR;
p_Rtc->p_RtcDriverParam->bypass = DEFAULT_BYPASS;
p_Rtc->clockPeriodNanoSec = DEFAULT_CLOCK_PERIOD; /* 1 usec */
/* Store RTC parameters in the RTC control structure */
p_Rtc->p_MemMap = (struct rtc_regs *)UINT_TO_PTR(p_FmRtcParam->baseAddress);
p_Rtc->h_App = p_FmRtcParam->h_App;
return p_Rtc;
}
/*****************************************************************************/
t_Error FM_RTC_Init(t_Handle h_FmRtc)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
struct rtc_cfg *p_RtcDriverParam;
struct rtc_regs *p_MemMap;
uint32_t freqCompensation = 0;
uint64_t tmpDouble;
bool init_freq_comp = FALSE;
p_RtcDriverParam = p_Rtc->p_RtcDriverParam;
p_MemMap = p_Rtc->p_MemMap;
if (CheckInitParameters(p_Rtc)!=E_OK)
RETURN_ERROR(MAJOR, E_CONFLICT,
("Init Parameters are not Valid"));
/* TODO check that no timestamping MACs are working in this stage. */
/* find source clock frequency in Mhz */
if (p_Rtc->p_RtcDriverParam->src_clk != E_FMAN_RTC_SOURCE_CLOCK_SYSTEM)
p_Rtc->srcClkFreqMhz = p_Rtc->p_RtcDriverParam->ext_src_clk_freq;
else
p_Rtc->srcClkFreqMhz = (uint32_t)(FmGetMacClockFreq(p_Rtc->h_Fm));
/* if timer in Master mode Initialize TMR_CTRL */
/* We want the counter (TMR_CNT) to count in nano-seconds */
if (!p_RtcDriverParam->timer_slave_mode && p_Rtc->p_RtcDriverParam->bypass)
p_Rtc->clockPeriodNanoSec = (1000 / p_Rtc->srcClkFreqMhz);
else
{
/* Initialize TMR_ADD with the initial frequency compensation value:
freqCompensation = (2^32 / frequency ratio) */
/* frequency ratio = sorce clock/rtc clock =
* (p_Rtc->srcClkFreqMhz*1000000))/ 1/(p_Rtc->clockPeriodNanoSec * 1000000000) */
init_freq_comp = TRUE;
freqCompensation = (uint32_t)DIV_CEIL(ACCUMULATOR_OVERFLOW * 1000,
p_Rtc->clockPeriodNanoSec * p_Rtc->srcClkFreqMhz);
}
/* check the legality of the relation between source and destination clocks */
/* should be larger than 1.0001 */
tmpDouble = 10000 * (uint64_t)p_Rtc->clockPeriodNanoSec * (uint64_t)p_Rtc->srcClkFreqMhz;
if ((tmpDouble) <= 10001)
RETURN_ERROR(MAJOR, E_CONFLICT,
("Invalid relation between source and destination clocks. Should be larger than 1.0001"));
fman_rtc_init(p_RtcDriverParam,
p_MemMap,
FM_RTC_NUM_OF_ALARMS,
FM_RTC_NUM_OF_PERIODIC_PULSES,
FM_RTC_NUM_OF_EXT_TRIGGERS,
init_freq_comp,
freqCompensation,
p_Rtc->outputClockDivisor);
/* Register the FM RTC interrupt */
FmRegisterIntr(p_Rtc->h_Fm, e_FM_MOD_TMR, 0, e_FM_INTR_TYPE_NORMAL, RtcExceptions , p_Rtc);
/* Free parameters structures */
XX_Free(p_Rtc->p_RtcDriverParam);
p_Rtc->p_RtcDriverParam = NULL;
return E_OK;
}
/*****************************************************************************/
t_Error FM_RTC_Free(t_Handle h_FmRtc)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
if (p_Rtc->p_RtcDriverParam)
{
XX_Free(p_Rtc->p_RtcDriverParam);
}
else
{
FM_RTC_Disable(h_FmRtc);
}
/* Unregister FM RTC interrupt */
FmUnregisterIntr(p_Rtc->h_Fm, e_FM_MOD_TMR, 0, e_FM_INTR_TYPE_NORMAL);
XX_Free(p_Rtc);
return E_OK;
}
/*****************************************************************************/
t_Error FM_RTC_ConfigSourceClock(t_Handle h_FmRtc,
e_FmSrcClk srcClk,
uint32_t freqInMhz)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
p_Rtc->p_RtcDriverParam->src_clk = (enum fman_src_clock)srcClk;
if (srcClk != e_FM_RTC_SOURCE_CLOCK_SYSTEM)
p_Rtc->p_RtcDriverParam->ext_src_clk_freq = freqInMhz;
return E_OK;
}
/*****************************************************************************/
t_Error FM_RTC_ConfigPeriod(t_Handle h_FmRtc, uint32_t period)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
p_Rtc->clockPeriodNanoSec = period;
return E_OK;
}
/*****************************************************************************/
t_Error FM_RTC_ConfigFrequencyBypass(t_Handle h_FmRtc, bool enabled)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
p_Rtc->p_RtcDriverParam->bypass = enabled;
return E_OK;
}
/*****************************************************************************/
t_Error FM_RTC_ConfigInvertedInputClockPhase(t_Handle h_FmRtc, bool inverted)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
p_Rtc->p_RtcDriverParam->invert_input_clk_phase = inverted;
return E_OK;
}
/*****************************************************************************/
t_Error FM_RTC_ConfigInvertedOutputClockPhase(t_Handle h_FmRtc, bool inverted)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
p_Rtc->p_RtcDriverParam->invert_output_clk_phase = inverted;
return E_OK;
}
/*****************************************************************************/
t_Error FM_RTC_ConfigOutputClockDivisor(t_Handle h_FmRtc, uint16_t divisor)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
p_Rtc->outputClockDivisor = divisor;
return E_OK;
}
/*****************************************************************************/
t_Error FM_RTC_ConfigPulseRealignment(t_Handle h_FmRtc, bool enable)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
p_Rtc->p_RtcDriverParam->pulse_realign = enable;
return E_OK;
}
/*****************************************************************************/
t_Error FM_RTC_ConfigAlarmPolarity(t_Handle h_FmRtc,
uint8_t alarmId,
e_FmRtcAlarmPolarity alarmPolarity)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
if (alarmId >= FM_RTC_NUM_OF_ALARMS)
RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("Alarm ID"));
p_Rtc->p_RtcDriverParam->alarm_polarity[alarmId] =
(enum fman_rtc_alarm_polarity)alarmPolarity;
return E_OK;
}
/*****************************************************************************/
t_Error FM_RTC_ConfigExternalTriggerPolarity(t_Handle h_FmRtc,
uint8_t triggerId,
e_FmRtcTriggerPolarity triggerPolarity)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
if (triggerId >= FM_RTC_NUM_OF_EXT_TRIGGERS)
{
RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("External trigger ID"));
}
p_Rtc->p_RtcDriverParam->trigger_polarity[triggerId] =
(enum fman_rtc_trigger_polarity)triggerPolarity;
return E_OK;
}
/*****************************************************************************/
t_Error FM_RTC_Enable(t_Handle h_FmRtc, bool resetClock)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
fman_rtc_enable(p_Rtc->p_MemMap, resetClock);
return E_OK;
}
/*****************************************************************************/
t_Error FM_RTC_Disable(t_Handle h_FmRtc)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
/* TODO A check must be added here, that no timestamping MAC's
* are working in this stage. */
fman_rtc_disable(p_Rtc->p_MemMap);
return E_OK;
}
/*****************************************************************************/
t_Error FM_RTC_SetClockOffset(t_Handle h_FmRtc, int64_t offset)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
fman_rtc_set_timer_offset(p_Rtc->p_MemMap, offset);
return E_OK;
}
/*****************************************************************************/
t_Error FM_RTC_SetAlarm(t_Handle h_FmRtc, t_FmRtcAlarmParams *p_FmRtcAlarmParams)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
uint64_t tmpAlarm;
bool enable = FALSE;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
if (p_FmRtcAlarmParams->alarmId >= FM_RTC_NUM_OF_ALARMS)
{
RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("Alarm ID"));
}
if (p_FmRtcAlarmParams->alarmTime < p_Rtc->clockPeriodNanoSec)
RETURN_ERROR(MAJOR, E_INVALID_SELECTION,
("Alarm time must be equal or larger than RTC period - %d nanoseconds",
p_Rtc->clockPeriodNanoSec));
tmpAlarm = p_FmRtcAlarmParams->alarmTime;
if (do_div(tmpAlarm, p_Rtc->clockPeriodNanoSec))
RETURN_ERROR(MAJOR, E_INVALID_SELECTION,
("Alarm time must be a multiple of RTC period - %d nanoseconds",
p_Rtc->clockPeriodNanoSec));
if (p_FmRtcAlarmParams->f_AlarmCallback)
{
p_Rtc->alarmParams[p_FmRtcAlarmParams->alarmId].f_AlarmCallback = p_FmRtcAlarmParams->f_AlarmCallback;
p_Rtc->alarmParams[p_FmRtcAlarmParams->alarmId].clearOnExpiration = p_FmRtcAlarmParams->clearOnExpiration;
enable = TRUE;
}
fman_rtc_set_alarm(p_Rtc->p_MemMap, p_FmRtcAlarmParams->alarmId, (unsigned long)tmpAlarm, enable);
return E_OK;
}
/*****************************************************************************/
t_Error FM_RTC_SetPeriodicPulse(t_Handle h_FmRtc, t_FmRtcPeriodicPulseParams *p_FmRtcPeriodicPulseParams)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
bool enable = FALSE;
uint64_t tmpFiper;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
if (p_FmRtcPeriodicPulseParams->periodicPulseId >= FM_RTC_NUM_OF_PERIODIC_PULSES)
{
RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("Periodic pulse ID"));
}
if (fman_rtc_is_enabled(p_Rtc->p_MemMap))
RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("Can't set Periodic pulse when RTC is enabled."));
if (p_FmRtcPeriodicPulseParams->periodicPulsePeriod < p_Rtc->clockPeriodNanoSec)
RETURN_ERROR(MAJOR, E_INVALID_SELECTION,
("Periodic pulse must be equal or larger than RTC period - %d nanoseconds",
p_Rtc->clockPeriodNanoSec));
tmpFiper = p_FmRtcPeriodicPulseParams->periodicPulsePeriod;
if (do_div(tmpFiper, p_Rtc->clockPeriodNanoSec))
RETURN_ERROR(MAJOR, E_INVALID_SELECTION,
("Periodic pulse must be a multiple of RTC period - %d nanoseconds",
p_Rtc->clockPeriodNanoSec));
if (tmpFiper & 0xffffffff00000000LL)
RETURN_ERROR(MAJOR, E_INVALID_SELECTION,
("Periodic pulse/RTC Period must be smaller than 4294967296",
p_Rtc->clockPeriodNanoSec));
if (p_FmRtcPeriodicPulseParams->f_PeriodicPulseCallback)
{
p_Rtc->periodicPulseParams[p_FmRtcPeriodicPulseParams->periodicPulseId].f_PeriodicPulseCallback =
p_FmRtcPeriodicPulseParams->f_PeriodicPulseCallback;
enable = TRUE;
}
fman_rtc_set_periodic_pulse(p_Rtc->p_MemMap, p_FmRtcPeriodicPulseParams->periodicPulseId, (uint32_t)tmpFiper, enable);
return E_OK;
}
/*****************************************************************************/
t_Error FM_RTC_ClearPeriodicPulse(t_Handle h_FmRtc, uint8_t periodicPulseId)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
if (periodicPulseId >= FM_RTC_NUM_OF_PERIODIC_PULSES)
{
RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("Periodic pulse ID"));
}
p_Rtc->periodicPulseParams[periodicPulseId].f_PeriodicPulseCallback = NULL;
fman_rtc_clear_periodic_pulse(p_Rtc->p_MemMap, periodicPulseId);
return E_OK;
}
/*****************************************************************************/
t_Error FM_RTC_SetExternalTrigger(t_Handle h_FmRtc, t_FmRtcExternalTriggerParams *p_FmRtcExternalTriggerParams)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
bool enable = FALSE;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
if (p_FmRtcExternalTriggerParams->externalTriggerId >= FM_RTC_NUM_OF_EXT_TRIGGERS)
{
RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("External Trigger ID"));
}
if (p_FmRtcExternalTriggerParams->f_ExternalTriggerCallback)
{
p_Rtc->externalTriggerParams[p_FmRtcExternalTriggerParams->externalTriggerId].f_ExternalTriggerCallback = p_FmRtcExternalTriggerParams->f_ExternalTriggerCallback;
enable = TRUE;
}
fman_rtc_set_ext_trigger(p_Rtc->p_MemMap, p_FmRtcExternalTriggerParams->externalTriggerId, enable, p_FmRtcExternalTriggerParams->usePulseAsInput);
return E_OK;
}
/*****************************************************************************/
t_Error FM_RTC_ClearExternalTrigger(t_Handle h_FmRtc, uint8_t externalTriggerId)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
if (externalTriggerId >= FM_RTC_NUM_OF_EXT_TRIGGERS)
RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("External Trigger ID"));
p_Rtc->externalTriggerParams[externalTriggerId].f_ExternalTriggerCallback = NULL;
fman_rtc_clear_external_trigger(p_Rtc->p_MemMap, externalTriggerId);
return E_OK;
}
/*****************************************************************************/
t_Error FM_RTC_GetExternalTriggerTimeStamp(t_Handle h_FmRtc,
uint8_t triggerId,
uint64_t *p_TimeStamp)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
if (triggerId >= FM_RTC_NUM_OF_EXT_TRIGGERS)
RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("External trigger ID"));
*p_TimeStamp = fman_rtc_get_trigger_stamp(p_Rtc->p_MemMap, triggerId)*p_Rtc->clockPeriodNanoSec;
return E_OK;
}
/*****************************************************************************/
t_Error FM_RTC_GetCurrentTime(t_Handle h_FmRtc, uint64_t *p_Ts)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
*p_Ts = fman_rtc_get_timer(p_Rtc->p_MemMap)*p_Rtc->clockPeriodNanoSec;
return E_OK;
}
/*****************************************************************************/
t_Error FM_RTC_SetCurrentTime(t_Handle h_FmRtc, uint64_t ts)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
do_div(ts, p_Rtc->clockPeriodNanoSec);
fman_rtc_set_timer(p_Rtc->p_MemMap, (int64_t)ts);
return E_OK;
}
/*****************************************************************************/
t_Error FM_RTC_GetFreqCompensation(t_Handle h_FmRtc, uint32_t *p_Compensation)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
*p_Compensation = fman_rtc_get_frequency_compensation(p_Rtc->p_MemMap);
return E_OK;
}
/*****************************************************************************/
t_Error FM_RTC_SetFreqCompensation(t_Handle h_FmRtc, uint32_t freqCompensation)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
/* set the new freqCompensation */
fman_rtc_set_frequency_compensation(p_Rtc->p_MemMap, freqCompensation);
return E_OK;
}
#ifdef CONFIG_PTP_1588_CLOCK_DPAA
/*****************************************************************************/
t_Error FM_RTC_EnableInterrupt(t_Handle h_FmRtc, uint32_t events)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
/* enable interrupt */
fman_rtc_enable_interupt(p_Rtc->p_MemMap, events);
return E_OK;
}
/*****************************************************************************/
t_Error FM_RTC_DisableInterrupt(t_Handle h_FmRtc, uint32_t events)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
/* disable interrupt */
fman_rtc_disable_interupt(p_Rtc->p_MemMap, events);
return E_OK;
}
#endif

96
drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Rtc/fm_rtc.h Normal file
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/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_rtc.h
@Description Memory map and internal definitions for FM RTC IEEE1588 Timer driver.
@Cautions None
*//***************************************************************************/
#ifndef __FM_RTC_H__
#define __FM_RTC_H__
#include "std_ext.h"
#include "fm_rtc_ext.h"
#define __ERR_MODULE__ MODULE_FM_RTC
/* General definitions */
#define ACCUMULATOR_OVERFLOW ((uint64_t)(1LL << 32))
#define DEFAULT_OUTPUT_CLOCK_DIVISOR 0x00000002
#define DEFAULT_BYPASS FALSE
#define DEFAULT_CLOCK_PERIOD 1000
typedef struct t_FmRtcAlarm
{
t_FmRtcExceptionsCallback *f_AlarmCallback;
bool clearOnExpiration;
} t_FmRtcAlarm;
typedef struct t_FmRtcPeriodicPulse
{
t_FmRtcExceptionsCallback *f_PeriodicPulseCallback;
} t_FmRtcPeriodicPulse;
typedef struct t_FmRtcExternalTrigger
{
t_FmRtcExceptionsCallback *f_ExternalTriggerCallback;
} t_FmRtcExternalTrigger;
/**************************************************************************//**
@Description RTC FM driver control structure.
*//***************************************************************************/
typedef struct t_FmRtc
{
t_Part *p_Part; /**< Pointer to the integration device */
t_Handle h_Fm;
t_Handle h_App; /**< Application handle */
struct rtc_regs *p_MemMap;
uint32_t clockPeriodNanoSec; /**< RTC clock period in nano-seconds (for FS mode) */
uint32_t srcClkFreqMhz;
uint16_t outputClockDivisor; /**< Output clock divisor (for FS mode) */
t_FmRtcAlarm alarmParams[FM_RTC_NUM_OF_ALARMS];
t_FmRtcPeriodicPulse periodicPulseParams[FM_RTC_NUM_OF_PERIODIC_PULSES];
t_FmRtcExternalTrigger externalTriggerParams[FM_RTC_NUM_OF_EXT_TRIGGERS];
struct rtc_cfg *p_RtcDriverParam; /**< RTC Driver parameters (for Init phase) */
} t_FmRtc;
#endif /* __FM_RTC_H__ */

334
drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Rtc/fman_rtc.c Executable file
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/*
* Copyright 2008-2013 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_fman_rtc.h"
void fman_rtc_defconfig(struct rtc_cfg *cfg)
{
int i;
cfg->src_clk = DEFAULT_SRC_CLOCK;
cfg->invert_input_clk_phase = DEFAULT_INVERT_INPUT_CLK_PHASE;
cfg->invert_output_clk_phase = DEFAULT_INVERT_OUTPUT_CLK_PHASE;
cfg->pulse_realign = DEFAULT_PULSE_REALIGN;
for (i = 0; i < FMAN_RTC_MAX_NUM_OF_ALARMS; i++)
cfg->alarm_polarity[i] = DEFAULT_ALARM_POLARITY;
for (i = 0; i < FMAN_RTC_MAX_NUM_OF_EXT_TRIGGERS; i++)
cfg->trigger_polarity[i] = DEFAULT_TRIGGER_POLARITY;
}
uint32_t fman_rtc_get_events(struct rtc_regs *regs)
{
return ioread32be(&regs->tmr_tevent);
}
uint32_t fman_rtc_get_event(struct rtc_regs *regs, uint32_t ev_mask)
{
return ioread32be(&regs->tmr_tevent) & ev_mask;
}
uint32_t fman_rtc_get_interrupt_mask(struct rtc_regs *regs)
{
return ioread32be(&regs->tmr_temask);
}
void fman_rtc_set_interrupt_mask(struct rtc_regs *regs, uint32_t mask)
{
iowrite32be(mask, &regs->tmr_temask);
}
void fman_rtc_ack_event(struct rtc_regs *regs, uint32_t events)
{
iowrite32be(events, &regs->tmr_tevent);
}
uint32_t fman_rtc_check_and_clear_event(struct rtc_regs *regs)
{
uint32_t event;
event = ioread32be(&regs->tmr_tevent);
event &= ioread32be(&regs->tmr_temask);
if (event)
iowrite32be(event, &regs->tmr_tevent);
return event;
}
uint32_t fman_rtc_get_frequency_compensation(struct rtc_regs *regs)
{
return ioread32be(&regs->tmr_add);
}
void fman_rtc_set_frequency_compensation(struct rtc_regs *regs, uint32_t val)
{
iowrite32be(val, &regs->tmr_add);
}
void fman_rtc_enable_interupt(struct rtc_regs *regs, uint32_t events)
{
fman_rtc_set_interrupt_mask(regs, fman_rtc_get_interrupt_mask(regs) | events);
}
void fman_rtc_disable_interupt(struct rtc_regs *regs, uint32_t events)
{
fman_rtc_set_interrupt_mask(regs, fman_rtc_get_interrupt_mask(regs) & ~events);
}
void fman_rtc_set_timer_alarm_l(struct rtc_regs *regs, int index, uint32_t val)
{
iowrite32be(val, &regs->tmr_alarm[index].tmr_alarm_l);
}
void fman_rtc_set_timer_fiper(struct rtc_regs *regs, int index, uint32_t val)
{
iowrite32be(val, &regs->tmr_fiper[index]);
}
void fman_rtc_set_timer_alarm(struct rtc_regs *regs, int index, int64_t val)
{
iowrite32be((uint32_t)val, &regs->tmr_alarm[index].tmr_alarm_l);
iowrite32be((uint32_t)(val >> 32), &regs->tmr_alarm[index].tmr_alarm_h);
}
void fman_rtc_set_timer_offset(struct rtc_regs *regs, int64_t val)
{
iowrite32be((uint32_t)val, &regs->tmr_off_l);
iowrite32be((uint32_t)(val >> 32), &regs->tmr_off_h);
}
uint64_t fman_rtc_get_trigger_stamp(struct rtc_regs *regs, int id)
{
uint64_t time;
/* TMR_CNT_L must be read first to get an accurate value */
time = (uint64_t)ioread32be(&regs->tmr_etts[id].tmr_etts_l);
time |= ((uint64_t)ioread32be(&regs->tmr_etts[id].tmr_etts_h)
<< 32);
return time;
}
uint32_t fman_rtc_get_timer_ctrl(struct rtc_regs *regs)
{
return ioread32be(&regs->tmr_ctrl);
}
void fman_rtc_set_timer_ctrl(struct rtc_regs *regs, uint32_t val)
{
iowrite32be(val, &regs->tmr_ctrl);
}
void fman_rtc_timers_soft_reset(struct rtc_regs *regs)
{
fman_rtc_set_timer_ctrl(regs, FMAN_RTC_TMR_CTRL_TMSR);
udelay(10);
fman_rtc_set_timer_ctrl(regs, 0);
}
void fman_rtc_init(struct rtc_cfg *cfg, struct rtc_regs *regs, int num_alarms,
int num_fipers, int num_ext_triggers, bool init_freq_comp,
uint32_t freq_compensation, uint32_t output_clock_divisor)
{
uint32_t tmr_ctrl;
int i;
fman_rtc_timers_soft_reset(regs);
/* Set the source clock */
switch (cfg->src_clk) {
case E_FMAN_RTC_SOURCE_CLOCK_SYSTEM:
tmr_ctrl = FMAN_RTC_TMR_CTRL_CKSEL_MAC_CLK;
break;
case E_FMAN_RTC_SOURCE_CLOCK_OSCILATOR:
tmr_ctrl = FMAN_RTC_TMR_CTRL_CKSEL_OSC_CLK;
break;
default:
/* Use a clock from the External TMR reference clock.*/
tmr_ctrl = FMAN_RTC_TMR_CTRL_CKSEL_EXT_CLK;
break;
}
/* whatever period the user picked, the timestamp will advance in '1'
* every time the period passed. */
tmr_ctrl |= ((1 << FMAN_RTC_TMR_CTRL_TCLK_PERIOD_SHIFT) &
FMAN_RTC_TMR_CTRL_TCLK_PERIOD_MASK);
if (cfg->invert_input_clk_phase)
tmr_ctrl |= FMAN_RTC_TMR_CTRL_CIPH;
if (cfg->invert_output_clk_phase)
tmr_ctrl |= FMAN_RTC_TMR_CTRL_COPH;
for (i = 0; i < num_alarms; i++) {
if (cfg->alarm_polarity[i] ==
E_FMAN_RTC_ALARM_POLARITY_ACTIVE_LOW)
tmr_ctrl |= (FMAN_RTC_TMR_CTRL_ALMP1 >> i);
}
for (i = 0; i < num_ext_triggers; i++)
if (cfg->trigger_polarity[i] ==
E_FMAN_RTC_TRIGGER_ON_FALLING_EDGE)
tmr_ctrl |= (FMAN_RTC_TMR_CTRL_ETEP1 << i);
if (!cfg->timer_slave_mode && cfg->bypass)
tmr_ctrl |= FMAN_RTC_TMR_CTRL_BYP;
fman_rtc_set_timer_ctrl(regs, tmr_ctrl);
if (init_freq_comp)
fman_rtc_set_frequency_compensation(regs, freq_compensation);
/* Clear TMR_ALARM registers */
for (i = 0; i < num_alarms; i++)
fman_rtc_set_timer_alarm(regs, i, 0xFFFFFFFFFFFFFFFFLL);
/* Clear TMR_TEVENT */
fman_rtc_ack_event(regs, FMAN_RTC_TMR_TEVENT_ALL);
/* Initialize TMR_TEMASK */
fman_rtc_set_interrupt_mask(regs, 0);
/* Clear TMR_FIPER registers */
for (i = 0; i < num_fipers; i++)
fman_rtc_set_timer_fiper(regs, i, 0xFFFFFFFF);
/* Initialize TMR_PRSC */
iowrite32be(output_clock_divisor, &regs->tmr_prsc);
/* Clear TMR_OFF */
fman_rtc_set_timer_offset(regs, 0);
}
bool fman_rtc_is_enabled(struct rtc_regs *regs)
{
return (bool)(fman_rtc_get_timer_ctrl(regs) & FMAN_RTC_TMR_CTRL_TE);
}
void fman_rtc_enable(struct rtc_regs *regs, bool reset_clock)
{
uint32_t tmr_ctrl = fman_rtc_get_timer_ctrl(regs);
/* TODO check that no timestamping MACs are working in this stage. */
if (reset_clock) {
fman_rtc_set_timer_ctrl(regs, (tmr_ctrl | FMAN_RTC_TMR_CTRL_TMSR));
udelay(10);
/* Clear TMR_OFF */
fman_rtc_set_timer_offset(regs, 0);
}
fman_rtc_set_timer_ctrl(regs, (tmr_ctrl | FMAN_RTC_TMR_CTRL_TE));
}
void fman_rtc_disable(struct rtc_regs *regs)
{
fman_rtc_set_timer_ctrl(regs, (fman_rtc_get_timer_ctrl(regs)
& ~(FMAN_RTC_TMR_CTRL_TE)));
}
void fman_rtc_clear_periodic_pulse(struct rtc_regs *regs, int id)
{
uint32_t tmp_reg;
if (id == 0)
tmp_reg = FMAN_RTC_TMR_TEVENT_PP1;
else
tmp_reg = FMAN_RTC_TMR_TEVENT_PP2;
fman_rtc_disable_interupt(regs, tmp_reg);
tmp_reg = fman_rtc_get_timer_ctrl(regs);
if (tmp_reg & FMAN_RTC_TMR_CTRL_FS)
fman_rtc_set_timer_ctrl(regs, tmp_reg & ~FMAN_RTC_TMR_CTRL_FS);
fman_rtc_set_timer_fiper(regs, id, 0xFFFFFFFF);
}
void fman_rtc_clear_external_trigger(struct rtc_regs *regs, int id)
{
uint32_t tmpReg, tmp_ctrl;
if (id == 0)
tmpReg = FMAN_RTC_TMR_TEVENT_ETS1;
else
tmpReg = FMAN_RTC_TMR_TEVENT_ETS2;
fman_rtc_disable_interupt(regs, tmpReg);
if (id == 0)
tmpReg = FMAN_RTC_TMR_CTRL_PP1L;
else
tmpReg = FMAN_RTC_TMR_CTRL_PP2L;
tmp_ctrl = fman_rtc_get_timer_ctrl(regs);
if (tmp_ctrl & tmpReg)
fman_rtc_set_timer_ctrl(regs, tmp_ctrl & ~tmpReg);
}
void fman_rtc_set_alarm(struct rtc_regs *regs, int id, uint32_t val, bool enable)
{
uint32_t tmpReg;
fman_rtc_set_timer_alarm(regs, id, val);
if (enable) {
if (id == 0)
tmpReg = FMAN_RTC_TMR_TEVENT_ALM1;
else
tmpReg = FMAN_RTC_TMR_TEVENT_ALM2;
fman_rtc_enable_interupt(regs, tmpReg);
}
}
void fman_rtc_set_periodic_pulse(struct rtc_regs *regs, int id, uint32_t val,
bool enable)
{
uint32_t tmpReg;
fman_rtc_set_timer_fiper(regs, id, val);
if (enable) {
if (id == 0)
tmpReg = FMAN_RTC_TMR_TEVENT_PP1;
else
tmpReg = FMAN_RTC_TMR_TEVENT_PP2;
fman_rtc_enable_interupt(regs, tmpReg);
}
}
void fman_rtc_set_ext_trigger(struct rtc_regs *regs, int id, bool enable,
bool use_pulse_as_input)
{
uint32_t tmpReg;
if (enable) {
if (id == 0)
tmpReg = FMAN_RTC_TMR_TEVENT_ETS1;
else
tmpReg = FMAN_RTC_TMR_TEVENT_ETS2;
fman_rtc_enable_interupt(regs, tmpReg);
}
if (use_pulse_as_input) {
if (id == 0)
tmpReg = FMAN_RTC_TMR_CTRL_PP1L;
else
tmpReg = FMAN_RTC_TMR_CTRL_PP2L;
fman_rtc_set_timer_ctrl(regs, fman_rtc_get_timer_ctrl(regs) | tmpReg);
}
}

15
drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/SP/Makefile Normal file
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#
# Makefile for the Freescale Ethernet controllers
#
ccflags-y += -DVERSION=\"\"
#
#Include netcomm SW specific definitions
include $(srctree)/drivers/net/ethernet/freescale/sdk_fman/ncsw_config.mk
NCSW_FM_INC = $(srctree)/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/inc
ccflags-y += -I$(NCSW_FM_INC)
obj-y += fsl-ncsw-sp.o
fsl-ncsw-sp-objs := fm_sp.o fman_sp.o

757
drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/SP/fm_sp.c Normal file
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/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_sp.c
@Description FM PCD Storage profile ...
*//***************************************************************************/
#include "std_ext.h"
#include "error_ext.h"
#include "string_ext.h"
#include "debug_ext.h"
#include "net_ext.h"
#include "fm_vsp_ext.h"
#include "fm_sp.h"
#include "fm_common.h"
#include "fsl_fman_sp.h"
#if (DPAA_VERSION >= 11)
static t_Error CheckParamsGeneratedInternally(t_FmVspEntry *p_FmVspEntry)
{
t_Error err = E_OK;
if ((err = FmSpCheckIntContextParams(&p_FmVspEntry->intContext))!= E_OK)
RETURN_ERROR(MAJOR, err, NO_MSG);
if ((err = FmSpCheckBufMargins(&p_FmVspEntry->bufMargins)) != E_OK)
RETURN_ERROR(MAJOR, err, NO_MSG);
return err;
}
static t_Error CheckParams(t_FmVspEntry *p_FmVspEntry)
{
t_Error err = E_OK;
SANITY_CHECK_RETURN_ERROR(p_FmVspEntry, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmVspEntry->p_FmVspEntryDriverParams, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmVspEntry->h_Fm, E_INVALID_HANDLE);
if ((err = FmSpCheckBufPoolsParams(&p_FmVspEntry->p_FmVspEntryDriverParams->extBufPools,
p_FmVspEntry->p_FmVspEntryDriverParams->p_BackupBmPools,
p_FmVspEntry->p_FmVspEntryDriverParams->p_BufPoolDepletion)) != E_OK)
RETURN_ERROR(MAJOR, err, NO_MSG);
if (p_FmVspEntry->p_FmVspEntryDriverParams->liodnOffset & ~FM_LIODN_OFFSET_MASK)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("liodnOffset is larger than %d", FM_LIODN_OFFSET_MASK+1));
err = FmVSPCheckRelativeProfile(p_FmVspEntry->h_Fm,
p_FmVspEntry->portType,
p_FmVspEntry->portId,
p_FmVspEntry->relativeProfileId);
return err;
}
#endif /* (DPAA_VERSION >= 11) */
/*****************************************************************************/
/* Inter-module API routines */
/*****************************************************************************/
void FmSpSetBufPoolsInAscOrderOfBufSizes(t_FmExtPools *p_FmExtPools,
uint8_t *orderedArray,
uint16_t *sizesArray)
{
uint16_t bufSize = 0;
int i=0, j=0, k=0;
/* First we copy the external buffers pools information to an ordered local array */
for (i=0;i<p_FmExtPools->numOfPoolsUsed;i++)
{
/* get pool size */
bufSize = p_FmExtPools->extBufPool[i].size;
/* keep sizes in an array according to poolId for direct access */
sizesArray[p_FmExtPools->extBufPool[i].id] = bufSize;
/* save poolId in an ordered array according to size */
for (j=0;j<=i;j++)
{
/* this is the next free place in the array */
if (j==i)
orderedArray[i] = p_FmExtPools->extBufPool[i].id;
else
{
/* find the right place for this poolId */
if (bufSize < sizesArray[orderedArray[j]])
{
/* move the poolIds one place ahead to make room for this poolId */
for (k=i;k>j;k--)
orderedArray[k] = orderedArray[k-1];
/* now k==j, this is the place for the new size */
orderedArray[k] = p_FmExtPools->extBufPool[i].id;
break;
}
}
}
}
}
t_Error FmSpCheckBufPoolsParams(t_FmExtPools *p_FmExtPools,
t_FmBackupBmPools *p_FmBackupBmPools,
t_FmBufPoolDepletion *p_FmBufPoolDepletion)
{
int i = 0, j = 0;
bool found;
uint8_t count = 0;
if (p_FmExtPools)
{
if (p_FmExtPools->numOfPoolsUsed > FM_PORT_MAX_NUM_OF_EXT_POOLS)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("numOfPoolsUsed can't be larger than %d", FM_PORT_MAX_NUM_OF_EXT_POOLS));
for (i=0;i<p_FmExtPools->numOfPoolsUsed;i++)
{
if (p_FmExtPools->extBufPool[i].id >= BM_MAX_NUM_OF_POOLS)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("extBufPools.extBufPool[%d].id can't be larger than %d", i, BM_MAX_NUM_OF_POOLS));
if (!p_FmExtPools->extBufPool[i].size)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("extBufPools.extBufPool[%d].size is 0", i));
}
}
if (!p_FmExtPools && (p_FmBackupBmPools || p_FmBufPoolDepletion))
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("backupBmPools ot bufPoolDepletion can not be defined without external pools"));
/* backup BM pools indication is valid only for some chip derivatives
(limited by the config routine) */
if (p_FmBackupBmPools)
{
if (p_FmBackupBmPools->numOfBackupPools >= p_FmExtPools->numOfPoolsUsed)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("p_BackupBmPools must be smaller than extBufPools.numOfPoolsUsed"));
found = FALSE;
for (i = 0;i<p_FmBackupBmPools->numOfBackupPools;i++)
{
for (j=0;j<p_FmExtPools->numOfPoolsUsed;j++)
{
if (p_FmBackupBmPools->poolIds[i] == p_FmExtPools->extBufPool[j].id)
{
found = TRUE;
break;
}
}
if (!found)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("All p_BackupBmPools.poolIds must be included in extBufPools.extBufPool[n].id"));
else
found = FALSE;
}
}
/* up to extBufPools.numOfPoolsUsed pools may be defined */
if (p_FmBufPoolDepletion && p_FmBufPoolDepletion->poolsGrpModeEnable)
{
if ((p_FmBufPoolDepletion->numOfPools > p_FmExtPools->numOfPoolsUsed))
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("bufPoolDepletion.numOfPools can't be larger than %d and can't be larger than numOfPoolsUsed", FM_PORT_MAX_NUM_OF_EXT_POOLS));
if (!p_FmBufPoolDepletion->numOfPools)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("bufPoolDepletion.numOfPoolsToConsider can not be 0 when poolsGrpModeEnable=TRUE"));
found = FALSE;
count = 0;
/* for each pool that is in poolsToConsider, check if it is defined
in extBufPool */
for (i=0;i<BM_MAX_NUM_OF_POOLS;i++)
{
if (p_FmBufPoolDepletion->poolsToConsider[i])
{
for (j=0;j<p_FmExtPools->numOfPoolsUsed;j++)
{
if (i == p_FmExtPools->extBufPool[j].id)
{
found = TRUE;
count++;
break;
}
}
if (!found)
RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Pools selected for depletion are not used."));
else
found = FALSE;
}
}
/* check that the number of pools that we have checked is equal to the number announced by the user */
if (count != p_FmBufPoolDepletion->numOfPools)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("bufPoolDepletion.numOfPools is larger than the number of pools defined."));
}
if (p_FmBufPoolDepletion && p_FmBufPoolDepletion->singlePoolModeEnable)
{
/* calculate vector for number of pools depletion */
found = FALSE;
count = 0;
for (i=0;i<BM_MAX_NUM_OF_POOLS;i++)
{
if (p_FmBufPoolDepletion->poolsToConsiderForSingleMode[i])
{
for (j=0;j<p_FmExtPools->numOfPoolsUsed;j++)
{
if (i == p_FmExtPools->extBufPool[j].id)
{
found = TRUE;
count++;
break;
}
}
if (!found)
RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Pools selected for depletion are not used."));
else
found = FALSE;
}
}
if (!count)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("No pools defined for single buffer mode pool depletion."));
}
return E_OK;
}
t_Error FmSpCheckIntContextParams(t_FmSpIntContextDataCopy *p_FmSpIntContextDataCopy)
{
/* Check that divisible by 16 and not larger than 240 */
if (p_FmSpIntContextDataCopy->intContextOffset >MAX_INT_OFFSET)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("intContext.intContextOffset can't be larger than %d", MAX_INT_OFFSET));
if (p_FmSpIntContextDataCopy->intContextOffset % OFFSET_UNITS)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("intContext.intContextOffset has to be divisible by %d", OFFSET_UNITS));
/* check that ic size+ic internal offset, does not exceed ic block size */
if (p_FmSpIntContextDataCopy->size + p_FmSpIntContextDataCopy->intContextOffset > MAX_IC_SIZE)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("intContext.size + intContext.intContextOffset has to be smaller than %d", MAX_IC_SIZE));
/* Check that divisible by 16 and not larger than 256 */
if (p_FmSpIntContextDataCopy->size % OFFSET_UNITS)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("intContext.size has to be divisible by %d", OFFSET_UNITS));
/* Check that divisible by 16 and not larger than 4K */
if (p_FmSpIntContextDataCopy->extBufOffset > MAX_EXT_OFFSET)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("intContext.extBufOffset can't be larger than %d", MAX_EXT_OFFSET));
if (p_FmSpIntContextDataCopy->extBufOffset % OFFSET_UNITS)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("intContext.extBufOffset has to be divisible by %d", OFFSET_UNITS));
return E_OK;
}
t_Error FmSpCheckBufMargins(t_FmSpBufMargins *p_FmSpBufMargins)
{
/* Check the margin definition */
if (p_FmSpBufMargins->startMargins > MAX_EXT_BUFFER_OFFSET)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("bufMargins.startMargins can't be larger than %d", MAX_EXT_BUFFER_OFFSET));
if (p_FmSpBufMargins->endMargins > MAX_EXT_BUFFER_OFFSET)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("bufMargins.endMargins can't be larger than %d", MAX_EXT_BUFFER_OFFSET));
return E_OK;
}
t_Error FmSpBuildBufferStructure(t_FmSpIntContextDataCopy *p_FmSpIntContextDataCopy,
t_FmBufferPrefixContent *p_BufferPrefixContent,
t_FmSpBufMargins *p_FmSpBufMargins,
t_FmSpBufferOffsets *p_FmSpBufferOffsets,
uint8_t *internalBufferOffset)
{
uint32_t tmp;
SANITY_CHECK_RETURN_ERROR(p_FmSpIntContextDataCopy, E_INVALID_VALUE);
ASSERT_COND(p_FmSpIntContextDataCopy);
ASSERT_COND(p_BufferPrefixContent);
ASSERT_COND(p_FmSpBufMargins);
ASSERT_COND(p_FmSpBufferOffsets);
/* Align start of internal context data to 16 byte */
p_FmSpIntContextDataCopy->extBufOffset =
(uint16_t)((p_BufferPrefixContent->privDataSize & (OFFSET_UNITS-1)) ?
((p_BufferPrefixContent->privDataSize + OFFSET_UNITS) & ~(uint16_t)(OFFSET_UNITS-1)) :
p_BufferPrefixContent->privDataSize);
/* Translate margin and intContext params to FM parameters */
/* Initialize with illegal value. Later we'll set legal values. */
p_FmSpBufferOffsets->prsResultOffset = (uint32_t)ILLEGAL_BASE;
p_FmSpBufferOffsets->timeStampOffset = (uint32_t)ILLEGAL_BASE;
p_FmSpBufferOffsets->hashResultOffset= (uint32_t)ILLEGAL_BASE;
p_FmSpBufferOffsets->pcdInfoOffset = (uint32_t)ILLEGAL_BASE;
/* Internally the driver supports 4 options
1. prsResult/timestamp/hashResult selection (in fact 8 options, but for simplicity we'll
relate to it as 1).
2. All IC context (from AD) not including debug.*/
/* This 'if' covers option 2. We copy from beginning of context. */
if (p_BufferPrefixContent->passAllOtherPCDInfo)
{
p_FmSpIntContextDataCopy->size = 128; /* must be aligned to 16 */
/* Start copying data after 16 bytes (FD) from the beginning of the internal context */
p_FmSpIntContextDataCopy->intContextOffset = 16;
if (p_BufferPrefixContent->passAllOtherPCDInfo)
p_FmSpBufferOffsets->pcdInfoOffset = p_FmSpIntContextDataCopy->extBufOffset;
if (p_BufferPrefixContent->passPrsResult)
p_FmSpBufferOffsets->prsResultOffset =
(uint32_t)(p_FmSpIntContextDataCopy->extBufOffset + 16);
if (p_BufferPrefixContent->passTimeStamp)
p_FmSpBufferOffsets->timeStampOffset =
(uint32_t)(p_FmSpIntContextDataCopy->extBufOffset + 48);
if (p_BufferPrefixContent->passHashResult)
p_FmSpBufferOffsets->hashResultOffset =
(uint32_t)(p_FmSpIntContextDataCopy->extBufOffset + 56);
}
else
{
/* This case covers the options under 1 */
/* Copy size must be in 16-byte granularity. */
p_FmSpIntContextDataCopy->size =
(uint16_t)((p_BufferPrefixContent->passPrsResult ? 32 : 0) +
((p_BufferPrefixContent->passTimeStamp ||
p_BufferPrefixContent->passHashResult) ? 16 : 0));
/* Align start of internal context data to 16 byte */
p_FmSpIntContextDataCopy->intContextOffset =
(uint8_t)(p_BufferPrefixContent->passPrsResult ? 32 :
((p_BufferPrefixContent->passTimeStamp ||
p_BufferPrefixContent->passHashResult) ? 64 : 0));
if (p_BufferPrefixContent->passPrsResult)
p_FmSpBufferOffsets->prsResultOffset = p_FmSpIntContextDataCopy->extBufOffset;
if (p_BufferPrefixContent->passTimeStamp)
p_FmSpBufferOffsets->timeStampOffset = p_BufferPrefixContent->passPrsResult ?
(p_FmSpIntContextDataCopy->extBufOffset + sizeof(t_FmPrsResult)) :
p_FmSpIntContextDataCopy->extBufOffset;
if (p_BufferPrefixContent->passHashResult)
/* If PR is not requested, whether TS is requested or not, IC will be copied from TS */
p_FmSpBufferOffsets->hashResultOffset = p_BufferPrefixContent->passPrsResult ?
(p_FmSpIntContextDataCopy->extBufOffset + sizeof(t_FmPrsResult) + 8) :
p_FmSpIntContextDataCopy->extBufOffset + 8;
}
if (p_FmSpIntContextDataCopy->size)
p_FmSpBufMargins->startMargins =
(uint16_t)(p_FmSpIntContextDataCopy->extBufOffset +
p_FmSpIntContextDataCopy->size);
else
/* No Internal Context passing, STartMargin is immediately after privateInfo */
p_FmSpBufMargins->startMargins = p_BufferPrefixContent->privDataSize;
/* save extra space for manip in both external and internal buffers */
if (p_BufferPrefixContent->manipExtraSpace)
{
uint8_t extraSpace;
#ifdef FM_CAPWAP_SUPPORT
if ((p_BufferPrefixContent->manipExtraSpace + CAPWAP_FRAG_EXTRA_SPACE) >= 256)
RETURN_ERROR(MAJOR, E_INVALID_VALUE,
("p_BufferPrefixContent->manipExtraSpace should be less than %d",
256-CAPWAP_FRAG_EXTRA_SPACE));
extraSpace = (uint8_t)(p_BufferPrefixContent->manipExtraSpace + CAPWAP_FRAG_EXTRA_SPACE);
#else
extraSpace = p_BufferPrefixContent->manipExtraSpace;
#endif /* FM_CAPWAP_SUPPORT */
p_FmSpBufferOffsets->manipOffset = p_FmSpBufMargins->startMargins;
p_FmSpBufMargins->startMargins += extraSpace;
*internalBufferOffset = extraSpace;
}
/* align data start */
tmp = (uint32_t)(p_FmSpBufMargins->startMargins % p_BufferPrefixContent->dataAlign);
if (tmp)
p_FmSpBufMargins->startMargins += (p_BufferPrefixContent->dataAlign-tmp);
p_FmSpBufferOffsets->dataOffset = p_FmSpBufMargins->startMargins;
return E_OK;
}
/*********************** End of inter-module routines ************************/
#if (DPAA_VERSION >= 11)
/*****************************************************************************/
/* API routines */
/*****************************************************************************/
t_Handle FM_VSP_Config(t_FmVspParams *p_FmVspParams)
{
t_FmVspEntry *p_FmVspEntry = NULL;
struct fm_storage_profile_params fm_vsp_params;
p_FmVspEntry = (t_FmVspEntry *)XX_Malloc(sizeof(t_FmVspEntry));
if (!p_FmVspEntry)
{
REPORT_ERROR(MAJOR, E_NO_MEMORY, ("p_StorageProfile allocation failed"));
return NULL;
}
memset(p_FmVspEntry, 0, sizeof(t_FmVspEntry));
p_FmVspEntry->p_FmVspEntryDriverParams = (t_FmVspEntryDriverParams *)XX_Malloc(sizeof(t_FmVspEntryDriverParams));
if (!p_FmVspEntry->p_FmVspEntryDriverParams)
{
REPORT_ERROR(MAJOR, E_NO_MEMORY, ("p_StorageProfile allocation failed"));
XX_Free(p_FmVspEntry);
return NULL;
}
memset(p_FmVspEntry->p_FmVspEntryDriverParams, 0, sizeof(t_FmVspEntryDriverParams));
fman_vsp_defconfig(&fm_vsp_params);
p_FmVspEntry->p_FmVspEntryDriverParams->dmaHeaderCacheAttr = fm_vsp_params.header_cache_attr;
p_FmVspEntry->p_FmVspEntryDriverParams->dmaIntContextCacheAttr = fm_vsp_params.int_context_cache_attr;
p_FmVspEntry->p_FmVspEntryDriverParams->dmaScatterGatherCacheAttr = fm_vsp_params.scatter_gather_cache_attr;
p_FmVspEntry->p_FmVspEntryDriverParams->dmaSwapData = fm_vsp_params.dma_swap_data;
p_FmVspEntry->p_FmVspEntryDriverParams->dmaWriteOptimize = fm_vsp_params.dma_write_optimize;
p_FmVspEntry->p_FmVspEntryDriverParams->noScatherGather = fm_vsp_params.no_scather_gather;
p_FmVspEntry->p_FmVspEntryDriverParams->bufferPrefixContent.privDataSize = DEFAULT_FM_SP_bufferPrefixContent_privDataSize;
p_FmVspEntry->p_FmVspEntryDriverParams->bufferPrefixContent.passPrsResult= DEFAULT_FM_SP_bufferPrefixContent_passPrsResult;
p_FmVspEntry->p_FmVspEntryDriverParams->bufferPrefixContent.passTimeStamp= DEFAULT_FM_SP_bufferPrefixContent_passTimeStamp;
p_FmVspEntry->p_FmVspEntryDriverParams->bufferPrefixContent.passAllOtherPCDInfo
= DEFAULT_FM_SP_bufferPrefixContent_passTimeStamp;
p_FmVspEntry->p_FmVspEntryDriverParams->bufferPrefixContent.dataAlign = DEFAULT_FM_SP_bufferPrefixContent_dataAlign;
p_FmVspEntry->p_FmVspEntryDriverParams->liodnOffset = p_FmVspParams->liodnOffset;
memcpy(&p_FmVspEntry->p_FmVspEntryDriverParams->extBufPools, &p_FmVspParams->extBufPools, sizeof(t_FmExtPools));
p_FmVspEntry->h_Fm = p_FmVspParams->h_Fm;
p_FmVspEntry->portType = p_FmVspParams->portParams.portType;
p_FmVspEntry->portId = p_FmVspParams->portParams.portId;
p_FmVspEntry->relativeProfileId = p_FmVspParams->relativeProfileId;
return p_FmVspEntry;
}
t_Error FM_VSP_Init(t_Handle h_FmVsp)
{
t_FmVspEntry *p_FmVspEntry = (t_FmVspEntry *)h_FmVsp;
struct fm_storage_profile_params fm_vsp_params;
uint8_t orderedArray[FM_PORT_MAX_NUM_OF_EXT_POOLS];
uint16_t sizesArray[BM_MAX_NUM_OF_POOLS];
t_Error err;
uint16_t absoluteProfileId = 0;
int i = 0;
SANITY_CHECK_RETURN_ERROR(p_FmVspEntry, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmVspEntry->p_FmVspEntryDriverParams,E_INVALID_HANDLE);
CHECK_INIT_PARAMETERS(p_FmVspEntry, CheckParams);
memset(&orderedArray, 0, sizeof(uint8_t) * FM_PORT_MAX_NUM_OF_EXT_POOLS);
memset(&sizesArray, 0, sizeof(uint16_t) * BM_MAX_NUM_OF_POOLS);
err = FmSpBuildBufferStructure(&p_FmVspEntry->intContext,
&p_FmVspEntry->p_FmVspEntryDriverParams->bufferPrefixContent,
&p_FmVspEntry->bufMargins,
&p_FmVspEntry->bufferOffsets,
&p_FmVspEntry->internalBufferOffset);
if (err != E_OK)
RETURN_ERROR(MAJOR, err, NO_MSG);
err = CheckParamsGeneratedInternally(p_FmVspEntry);
if (err != E_OK)
RETURN_ERROR(MAJOR, err, NO_MSG);
p_FmVspEntry->p_FmSpRegsBase =
(struct fm_pcd_storage_profile_regs *)FmGetVSPBaseAddr(p_FmVspEntry->h_Fm);
if (!p_FmVspEntry->p_FmSpRegsBase)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("impossible to initialize SpRegsBase"));
/* order external buffer pools in ascending order of buffer pools sizes */
FmSpSetBufPoolsInAscOrderOfBufSizes(&(p_FmVspEntry->p_FmVspEntryDriverParams)->extBufPools,
orderedArray,
sizesArray);
p_FmVspEntry->extBufPools.numOfPoolsUsed =
p_FmVspEntry->p_FmVspEntryDriverParams->extBufPools.numOfPoolsUsed;
for (i = 0; i < p_FmVspEntry->extBufPools.numOfPoolsUsed; i++)
{
p_FmVspEntry->extBufPools.extBufPool[i].id = orderedArray[i];
p_FmVspEntry->extBufPools.extBufPool[i].size = sizesArray[orderedArray[i]];
}
/* on user responsibility to fill it according requirement */
memset(&fm_vsp_params, 0, sizeof(struct fm_storage_profile_params));
fm_vsp_params.dma_swap_data = p_FmVspEntry->p_FmVspEntryDriverParams->dmaSwapData;
fm_vsp_params.int_context_cache_attr = p_FmVspEntry->p_FmVspEntryDriverParams->dmaIntContextCacheAttr;
fm_vsp_params.header_cache_attr = p_FmVspEntry->p_FmVspEntryDriverParams->dmaHeaderCacheAttr;
fm_vsp_params.scatter_gather_cache_attr = p_FmVspEntry->p_FmVspEntryDriverParams->dmaScatterGatherCacheAttr;
fm_vsp_params.dma_write_optimize = p_FmVspEntry->p_FmVspEntryDriverParams->dmaWriteOptimize;
fm_vsp_params.liodn_offset = p_FmVspEntry->p_FmVspEntryDriverParams->liodnOffset;
fm_vsp_params.no_scather_gather = p_FmVspEntry->p_FmVspEntryDriverParams->noScatherGather;
if (p_FmVspEntry->p_FmVspEntryDriverParams->p_BufPoolDepletion)
{
fm_vsp_params.buf_pool_depletion.buf_pool_depletion_enabled = TRUE;
fm_vsp_params.buf_pool_depletion.pools_grp_mode_enable = p_FmVspEntry->p_FmVspEntryDriverParams->p_BufPoolDepletion->poolsGrpModeEnable;
fm_vsp_params.buf_pool_depletion.num_pools = p_FmVspEntry->p_FmVspEntryDriverParams->p_BufPoolDepletion->numOfPools;
fm_vsp_params.buf_pool_depletion.pools_to_consider = p_FmVspEntry->p_FmVspEntryDriverParams->p_BufPoolDepletion->poolsToConsider;
fm_vsp_params.buf_pool_depletion.single_pool_mode_enable = p_FmVspEntry->p_FmVspEntryDriverParams->p_BufPoolDepletion->singlePoolModeEnable;
fm_vsp_params.buf_pool_depletion.pools_to_consider_for_single_mode = p_FmVspEntry->p_FmVspEntryDriverParams->p_BufPoolDepletion->poolsToConsiderForSingleMode;
fm_vsp_params.buf_pool_depletion.has_pfc_priorities = TRUE;
fm_vsp_params.buf_pool_depletion.pfc_priorities_en = p_FmVspEntry->p_FmVspEntryDriverParams->p_BufPoolDepletion->pfcPrioritiesEn;
}
else
fm_vsp_params.buf_pool_depletion.buf_pool_depletion_enabled = FALSE;
if (p_FmVspEntry->p_FmVspEntryDriverParams->p_BackupBmPools)
{
fm_vsp_params.backup_pools.num_backup_pools = p_FmVspEntry->p_FmVspEntryDriverParams->p_BackupBmPools->numOfBackupPools;
fm_vsp_params.backup_pools.pool_ids = p_FmVspEntry->p_FmVspEntryDriverParams->p_BackupBmPools->poolIds;
}
else
fm_vsp_params.backup_pools.num_backup_pools = 0;
fm_vsp_params.fm_ext_pools.num_pools_used = p_FmVspEntry->extBufPools.numOfPoolsUsed;
fm_vsp_params.fm_ext_pools.ext_buf_pool = (struct fman_ext_pool_params*)&p_FmVspEntry->extBufPools.extBufPool;
fm_vsp_params.buf_margins = (struct fman_sp_buf_margins*)&p_FmVspEntry->bufMargins;
fm_vsp_params.int_context = (struct fman_sp_int_context_data_copy*)&p_FmVspEntry->intContext;
/* no check on err - it was checked earlier */
FmVSPGetAbsoluteProfileId(p_FmVspEntry->h_Fm,
p_FmVspEntry->portType,
p_FmVspEntry->portId,
p_FmVspEntry->relativeProfileId,
&absoluteProfileId);
ASSERT_COND(p_FmVspEntry->p_FmSpRegsBase);
ASSERT_COND(fm_vsp_params.int_context);
ASSERT_COND(fm_vsp_params.buf_margins);
ASSERT_COND((absoluteProfileId <= FM_VSP_MAX_NUM_OF_ENTRIES));
/* Set all registers related to VSP */
fman_vsp_init(p_FmVspEntry->p_FmSpRegsBase, absoluteProfileId, &fm_vsp_params,FM_PORT_MAX_NUM_OF_EXT_POOLS, BM_MAX_NUM_OF_POOLS, FM_MAX_NUM_OF_PFC_PRIORITIES);
p_FmVspEntry->absoluteSpId = absoluteProfileId;
if (p_FmVspEntry->p_FmVspEntryDriverParams)
XX_Free(p_FmVspEntry->p_FmVspEntryDriverParams);
p_FmVspEntry->p_FmVspEntryDriverParams = NULL;
return E_OK;
}
t_Error FM_VSP_Free(t_Handle h_FmVsp)
{
t_FmVspEntry *p_FmVspEntry = (t_FmVspEntry *)h_FmVsp;
SANITY_CHECK_RETURN_ERROR(h_FmVsp, E_INVALID_HANDLE);
XX_Free(p_FmVspEntry);
return E_OK;
}
t_Error FM_VSP_ConfigBufferPrefixContent(t_Handle h_FmVsp, t_FmBufferPrefixContent *p_FmBufferPrefixContent)
{
t_FmVspEntry *p_FmVspEntry = (t_FmVspEntry*)h_FmVsp;
SANITY_CHECK_RETURN_ERROR(p_FmVspEntry, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmVspEntry->p_FmVspEntryDriverParams, E_INVALID_HANDLE);
memcpy(&p_FmVspEntry->p_FmVspEntryDriverParams->bufferPrefixContent, p_FmBufferPrefixContent, sizeof(t_FmBufferPrefixContent));
/* if dataAlign was not initialized by user, we return to driver's default */
if (!p_FmVspEntry->p_FmVspEntryDriverParams->bufferPrefixContent.dataAlign)
p_FmVspEntry->p_FmVspEntryDriverParams->bufferPrefixContent.dataAlign = DEFAULT_FM_SP_bufferPrefixContent_dataAlign;
return E_OK;
}
t_Error FM_VSP_ConfigDmaSwapData(t_Handle h_FmVsp, e_FmDmaSwapOption swapData)
{
t_FmVspEntry *p_FmVspEntry = (t_FmVspEntry*)h_FmVsp;
SANITY_CHECK_RETURN_ERROR(p_FmVspEntry, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmVspEntry->p_FmVspEntryDriverParams, E_INVALID_HANDLE);
p_FmVspEntry->p_FmVspEntryDriverParams->dmaSwapData = swapData;
return E_OK;
}
t_Error FM_VSP_ConfigDmaIcCacheAttr(t_Handle h_FmVsp, e_FmDmaCacheOption intContextCacheAttr)
{
t_FmVspEntry *p_FmVspEntry = (t_FmVspEntry*)h_FmVsp;
SANITY_CHECK_RETURN_ERROR(p_FmVspEntry, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmVspEntry->p_FmVspEntryDriverParams, E_INVALID_HANDLE);
p_FmVspEntry->p_FmVspEntryDriverParams->dmaIntContextCacheAttr = intContextCacheAttr;
return E_OK;
}
t_Error FM_VSP_ConfigDmaHdrAttr(t_Handle h_FmVsp, e_FmDmaCacheOption headerCacheAttr)
{
t_FmVspEntry *p_FmVspEntry = (t_FmVspEntry*)h_FmVsp;
SANITY_CHECK_RETURN_ERROR(p_FmVspEntry, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmVspEntry->p_FmVspEntryDriverParams, E_INVALID_HANDLE);
p_FmVspEntry->p_FmVspEntryDriverParams->dmaHeaderCacheAttr = headerCacheAttr;
return E_OK;
}
t_Error FM_VSP_ConfigDmaScatterGatherAttr(t_Handle h_FmVsp, e_FmDmaCacheOption scatterGatherCacheAttr)
{
t_FmVspEntry *p_FmVspEntry = (t_FmVspEntry*)h_FmVsp;
SANITY_CHECK_RETURN_ERROR(p_FmVspEntry, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmVspEntry->p_FmVspEntryDriverParams, E_INVALID_HANDLE);
p_FmVspEntry->p_FmVspEntryDriverParams->dmaScatterGatherCacheAttr = scatterGatherCacheAttr;
return E_OK;
}
t_Error FM_VSP_ConfigDmaWriteOptimize(t_Handle h_FmVsp, bool optimize)
{
t_FmVspEntry *p_FmVspEntry = (t_FmVspEntry*)h_FmVsp;
SANITY_CHECK_RETURN_ERROR(p_FmVspEntry, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmVspEntry->p_FmVspEntryDriverParams, E_INVALID_HANDLE);
p_FmVspEntry->p_FmVspEntryDriverParams->dmaWriteOptimize = optimize;
return E_OK;
}
t_Error FM_VSP_ConfigNoScatherGather(t_Handle h_FmVsp, bool noScatherGather)
{
t_FmVspEntry *p_FmVspEntry = (t_FmVspEntry*)h_FmVsp;
SANITY_CHECK_RETURN_ERROR(p_FmVspEntry, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmVspEntry->p_FmVspEntryDriverParams, E_INVALID_HANDLE);
p_FmVspEntry->p_FmVspEntryDriverParams->noScatherGather = noScatherGather;
return E_OK;
}
t_Error FM_VSP_ConfigPoolDepletion(t_Handle h_FmVsp, t_FmBufPoolDepletion *p_BufPoolDepletion)
{
t_FmVspEntry *p_FmVspEntry = (t_FmVspEntry*)h_FmVsp;
SANITY_CHECK_RETURN_ERROR(h_FmVsp, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmVspEntry->p_FmVspEntryDriverParams, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_BufPoolDepletion, E_INVALID_HANDLE);
p_FmVspEntry->p_FmVspEntryDriverParams->p_BufPoolDepletion = (t_FmBufPoolDepletion *)XX_Malloc(sizeof(t_FmBufPoolDepletion));
if (!p_FmVspEntry->p_FmVspEntryDriverParams->p_BufPoolDepletion)
RETURN_ERROR(MAJOR, E_NO_MEMORY, ("p_BufPoolDepletion allocation failed"));
memcpy(p_FmVspEntry->p_FmVspEntryDriverParams->p_BufPoolDepletion, p_BufPoolDepletion, sizeof(t_FmBufPoolDepletion));
return E_OK;
}
t_Error FM_VSP_ConfigBackupPools(t_Handle h_FmVsp, t_FmBackupBmPools *p_BackupBmPools)
{
t_FmVspEntry *p_FmVspEntry = (t_FmVspEntry*)h_FmVsp;
SANITY_CHECK_RETURN_ERROR(h_FmVsp, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmVspEntry->p_FmVspEntryDriverParams, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_BackupBmPools, E_INVALID_HANDLE);
p_FmVspEntry->p_FmVspEntryDriverParams->p_BackupBmPools = (t_FmBackupBmPools *)XX_Malloc(sizeof(t_FmBackupBmPools));
if (!p_FmVspEntry->p_FmVspEntryDriverParams->p_BackupBmPools)
RETURN_ERROR(MAJOR, E_NO_MEMORY, ("p_BackupBmPools allocation failed"));
memcpy(p_FmVspEntry->p_FmVspEntryDriverParams->p_BackupBmPools, p_BackupBmPools, sizeof(t_FmBackupBmPools));
return E_OK;
}
uint32_t FM_VSP_GetBufferDataOffset(t_Handle h_FmVsp)
{
t_FmVspEntry *p_FmVspEntry = (t_FmVspEntry*)h_FmVsp;
SANITY_CHECK_RETURN_VALUE(p_FmVspEntry, E_INVALID_HANDLE, 0);
SANITY_CHECK_RETURN_VALUE(!p_FmVspEntry->p_FmVspEntryDriverParams, E_INVALID_STATE, 0);
return p_FmVspEntry->bufferOffsets.dataOffset;
}
uint8_t * FM_VSP_GetBufferICInfo(t_Handle h_FmVsp, char *p_Data)
{
t_FmVspEntry *p_FmVspEntry = (t_FmVspEntry*)h_FmVsp;
SANITY_CHECK_RETURN_VALUE(p_FmVspEntry, E_INVALID_HANDLE, NULL);
SANITY_CHECK_RETURN_VALUE(!p_FmVspEntry->p_FmVspEntryDriverParams, E_INVALID_STATE, NULL);
if (p_FmVspEntry->bufferOffsets.pcdInfoOffset == ILLEGAL_BASE)
return NULL;
return (uint8_t *)PTR_MOVE(p_Data, p_FmVspEntry->bufferOffsets.pcdInfoOffset);
}
t_FmPrsResult * FM_VSP_GetBufferPrsResult(t_Handle h_FmVsp, char *p_Data)
{
t_FmVspEntry *p_FmVspEntry = (t_FmVspEntry*)h_FmVsp;
SANITY_CHECK_RETURN_VALUE(p_FmVspEntry, E_INVALID_HANDLE, NULL);
SANITY_CHECK_RETURN_VALUE(!p_FmVspEntry->p_FmVspEntryDriverParams, E_INVALID_STATE, NULL);
if (p_FmVspEntry->bufferOffsets.prsResultOffset == ILLEGAL_BASE)
return NULL;
return (t_FmPrsResult *)PTR_MOVE(p_Data, p_FmVspEntry->bufferOffsets.prsResultOffset);
}
uint64_t * FM_VSP_GetBufferTimeStamp(t_Handle h_FmVsp, char *p_Data)
{
t_FmVspEntry *p_FmVspEntry = (t_FmVspEntry*)h_FmVsp;
SANITY_CHECK_RETURN_VALUE(p_FmVspEntry, E_INVALID_HANDLE, NULL);
SANITY_CHECK_RETURN_VALUE(!p_FmVspEntry->p_FmVspEntryDriverParams, E_INVALID_STATE, NULL);
if (p_FmVspEntry->bufferOffsets.timeStampOffset == ILLEGAL_BASE)
return NULL;
return (uint64_t *)PTR_MOVE(p_Data, p_FmVspEntry->bufferOffsets.timeStampOffset);
}
uint8_t * FM_VSP_GetBufferHashResult(t_Handle h_FmVsp, char *p_Data)
{
t_FmVspEntry *p_FmVspEntry = (t_FmVspEntry*)h_FmVsp;
SANITY_CHECK_RETURN_VALUE(p_FmVspEntry, E_INVALID_HANDLE, NULL);
SANITY_CHECK_RETURN_VALUE(!p_FmVspEntry->p_FmVspEntryDriverParams, E_INVALID_STATE, NULL);
if (p_FmVspEntry->bufferOffsets.hashResultOffset == ILLEGAL_BASE)
return NULL;
return (uint8_t *)PTR_MOVE(p_Data, p_FmVspEntry->bufferOffsets.hashResultOffset);
}
#endif /* (DPAA_VERSION >= 11) */

85
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/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_sp.h
@Description FM SP ...
*//***************************************************************************/
#ifndef __FM_SP_H
#define __FM_SP_H
#include "std_ext.h"
#include "error_ext.h"
#include "list_ext.h"
#include "fm_sp_common.h"
#include "fm_common.h"
#define __ERR_MODULE__ MODULE_FM_SP
typedef struct {
t_FmBufferPrefixContent bufferPrefixContent;
e_FmDmaSwapOption dmaSwapData;
e_FmDmaCacheOption dmaIntContextCacheAttr;
e_FmDmaCacheOption dmaHeaderCacheAttr;
e_FmDmaCacheOption dmaScatterGatherCacheAttr;
bool dmaWriteOptimize;
uint16_t liodnOffset;
bool noScatherGather;
t_FmBufPoolDepletion *p_BufPoolDepletion;
t_FmBackupBmPools *p_BackupBmPools;
t_FmExtPools extBufPools;
} t_FmVspEntryDriverParams;
typedef struct {
bool valid;
volatile bool lock;
uint8_t pointedOwners;
uint16_t absoluteSpId;
uint8_t internalBufferOffset;
t_FmSpBufMargins bufMargins;
t_FmSpIntContextDataCopy intContext;
t_FmSpBufferOffsets bufferOffsets;
t_Handle h_Fm;
e_FmPortType portType; /**< Port type */
uint8_t portId; /**< Port Id - relative to type */
uint8_t relativeProfileId;
struct fm_pcd_storage_profile_regs *p_FmSpRegsBase;
t_FmExtPools extBufPools;
t_FmVspEntryDriverParams *p_FmVspEntryDriverParams;
} t_FmVspEntry;
#endif /* __FM_SP_H */

197
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/*
* Copyright 2013 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fsl_fman_sp.h"
uint32_t fman_vsp_get_statistics(struct fm_pcd_storage_profile_regs *regs,
uint16_t index)
{
struct fm_pcd_storage_profile_regs *sp_regs;
sp_regs = &regs[index];
return ioread32be(&sp_regs->fm_sp_acnt);
}
void fman_vsp_set_statistics(struct fm_pcd_storage_profile_regs *regs,
uint16_t index, uint32_t value)
{
struct fm_pcd_storage_profile_regs *sp_regs;
sp_regs = &regs[index];
iowrite32be(value, &sp_regs->fm_sp_acnt);
}
void fman_vsp_defconfig(struct fm_storage_profile_params *cfg)
{
cfg->dma_swap_data =
DEFAULT_FMAN_SP_DMA_SWAP_DATA;
cfg->int_context_cache_attr =
DEFAULT_FMAN_SP_DMA_INT_CONTEXT_CACHE_ATTR;
cfg->header_cache_attr =
DEFAULT_FMAN_SP_DMA_HEADER_CACHE_ATTR;
cfg->scatter_gather_cache_attr =
DEFAULT_FMAN_SP_DMA_SCATTER_GATHER_CACHE_ATTR;
cfg->dma_write_optimize =
DEFAULT_FMAN_SP_DMA_WRITE_OPTIMIZE;
cfg->no_scather_gather =
DEFAULT_FMAN_SP_NO_SCATTER_GATHER;
}
static inline uint32_t calc_vec_dep(int max_pools, bool *pools,
struct fman_ext_pools *ext_buf_pools, uint32_t mask)
{
int i, j;
uint32_t vector = 0;
for (i = 0; i < max_pools; i++)
if (pools[i])
for (j = 0; j < ext_buf_pools->num_pools_used; j++)
if (i == ext_buf_pools->ext_buf_pool[j].id) {
vector |= mask >> j;
break;
}
return vector;
}
void fman_vsp_init(struct fm_pcd_storage_profile_regs *regs,
uint16_t index, struct fm_storage_profile_params *fm_vsp_params,
int port_max_num_of_ext_pools, int bm_max_num_of_pools,
int max_num_of_pfc_priorities)
{
int i = 0, j = 0;
struct fm_pcd_storage_profile_regs *sp_regs;
uint32_t tmp_reg, vector;
struct fman_ext_pools *ext_buf_pools = &fm_vsp_params->fm_ext_pools;
struct fman_buf_pool_depletion *buf_pool_depletion =
&fm_vsp_params->buf_pool_depletion;
struct fman_backup_bm_pools *backup_pools =
&fm_vsp_params->backup_pools;
struct fman_sp_int_context_data_copy *int_context_data_copy =
fm_vsp_params->int_context;
struct fman_sp_buf_margins *external_buffer_margins =
fm_vsp_params->buf_margins;
bool no_scather_gather = fm_vsp_params->no_scather_gather;
uint16_t liodn_offset = fm_vsp_params->liodn_offset;
sp_regs = &regs[index];
/* fill external buffers manager pool information register*/
for (i = 0; i < ext_buf_pools->num_pools_used; i++) {
tmp_reg = FMAN_SP_EXT_BUF_POOL_VALID |
FMAN_SP_EXT_BUF_POOL_EN_COUNTER;
tmp_reg |= ((uint32_t)ext_buf_pools->ext_buf_pool[i].id <<
FMAN_SP_EXT_BUF_POOL_ID_SHIFT);
tmp_reg |= ext_buf_pools->ext_buf_pool[i].size;
/* functionality available only for some deriviatives
(limited by config) */
for (j = 0; j < backup_pools->num_backup_pools; j++)
if (ext_buf_pools->ext_buf_pool[i].id ==
backup_pools->pool_ids[j]) {
tmp_reg |= FMAN_SP_EXT_BUF_POOL_BACKUP;
break;
}
iowrite32be(tmp_reg, &sp_regs->fm_sp_ebmpi[i]);
}
/* clear unused pools */
for (i = ext_buf_pools->num_pools_used;
i < port_max_num_of_ext_pools; i++)
iowrite32be(0, &sp_regs->fm_sp_ebmpi[i]);
/* fill pool depletion register*/
tmp_reg = 0;
if (buf_pool_depletion->buf_pool_depletion_enabled && buf_pool_depletion->pools_grp_mode_enable) {
/* calculate vector for number of pools depletion */
vector = calc_vec_dep(bm_max_num_of_pools, buf_pool_depletion->
pools_to_consider, ext_buf_pools, 0x80000000);
/* configure num of pools and vector for number of pools mode */
tmp_reg |= (((uint32_t)buf_pool_depletion->num_pools - 1) <<
FMAN_SP_POOL_DEP_NUM_OF_POOLS_SHIFT);
tmp_reg |= vector;
}
if (buf_pool_depletion->buf_pool_depletion_enabled && buf_pool_depletion->single_pool_mode_enable) {
/* calculate vector for number of pools depletion */
vector = calc_vec_dep(bm_max_num_of_pools, buf_pool_depletion->
pools_to_consider_for_single_mode,
ext_buf_pools, 0x00000080);
/* configure num of pools and vector for number of pools mode */
tmp_reg |= vector;
}
/* fill QbbPEV */
if (buf_pool_depletion->buf_pool_depletion_enabled) {
vector = 0;
for (i = 0; i < max_num_of_pfc_priorities; i++)
if (buf_pool_depletion->pfc_priorities_en[i] == TRUE)
vector |= 0x00000100 << i;
tmp_reg |= vector;
}
iowrite32be(tmp_reg, &sp_regs->fm_sp_mpd);
/* fill dma attributes register */
tmp_reg = 0;
tmp_reg |= (uint32_t)fm_vsp_params->dma_swap_data <<
FMAN_SP_DMA_ATTR_SWP_SHIFT;
tmp_reg |= (uint32_t)fm_vsp_params->int_context_cache_attr <<
FMAN_SP_DMA_ATTR_IC_CACHE_SHIFT;
tmp_reg |= (uint32_t)fm_vsp_params->header_cache_attr <<
FMAN_SP_DMA_ATTR_HDR_CACHE_SHIFT;
tmp_reg |= (uint32_t)fm_vsp_params->scatter_gather_cache_attr <<
FMAN_SP_DMA_ATTR_SG_CACHE_SHIFT;
if (fm_vsp_params->dma_write_optimize)
tmp_reg |= FMAN_SP_DMA_ATTR_WRITE_OPTIMIZE;
iowrite32be(tmp_reg, &sp_regs->fm_sp_da);
/* IC parameters - fill internal context parameters register */
tmp_reg = 0;
tmp_reg |= (((uint32_t)int_context_data_copy->ext_buf_offset/
OFFSET_UNITS) << FMAN_SP_IC_TO_EXT_SHIFT);
tmp_reg |= (((uint32_t)int_context_data_copy->int_context_offset/
OFFSET_UNITS) << FMAN_SP_IC_FROM_INT_SHIFT);
tmp_reg |= (((uint32_t)int_context_data_copy->size/OFFSET_UNITS) <<
FMAN_SP_IC_SIZE_SHIFT);
iowrite32be(tmp_reg, &sp_regs->fm_sp_icp);
/* buffer margins - fill external buffer margins register */
tmp_reg = 0;
tmp_reg |= (((uint32_t)external_buffer_margins->start_margins) <<
FMAN_SP_EXT_BUF_MARG_START_SHIFT);
tmp_reg |= (((uint32_t)external_buffer_margins->end_margins) <<
FMAN_SP_EXT_BUF_MARG_END_SHIFT);
if (no_scather_gather)
tmp_reg |= FMAN_SP_SG_DISABLE;
iowrite32be(tmp_reg, &sp_regs->fm_sp_ebm);
/* buffer margins - fill spliodn register */
iowrite32be(liodn_offset, &sp_regs->fm_sp_spliodn);
}

5216
drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/fm.c Normal file
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648
drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/fm.h Normal file
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/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm.h
@Description FM internal structures and definitions.
*//***************************************************************************/
#ifndef __FM_H
#define __FM_H
#include "error_ext.h"
#include "std_ext.h"
#include "fm_ext.h"
#include "fm_ipc.h"
#include "fsl_fman.h"
#define __ERR_MODULE__ MODULE_FM
#define FM_MAX_NUM_OF_HW_PORT_IDS 64
#define FM_MAX_NUM_OF_GUESTS 100
/**************************************************************************//**
@Description Exceptions
*//***************************************************************************/
#define FM_EX_DMA_BUS_ERROR 0x80000000 /**< DMA bus error. */
#define FM_EX_DMA_READ_ECC 0x40000000
#define FM_EX_DMA_SYSTEM_WRITE_ECC 0x20000000
#define FM_EX_DMA_FM_WRITE_ECC 0x10000000
#define FM_EX_FPM_STALL_ON_TASKS 0x08000000 /**< Stall of tasks on FPM */
#define FM_EX_FPM_SINGLE_ECC 0x04000000 /**< Single ECC on FPM */
#define FM_EX_FPM_DOUBLE_ECC 0x02000000
#define FM_EX_QMI_SINGLE_ECC 0x01000000 /**< Single ECC on FPM */
#define FM_EX_QMI_DEQ_FROM_UNKNOWN_PORTID 0x00800000 /**< Dequeu from default queue id */
#define FM_EX_QMI_DOUBLE_ECC 0x00400000
#define FM_EX_BMI_LIST_RAM_ECC 0x00200000
#define FM_EX_BMI_STORAGE_PROFILE_ECC 0x00100000
#define FM_EX_BMI_STATISTICS_RAM_ECC 0x00080000
#define FM_EX_IRAM_ECC 0x00040000
#define FM_EX_MURAM_ECC 0x00020000
#define FM_EX_BMI_DISPATCH_RAM_ECC 0x00010000
#define FM_EX_DMA_SINGLE_PORT_ECC 0x00008000
#define DMA_EMSR_EMSTR_MASK 0x0000FFFF
#define DMA_THRESH_COMMQ_MASK 0xFF000000
#define DMA_THRESH_READ_INT_BUF_MASK 0x007F0000
#define DMA_THRESH_WRITE_INT_BUF_MASK 0x0000007F
#define GET_EXCEPTION_FLAG(bitMask, exception) \
switch (exception){ \
case e_FM_EX_DMA_BUS_ERROR: \
bitMask = FM_EX_DMA_BUS_ERROR; break; \
case e_FM_EX_DMA_SINGLE_PORT_ECC: \
bitMask = FM_EX_DMA_SINGLE_PORT_ECC; break; \
case e_FM_EX_DMA_READ_ECC: \
bitMask = FM_EX_DMA_READ_ECC; break; \
case e_FM_EX_DMA_SYSTEM_WRITE_ECC: \
bitMask = FM_EX_DMA_SYSTEM_WRITE_ECC; break; \
case e_FM_EX_DMA_FM_WRITE_ECC: \
bitMask = FM_EX_DMA_FM_WRITE_ECC; break; \
case e_FM_EX_FPM_STALL_ON_TASKS: \
bitMask = FM_EX_FPM_STALL_ON_TASKS; break; \
case e_FM_EX_FPM_SINGLE_ECC: \
bitMask = FM_EX_FPM_SINGLE_ECC; break; \
case e_FM_EX_FPM_DOUBLE_ECC: \
bitMask = FM_EX_FPM_DOUBLE_ECC; break; \
case e_FM_EX_QMI_SINGLE_ECC: \
bitMask = FM_EX_QMI_SINGLE_ECC; break; \
case e_FM_EX_QMI_DOUBLE_ECC: \
bitMask = FM_EX_QMI_DOUBLE_ECC; break; \
case e_FM_EX_QMI_DEQ_FROM_UNKNOWN_PORTID: \
bitMask = FM_EX_QMI_DEQ_FROM_UNKNOWN_PORTID; break; \
case e_FM_EX_BMI_LIST_RAM_ECC: \
bitMask = FM_EX_BMI_LIST_RAM_ECC; break; \
case e_FM_EX_BMI_STORAGE_PROFILE_ECC: \
bitMask = FM_EX_BMI_STORAGE_PROFILE_ECC; break; \
case e_FM_EX_BMI_STATISTICS_RAM_ECC: \
bitMask = FM_EX_BMI_STATISTICS_RAM_ECC; break; \
case e_FM_EX_BMI_DISPATCH_RAM_ECC: \
bitMask = FM_EX_BMI_DISPATCH_RAM_ECC; break; \
case e_FM_EX_IRAM_ECC: \
bitMask = FM_EX_IRAM_ECC; break; \
case e_FM_EX_MURAM_ECC: \
bitMask = FM_EX_MURAM_ECC; break; \
default: bitMask = 0;break; \
}
#define GET_FM_MODULE_EVENT(_mod, _id, _intrType, _event) \
switch (_mod) { \
case e_FM_MOD_PRS: \
if (_id) _event = e_FM_EV_DUMMY_LAST; \
else _event = (_intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_PRS : e_FM_EV_PRS; \
break; \
case e_FM_MOD_KG: \
if (_id) _event = e_FM_EV_DUMMY_LAST; \
else _event = (_intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_KG : e_FM_EV_DUMMY_LAST; \
break; \
case e_FM_MOD_PLCR: \
if (_id) _event = e_FM_EV_DUMMY_LAST; \
else _event = (_intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_PLCR : e_FM_EV_PLCR; \
break; \
case e_FM_MOD_TMR: \
if (_id) _event = e_FM_EV_DUMMY_LAST; \
else _event = (_intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_DUMMY_LAST : e_FM_EV_TMR; \
break; \
case e_FM_MOD_10G_MAC: \
if (_id >= FM_MAX_NUM_OF_10G_MACS) _event = e_FM_EV_DUMMY_LAST; \
else _event = (_intrType == e_FM_INTR_TYPE_ERR) ? (e_FM_EV_ERR_10G_MAC0 + _id) : (e_FM_EV_10G_MAC0 + _id); \
break; \
case e_FM_MOD_1G_MAC: \
if (_id >= FM_MAX_NUM_OF_1G_MACS) _event = e_FM_EV_DUMMY_LAST; \
else _event = (_intrType == e_FM_INTR_TYPE_ERR) ? (e_FM_EV_ERR_1G_MAC0 + _id) : (e_FM_EV_1G_MAC0 + _id); \
break; \
case e_FM_MOD_MACSEC: \
switch (_id){ \
case (0): _event = (_intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_MACSEC_MAC0:e_FM_EV_MACSEC_MAC0; \
break; \
} \
break; \
case e_FM_MOD_FMAN_CTRL: \
if (_intrType == e_FM_INTR_TYPE_ERR) _event = e_FM_EV_DUMMY_LAST; \
else _event = (e_FM_EV_FMAN_CTRL_0 + _id); \
break; \
default: _event = e_FM_EV_DUMMY_LAST; \
break; \
}
#define FMAN_CACHE_OVERRIDE_TRANS(fsl_cache_override, _cache_override) \
switch (_cache_override){ \
case e_FM_DMA_NO_CACHE_OR: \
fsl_cache_override = E_FMAN_DMA_NO_CACHE_OR; break; \
case e_FM_DMA_NO_STASH_DATA: \
fsl_cache_override = E_FMAN_DMA_NO_STASH_DATA; break; \
case e_FM_DMA_MAY_STASH_DATA: \
fsl_cache_override = E_FMAN_DMA_MAY_STASH_DATA; break; \
case e_FM_DMA_STASH_DATA: \
fsl_cache_override = E_FMAN_DMA_STASH_DATA; break; \
default: \
fsl_cache_override = E_FMAN_DMA_NO_CACHE_OR; break; \
}
#define FMAN_AID_MODE_TRANS(fsl_aid_mode, _aid_mode) \
switch (_aid_mode){ \
case e_FM_DMA_AID_OUT_PORT_ID: \
fsl_aid_mode = E_FMAN_DMA_AID_OUT_PORT_ID; break; \
case e_FM_DMA_AID_OUT_TNUM: \
fsl_aid_mode = E_FMAN_DMA_AID_OUT_TNUM; break; \
default: \
fsl_aid_mode = E_FMAN_DMA_AID_OUT_PORT_ID; break; \
}
#define FMAN_DMA_DBG_CNT_TRANS(fsl_dma_dbg_cnt, _dma_dbg_cnt) \
switch (_dma_dbg_cnt){ \
case e_FM_DMA_DBG_NO_CNT: \
fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_NO_CNT; break; \
case e_FM_DMA_DBG_CNT_DONE: \
fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_CNT_DONE; break; \
case e_FM_DMA_DBG_CNT_COMM_Q_EM: \
fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_CNT_COMM_Q_EM; break; \
case e_FM_DMA_DBG_CNT_INT_READ_EM: \
fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_CNT_INT_READ_EM; break; \
case e_FM_DMA_DBG_CNT_INT_WRITE_EM: \
fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_CNT_INT_WRITE_EM ; break; \
case e_FM_DMA_DBG_CNT_FPM_WAIT: \
fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_CNT_FPM_WAIT ; break; \
case e_FM_DMA_DBG_CNT_SIGLE_BIT_ECC: \
fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_CNT_SIGLE_BIT_ECC ; break; \
case e_FM_DMA_DBG_CNT_RAW_WAR_PROT: \
fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_CNT_RAW_WAR_PROT ; break; \
default: \
fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_NO_CNT; break; \
}
#define FMAN_DMA_EMER_TRANS(fsl_dma_emer, _dma_emer) \
switch (_dma_emer){ \
case e_FM_DMA_EM_EBS: \
fsl_dma_emer = E_FMAN_DMA_EM_EBS; break; \
case e_FM_DMA_EM_SOS: \
fsl_dma_emer = E_FMAN_DMA_EM_SOS; break; \
default: \
fsl_dma_emer = E_FMAN_DMA_EM_EBS; break; \
}
#define FMAN_DMA_ERR_TRANS(fsl_dma_err, _dma_err) \
switch (_dma_err){ \
case e_FM_DMA_ERR_CATASTROPHIC: \
fsl_dma_err = E_FMAN_DMA_ERR_CATASTROPHIC; break; \
case e_FM_DMA_ERR_REPORT: \
fsl_dma_err = E_FMAN_DMA_ERR_REPORT; break; \
default: \
fsl_dma_err = E_FMAN_DMA_ERR_CATASTROPHIC; break; \
}
#define FMAN_CATASTROPHIC_ERR_TRANS(fsl_catastrophic_err, _catastrophic_err) \
switch (_catastrophic_err){ \
case e_FM_CATASTROPHIC_ERR_STALL_PORT: \
fsl_catastrophic_err = E_FMAN_CATAST_ERR_STALL_PORT; break; \
case e_FM_CATASTROPHIC_ERR_STALL_TASK: \
fsl_catastrophic_err = E_FMAN_CATAST_ERR_STALL_TASK; break; \
default: \
fsl_catastrophic_err = E_FMAN_CATAST_ERR_STALL_PORT; break; \
}
#define FMAN_COUNTERS_TRANS(fsl_counters, _counters) \
switch (_counters){ \
case e_FM_COUNTERS_ENQ_TOTAL_FRAME: \
fsl_counters = E_FMAN_COUNTERS_ENQ_TOTAL_FRAME; break; \
case e_FM_COUNTERS_DEQ_TOTAL_FRAME: \
fsl_counters = E_FMAN_COUNTERS_DEQ_TOTAL_FRAME; break; \
case e_FM_COUNTERS_DEQ_0: \
fsl_counters = E_FMAN_COUNTERS_DEQ_0; break; \
case e_FM_COUNTERS_DEQ_1: \
fsl_counters = E_FMAN_COUNTERS_DEQ_1; break; \
case e_FM_COUNTERS_DEQ_2: \
fsl_counters = E_FMAN_COUNTERS_DEQ_2; break; \
case e_FM_COUNTERS_DEQ_3: \
fsl_counters = E_FMAN_COUNTERS_DEQ_3; break; \
case e_FM_COUNTERS_DEQ_FROM_DEFAULT: \
fsl_counters = E_FMAN_COUNTERS_DEQ_FROM_DEFAULT; break; \
case e_FM_COUNTERS_DEQ_FROM_CONTEXT: \
fsl_counters = E_FMAN_COUNTERS_DEQ_FROM_CONTEXT; break; \
case e_FM_COUNTERS_DEQ_FROM_FD: \
fsl_counters = E_FMAN_COUNTERS_DEQ_FROM_FD; break; \
case e_FM_COUNTERS_DEQ_CONFIRM: \
fsl_counters = E_FMAN_COUNTERS_DEQ_CONFIRM; break; \
default: \
fsl_counters = E_FMAN_COUNTERS_ENQ_TOTAL_FRAME; break; \
}
/**************************************************************************//**
@Description defaults
*//***************************************************************************/
#define DEFAULT_exceptions (FM_EX_DMA_BUS_ERROR |\
FM_EX_DMA_READ_ECC |\
FM_EX_DMA_SYSTEM_WRITE_ECC |\
FM_EX_DMA_FM_WRITE_ECC |\
FM_EX_FPM_STALL_ON_TASKS |\
FM_EX_FPM_SINGLE_ECC |\
FM_EX_FPM_DOUBLE_ECC |\
FM_EX_QMI_DEQ_FROM_UNKNOWN_PORTID|\
FM_EX_BMI_LIST_RAM_ECC |\
FM_EX_BMI_STORAGE_PROFILE_ECC |\
FM_EX_BMI_STATISTICS_RAM_ECC |\
FM_EX_IRAM_ECC |\
FM_EX_MURAM_ECC |\
FM_EX_BMI_DISPATCH_RAM_ECC |\
FM_EX_QMI_DOUBLE_ECC |\
FM_EX_QMI_SINGLE_ECC)
#define DEFAULT_eccEnable FALSE
#ifdef FM_PEDANTIC_DMA
#define DEFAULT_aidOverride TRUE
#else
#define DEFAULT_aidOverride FALSE
#endif /* FM_PEDANTIC_DMA */
#define DEFAULT_aidMode e_FM_DMA_AID_OUT_TNUM
#define DEFAULT_dmaStopOnBusError FALSE
#define DEFAULT_stopAtBusError FALSE
#define DEFAULT_axiDbgNumOfBeats 1
#define DEFAULT_dmaReadIntBufLow ((DMA_THRESH_MAX_BUF+1)/2)
#define DEFAULT_dmaReadIntBufHigh ((DMA_THRESH_MAX_BUF+1)*3/4)
#define DEFAULT_dmaWriteIntBufLow ((DMA_THRESH_MAX_BUF+1)/2)
#define DEFAULT_dmaWriteIntBufHigh ((DMA_THRESH_MAX_BUF+1)*3/4)
#define DEFAULT_catastrophicErr e_FM_CATASTROPHIC_ERR_STALL_PORT
#define DEFAULT_dmaErr e_FM_DMA_ERR_CATASTROPHIC
#define DEFAULT_resetOnInit FALSE
#define DEFAULT_resetOnInitOverrideCallback NULL
#define DEFAULT_haltOnExternalActivation FALSE /* do not change! if changed, must be disabled for rev1 ! */
#define DEFAULT_haltOnUnrecoverableEccError FALSE /* do not change! if changed, must be disabled for rev1 ! */
#define DEFAULT_externalEccRamsEnable FALSE
#define DEFAULT_VerifyUcode FALSE
#if (DPAA_VERSION < 11)
#define DEFAULT_totalFifoSize(major, minor) \
(((major == 2) || (major == 5)) ? \
(100*KILOBYTE) : ((major == 4) ? \
(49*KILOBYTE) : (122*KILOBYTE)))
#define DEFAULT_totalNumOfTasks(major, minor) \
BMI_MAX_NUM_OF_TASKS
#define DEFAULT_dmaCommQLow ((DMA_THRESH_MAX_COMMQ+1)/2)
#define DEFAULT_dmaCommQHigh ((DMA_THRESH_MAX_COMMQ+1)*3/4)
#define DEFAULT_cacheOverride e_FM_DMA_NO_CACHE_OR
#define DEFAULT_dmaCamNumOfEntries 32
#define DEFAULT_dmaDbgCntMode e_FM_DMA_DBG_NO_CNT
#define DEFAULT_dmaEnEmergency FALSE
#define DEFAULT_dmaSosEmergency 0
#define DEFAULT_dmaWatchdog 0 /* disabled */
#define DEFAULT_dmaEnEmergencySmoother FALSE
#define DEFAULT_dmaEmergencySwitchCounter 0
#define DEFAULT_dispLimit 0
#define DEFAULT_prsDispTh 16
#define DEFAULT_plcrDispTh 16
#define DEFAULT_kgDispTh 16
#define DEFAULT_bmiDispTh 16
#define DEFAULT_qmiEnqDispTh 16
#define DEFAULT_qmiDeqDispTh 16
#define DEFAULT_fmCtl1DispTh 16
#define DEFAULT_fmCtl2DispTh 16
#else /* (DPAA_VERSION < 11) */
/* Defaults are registers' reset values */
#define DEFAULT_totalFifoSize(major, minor) \
(((major == 6) && ((minor == 1) || (minor == 4))) ? \
(156*KILOBYTE) : (295*KILOBYTE))
/* According to the default value of FMBM_CFG2[TNTSKS] */
#define DEFAULT_totalNumOfTasks(major, minor) \
(((major == 6) && ((minor == 1) || (minor == 4))) ? 59 : 124)
#define DEFAULT_dmaCommQLow 0x2A
#define DEFAULT_dmaCommQHigh 0x3F
#define DEFAULT_cacheOverride e_FM_DMA_NO_CACHE_OR
#define DEFAULT_dmaCamNumOfEntries 64
#define DEFAULT_dmaDbgCntMode e_FM_DMA_DBG_NO_CNT
#define DEFAULT_dmaEnEmergency FALSE
#define DEFAULT_dmaSosEmergency 0
#define DEFAULT_dmaWatchdog 0 /* disabled */
#define DEFAULT_dmaEnEmergencySmoother FALSE
#define DEFAULT_dmaEmergencySwitchCounter 0
#define DEFAULT_dispLimit 0
#define DEFAULT_prsDispTh 16
#define DEFAULT_plcrDispTh 16
#define DEFAULT_kgDispTh 16
#define DEFAULT_bmiDispTh 16
#define DEFAULT_qmiEnqDispTh 16
#define DEFAULT_qmiDeqDispTh 16
#define DEFAULT_fmCtl1DispTh 16
#define DEFAULT_fmCtl2DispTh 16
#endif /* (DPAA_VERSION < 11) */
#define FM_TIMESTAMP_1_USEC_BIT 8
/**************************************************************************//**
@Collection Defines used for enabling/disabling FM interrupts
@{
*//***************************************************************************/
#define ERR_INTR_EN_DMA 0x00010000
#define ERR_INTR_EN_FPM 0x80000000
#define ERR_INTR_EN_BMI 0x00800000
#define ERR_INTR_EN_QMI 0x00400000
#define ERR_INTR_EN_PRS 0x00200000
#define ERR_INTR_EN_KG 0x00100000
#define ERR_INTR_EN_PLCR 0x00080000
#define ERR_INTR_EN_MURAM 0x00040000
#define ERR_INTR_EN_IRAM 0x00020000
#define ERR_INTR_EN_10G_MAC0 0x00008000
#define ERR_INTR_EN_10G_MAC1 0x00000040
#define ERR_INTR_EN_1G_MAC0 0x00004000
#define ERR_INTR_EN_1G_MAC1 0x00002000
#define ERR_INTR_EN_1G_MAC2 0x00001000
#define ERR_INTR_EN_1G_MAC3 0x00000800
#define ERR_INTR_EN_1G_MAC4 0x00000400
#define ERR_INTR_EN_1G_MAC5 0x00000200
#define ERR_INTR_EN_1G_MAC6 0x00000100
#define ERR_INTR_EN_1G_MAC7 0x00000080
#define ERR_INTR_EN_MACSEC_MAC0 0x00000001
#define INTR_EN_QMI 0x40000000
#define INTR_EN_PRS 0x20000000
#define INTR_EN_WAKEUP 0x10000000
#define INTR_EN_PLCR 0x08000000
#define INTR_EN_1G_MAC0 0x00080000
#define INTR_EN_1G_MAC1 0x00040000
#define INTR_EN_1G_MAC2 0x00020000
#define INTR_EN_1G_MAC3 0x00010000
#define INTR_EN_1G_MAC4 0x00000040
#define INTR_EN_1G_MAC5 0x00000020
#define INTR_EN_1G_MAC6 0x00000008
#define INTR_EN_1G_MAC7 0x00000002
#define INTR_EN_10G_MAC0 0x00200000
#define INTR_EN_10G_MAC1 0x00100000
#define INTR_EN_REV0 0x00008000
#define INTR_EN_REV1 0x00004000
#define INTR_EN_REV2 0x00002000
#define INTR_EN_REV3 0x00001000
#define INTR_EN_BRK 0x00000080
#define INTR_EN_TMR 0x01000000
#define INTR_EN_MACSEC_MAC0 0x00000001
/* @} */
/**************************************************************************//**
@Description Memory Mapped Registers
*//***************************************************************************/
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(push,1)
#endif /* defined(__MWERKS__) && ... */
typedef struct
{
volatile uint32_t iadd; /**< FM IRAM instruction address register */
volatile uint32_t idata; /**< FM IRAM instruction data register */
volatile uint32_t itcfg; /**< FM IRAM timing config register */
volatile uint32_t iready; /**< FM IRAM ready register */
volatile uint32_t res[0x1FFFC];
} t_FMIramRegs;
/* Trace buffer registers -
each FM Controller has its own trace buffer residing at FM_MM_TRB(fmCtrlIndex) offset */
typedef struct t_FmTrbRegs
{
volatile uint32_t tcrh;
volatile uint32_t tcrl;
volatile uint32_t tesr;
volatile uint32_t tecr0h;
volatile uint32_t tecr0l;
volatile uint32_t terf0h;
volatile uint32_t terf0l;
volatile uint32_t tecr1h;
volatile uint32_t tecr1l;
volatile uint32_t terf1h;
volatile uint32_t terf1l;
volatile uint32_t tpcch;
volatile uint32_t tpccl;
volatile uint32_t tpc1h;
volatile uint32_t tpc1l;
volatile uint32_t tpc2h;
volatile uint32_t tpc2l;
volatile uint32_t twdimr;
volatile uint32_t twicvr;
volatile uint32_t tar;
volatile uint32_t tdr;
volatile uint32_t tsnum1;
volatile uint32_t tsnum2;
volatile uint32_t tsnum3;
volatile uint32_t tsnum4;
} t_FmTrbRegs;
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(pop)
#endif /* defined(__MWERKS__) && ... */
/**************************************************************************//**
@Description General defines
*//***************************************************************************/
#define FM_DEBUG_STATUS_REGISTER_OFFSET 0x000d1084UL
#define FM_FW_DEBUG_INSTRUCTION 0x6ffff805UL
/**************************************************************************//**
@Description FPM defines
*//***************************************************************************/
/* masks */
#define FPM_BRKC_RDBG 0x00000200
#define FPM_BRKC_SLP 0x00000800
/**************************************************************************//**
@Description BMI defines
*//***************************************************************************/
/* masks */
#define BMI_INIT_START 0x80000000
#define BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC 0x80000000
#define BMI_ERR_INTR_EN_LIST_RAM_ECC 0x40000000
#define BMI_ERR_INTR_EN_STATISTICS_RAM_ECC 0x20000000
#define BMI_ERR_INTR_EN_DISPATCH_RAM_ECC 0x10000000
/**************************************************************************//**
@Description QMI defines
*//***************************************************************************/
/* masks */
#define QMI_ERR_INTR_EN_DOUBLE_ECC 0x80000000
#define QMI_ERR_INTR_EN_DEQ_FROM_DEF 0x40000000
#define QMI_INTR_EN_SINGLE_ECC 0x80000000
/**************************************************************************//**
@Description IRAM defines
*//***************************************************************************/
/* masks */
#define IRAM_IADD_AIE 0x80000000
#define IRAM_READY 0x80000000
/**************************************************************************//**
@Description TRB defines
*//***************************************************************************/
/* masks */
#define TRB_TCRH_RESET 0x04000000
#define TRB_TCRH_ENABLE_COUNTERS 0x84008000
#define TRB_TCRH_DISABLE_COUNTERS 0x8400C000
#define TRB_TCRL_RESET 0x20000000
#define TRB_TCRL_UTIL 0x00000460
typedef struct {
void (*f_Isr) (t_Handle h_Arg, uint32_t event);
t_Handle h_SrcHandle;
} t_FmanCtrlIntrSrc;
typedef void (t_FmanCtrlIsr)( t_Handle h_Fm, uint32_t event);
typedef struct
{
/***************************/
/* Master/Guest parameters */
/***************************/
uint8_t fmId;
e_FmPortType portsTypes[FM_MAX_NUM_OF_HW_PORT_IDS];
uint16_t fmClkFreq;
uint16_t fmMacClkFreq;
t_FmRevisionInfo revInfo;
/**************************/
/* Master Only parameters */
/**************************/
bool enabledTimeStamp;
uint8_t count1MicroBit;
uint8_t totalNumOfTasks;
uint32_t totalFifoSize;
uint8_t maxNumOfOpenDmas;
uint8_t accumulatedNumOfTasks;
uint32_t accumulatedFifoSize;
uint8_t accumulatedNumOfOpenDmas;
uint8_t accumulatedNumOfDeqTnums;
#ifdef FM_LOW_END_RESTRICTION
bool lowEndRestriction;
#endif /* FM_LOW_END_RESTRICTION */
uint32_t exceptions;
int irq;
int errIrq;
bool ramsEccEnable;
bool explicitEnable;
bool internalCall;
uint8_t ramsEccOwners;
uint32_t extraFifoPoolSize;
uint8_t extraTasksPoolSize;
uint8_t extraOpenDmasPoolSize;
#if defined(FM_MAX_NUM_OF_10G_MACS) && (FM_MAX_NUM_OF_10G_MACS)
uint16_t portMaxFrameLengths10G[FM_MAX_NUM_OF_10G_MACS];
uint16_t macMaxFrameLengths10G[FM_MAX_NUM_OF_10G_MACS];
#endif /* defined(FM_MAX_NUM_OF_10G_MACS) && ... */
uint16_t portMaxFrameLengths1G[FM_MAX_NUM_OF_1G_MACS];
uint16_t macMaxFrameLengths1G[FM_MAX_NUM_OF_1G_MACS];
} t_FmStateStruct;
#if (DPAA_VERSION >= 11)
typedef struct t_FmMapParam {
uint16_t profilesBase;
uint16_t numOfProfiles;
t_Handle h_FmPort;
} t_FmMapParam;
typedef struct t_FmAllocMng {
bool allocated;
uint8_t ownerId; /* guestId for KG in multi-partition only,
portId for PLCR in any environment */
} t_FmAllocMng;
typedef struct t_FmPcdSpEntry {
bool valid;
t_FmAllocMng profilesMng;
} t_FmPcdSpEntry;
typedef struct t_FmSp {
void *p_FmPcdStoragePrflRegs;
t_FmPcdSpEntry profiles[FM_VSP_MAX_NUM_OF_ENTRIES];
t_FmMapParam portsMapping[FM_MAX_NUM_OF_PORTS];
} t_FmSp;
#endif /* (DPAA_VERSION >= 11) */
typedef struct t_Fm
{
/***************************/
/* Master/Guest parameters */
/***************************/
/* locals for recovery */
uintptr_t baseAddr;
/* un-needed for recovery */
t_Handle h_Pcd;
char fmModuleName[MODULE_NAME_SIZE];
char fmIpcHandlerModuleName[FM_MAX_NUM_OF_GUESTS][MODULE_NAME_SIZE];
t_Handle h_IpcSessions[FM_MAX_NUM_OF_GUESTS];
t_FmIntrSrc intrMng[e_FM_EV_DUMMY_LAST]; /* FM exceptions user callback */
uint8_t guestId;
/**************************/
/* Master Only parameters */
/**************************/
/* locals for recovery */
struct fman_fpm_regs *p_FmFpmRegs;
struct fman_bmi_regs *p_FmBmiRegs;
struct fman_qmi_regs *p_FmQmiRegs;
struct fman_dma_regs *p_FmDmaRegs;
struct fman_regs *p_FmRegs;
t_FmExceptionsCallback *f_Exception;
t_FmBusErrorCallback *f_BusError;
t_Handle h_App; /* Application handle */
t_Handle h_Spinlock;
bool recoveryMode;
t_FmStateStruct *p_FmStateStruct;
uint16_t tnumAgingPeriod;
#if (DPAA_VERSION >= 11)
t_FmSp *p_FmSp;
uint8_t partNumOfVSPs;
uint8_t partVSPBase;
uintptr_t vspBaseAddr;
#endif /* (DPAA_VERSION >= 11) */
bool portsPreFetchConfigured[FM_MAX_NUM_OF_HW_PORT_IDS]; /* Prefetch configration per Tx-port */
bool portsPreFetchValue[FM_MAX_NUM_OF_HW_PORT_IDS]; /* Prefetch configration per Tx-port */
/* un-needed for recovery */
struct fman_cfg *p_FmDriverParam;
t_Handle h_FmMuram;
uint64_t fmMuramPhysBaseAddr;
bool independentMode;
bool hcPortInitialized;
uintptr_t camBaseAddr; /* save for freeing */
uintptr_t resAddr;
uintptr_t fifoBaseAddr; /* save for freeing */
t_FmanCtrlIntrSrc fmanCtrlIntr[FM_NUM_OF_FMAN_CTRL_EVENT_REGS]; /* FM exceptions user callback */
bool usedEventRegs[FM_NUM_OF_FMAN_CTRL_EVENT_REGS];
t_FmFirmwareParams firmware;
bool fwVerify;
bool resetOnInit;
t_FmResetOnInitOverrideCallback *f_ResetOnInitOverride;
uint32_t userSetExceptions;
} t_Fm;
#endif /* __FM_H */

465
drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/fm_ipc.h Normal file
View File

@ -0,0 +1,465 @@
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**************************************************************************//**
@File fm_ipc.h
@Description FM Inter-Partition prototypes, structures and definitions.
*//***************************************************************************/
#ifndef __FM_IPC_H
#define __FM_IPC_H
#include "error_ext.h"
#include "std_ext.h"
/**************************************************************************//**
@Group FM_grp Frame Manager API
@Description FM API functions, definitions and enums
@{
*//***************************************************************************/
/**************************************************************************//**
@Group FM_IPC_grp FM Inter-Partition messaging Unit
@Description FM Inter-Partition messaging unit API definitions and enums.
@{
*//***************************************************************************/
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(push,1)
#endif /* defined(__MWERKS__) && ... */
/**************************************************************************//**
@Description enum for defining MAC types
*//***************************************************************************/
/**************************************************************************//**
@Description A structure of parameters for specifying a MAC.
*//***************************************************************************/
typedef _Packed struct
{
uint8_t id;
uint32_t enumType;
} _PackedType t_FmIpcMacParams;
/**************************************************************************//**
@Description A structure of parameters for specifying a MAC.
*//***************************************************************************/
typedef _Packed struct
{
t_FmIpcMacParams macParams;
uint16_t maxFrameLength;
} _PackedType t_FmIpcMacMaxFrameParams;
/**************************************************************************//**
@Description FM physical Address
*//***************************************************************************/
typedef _Packed struct t_FmIpcPhysAddr
{
volatile uint8_t high;
volatile uint32_t low;
} _PackedType t_FmIpcPhysAddr;
typedef _Packed struct t_FmIpcPortOutInitParams {
uint8_t numOfTasks; /**< OUT */
uint8_t numOfExtraTasks; /**< OUT */
uint8_t numOfOpenDmas; /**< OUT */
uint8_t numOfExtraOpenDmas; /**< OUT */
uint32_t sizeOfFifo; /**< OUT */
uint32_t extraSizeOfFifo; /**< OUT */
t_FmIpcPhysAddr ipcPhysAddr; /**< OUT */
} _PackedType t_FmIpcPortOutInitParams;
/**************************************************************************//**
@Description Structure for IPC communication during FM_PORT_Init.
*//***************************************************************************/
typedef _Packed struct t_FmIpcPortInInitParams {
uint8_t hardwarePortId; /**< IN. port Id */
uint32_t enumPortType; /**< IN. Port type */
uint8_t boolIndependentMode;/**< IN. TRUE if FM Port operates in independent mode */
uint16_t liodnOffset; /**< IN. Port's requested resource */
uint8_t numOfTasks; /**< IN. Port's requested resource */
uint8_t numOfExtraTasks; /**< IN. Port's requested resource */
uint8_t numOfOpenDmas; /**< IN. Port's requested resource */
uint8_t numOfExtraOpenDmas; /**< IN. Port's requested resource */
uint32_t sizeOfFifo; /**< IN. Port's requested resource */
uint32_t extraSizeOfFifo; /**< IN. Port's requested resource */
uint8_t deqPipelineDepth; /**< IN. Port's requested resource */
uint16_t maxFrameLength; /**< IN. Port's max frame length. */
uint16_t liodnBase; /**< IN. Irrelevant for P4080 rev 1.
LIODN base for this port, to be
used together with LIODN offset. */
} _PackedType t_FmIpcPortInInitParams;
/**************************************************************************//**
@Description Structure for IPC communication between port and FM
regarding tasks and open DMA resources management.
*//***************************************************************************/
typedef _Packed struct t_FmIpcPortRsrcParams {
uint8_t hardwarePortId; /**< IN. port Id */
uint32_t val; /**< IN. Port's requested resource */
uint32_t extra; /**< IN. Port's requested resource */
uint8_t boolInitialConfig;
} _PackedType t_FmIpcPortRsrcParams;
/**************************************************************************//**
@Description Structure for IPC communication between port and FM
regarding tasks and open DMA resources management.
*//***************************************************************************/
typedef _Packed struct t_FmIpcPortFifoParams {
t_FmIpcPortRsrcParams rsrcParams;
uint32_t enumPortType;
uint8_t boolIndependentMode;
uint8_t deqPipelineDepth;
uint8_t numOfPools;
uint16_t secondLargestBufSize;
uint16_t largestBufSize;
uint8_t boolInitialConfig;
} _PackedType t_FmIpcPortFifoParams;
/**************************************************************************//**
@Description Structure for port-FM communication during FM_PORT_Free.
*//***************************************************************************/
typedef _Packed struct t_FmIpcPortFreeParams {
uint8_t hardwarePortId; /**< IN. port Id */
uint32_t enumPortType; /**< IN. Port type */
uint8_t deqPipelineDepth; /**< IN. Port's requested resource */
} _PackedType t_FmIpcPortFreeParams;
/**************************************************************************//**
@Description Structure for defining DMA status
*//***************************************************************************/
typedef _Packed struct t_FmIpcDmaStatus {
uint8_t boolCmqNotEmpty; /**< Command queue is not empty */
uint8_t boolBusError; /**< Bus error occurred */
uint8_t boolReadBufEccError; /**< Double ECC error on buffer Read */
uint8_t boolWriteBufEccSysError; /**< Double ECC error on buffer write from system side */
uint8_t boolWriteBufEccFmError; /**< Double ECC error on buffer write from FM side */
uint8_t boolSinglePortEccError; /**< Single port ECC error from FM side */
} _PackedType t_FmIpcDmaStatus;
typedef _Packed struct t_FmIpcRegisterIntr
{
uint8_t guestId; /* IN */
uint32_t event; /* IN */
} _PackedType t_FmIpcRegisterIntr;
typedef _Packed struct t_FmIpcIsr
{
uint8_t boolErr; /* IN */
uint32_t pendingReg; /* IN */
} _PackedType t_FmIpcIsr;
/**************************************************************************//**
@Description structure for returning FM parameters
*//***************************************************************************/
typedef _Packed struct t_FmIpcParams {
uint16_t fmClkFreq; /**< OUT: FM Clock frequency */
uint16_t fmMacClkFreq; /**< OUT: FM MAC clock frequence */
uint8_t majorRev; /**< OUT: FM Major revision */
uint8_t minorRev; /**< OUT: FM Minor revision */
} _PackedType t_FmIpcParams;
/**************************************************************************//**
@Description structure for returning Fman Ctrl Code revision information
*//***************************************************************************/
typedef _Packed struct t_FmIpcFmanCtrlCodeRevisionInfo {
uint16_t packageRev; /**< OUT: Package revision */
uint8_t majorRev; /**< OUT: Major revision */
uint8_t minorRev; /**< OUT: Minor revision */
} _PackedType t_FmIpcFmanCtrlCodeRevisionInfo;
/**************************************************************************//**
@Description Structure for defining Fm number of Fman controlers
*//***************************************************************************/
typedef _Packed struct t_FmIpcPortNumOfFmanCtrls {
uint8_t hardwarePortId; /**< IN. port Id */
uint8_t numOfFmanCtrls; /**< IN. Port type */
t_FmFmanCtrl orFmanCtrl; /**< IN. fman controller for order restoration*/
} t_FmIpcPortNumOfFmanCtrls;
/**************************************************************************//**
@Description structure for setting Fman contriller events
*//***************************************************************************/
typedef _Packed struct t_FmIpcFmanEvents {
uint8_t eventRegId; /**< IN: Fman controller event register id */
uint32_t enableEvents; /**< IN/OUT: required enabled events mask */
} _PackedType t_FmIpcFmanEvents;
typedef _Packed struct t_FmIpcResourceAllocParams {
uint8_t guestId;
uint16_t base;
uint16_t num;
}_PackedType t_FmIpcResourceAllocParams;
typedef _Packed struct t_FmIpcVspSetPortWindow {
uint8_t hardwarePortId;
uint8_t baseStorageProfile;
uint8_t log2NumOfProfiles;
}_PackedType t_FmIpcVspSetPortWindow;
typedef _Packed struct t_FmIpcSetCongestionGroupPfcPriority {
uint32_t congestionGroupId;
uint8_t priorityBitMap;
}_PackedType t_FmIpcSetCongestionGroupPfcPriority;
#define FM_IPC_MAX_REPLY_BODY_SIZE 20
#define FM_IPC_MAX_REPLY_SIZE (FM_IPC_MAX_REPLY_BODY_SIZE + sizeof(uint32_t))
#define FM_IPC_MAX_MSG_SIZE 30
typedef _Packed struct t_FmIpcMsg
{
uint32_t msgId;
uint8_t msgBody[FM_IPC_MAX_MSG_SIZE];
} _PackedType t_FmIpcMsg;
typedef _Packed struct t_FmIpcReply
{
uint32_t error;
uint8_t replyBody[FM_IPC_MAX_REPLY_BODY_SIZE];
} _PackedType t_FmIpcReply;
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(pop)
#endif /* defined(__MWERKS__) && ... */
/***************************************************************************/
/************************ FRONT-END-TO-BACK-END*****************************/
/***************************************************************************/
/**************************************************************************//**
@Function FM_GET_TIMESTAMP_SCALE
@Description Used by FM front-end.
@Param[out] uint32_t Pointer
*//***************************************************************************/
#define FM_GET_TIMESTAMP_SCALE 1
/**************************************************************************//**
@Function FM_GET_COUNTER
@Description Used by FM front-end.
@Param[in/out] t_FmIpcGetCounter Pointer
*//***************************************************************************/
#define FM_GET_COUNTER 2
/**************************************************************************//**
@Function FM_GET_SET_PORT_PARAMS
@Description Used by FM front-end for the PORT module in order to set and get
parameters in/from master FM module on FM PORT initialization time.
@Param[in/out] t_FmIcPortInitParams Pointer
*//***************************************************************************/
#define FM_GET_SET_PORT_PARAMS 4
/**************************************************************************//**
@Function FM_FREE_PORT
@Description Used by FM front-end for the PORT module when a port is freed
to free all FM PORT resources.
@Param[in] uint8_t Pointer
*//***************************************************************************/
#define FM_FREE_PORT 5
/**************************************************************************//**
@Function FM_RESET_MAC
@Description Used by front-end for the MAC module to reset the MAC registers
@Param[in] t_FmIpcMacParams Pointer .
*//***************************************************************************/
#define FM_RESET_MAC 6
/**************************************************************************//**
@Function FM_RESUME_STALLED_PORT
@Description Used by FM front-end for the PORT module in order to
release a stalled FM Port.
@Param[in] uint8_t Pointer
*//***************************************************************************/
#define FM_RESUME_STALLED_PORT 7
/**************************************************************************//**
@Function FM_IS_PORT_STALLED
@Description Used by FM front-end for the PORT module in order to check whether
an FM port is stalled.
@Param[in/out] t_FmIcPortIsStalled Pointer
*//***************************************************************************/
#define FM_IS_PORT_STALLED 8
/**************************************************************************//**
@Function FM_GET_PARAMS
@Description Used by FM front-end for the PORT module in order to dump
return FM parameters.
@Param[in] uint8_t Pointer
*//***************************************************************************/
#define FM_GET_PARAMS 10
/**************************************************************************//**
@Function FM_REGISTER_INTR
@Description Used by FM front-end to register an interrupt handler to
be called upon interrupt for guest.
@Param[out] t_FmIpcRegisterIntr Pointer
*//***************************************************************************/
#define FM_REGISTER_INTR 11
/**************************************************************************//**
@Function FM_DMA_STAT
@Description Used by FM front-end to read the FM DMA status.
@Param[out] t_FmIpcDmaStatus Pointer
*//***************************************************************************/
#define FM_DMA_STAT 13
/**************************************************************************//**
@Function FM_ALLOC_FMAN_CTRL_EVENT_REG
@Description Used by FM front-end to allocate event register.
@Param[out] Event register id Pointer
*//***************************************************************************/
#define FM_ALLOC_FMAN_CTRL_EVENT_REG 14
/**************************************************************************//**
@Function FM_FREE_FMAN_CTRL_EVENT_REG
@Description Used by FM front-end to free locate event register.
@Param[in] uint8_t Pointer - Event register id
*//***************************************************************************/
#define FM_FREE_FMAN_CTRL_EVENT_REG 15
/**************************************************************************//**
@Function FM_SET_FMAN_CTRL_EVENTS_ENABLE
@Description Used by FM front-end to enable events in the FPM
Fman controller event register.
@Param[in] t_FmIpcFmanEvents Pointer
*//***************************************************************************/
#define FM_SET_FMAN_CTRL_EVENTS_ENABLE 16
/**************************************************************************//**
@Function FM_SET_FMAN_CTRL_EVENTS_ENABLE
@Description Used by FM front-end to enable events in the FPM
Fman controller event register.
@Param[in/out] t_FmIpcFmanEvents Pointer
*//***************************************************************************/
#define FM_GET_FMAN_CTRL_EVENTS_ENABLE 17
/**************************************************************************//**
@Function FM_SET_MAC_MAX_FRAME
@Description Used by FM front-end to set MAC's MTU/RTU's in
back-end.
@Param[in/out] t_FmIpcMacMaxFrameParams Pointer
*//***************************************************************************/
#define FM_SET_MAC_MAX_FRAME 18
/**************************************************************************//**
@Function FM_GET_PHYS_MURAM_BASE
@Description Used by FM front-end in order to get MURAM base address
@Param[in/out] t_FmIpcPhysAddr Pointer
*//***************************************************************************/
#define FM_GET_PHYS_MURAM_BASE 19
/**************************************************************************//**
@Function FM_MASTER_IS_ALIVE
@Description Used by FM front-end in order to verify Master is up
@Param[in/out] bool
*//***************************************************************************/
#define FM_MASTER_IS_ALIVE 20
#define FM_ENABLE_RAM_ECC 21
#define FM_DISABLE_RAM_ECC 22
#define FM_SET_NUM_OF_FMAN_CTRL 23
#define FM_SET_SIZE_OF_FIFO 24
#define FM_SET_NUM_OF_TASKS 25
#define FM_SET_NUM_OF_OPEN_DMAS 26
#define FM_VSP_ALLOC 27
#define FM_VSP_FREE 28
#define FM_VSP_SET_PORT_WINDOW 29
#define FM_GET_FMAN_CTRL_CODE_REV 30
#define FM_SET_CONG_GRP_PFC_PRIO 31
#ifdef FM_TX_ECC_FRMS_ERRATA_10GMAC_A004
#define FM_10G_TX_ECC_WA 100
#endif /* FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 */
/***************************************************************************/
/************************ BACK-END-TO-FRONT-END*****************************/
/***************************************************************************/
/**************************************************************************//**
@Function FM_GUEST_ISR
@Description Used by FM back-end to report an interrupt to the front-end.
@Param[out] t_FmIpcIsr Pointer
*//***************************************************************************/
#define FM_GUEST_ISR 1
/** @} */ /* end of FM_IPC_grp group */
/** @} */ /* end of FM_grp group */
#endif /* __FM_IPC_H */

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/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File FM_muram.c
@Description FM MURAM ...
*//***************************************************************************/
#include "error_ext.h"
#include "std_ext.h"
#include "mm_ext.h"
#include "string_ext.h"
#include "sprint_ext.h"
#include "fm_muram_ext.h"
#include "fm_common.h"
#define __ERR_MODULE__ MODULE_FM_MURAM
typedef struct
{
t_Handle h_Mem;
uintptr_t baseAddr;
uint32_t size;
} t_FmMuram;
void FmMuramClear(t_Handle h_FmMuram)
{
t_FmMuram *p_FmMuram = ( t_FmMuram *)h_FmMuram;
SANITY_CHECK_RETURN(h_FmMuram, E_INVALID_HANDLE);
IOMemSet32(UINT_TO_PTR(p_FmMuram->baseAddr), 0, p_FmMuram->size);
}
t_Handle FM_MURAM_ConfigAndInit(uintptr_t baseAddress, uint32_t size)
{
t_Handle h_Mem;
t_FmMuram *p_FmMuram;
if (!baseAddress)
{
REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("baseAddress 0 is not supported"));
return NULL;
}
if (baseAddress%4)
{
REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("baseAddress not 4 bytes aligned!"));
return NULL;
}
/* Allocate FM MURAM structure */
p_FmMuram = (t_FmMuram *) XX_Malloc(sizeof(t_FmMuram));
if (!p_FmMuram)
{
REPORT_ERROR(MAJOR, E_NO_MEMORY, ("FM MURAM driver structure"));
return NULL;
}
memset(p_FmMuram, 0, sizeof(t_FmMuram));
if ((MM_Init(&h_Mem, baseAddress, size) != E_OK) || (!h_Mem))
{
XX_Free(p_FmMuram);
REPORT_ERROR(MAJOR, E_INVALID_HANDLE, ("FM-MURAM partition!!!"));
return NULL;
}
/* Initialize FM MURAM parameters which will be kept by the driver */
p_FmMuram->baseAddr = baseAddress;
p_FmMuram->size = size;
p_FmMuram->h_Mem = h_Mem;
return p_FmMuram;
}
t_Error FM_MURAM_Free(t_Handle h_FmMuram)
{
t_FmMuram *p_FmMuram = ( t_FmMuram *)h_FmMuram;
if (p_FmMuram->h_Mem)
MM_Free(p_FmMuram->h_Mem);
XX_Free(h_FmMuram);
return E_OK;
}
void * FM_MURAM_AllocMem(t_Handle h_FmMuram, uint32_t size, uint32_t align)
{
t_FmMuram *p_FmMuram = ( t_FmMuram *)h_FmMuram;
uintptr_t addr;
SANITY_CHECK_RETURN_VALUE(h_FmMuram, E_INVALID_HANDLE, NULL);
SANITY_CHECK_RETURN_VALUE(p_FmMuram->h_Mem, E_INVALID_HANDLE, NULL);
addr = (uintptr_t)MM_Get(p_FmMuram->h_Mem, size, align ,"FM MURAM");
if (addr == ILLEGAL_BASE)
return NULL;
return UINT_TO_PTR(addr);
}
void * FM_MURAM_AllocMemForce(t_Handle h_FmMuram, uint64_t base, uint32_t size)
{
t_FmMuram *p_FmMuram = ( t_FmMuram *)h_FmMuram;
uintptr_t addr;
SANITY_CHECK_RETURN_VALUE(h_FmMuram, E_INVALID_HANDLE, NULL);
SANITY_CHECK_RETURN_VALUE(p_FmMuram->h_Mem, E_INVALID_HANDLE, NULL);
addr = (uintptr_t)MM_GetForce(p_FmMuram->h_Mem, base, size, "FM MURAM");
if (addr == ILLEGAL_BASE)
return NULL;
return UINT_TO_PTR(addr);
}
t_Error FM_MURAM_FreeMem(t_Handle h_FmMuram, void *ptr)
{
t_FmMuram *p_FmMuram = ( t_FmMuram *)h_FmMuram;
SANITY_CHECK_RETURN_ERROR(h_FmMuram, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmMuram->h_Mem, E_INVALID_HANDLE);
if (MM_Put(p_FmMuram->h_Mem, PTR_TO_UINT(ptr)) == 0)
RETURN_ERROR(MINOR, E_INVALID_ADDRESS, ("memory pointer!!!"));
return E_OK;
}
uint64_t FM_MURAM_GetFreeMemSize(t_Handle h_FmMuram)
{
t_FmMuram *p_FmMuram = ( t_FmMuram *)h_FmMuram;
SANITY_CHECK_RETURN_VALUE(h_FmMuram, E_INVALID_HANDLE, 0);
SANITY_CHECK_RETURN_VALUE(p_FmMuram->h_Mem, E_INVALID_HANDLE, 0);
return MM_GetFreeMemSize(p_FmMuram->h_Mem);
}

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93
drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/inc/fm_hc.h Normal file
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/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __FM_HC_H
#define __FM_HC_H
#include "std_ext.h"
#include "error_ext.h"
#include "fsl_fman_kg.h"
#define __ERR_MODULE__ MODULE_FM_PCD
typedef struct t_FmHcParams {
t_Handle h_Fm;
t_Handle h_FmPcd;
t_FmPcdHcParams params;
} t_FmHcParams;
t_Handle FmHcConfigAndInit(t_FmHcParams *p_FmHcParams);
void FmHcFree(t_Handle h_FmHc);
t_Error FmHcSetFramesDataMemory(t_Handle h_FmHc,
uint8_t memId);
t_Error FmHcDumpRegs(t_Handle h_FmHc);
void FmHcTxConf(t_Handle h_FmHc, t_DpaaFD *p_Fd);
t_Error FmHcPcdKgSetScheme(t_Handle h_FmHc,
t_Handle h_Scheme,
struct fman_kg_scheme_regs *p_SchemeRegs,
bool updateCounter);
t_Error FmHcPcdKgDeleteScheme(t_Handle h_FmHc, t_Handle h_Scheme);
t_Error FmHcPcdCcCapwapTimeoutReassm(t_Handle h_FmHc, t_FmPcdCcCapwapReassmTimeoutParams *p_CcCapwapReassmTimeoutParams );
t_Error FmHcPcdCcIpFragScratchPollCmd(t_Handle h_FmHc, bool fill, t_FmPcdCcFragScratchPoolCmdParams *p_FmPcdCcFragScratchPoolCmdParams);
t_Error FmHcPcdCcTimeoutReassm(t_Handle h_FmHc, t_FmPcdCcReassmTimeoutParams *p_CcReassmTimeoutParams, uint8_t *p_Result);
t_Error FmHcPcdKgSetClsPlan(t_Handle h_FmHc, t_FmPcdKgInterModuleClsPlanSet *p_Set);
t_Error FmHcPcdKgDeleteClsPlan(t_Handle h_FmHc, uint8_t clsPlanGrpId);
t_Error FmHcPcdKgSetSchemeCounter(t_Handle h_FmHc, t_Handle h_Scheme, uint32_t value);
uint32_t FmHcPcdKgGetSchemeCounter(t_Handle h_FmHc, t_Handle h_Scheme);
t_Error FmHcPcdCcDoDynamicChange(t_Handle h_FmHc, uint32_t oldAdAddrOffset, uint32_t newAdAddrOffset);
t_Error FmHcPcdPlcrSetProfile(t_Handle h_FmHc, t_Handle h_Profile, t_FmPcdPlcrProfileRegs *p_PlcrRegs);
t_Error FmHcPcdPlcrDeleteProfile(t_Handle h_FmHc, t_Handle h_Profile);
t_Error FmHcPcdPlcrSetProfileCounter(t_Handle h_FmHc, t_Handle h_Profile, e_FmPcdPlcrProfileCounters counter, uint32_t value);
uint32_t FmHcPcdPlcrGetProfileCounter(t_Handle h_FmHc, t_Handle h_Profile, e_FmPcdPlcrProfileCounters counter);
t_Error FmHcKgWriteSp(t_Handle h_FmHc, uint8_t hardwarePortId, uint32_t spReg, bool add);
t_Error FmHcKgWriteCpp(t_Handle h_FmHc, uint8_t hardwarePortId, uint32_t cppReg);
t_Error FmHcPcdKgCcGetSetParams(t_Handle h_FmHc, t_Handle h_Scheme, uint32_t requiredAction, uint32_t value);
t_Error FmHcPcdPlcrCcGetSetParams(t_Handle h_FmHc,uint16_t absoluteProfileId, uint32_t requiredAction);
t_Error FmHcPcdSync(t_Handle h_FmHc);
t_Handle FmHcGetPort(t_Handle h_FmHc);
#endif /* __FM_HC_H */

117
drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/inc/fm_sp_common.h Normal file
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/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_sp_common.h
@Description FM SP ...
*//***************************************************************************/
#ifndef __FM_SP_COMMON_H
#define __FM_SP_COMMON_H
#include "std_ext.h"
#include "error_ext.h"
#include "list_ext.h"
#include "fm_ext.h"
#include "fm_pcd_ext.h"
#include "fsl_fman.h"
/**************************************************************************//**
@Description defaults
*//***************************************************************************/
#define DEFAULT_FM_SP_bufferPrefixContent_privDataSize 0
#define DEFAULT_FM_SP_bufferPrefixContent_passPrsResult FALSE
#define DEFAULT_FM_SP_bufferPrefixContent_passTimeStamp FALSE
#define DEFAULT_FM_SP_bufferPrefixContent_allOtherPCDInfo FALSE
#define DEFAULT_FM_SP_bufferPrefixContent_dataAlign 64
/**************************************************************************//**
@Description structure for defining internal context copying
*//***************************************************************************/
typedef struct
{
uint16_t extBufOffset; /**< Offset in External buffer to which internal
context is copied to (Rx) or taken from (Tx, Op). */
uint8_t intContextOffset; /**< Offset within internal context to copy from
(Rx) or to copy to (Tx, Op). */
uint16_t size; /**< Internal offset size to be copied */
} t_FmSpIntContextDataCopy;
/**************************************************************************//**
@Description struct for defining external buffer margins
*//***************************************************************************/
typedef struct {
uint16_t startMargins; /**< Number of bytes to be left at the beginning
of the external buffer (must be divisible by 16) */
uint16_t endMargins; /**< number of bytes to be left at the end
of the external buffer(must be divisible by 16) */
} t_FmSpBufMargins;
typedef struct {
uint32_t dataOffset;
uint32_t prsResultOffset;
uint32_t timeStampOffset;
uint32_t hashResultOffset;
uint32_t pcdInfoOffset;
uint32_t manipOffset;
} t_FmSpBufferOffsets;
t_Error FmSpBuildBufferStructure(t_FmSpIntContextDataCopy *p_FmPortIntContextDataCopy,
t_FmBufferPrefixContent *p_BufferPrefixContent,
t_FmSpBufMargins *p_FmPortBufMargins,
t_FmSpBufferOffsets *p_FmPortBufferOffsets,
uint8_t *internalBufferOffset);
t_Error FmSpCheckIntContextParams(t_FmSpIntContextDataCopy *p_FmSpIntContextDataCopy);
t_Error FmSpCheckBufPoolsParams(t_FmExtPools *p_FmExtPools,
t_FmBackupBmPools *p_FmBackupBmPools,
t_FmBufPoolDepletion *p_FmBufPoolDepletion);
t_Error FmSpCheckBufMargins(t_FmSpBufMargins *p_FmSpBufMargins);
void FmSpSetBufPoolsInAscOrderOfBufSizes(t_FmExtPools *p_FmExtPools, uint8_t *orderedArray, uint16_t *sizesArray);
t_Error FmPcdSpAllocProfiles(t_Handle h_FmPcd,
uint8_t hardwarePortId,
uint16_t numOfStorageProfiles,
uint16_t *base,
uint8_t *log2Num);
t_Error FmPcdSpGetAbsoluteProfileId(t_Handle h_FmPcd,
t_Handle h_FmPort,
uint16_t relativeProfile,
uint16_t *p_AbsoluteId);
void SpInvalidateProfileSw(t_Handle h_FmPcd, uint16_t absoluteProfileId);
void SpValidateProfileSw(t_Handle h_FmPcd, uint16_t absoluteProfileId);
#endif /* __FM_SP_COMMON_H */

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drivers/net/ethernet/freescale/sdk_fman/etc/Makefile Normal file
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#
# Makefile for the Freescale Ethernet controllers
#
ccflags-y += -DVERSION=\"\"
#
#Include netcomm SW specific definitions
include $(srctree)/drivers/net/ethernet/freescale/sdk_fman/ncsw_config.mk
obj-y += fsl-ncsw-etc.o
fsl-ncsw-etc-objs := mm.o memcpy.o sprint.o list.o error.o

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/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
@File error.c
@Description General errors and events reporting utilities.
*//***************************************************************************/
#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0))
#include "error_ext.h"
const char *dbgLevelStrings[] =
{
"CRITICAL"
,"MAJOR"
,"MINOR"
,"WARNING"
,"INFO"
,"TRACE"
};
char * ErrTypeStrings (e_ErrorType err)
{
switch (err)
{
case (E_OK): return "OK";
case (E_WRITE_FAILED): return "Write Access Failed";
case (E_NO_DEVICE): return "No Device";
case (E_NOT_AVAILABLE): return "Resource Is Unavailable";
case (E_NO_MEMORY): return "Memory Allocation Failed";
case (E_INVALID_ADDRESS): return "Invalid Address";
case (E_BUSY): return "Resource Is Busy";
case (E_ALREADY_EXISTS): return "Resource Already Exists";
case (E_INVALID_OPERATION): return "Invalid Operation";
case (E_INVALID_VALUE): return "Invalid Value";
case (E_NOT_IN_RANGE): return "Value Out Of Range";
case (E_NOT_SUPPORTED): return "Unsupported Operation";
case (E_INVALID_STATE): return "Invalid State";
case (E_INVALID_HANDLE): return "Invalid Handle";
case (E_INVALID_ID): return "Invalid ID";
case (E_NULL_POINTER): return "Unexpected NULL Pointer";
case (E_INVALID_SELECTION): return "Invalid Selection";
case (E_INVALID_COMM_MODE): return "Invalid Communication Mode";
case (E_INVALID_MEMORY_TYPE): return "Invalid Memory Type";
case (E_INVALID_CLOCK): return "Invalid Clock";
case (E_CONFLICT): return "Conflict In Settings";
case (E_NOT_ALIGNED): return "Incorrect Alignment";
case (E_NOT_FOUND): return "Resource Not Found";
case (E_FULL): return "Resource Is Full";
case (E_EMPTY): return "Resource Is Empty";
case (E_ALREADY_FREE): return "Resource Already Free";
case (E_READ_FAILED): return "Read Access Failed";
case (E_INVALID_FRAME): return "Invalid Frame";
case (E_SEND_FAILED): return "Send Operation Failed";
case (E_RECEIVE_FAILED): return "Receive Operation Failed";
case (E_TIMEOUT): return "Operation Timed Out";
default:
break;
}
return NULL;
}
#endif /* (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)) */

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/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**************************************************************************//**
@File list.c
@Description Implementation of list.
*//***************************************************************************/
#include "std_ext.h"
#include "list_ext.h"
void LIST_Append(t_List *p_NewList, t_List *p_Head)
{
t_List *p_First = LIST_FIRST(p_NewList);
if (p_First != p_NewList)
{
t_List *p_Last = LIST_LAST(p_NewList);
t_List *p_Cur = LIST_NEXT(p_Head);
LIST_PREV(p_First) = p_Head;
LIST_FIRST(p_Head) = p_First;
LIST_NEXT(p_Last) = p_Cur;
LIST_LAST(p_Cur) = p_Last;
}
}
int LIST_NumOfObjs(t_List *p_List)
{
t_List *p_Tmp;
int numOfObjs = 0;
if (!LIST_IsEmpty(p_List))
LIST_FOR_EACH(p_Tmp, p_List)
numOfObjs++;
return numOfObjs;
}

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/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "std_ext.h"
#include "xx_ext.h"
#include "memcpy_ext.h"
void * MemCpy8(void* pDst, void* pSrc, uint32_t size)
{
int i;
for(i = 0; i < size; ++i)
*(((uint8_t*)(pDst)) + i) = *(((uint8_t*)(pSrc)) + i);
return pDst;
}
void * MemSet8(void* pDst, int c, uint32_t size)
{
int i;
for(i = 0; i < size; ++i)
*(((uint8_t*)(pDst)) + i) = (uint8_t)(c);
return pDst;
}
void * MemCpy32(void* pDst,void* pSrc, uint32_t size)
{
uint32_t leftAlign;
uint32_t rightAlign;
uint32_t lastWord;
uint32_t currWord;
uint32_t *p_Src32;
uint32_t *p_Dst32;
uint8_t *p_Src8;
uint8_t *p_Dst8;
p_Src8 = (uint8_t*)(pSrc);
p_Dst8 = (uint8_t*)(pDst);
/* first copy byte by byte till the source first alignment
* this step is necessary to ensure we do not even try to access
* data which is before the source buffer, hence it is not ours.
*/
while((PTR_TO_UINT(p_Src8) & 3) && size) /* (pSrc mod 4) > 0 and size > 0 */
{
*p_Dst8++ = *p_Src8++;
size--;
}
/* align destination (possibly disaligning source)*/
while((PTR_TO_UINT(p_Dst8) & 3) && size) /* (pDst mod 4) > 0 and size > 0 */
{
*p_Dst8++ = *p_Src8++;
size--;
}
/* dest is aligned and source is not necessarily aligned */
leftAlign = (uint32_t)((PTR_TO_UINT(p_Src8) & 3) << 3); /* leftAlign = (pSrc mod 4)*8 */
rightAlign = 32 - leftAlign;
if (leftAlign == 0)
{
/* source is also aligned */
p_Src32 = (uint32_t*)(p_Src8);
p_Dst32 = (uint32_t*)(p_Dst8);
while (size >> 2) /* size >= 4 */
{
*p_Dst32++ = *p_Src32++;
size -= 4;
}
p_Src8 = (uint8_t*)(p_Src32);
p_Dst8 = (uint8_t*)(p_Dst32);
}
else
{
/* source is not aligned (destination is aligned)*/
p_Src32 = (uint32_t*)(p_Src8 - (leftAlign >> 3));
p_Dst32 = (uint32_t*)(p_Dst8);
lastWord = *p_Src32++;
while(size >> 3) /* size >= 8 */
{
currWord = *p_Src32;
*p_Dst32 = (lastWord << leftAlign) | (currWord >> rightAlign);
lastWord = currWord;
p_Src32++;
p_Dst32++;
size -= 4;
}
p_Dst8 = (uint8_t*)(p_Dst32);
p_Src8 = (uint8_t*)(p_Src32) - 4 + (leftAlign >> 3);
}
/* complete the left overs */
while (size--)
*p_Dst8++ = *p_Src8++;
return pDst;
}
void * IO2IOCpy32(void* pDst,void* pSrc, uint32_t size)
{
uint32_t leftAlign;
uint32_t rightAlign;
uint32_t lastWord;
uint32_t currWord;
uint32_t *p_Src32;
uint32_t *p_Dst32;
uint8_t *p_Src8;
uint8_t *p_Dst8;
p_Src8 = (uint8_t*)(pSrc);
p_Dst8 = (uint8_t*)(pDst);
/* first copy byte by byte till the source first alignment
* this step is necessary to ensure we do not even try to access
* data which is before the source buffer, hence it is not ours.
*/
while((PTR_TO_UINT(p_Src8) & 3) && size) /* (pSrc mod 4) > 0 and size > 0 */
{
WRITE_UINT8(*p_Dst8, GET_UINT8(*p_Src8));
p_Dst8++;p_Src8++;
size--;
}
/* align destination (possibly disaligning source)*/
while((PTR_TO_UINT(p_Dst8) & 3) && size) /* (pDst mod 4) > 0 and size > 0 */
{
WRITE_UINT8(*p_Dst8, GET_UINT8(*p_Src8));
p_Dst8++;p_Src8++;
size--;
}
/* dest is aligned and source is not necessarily aligned */
leftAlign = (uint32_t)((PTR_TO_UINT(p_Src8) & 3) << 3); /* leftAlign = (pSrc mod 4)*8 */
rightAlign = 32 - leftAlign;
if (leftAlign == 0)
{
/* source is also aligned */
p_Src32 = (uint32_t*)(p_Src8);
p_Dst32 = (uint32_t*)(p_Dst8);
while (size >> 2) /* size >= 4 */
{
WRITE_UINT32(*p_Dst32, GET_UINT32(*p_Src32));
p_Dst32++;p_Src32++;
size -= 4;
}
p_Src8 = (uint8_t*)(p_Src32);
p_Dst8 = (uint8_t*)(p_Dst32);
}
else
{
/* source is not aligned (destination is aligned)*/
p_Src32 = (uint32_t*)(p_Src8 - (leftAlign >> 3));
p_Dst32 = (uint32_t*)(p_Dst8);
lastWord = GET_UINT32(*p_Src32);
p_Src32++;
while(size >> 3) /* size >= 8 */
{
currWord = GET_UINT32(*p_Src32);
WRITE_UINT32(*p_Dst32, (lastWord << leftAlign) | (currWord >> rightAlign));
lastWord = currWord;
p_Src32++;p_Dst32++;
size -= 4;
}
p_Dst8 = (uint8_t*)(p_Dst32);
p_Src8 = (uint8_t*)(p_Src32) - 4 + (leftAlign >> 3);
}
/* complete the left overs */
while (size--)
{
WRITE_UINT8(*p_Dst8, GET_UINT8(*p_Src8));
p_Dst8++;p_Src8++;
}
return pDst;
}
void * Mem2IOCpy32(void* pDst,void* pSrc, uint32_t size)
{
uint32_t leftAlign;
uint32_t rightAlign;
uint32_t lastWord;
uint32_t currWord;
uint32_t *p_Src32;
uint32_t *p_Dst32;
uint8_t *p_Src8;
uint8_t *p_Dst8;
p_Src8 = (uint8_t*)(pSrc);
p_Dst8 = (uint8_t*)(pDst);
/* first copy byte by byte till the source first alignment
* this step is necessary to ensure we do not even try to access
* data which is before the source buffer, hence it is not ours.
*/
while((PTR_TO_UINT(p_Src8) & 3) && size) /* (pSrc mod 4) > 0 and size > 0 */
{
WRITE_UINT8(*p_Dst8, *p_Src8);
p_Dst8++;p_Src8++;
size--;
}
/* align destination (possibly disaligning source)*/
while((PTR_TO_UINT(p_Dst8) & 3) && size) /* (pDst mod 4) > 0 and size > 0 */
{
WRITE_UINT8(*p_Dst8, *p_Src8);
p_Dst8++;p_Src8++;
size--;
}
/* dest is aligned and source is not necessarily aligned */
leftAlign = (uint32_t)((PTR_TO_UINT(p_Src8) & 3) << 3); /* leftAlign = (pSrc mod 4)*8 */
rightAlign = 32 - leftAlign;
if (leftAlign == 0)
{
/* source is also aligned */
p_Src32 = (uint32_t*)(p_Src8);
p_Dst32 = (uint32_t*)(p_Dst8);
while (size >> 2) /* size >= 4 */
{
WRITE_UINT32(*p_Dst32, *p_Src32);
p_Dst32++;p_Src32++;
size -= 4;
}
p_Src8 = (uint8_t*)(p_Src32);
p_Dst8 = (uint8_t*)(p_Dst32);
}
else
{
/* source is not aligned (destination is aligned)*/
p_Src32 = (uint32_t*)(p_Src8 - (leftAlign >> 3));
p_Dst32 = (uint32_t*)(p_Dst8);
lastWord = *p_Src32++;
while(size >> 3) /* size >= 8 */
{
currWord = *p_Src32;
WRITE_UINT32(*p_Dst32, (lastWord << leftAlign) | (currWord >> rightAlign));
lastWord = currWord;
p_Src32++;p_Dst32++;
size -= 4;
}
p_Dst8 = (uint8_t*)(p_Dst32);
p_Src8 = (uint8_t*)(p_Src32) - 4 + (leftAlign >> 3);
}
/* complete the left overs */
while (size--)
{
WRITE_UINT8(*p_Dst8, *p_Src8);
p_Dst8++;p_Src8++;
}
return pDst;
}
void * IO2MemCpy32(void* pDst,void* pSrc, uint32_t size)
{
uint32_t leftAlign;
uint32_t rightAlign;
uint32_t lastWord;
uint32_t currWord;
uint32_t *p_Src32;
uint32_t *p_Dst32;
uint8_t *p_Src8;
uint8_t *p_Dst8;
p_Src8 = (uint8_t*)(pSrc);
p_Dst8 = (uint8_t*)(pDst);
/* first copy byte by byte till the source first alignment
* this step is necessary to ensure we do not even try to access
* data which is before the source buffer, hence it is not ours.
*/
while((PTR_TO_UINT(p_Src8) & 3) && size) /* (pSrc mod 4) > 0 and size > 0 */
{
*p_Dst8 = GET_UINT8(*p_Src8);
p_Dst8++;p_Src8++;
size--;
}
/* align destination (possibly disaligning source)*/
while((PTR_TO_UINT(p_Dst8) & 3) && size) /* (pDst mod 4) > 0 and size > 0 */
{
*p_Dst8 = GET_UINT8(*p_Src8);
p_Dst8++;p_Src8++;
size--;
}
/* dest is aligned and source is not necessarily aligned */
leftAlign = (uint32_t)((PTR_TO_UINT(p_Src8) & 3) << 3); /* leftAlign = (pSrc mod 4)*8 */
rightAlign = 32 - leftAlign;
if (leftAlign == 0)
{
/* source is also aligned */
p_Src32 = (uint32_t*)(p_Src8);
p_Dst32 = (uint32_t*)(p_Dst8);
while (size >> 2) /* size >= 4 */
{
*p_Dst32 = GET_UINT32(*p_Src32);
p_Dst32++;p_Src32++;
size -= 4;
}
p_Src8 = (uint8_t*)(p_Src32);
p_Dst8 = (uint8_t*)(p_Dst32);
}
else
{
/* source is not aligned (destination is aligned)*/
p_Src32 = (uint32_t*)(p_Src8 - (leftAlign >> 3));
p_Dst32 = (uint32_t*)(p_Dst8);
lastWord = GET_UINT32(*p_Src32);
p_Src32++;
while(size >> 3) /* size >= 8 */
{
currWord = GET_UINT32(*p_Src32);
*p_Dst32 = (lastWord << leftAlign) | (currWord >> rightAlign);
lastWord = currWord;
p_Src32++;p_Dst32++;
size -= 4;
}
p_Dst8 = (uint8_t*)(p_Dst32);
p_Src8 = (uint8_t*)(p_Src32) - 4 + (leftAlign >> 3);
}
/* complete the left overs */
while (size--)
{
*p_Dst8 = GET_UINT8(*p_Src8);
p_Dst8++;p_Src8++;
}
return pDst;
}
void * MemCpy64(void* pDst,void* pSrc, uint32_t size)
{
uint32_t leftAlign;
uint32_t rightAlign;
uint64_t lastWord;
uint64_t currWord;
uint64_t *pSrc64;
uint64_t *pDst64;
uint8_t *p_Src8;
uint8_t *p_Dst8;
p_Src8 = (uint8_t*)(pSrc);
p_Dst8 = (uint8_t*)(pDst);
/* first copy byte by byte till the source first alignment
* this step is necessarily to ensure we do not even try to access
* data which is before the source buffer, hence it is not ours.
*/
while((PTR_TO_UINT(p_Src8) & 7) && size) /* (pSrc mod 8) > 0 and size > 0 */
{
*p_Dst8++ = *p_Src8++;
size--;
}
/* align destination (possibly disaligning source)*/
while((PTR_TO_UINT(p_Dst8) & 7) && size) /* (pDst mod 8) > 0 and size > 0 */
{
*p_Dst8++ = *p_Src8++;
size--;
}
/* dest is aligned and source is not necessarily aligned */
leftAlign = (uint32_t)((PTR_TO_UINT(p_Src8) & 7) << 3); /* leftAlign = (pSrc mod 8)*8 */
rightAlign = 64 - leftAlign;
if (leftAlign == 0)
{
/* source is also aligned */
pSrc64 = (uint64_t*)(p_Src8);
pDst64 = (uint64_t*)(p_Dst8);
while (size >> 3) /* size >= 8 */
{
*pDst64++ = *pSrc64++;
size -= 8;
}
p_Src8 = (uint8_t*)(pSrc64);
p_Dst8 = (uint8_t*)(pDst64);
}
else
{
/* source is not aligned (destination is aligned)*/
pSrc64 = (uint64_t*)(p_Src8 - (leftAlign >> 3));
pDst64 = (uint64_t*)(p_Dst8);
lastWord = *pSrc64++;
while(size >> 4) /* size >= 16 */
{
currWord = *pSrc64;
*pDst64 = (lastWord << leftAlign) | (currWord >> rightAlign);
lastWord = currWord;
pSrc64++;
pDst64++;
size -= 8;
}
p_Dst8 = (uint8_t*)(pDst64);
p_Src8 = (uint8_t*)(pSrc64) - 8 + (leftAlign >> 3);
}
/* complete the left overs */
while (size--)
*p_Dst8++ = *p_Src8++;
return pDst;
}
void * MemSet32(void* pDst, uint8_t val, uint32_t size)
{
uint32_t val32;
uint32_t *p_Dst32;
uint8_t *p_Dst8;
p_Dst8 = (uint8_t*)(pDst);
/* generate four 8-bit val's in 32-bit container */
val32 = (uint32_t) val;
val32 |= (val32 << 8);
val32 |= (val32 << 16);
/* align destination to 32 */
while((PTR_TO_UINT(p_Dst8) & 3) && size) /* (pDst mod 4) > 0 and size > 0 */
{
*p_Dst8++ = val;
size--;
}
/* 32-bit chunks */
p_Dst32 = (uint32_t*)(p_Dst8);
while (size >> 2) /* size >= 4 */
{
*p_Dst32++ = val32;
size -= 4;
}
/* complete the leftovers */
p_Dst8 = (uint8_t*)(p_Dst32);
while (size--)
*p_Dst8++ = val;
return pDst;
}
void * IOMemSet32(void* pDst, uint8_t val, uint32_t size)
{
uint32_t val32;
uint32_t *p_Dst32;
uint8_t *p_Dst8;
p_Dst8 = (uint8_t*)(pDst);
/* generate four 8-bit val's in 32-bit container */
val32 = (uint32_t) val;
val32 |= (val32 << 8);
val32 |= (val32 << 16);
/* align destination to 32 */
while((PTR_TO_UINT(p_Dst8) & 3) && size) /* (pDst mod 4) > 0 and size > 0 */
{
WRITE_UINT8(*p_Dst8, val);
p_Dst8++;
size--;
}
/* 32-bit chunks */
p_Dst32 = (uint32_t*)(p_Dst8);
while (size >> 2) /* size >= 4 */
{
WRITE_UINT32(*p_Dst32, val32);
p_Dst32++;
size -= 4;
}
/* complete the leftovers */
p_Dst8 = (uint8_t*)(p_Dst32);
while (size--)
{
WRITE_UINT8(*p_Dst8, val);
p_Dst8++;
}
return pDst;
}
void * MemSet64(void* pDst, uint8_t val, uint32_t size)
{
uint64_t val64;
uint64_t *pDst64;
uint8_t *p_Dst8;
p_Dst8 = (uint8_t*)(pDst);
/* generate four 8-bit val's in 32-bit container */
val64 = (uint64_t) val;
val64 |= (val64 << 8);
val64 |= (val64 << 16);
val64 |= (val64 << 24);
val64 |= (val64 << 32);
/* align destination to 64 */
while((PTR_TO_UINT(p_Dst8) & 7) && size) /* (pDst mod 8) > 0 and size > 0 */
{
*p_Dst8++ = val;
size--;
}
/* 64-bit chunks */
pDst64 = (uint64_t*)(p_Dst8);
while (size >> 4) /* size >= 8 */
{
*pDst64++ = val64;
size -= 8;
}
/* complete the leftovers */
p_Dst8 = (uint8_t*)(pDst64);
while (size--)
*p_Dst8++ = val;
return pDst;
}
void MemDisp(uint8_t *p, int size)
{
uint32_t space = (uint32_t)(PTR_TO_UINT(p) & 0x3);
uint8_t *p_Limit;
if (space)
{
p_Limit = (p - space + 4);
XX_Print("0x%08X: ", (p - space));
while (space--)
{
XX_Print("--");
}
while (size && (p < p_Limit))
{
XX_Print("%02x", *(uint8_t*)p);
size--;
p++;
}
XX_Print(" ");
p_Limit += 12;
while ((size > 3) && (p < p_Limit))
{
XX_Print("%08x ", *(uint32_t*)p);
size -= 4;
p += 4;
}
XX_Print("\r\n");
}
while (size > 15)
{
XX_Print("0x%08X: %08x %08x %08x %08x\r\n",
p, *(uint32_t *)p, *(uint32_t *)(p + 4),
*(uint32_t *)(p + 8), *(uint32_t *)(p + 12));
size -= 16;
p += 16;
}
if (size)
{
XX_Print("0x%08X: ", p);
while (size > 3)
{
XX_Print("%08x ", *(uint32_t *)p);
size -= 4;
p += 4;
}
while (size)
{
XX_Print("%02x", *(uint8_t *)p);
size--;
p++;
}
XX_Print("\r\n");
}
}

1155
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/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/****************************************************************
*
* File: mm.h
*
*
* Description:
* MM (Memory Management) object definitions.
* It also includes definitions of the Free Block, Busy Block
* and Memory Block structures used by the MM object.
*
****************************************************************/
#ifndef __MM_H
#define __MM_H
#include "mm_ext.h"
#define __ERR_MODULE__ MODULE_MM
#define MAKE_ALIGNED(addr, align) \
(((uint64_t)(addr) + ((align) - 1)) & (~(((uint64_t)align) - 1)))
/* t_MemBlock data structure defines parameters of the Memory Block */
typedef struct t_MemBlock
{
struct t_MemBlock *p_Next; /* Pointer to the next memory block */
uint64_t base; /* Base address of the memory block */
uint64_t end; /* End address of the memory block */
} t_MemBlock;
/* t_FreeBlock data structure defines parameters of the Free Block */
typedef struct t_FreeBlock
{
struct t_FreeBlock *p_Next; /* Pointer to the next free block */
uint64_t base; /* Base address of the block */
uint64_t end; /* End address of the block */
} t_FreeBlock;
/* t_BusyBlock data structure defines parameters of the Busy Block */
typedef struct t_BusyBlock
{
struct t_BusyBlock *p_Next; /* Pointer to the next free block */
uint64_t base; /* Base address of the block */
uint64_t end; /* End address of the block */
char name[MM_MAX_NAME_LEN]; /* That block of memory was allocated for
something specified by the Name */
} t_BusyBlock;
/* t_MM data structure defines parameters of the MM object */
typedef struct t_MM
{
t_Handle h_Spinlock;
t_MemBlock *memBlocks; /* List of memory blocks (Memory list) */
t_BusyBlock *busyBlocks; /* List of busy blocks (Busy list) */
t_FreeBlock *freeBlocks[MM_MAX_ALIGNMENT + 1];
/* Alignment lists of free blocks (Free lists) */
uint64_t freeMemSize; /* Total size of free memory (in bytes) */
} t_MM;
#endif /* __MM_H */

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/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*------------------------------------------------------*/
/* File: sprint.c */
/* */
/* Description: */
/* Debug routines (externals) */
/*------------------------------------------------------*/
#include "string_ext.h"
#include "stdlib_ext.h"
#include "stdarg_ext.h"
#include "sprint_ext.h"
#include "std_ext.h"
#include "xx_ext.h"
int Sprint(char * buf, const char *fmt, ...)
{
va_list args;
int i;
va_start(args, fmt);
i=vsprintf(buf,fmt,args);
va_end(args);
return i;
}
int Snprint(char * buf, uint32_t size, const char *fmt, ...)
{
va_list args;
int i;
va_start(args, fmt);
i=vsnprintf(buf,size,fmt,args);
va_end(args);
return i;
}
#ifndef NCSW_VXWORKS
int Sscan(const char * buf, const char * fmt, ...)
{
va_list args;
int i;
va_start(args,fmt);
i = vsscanf(buf,fmt,args);
va_end(args);
return i;
}
#endif /* NCSW_VXWORKS */

57
drivers/net/ethernet/freescale/sdk_fman/fmanv3h_dflags.h Normal file
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/*
* Copyright 2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __dflags_h
#define __dflags_h
#define NCSW_LINUX
#define T4240
#define NCSW_PPC_CORE
#define DEBUG_ERRORS 1
#if defined(DEBUG)
#define DEBUG_GLOBAL_LEVEL REPORT_LEVEL_INFO
#define DEBUG_XX_MALLOC
#define DEBUG_MEM_LEAKS
#else
#define DEBUG_GLOBAL_LEVEL REPORT_LEVEL_WARNING
#endif /* (DEBUG) */
#define REPORT_EVENTS 1
#define EVENT_GLOBAL_LEVEL REPORT_LEVEL_MINOR
#endif /* __dflags_h */

56
drivers/net/ethernet/freescale/sdk_fman/fmanv3l_dflags.h Normal file
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/*
* Copyright 2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __dflags_h
#define __dflags_h
#define NCSW_LINUX
#define NCSW_PPC_CORE
#define DEBUG_ERRORS 1
#if defined(DEBUG)
#define DEBUG_GLOBAL_LEVEL REPORT_LEVEL_INFO
#define DEBUG_XX_MALLOC
#define DEBUG_MEM_LEAKS
#else
#define DEBUG_GLOBAL_LEVEL REPORT_LEVEL_WARNING
#endif /* (DEBUG) */
#define REPORT_EVENTS 1
#define EVENT_GLOBAL_LEVEL REPORT_LEVEL_MINOR
#endif /* __dflags_h */

364
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/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*------------------------------------------------------*/
/* */
/* File: crc_mac_addr_ext.h */
/* */
/* Description: */
/* Define a macro that calculate the crc value of */
/* an Ethernet MAC address (48 bitd address */
/*------------------------------------------------------*/
#ifndef __crc_mac_addr_ext_h
#define __crc_mac_addr_ext_h
#include "std_ext.h"
static uint32_t crc_table[256] =
{
0x00000000,
0x77073096,
0xee0e612c,
0x990951ba,
0x076dc419,
0x706af48f,
0xe963a535,
0x9e6495a3,
0x0edb8832,
0x79dcb8a4,
0xe0d5e91e,
0x97d2d988,
0x09b64c2b,
0x7eb17cbd,
0xe7b82d07,
0x90bf1d91,
0x1db71064,
0x6ab020f2,
0xf3b97148,
0x84be41de,
0x1adad47d,
0x6ddde4eb,
0xf4d4b551,
0x83d385c7,
0x136c9856,
0x646ba8c0,
0xfd62f97a,
0x8a65c9ec,
0x14015c4f,
0x63066cd9,
0xfa0f3d63,
0x8d080df5,
0x3b6e20c8,
0x4c69105e,
0xd56041e4,
0xa2677172,
0x3c03e4d1,
0x4b04d447,
0xd20d85fd,
0xa50ab56b,
0x35b5a8fa,
0x42b2986c,
0xdbbbc9d6,
0xacbcf940,
0x32d86ce3,
0x45df5c75,
0xdcd60dcf,
0xabd13d59,
0x26d930ac,
0x51de003a,
0xc8d75180,
0xbfd06116,
0x21b4f4b5,
0x56b3c423,
0xcfba9599,
0xb8bda50f,
0x2802b89e,
0x5f058808,
0xc60cd9b2,
0xb10be924,
0x2f6f7c87,
0x58684c11,
0xc1611dab,
0xb6662d3d,
0x76dc4190,
0x01db7106,
0x98d220bc,
0xefd5102a,
0x71b18589,
0x06b6b51f,
0x9fbfe4a5,
0xe8b8d433,
0x7807c9a2,
0x0f00f934,
0x9609a88e,
0xe10e9818,
0x7f6a0dbb,
0x086d3d2d,
0x91646c97,
0xe6635c01,
0x6b6b51f4,
0x1c6c6162,
0x856530d8,
0xf262004e,
0x6c0695ed,
0x1b01a57b,
0x8208f4c1,
0xf50fc457,
0x65b0d9c6,
0x12b7e950,
0x8bbeb8ea,
0xfcb9887c,
0x62dd1ddf,
0x15da2d49,
0x8cd37cf3,
0xfbd44c65,
0x4db26158,
0x3ab551ce,
0xa3bc0074,
0xd4bb30e2,
0x4adfa541,
0x3dd895d7,
0xa4d1c46d,
0xd3d6f4fb,
0x4369e96a,
0x346ed9fc,
0xad678846,
0xda60b8d0,
0x44042d73,
0x33031de5,
0xaa0a4c5f,
0xdd0d7cc9,
0x5005713c,
0x270241aa,
0xbe0b1010,
0xc90c2086,
0x5768b525,
0x206f85b3,
0xb966d409,
0xce61e49f,
0x5edef90e,
0x29d9c998,
0xb0d09822,
0xc7d7a8b4,
0x59b33d17,
0x2eb40d81,
0xb7bd5c3b,
0xc0ba6cad,
0xedb88320,
0x9abfb3b6,
0x03b6e20c,
0x74b1d29a,
0xead54739,
0x9dd277af,
0x04db2615,
0x73dc1683,
0xe3630b12,
0x94643b84,
0x0d6d6a3e,
0x7a6a5aa8,
0xe40ecf0b,
0x9309ff9d,
0x0a00ae27,
0x7d079eb1,
0xf00f9344,
0x8708a3d2,
0x1e01f268,
0x6906c2fe,
0xf762575d,
0x806567cb,
0x196c3671,
0x6e6b06e7,
0xfed41b76,
0x89d32be0,
0x10da7a5a,
0x67dd4acc,
0xf9b9df6f,
0x8ebeeff9,
0x17b7be43,
0x60b08ed5,
0xd6d6a3e8,
0xa1d1937e,
0x38d8c2c4,
0x4fdff252,
0xd1bb67f1,
0xa6bc5767,
0x3fb506dd,
0x48b2364b,
0xd80d2bda,
0xaf0a1b4c,
0x36034af6,
0x41047a60,
0xdf60efc3,
0xa867df55,
0x316e8eef,
0x4669be79,
0xcb61b38c,
0xbc66831a,
0x256fd2a0,
0x5268e236,
0xcc0c7795,
0xbb0b4703,
0x220216b9,
0x5505262f,
0xc5ba3bbe,
0xb2bd0b28,
0x2bb45a92,
0x5cb36a04,
0xc2d7ffa7,
0xb5d0cf31,
0x2cd99e8b,
0x5bdeae1d,
0x9b64c2b0,
0xec63f226,
0x756aa39c,
0x026d930a,
0x9c0906a9,
0xeb0e363f,
0x72076785,
0x05005713,
0x95bf4a82,
0xe2b87a14,
0x7bb12bae,
0x0cb61b38,
0x92d28e9b,
0xe5d5be0d,
0x7cdcefb7,
0x0bdbdf21,
0x86d3d2d4,
0xf1d4e242,
0x68ddb3f8,
0x1fda836e,
0x81be16cd,
0xf6b9265b,
0x6fb077e1,
0x18b74777,
0x88085ae6,
0xff0f6a70,
0x66063bca,
0x11010b5c,
0x8f659eff,
0xf862ae69,
0x616bffd3,
0x166ccf45,
0xa00ae278,
0xd70dd2ee,
0x4e048354,
0x3903b3c2,
0xa7672661,
0xd06016f7,
0x4969474d,
0x3e6e77db,
0xaed16a4a,
0xd9d65adc,
0x40df0b66,
0x37d83bf0,
0xa9bcae53,
0xdebb9ec5,
0x47b2cf7f,
0x30b5ffe9,
0xbdbdf21c,
0xcabac28a,
0x53b39330,
0x24b4a3a6,
0xbad03605,
0xcdd70693,
0x54de5729,
0x23d967bf,
0xb3667a2e,
0xc4614ab8,
0x5d681b02,
0x2a6f2b94,
0xb40bbe37,
0xc30c8ea1,
0x5a05df1b,
0x2d02ef8d
};
#define GET_MAC_ADDR_CRC(addr, crc) \
{ \
uint32_t i; \
uint8_t data; \
\
/* CRC calculation */ \
crc = 0xffffffff; \
for (i=0; i < 6; i++) \
{ \
data = (uint8_t)(addr >> ((5-i)*8)); \
crc = crc^data; \
crc = crc_table[crc&0xff] ^ (crc>>8); \
} \
} \
/* Define a macro for getting the mirrored value of */
/* a byte size number. (0x11010011 --> 0x11001011) */
/* Sometimes the mirrored value of the CRC is required */
static __inline__ uint8_t GetMirror(uint8_t n)
{
uint8_t mirror[16] =
{
0x00,
0x08,
0x04,
0x0c,
0x02,
0x0a,
0x06,
0x0e,
0x01,
0x09,
0x05,
0x0d,
0x03,
0x0b,
0x07,
0x0f
};
return ((uint8_t)(((mirror[n & 0x0f] << 4) | (mirror[n >> 4]))));
}
static __inline__ uint32_t GetMirror32(uint32_t n)
{
return (((uint32_t)GetMirror((uint8_t)(n))<<24) |
((uint32_t)GetMirror((uint8_t)(n>>8))<<16) |
((uint32_t)GetMirror((uint8_t)(n>>16))<<8) |
((uint32_t)GetMirror((uint8_t)(n>>24))));
}
#define MIRROR GetMirror
#define MIRROR_32 GetMirror32
#endif /* __crc_mac_addr_ext_h */

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/* Copyright (c) 2008-2012 Freescale Semiconductor, Inc
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**************************************************************************//**
@File dpaa_ext.h
@Description DPAA Application Programming Interface.
*//***************************************************************************/
#ifndef __DPAA_EXT_H
#define __DPAA_EXT_H
#include "std_ext.h"
#include "error_ext.h"
/**************************************************************************//**
@Group DPAA_grp Data Path Acceleration Architecture API
@Description DPAA API functions, definitions and enums.
@{
*//***************************************************************************/
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(push,1)
#endif /* defined(__MWERKS__) && ... */
/**************************************************************************//**
@Description Frame descriptor
*//***************************************************************************/
typedef _Packed struct t_DpaaFD {
#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
volatile uint8_t liodn;
volatile uint8_t bpid;
volatile uint8_t elion;
volatile uint8_t addrh;
volatile uint32_t addrl;
#else
volatile uint32_t addrl;
volatile uint8_t addrh;
volatile uint8_t elion;
volatile uint8_t bpid;
volatile uint8_t liodn;
#endif
volatile uint32_t length; /**< Frame length */
volatile uint32_t status; /**< FD status */
} _PackedType t_DpaaFD;
/**************************************************************************//**
@Description enum for defining frame format
*//***************************************************************************/
typedef enum e_DpaaFDFormatType {
e_DPAA_FD_FORMAT_TYPE_SHORT_SBSF = 0x0, /**< Simple frame Single buffer; Offset and
small length (9b OFFSET, 20b LENGTH) */
e_DPAA_FD_FORMAT_TYPE_LONG_SBSF = 0x2, /**< Simple frame, single buffer; big length
(29b LENGTH ,No OFFSET) */
e_DPAA_FD_FORMAT_TYPE_SHORT_MBSF = 0x4, /**< Simple frame, Scatter Gather table; Offset
and small length (9b OFFSET, 20b LENGTH) */
e_DPAA_FD_FORMAT_TYPE_LONG_MBSF = 0x6, /**< Simple frame, Scatter Gather table;
big length (29b LENGTH ,No OFFSET) */
e_DPAA_FD_FORMAT_TYPE_COMPOUND = 0x1, /**< Compound Frame (29b CONGESTION-WEIGHT
No LENGTH or OFFSET) */
e_DPAA_FD_FORMAT_TYPE_DUMMY
} e_DpaaFDFormatType;
/**************************************************************************//**
@Collection Frame descriptor macros
*//***************************************************************************/
#define DPAA_FD_DD_MASK 0xc0000000 /**< FD DD field mask */
#define DPAA_FD_PID_MASK 0x3f000000 /**< FD PID field mask */
#define DPAA_FD_ELIODN_MASK 0x0000f000 /**< FD ELIODN field mask */
#define DPAA_FD_BPID_MASK 0x00ff0000 /**< FD BPID field mask */
#define DPAA_FD_ADDRH_MASK 0x000000ff /**< FD ADDRH field mask */
#define DPAA_FD_ADDRL_MASK 0xffffffff /**< FD ADDRL field mask */
#define DPAA_FD_FORMAT_MASK 0xe0000000 /**< FD FORMAT field mask */
#define DPAA_FD_OFFSET_MASK 0x1ff00000 /**< FD OFFSET field mask */
#define DPAA_FD_LENGTH_MASK 0x000fffff /**< FD LENGTH field mask */
#define DPAA_FD_GET_ADDRH(fd) ((t_DpaaFD *)fd)->addrh /**< Macro to get FD ADDRH field */
#define DPAA_FD_GET_ADDRL(fd) ((t_DpaaFD *)fd)->addrl /**< Macro to get FD ADDRL field */
#define DPAA_FD_GET_PHYS_ADDR(fd) ((physAddress_t)(((uint64_t)DPAA_FD_GET_ADDRH(fd) << 32) | (uint64_t)DPAA_FD_GET_ADDRL(fd))) /**< Macro to get FD ADDR field */
#define DPAA_FD_GET_FORMAT(fd) ((((t_DpaaFD *)fd)->length & DPAA_FD_FORMAT_MASK) >> (31-2)) /**< Macro to get FD FORMAT field */
#define DPAA_FD_GET_OFFSET(fd) ((((t_DpaaFD *)fd)->length & DPAA_FD_OFFSET_MASK) >> (31-11)) /**< Macro to get FD OFFSET field */
#define DPAA_FD_GET_LENGTH(fd) (((t_DpaaFD *)fd)->length & DPAA_FD_LENGTH_MASK) /**< Macro to get FD LENGTH field */
#define DPAA_FD_GET_STATUS(fd) ((t_DpaaFD *)fd)->status /**< Macro to get FD STATUS field */
#define DPAA_FD_GET_ADDR(fd) XX_PhysToVirt(DPAA_FD_GET_PHYS_ADDR(fd)) /**< Macro to get FD ADDR (virtual) */
#define DPAA_FD_SET_ADDRH(fd,val) ((t_DpaaFD *)fd)->addrh = (val) /**< Macro to set FD ADDRH field */
#define DPAA_FD_SET_ADDRL(fd,val) ((t_DpaaFD *)fd)->addrl = (val) /**< Macro to set FD ADDRL field */
#define DPAA_FD_SET_ADDR(fd,val) \
do { \
uint64_t physAddr = (uint64_t)(XX_VirtToPhys(val)); \
DPAA_FD_SET_ADDRH(fd, ((uint32_t)(physAddr >> 32))); \
DPAA_FD_SET_ADDRL(fd, (uint32_t)physAddr); \
} while (0) /**< Macro to set FD ADDR field */
#define DPAA_FD_SET_FORMAT(fd,val) (((t_DpaaFD *)fd)->length = ((((t_DpaaFD *)fd)->length & ~DPAA_FD_FORMAT_MASK) | (((val) << (31-2))& DPAA_FD_FORMAT_MASK))) /**< Macro to set FD FORMAT field */
#define DPAA_FD_SET_OFFSET(fd,val) (((t_DpaaFD *)fd)->length = ((((t_DpaaFD *)fd)->length & ~DPAA_FD_OFFSET_MASK) | (((val) << (31-11))& DPAA_FD_OFFSET_MASK) )) /**< Macro to set FD OFFSET field */
#define DPAA_FD_SET_LENGTH(fd,val) (((t_DpaaFD *)fd)->length = (((t_DpaaFD *)fd)->length & ~DPAA_FD_LENGTH_MASK) | ((val) & DPAA_FD_LENGTH_MASK)) /**< Macro to set FD LENGTH field */
#define DPAA_FD_SET_STATUS(fd,val) ((t_DpaaFD *)fd)->status = (val) /**< Macro to set FD STATUS field */
/* @} */
/**************************************************************************//**
@Description Frame Scatter/Gather Table Entry
*//***************************************************************************/
typedef _Packed struct t_DpaaSGTE {
volatile uint32_t addrh; /**< Buffer Address high */
volatile uint32_t addrl; /**< Buffer Address low */
volatile uint32_t length; /**< Buffer length */
volatile uint32_t offset; /**< SGTE offset */
} _PackedType t_DpaaSGTE;
#define DPAA_NUM_OF_SG_TABLE_ENTRY 16
/**************************************************************************//**
@Description Frame Scatter/Gather Table
*//***************************************************************************/
typedef _Packed struct t_DpaaSGT {
t_DpaaSGTE tableEntry[DPAA_NUM_OF_SG_TABLE_ENTRY];
/**< Structure that holds information about
a single S/G entry. */
} _PackedType t_DpaaSGT;
/**************************************************************************//**
@Description Compound Frame Table
*//***************************************************************************/
typedef _Packed struct t_DpaaCompTbl {
t_DpaaSGTE outputBuffInfo; /**< Structure that holds information about
the compound-frame output buffer;
NOTE: this may point to a S/G table */
t_DpaaSGTE inputBuffInfo; /**< Structure that holds information about
the compound-frame input buffer;
NOTE: this may point to a S/G table */
} _PackedType t_DpaaCompTbl;
/**************************************************************************//**
@Collection Frame Scatter/Gather Table Entry macros
*//***************************************************************************/
#define DPAA_SGTE_ADDRH_MASK 0x000000ff /**< SGTE ADDRH field mask */
#define DPAA_SGTE_ADDRL_MASK 0xffffffff /**< SGTE ADDRL field mask */
#define DPAA_SGTE_E_MASK 0x80000000 /**< SGTE Extension field mask */
#define DPAA_SGTE_F_MASK 0x40000000 /**< SGTE Final field mask */
#define DPAA_SGTE_LENGTH_MASK 0x3fffffff /**< SGTE LENGTH field mask */
#define DPAA_SGTE_BPID_MASK 0x00ff0000 /**< SGTE BPID field mask */
#define DPAA_SGTE_OFFSET_MASK 0x00001fff /**< SGTE OFFSET field mask */
#define DPAA_SGTE_GET_ADDRH(sgte) (((t_DpaaSGTE *)sgte)->addrh & DPAA_SGTE_ADDRH_MASK) /**< Macro to get SGTE ADDRH field */
#define DPAA_SGTE_GET_ADDRL(sgte) ((t_DpaaSGTE *)sgte)->addrl /**< Macro to get SGTE ADDRL field */
#define DPAA_SGTE_GET_PHYS_ADDR(sgte) ((physAddress_t)(((uint64_t)DPAA_SGTE_GET_ADDRH(sgte) << 32) | (uint64_t)DPAA_SGTE_GET_ADDRL(sgte))) /**< Macro to get FD ADDR field */
#define DPAA_SGTE_GET_EXTENSION(sgte) ((((t_DpaaSGTE *)sgte)->length & DPAA_SGTE_E_MASK) >> (31-0)) /**< Macro to get SGTE EXTENSION field */
#define DPAA_SGTE_GET_FINAL(sgte) ((((t_DpaaSGTE *)sgte)->length & DPAA_SGTE_F_MASK) >> (31-1)) /**< Macro to get SGTE FINAL field */
#define DPAA_SGTE_GET_LENGTH(sgte) (((t_DpaaSGTE *)sgte)->length & DPAA_SGTE_LENGTH_MASK) /**< Macro to get SGTE LENGTH field */
#define DPAA_SGTE_GET_BPID(sgte) ((((t_DpaaSGTE *)sgte)->offset & DPAA_SGTE_BPID_MASK) >> (31-15)) /**< Macro to get SGTE BPID field */
#define DPAA_SGTE_GET_OFFSET(sgte) (((t_DpaaSGTE *)sgte)->offset & DPAA_SGTE_OFFSET_MASK) /**< Macro to get SGTE OFFSET field */
#define DPAA_SGTE_GET_ADDR(sgte) XX_PhysToVirt(DPAA_SGTE_GET_PHYS_ADDR(sgte))
#define DPAA_SGTE_SET_ADDRH(sgte,val) (((t_DpaaSGTE *)sgte)->addrh = ((((t_DpaaSGTE *)sgte)->addrh & ~DPAA_SGTE_ADDRH_MASK) | ((val) & DPAA_SGTE_ADDRH_MASK))) /**< Macro to set SGTE ADDRH field */
#define DPAA_SGTE_SET_ADDRL(sgte,val) ((t_DpaaSGTE *)sgte)->addrl = (val) /**< Macro to set SGTE ADDRL field */
#define DPAA_SGTE_SET_ADDR(sgte,val) \
do { \
uint64_t physAddr = (uint64_t)(XX_VirtToPhys(val)); \
DPAA_SGTE_SET_ADDRH(sgte, ((uint32_t)(physAddr >> 32))); \
DPAA_SGTE_SET_ADDRL(sgte, (uint32_t)physAddr); \
} while (0) /**< Macro to set SGTE ADDR field */
#define DPAA_SGTE_SET_EXTENSION(sgte,val) (((t_DpaaSGTE *)sgte)->length = ((((t_DpaaSGTE *)sgte)->length & ~DPAA_SGTE_E_MASK) | (((val) << (31-0))& DPAA_SGTE_E_MASK))) /**< Macro to set SGTE EXTENSION field */
#define DPAA_SGTE_SET_FINAL(sgte,val) (((t_DpaaSGTE *)sgte)->length = ((((t_DpaaSGTE *)sgte)->length & ~DPAA_SGTE_F_MASK) | (((val) << (31-1))& DPAA_SGTE_F_MASK))) /**< Macro to set SGTE FINAL field */
#define DPAA_SGTE_SET_LENGTH(sgte,val) (((t_DpaaSGTE *)sgte)->length = (((t_DpaaSGTE *)sgte)->length & ~DPAA_SGTE_LENGTH_MASK) | ((val) & DPAA_SGTE_LENGTH_MASK)) /**< Macro to set SGTE LENGTH field */
#define DPAA_SGTE_SET_BPID(sgte,val) (((t_DpaaSGTE *)sgte)->offset = ((((t_DpaaSGTE *)sgte)->offset & ~DPAA_SGTE_BPID_MASK) | (((val) << (31-15))& DPAA_SGTE_BPID_MASK))) /**< Macro to set SGTE BPID field */
#define DPAA_SGTE_SET_OFFSET(sgte,val) (((t_DpaaSGTE *)sgte)->offset = ((((t_DpaaSGTE *)sgte)->offset & ~DPAA_SGTE_OFFSET_MASK) | (((val) << (31-31))& DPAA_SGTE_OFFSET_MASK) )) /**< Macro to set SGTE OFFSET field */
/* @} */
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(pop)
#endif /* defined(__MWERKS__) && ... */
#define DPAA_LIODN_DONT_OVERRIDE (-1)
/** @} */ /* end of DPAA_grp group */
#endif /* __DPAA_EXT_H */

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/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**************************************************************************//**
@File fm_mac_ext.h
@Description FM MAC ...
*//***************************************************************************/
#ifndef __FM_MAC_EXT_H
#define __FM_MAC_EXT_H
#include "std_ext.h"
#include "enet_ext.h"
/**************************************************************************//**
@Group FM_grp Frame Manager API
@Description FM API functions, definitions and enums
@{
*//***************************************************************************/
/**************************************************************************//**
@Group FM_mac_grp FM MAC
@Description FM MAC API functions, definitions and enums
@{
*//***************************************************************************/
#define FM_MAC_NO_PFC 0xff
/**************************************************************************//**
@Description FM MAC Exceptions
*//***************************************************************************/
typedef enum e_FmMacExceptions {
e_FM_MAC_EX_10G_MDIO_SCAN_EVENTMDIO = 0 /**< 10GEC MDIO scan event interrupt */
,e_FM_MAC_EX_10G_MDIO_CMD_CMPL /**< 10GEC MDIO command completion interrupt */
,e_FM_MAC_EX_10G_REM_FAULT /**< 10GEC, mEMAC Remote fault interrupt */
,e_FM_MAC_EX_10G_LOC_FAULT /**< 10GEC, mEMAC Local fault interrupt */
,e_FM_MAC_EX_10G_1TX_ECC_ER /**< 10GEC, mEMAC Transmit frame ECC error interrupt */
,e_FM_MAC_EX_10G_TX_FIFO_UNFL /**< 10GEC, mEMAC Transmit FIFO underflow interrupt */
,e_FM_MAC_EX_10G_TX_FIFO_OVFL /**< 10GEC, mEMAC Transmit FIFO overflow interrupt */
,e_FM_MAC_EX_10G_TX_ER /**< 10GEC Transmit frame error interrupt */
,e_FM_MAC_EX_10G_RX_FIFO_OVFL /**< 10GEC, mEMAC Receive FIFO overflow interrupt */
,e_FM_MAC_EX_10G_RX_ECC_ER /**< 10GEC, mEMAC Receive frame ECC error interrupt */
,e_FM_MAC_EX_10G_RX_JAB_FRM /**< 10GEC Receive jabber frame interrupt */
,e_FM_MAC_EX_10G_RX_OVRSZ_FRM /**< 10GEC Receive oversized frame interrupt */
,e_FM_MAC_EX_10G_RX_RUNT_FRM /**< 10GEC Receive runt frame interrupt */
,e_FM_MAC_EX_10G_RX_FRAG_FRM /**< 10GEC Receive fragment frame interrupt */
,e_FM_MAC_EX_10G_RX_LEN_ER /**< 10GEC Receive payload length error interrupt */
,e_FM_MAC_EX_10G_RX_CRC_ER /**< 10GEC Receive CRC error interrupt */
,e_FM_MAC_EX_10G_RX_ALIGN_ER /**< 10GEC Receive alignment error interrupt */
,e_FM_MAC_EX_1G_BAB_RX /**< dTSEC Babbling receive error */
,e_FM_MAC_EX_1G_RX_CTL /**< dTSEC Receive control (pause frame) interrupt */
,e_FM_MAC_EX_1G_GRATEFUL_TX_STP_COMPLET /**< dTSEC Graceful transmit stop complete */
,e_FM_MAC_EX_1G_BAB_TX /**< dTSEC Babbling transmit error */
,e_FM_MAC_EX_1G_TX_CTL /**< dTSEC Transmit control (pause frame) interrupt */
,e_FM_MAC_EX_1G_TX_ERR /**< dTSEC Transmit error */
,e_FM_MAC_EX_1G_LATE_COL /**< dTSEC Late collision */
,e_FM_MAC_EX_1G_COL_RET_LMT /**< dTSEC Collision retry limit */
,e_FM_MAC_EX_1G_TX_FIFO_UNDRN /**< dTSEC Transmit FIFO underrun */
,e_FM_MAC_EX_1G_MAG_PCKT /**< dTSEC Magic Packet detection */
,e_FM_MAC_EX_1G_MII_MNG_RD_COMPLET /**< dTSEC MII management read completion */
,e_FM_MAC_EX_1G_MII_MNG_WR_COMPLET /**< dTSEC MII management write completion */
,e_FM_MAC_EX_1G_GRATEFUL_RX_STP_COMPLET /**< dTSEC Graceful receive stop complete */
,e_FM_MAC_EX_1G_TX_DATA_ERR /**< dTSEC Internal data error on transmit */
,e_FM_MAC_EX_1G_RX_DATA_ERR /**< dTSEC Internal data error on receive */
,e_FM_MAC_EX_1G_1588_TS_RX_ERR /**< dTSEC Time-Stamp Receive Error */
,e_FM_MAC_EX_1G_RX_MIB_CNT_OVFL /**< dTSEC MIB counter overflow */
,e_FM_MAC_EX_TS_FIFO_ECC_ERR /**< mEMAC Time-stamp FIFO ECC error interrupt;
not supported on T4240/B4860 rev1 chips */
,e_FM_MAC_EX_MAGIC_PACKET_INDICATION = e_FM_MAC_EX_1G_MAG_PCKT
/**< mEMAC Magic Packet Indication Interrupt */
} e_FmMacExceptions;
/**************************************************************************//**
@Description TM MAC statistics level
*//***************************************************************************/
typedef enum e_FmMacStatisticsLevel {
e_FM_MAC_NONE_STATISTICS = 0, /**< No statistics */
e_FM_MAC_PARTIAL_STATISTICS, /**< Only error counters are available; Optimized for performance */
e_FM_MAC_FULL_STATISTICS /**< All counters available; Not optimized for performance */
} e_FmMacStatisticsLevel;
#if (DPAA_VERSION >= 11)
/**************************************************************************//**
@Description Priority Flow Control Parameters
*//***************************************************************************/
typedef struct t_FmMacPfcParams {
bool pfcEnable; /**< Enable/Disable PFC */
uint16_t pauseQuanta[FM_MAX_NUM_OF_PFC_PRIORITIES]; /**< Pause Quanta per priority to be sent in a pause frame. Each quanta represents a 512 bit-times*/
uint16_t pauseThresholdQuanta[FM_MAX_NUM_OF_PFC_PRIORITIES];/**< Pause threshold per priority, when timer passes this threshold time a PFC frames is sent again if the port is still congested or BM pool in depletion*/
} t_FmMacPfcParams;
#endif /* (DPAA_VERSION >= 11) */
/**************************************************************************//**
@Function t_FmMacExceptionCallback
@Description Fm Mac Exception Callback from FM MAC to the user
@Param[in] h_App - Handle to the upper layer handler
@Param[in] exceptions - The exception that occurred
@Return void.
*//***************************************************************************/
typedef void (t_FmMacExceptionCallback)(t_Handle h_App, e_FmMacExceptions exceptions);
/**************************************************************************//**
@Description TM MAC statistics rfc3635
*//***************************************************************************/
typedef struct t_FmMacStatistics {
/* RMON */
uint64_t eStatPkts64; /**< r-10G tr-DT 64 byte frame counter */
uint64_t eStatPkts65to127; /**< r-10G 65 to 127 byte frame counter */
uint64_t eStatPkts128to255; /**< r-10G 128 to 255 byte frame counter */
uint64_t eStatPkts256to511; /**< r-10G 256 to 511 byte frame counter */
uint64_t eStatPkts512to1023; /**< r-10G 512 to 1023 byte frame counter */
uint64_t eStatPkts1024to1518; /**< r-10G 1024 to 1518 byte frame counter */
uint64_t eStatPkts1519to1522; /**< r-10G 1519 to 1522 byte good frame count */
/* */
uint64_t eStatFragments; /**< Total number of packets that were less than 64 octets long with a wrong CRC.*/
uint64_t eStatJabbers; /**< Total number of packets longer than valid maximum length octets */
uint64_t eStatsDropEvents; /**< number of dropped packets due to internal errors of the MAC Client (during receive). */
uint64_t eStatCRCAlignErrors; /**< Incremented when frames of correct length but with CRC error are received.*/
uint64_t eStatUndersizePkts; /**< Incremented for frames under 64 bytes with a valid FCS and otherwise well formed;
This count does not include range length errors */
uint64_t eStatOversizePkts; /**< Incremented for frames which exceed 1518 (non VLAN) or 1522 (VLAN) and contains
a valid FCS and otherwise well formed */
/* Pause */
uint64_t teStatPause; /**< Pause MAC Control received */
uint64_t reStatPause; /**< Pause MAC Control sent */
/* MIB II */
uint64_t ifInOctets; /**< Total number of byte received. */
uint64_t ifInPkts; /**< Total number of packets received.*/
uint64_t ifInUcastPkts; /**< Total number of unicast frame received;
NOTE: this counter is not supported on dTSEC MAC */
uint64_t ifInMcastPkts; /**< Total number of multicast frame received*/
uint64_t ifInBcastPkts; /**< Total number of broadcast frame received */
uint64_t ifInDiscards; /**< Frames received, but discarded due to problems within the MAC RX. */
uint64_t ifInErrors; /**< Number of frames received with error:
- FIFO Overflow Error
- CRC Error
- Frame Too Long Error
- Alignment Error
- The dedicated Error Code (0xfe, not a code error) was received */
uint64_t ifOutOctets; /**< Total number of byte sent. */
uint64_t ifOutPkts; /**< Total number of packets sent .*/
uint64_t ifOutUcastPkts; /**< Total number of unicast frame sent;
NOTE: this counter is not supported on dTSEC MAC */
uint64_t ifOutMcastPkts; /**< Total number of multicast frame sent */
uint64_t ifOutBcastPkts; /**< Total number of multicast frame sent */
uint64_t ifOutDiscards; /**< Frames received, but discarded due to problems within the MAC TX N/A!.*/
uint64_t ifOutErrors; /**< Number of frames transmitted with error:
- FIFO Overflow Error
- FIFO Underflow Error
- Other */
} t_FmMacStatistics;
/**************************************************************************//**
@Group FM_mac_init_grp FM MAC Initialization Unit
@Description FM MAC Initialization Unit
@{
*//***************************************************************************/
/**************************************************************************//**
@Description FM MAC config input
*//***************************************************************************/
typedef struct t_FmMacParams {
uintptr_t baseAddr; /**< Base of memory mapped FM MAC registers */
t_EnetAddr addr; /**< MAC address of device; First octet is sent first */
uint8_t macId; /**< MAC ID;
numbering of dTSEC and 1G-mEMAC:
0 - FM_MAX_NUM_OF_1G_MACS;
numbering of 10G-MAC (TGEC) and 10G-mEMAC:
0 - FM_MAX_NUM_OF_10G_MACS */
e_EnetMode enetMode; /**< Ethernet operation mode (MAC-PHY interface and speed);
Note that the speed should indicate the maximum rate that
this MAC should support rather than the actual speed;
i.e. user should use the FM_MAC_AdjustLink() routine to
provide accurate speed;
In case of mEMAC RGMII mode, the MAC is configured to RGMII
automatic mode, where actual speed/duplex mode information
is provided by PHY automatically in-band; FM_MAC_AdjustLink()
function should be used to switch to manual RGMII speed/duplex mode
configuration if RGMII PHY doesn't support in-band status signaling;
In addition, in mEMAC, in case where user is using the higher MACs
(i.e. the MACs that should support 10G), user should pass here
speed=10000 even if the interface is not allowing that (e.g. SGMII). */
t_Handle h_Fm; /**< A handle to the FM object this port related to */
int mdioIrq; /**< MDIO exceptions interrupt source - not valid for all
MACs; MUST be set to 'NO_IRQ' for MACs that don't have
mdio-irq, or for polling */
t_FmMacExceptionCallback *f_Event; /**< MDIO Events Callback Routine */
t_FmMacExceptionCallback *f_Exception; /**< Exception Callback Routine */
t_Handle h_App; /**< A handle to an application layer object; This handle will
be passed by the driver upon calling the above callbacks */
} t_FmMacParams;
/**************************************************************************//**
@Function FM_MAC_Config
@Description Creates descriptor for the FM MAC module.
The routine returns a handle (descriptor) to the FM MAC object.
This descriptor must be passed as first parameter to all other
FM MAC function calls.
No actual initialization or configuration of FM MAC hardware is
done by this routine.
@Param[in] p_FmMacParam - Pointer to data structure of parameters
@Retval Handle to FM MAC object, or NULL for Failure.
*//***************************************************************************/
t_Handle FM_MAC_Config(t_FmMacParams *p_FmMacParam);
/**************************************************************************//**
@Function FM_MAC_Init
@Description Initializes the FM MAC module
@Param[in] h_FmMac - FM module descriptor
@Return E_OK on success; Error code otherwise.
*//***************************************************************************/
t_Error FM_MAC_Init(t_Handle h_FmMac);
/**************************************************************************//**
@Function FM_Free
@Description Frees all resources that were assigned to FM MAC module.
Calling this routine invalidates the descriptor.
@Param[in] h_FmMac - FM module descriptor
@Return E_OK on success; Error code otherwise.
*//***************************************************************************/
t_Error FM_MAC_Free(t_Handle h_FmMac);
/**************************************************************************//**
@Group FM_mac_advanced_init_grp FM MAC Advanced Configuration Unit
@Description Configuration functions used to change default values.
@{
*//***************************************************************************/
/**************************************************************************//**
@Function FM_MAC_ConfigResetOnInit
@Description Tell the driver whether to reset the FM MAC before initialization or
not. It changes the default configuration [DEFAULT_resetOnInit].
@Param[in] h_FmMac A handle to a FM MAC Module.
@Param[in] enable When TRUE, FM will be reset before any initialization.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_MAC_Config() and before FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_ConfigResetOnInit(t_Handle h_FmMac, bool enable);
/**************************************************************************//**
@Function FM_MAC_ConfigLoopback
@Description Enable/Disable internal loopback mode
@Param[in] h_FmMac A handle to a FM MAC Module.
@Param[in] enable TRUE to enable or FALSE to disable.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_MAC_Config() and before FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_ConfigLoopback(t_Handle h_FmMac, bool enable);
/**************************************************************************//**
@Function FM_MAC_ConfigMaxFrameLength
@Description Setup maximum Rx Frame Length (in 1G MAC, effects also Tx)
@Param[in] h_FmMac A handle to a FM MAC Module.
@Param[in] newVal MAX Frame length
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_MAC_Config() and before FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_ConfigMaxFrameLength(t_Handle h_FmMac, uint16_t newVal);
/**************************************************************************//**
@Function FM_MAC_ConfigWan
@Description ENABLE WAN mode in 10G-MAC
@Param[in] h_FmMac A handle to a FM MAC Module.
@Param[in] enable TRUE to enable or FALSE to disable.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_MAC_Config() and before FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_ConfigWan(t_Handle h_FmMac, bool enable);
/**************************************************************************//**
@Function FM_MAC_ConfigPadAndCrc
@Description Config PAD and CRC mode
@Param[in] h_FmMac A handle to a FM MAC Module.
@Param[in] enable TRUE to enable or FALSE to disable.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_MAC_Config() and before FM_MAC_Init().
Not supported on 10G-MAC (i.e. CRC & PAD are added automatically
by HW); on mEMAC, this routine supports only PAD (i.e. CRC is
added automatically by HW).
*//***************************************************************************/
t_Error FM_MAC_ConfigPadAndCrc(t_Handle h_FmMac, bool enable);
/**************************************************************************//**
@Function FM_MAC_ConfigHalfDuplex
@Description Config Half Duplex Mode
@Param[in] h_FmMac A handle to a FM MAC Module.
@Param[in] enable TRUE to enable or FALSE to disable.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_MAC_Config() and before FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_ConfigHalfDuplex(t_Handle h_FmMac, bool enable);
/**************************************************************************//**
@Function FM_MAC_ConfigTbiPhyAddr
@Description Configures the address of internal TBI PHY.
@Param[in] h_FmMac A handle to a FM MAC Module.
@Param[in] newVal TBI PHY address (1-31).
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_MAC_Config() and before FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_ConfigTbiPhyAddr(t_Handle h_FmMac, uint8_t newVal);
/**************************************************************************//**
@Function FM_MAC_ConfigLengthCheck
@Description Configure the frame length checking.
@Param[in] h_FmMac A handle to a FM MAC Module.
@Param[in] enable TRUE to enable or FALSE to disable.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_MAC_Config() and before FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_ConfigLengthCheck(t_Handle h_FmMac, bool enable);
/**************************************************************************//**
@Function FM_MAC_ConfigException
@Description Change Exception selection from default
@Param[in] h_FmMac A handle to a FM MAC Module.
@Param[in] ex Type of the desired exceptions
@Param[in] enable TRUE to enable the specified exception, FALSE to disable it.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_MAC_Config() and before FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_ConfigException(t_Handle h_FmMac, e_FmMacExceptions ex, bool enable);
#ifdef FM_TX_ECC_FRMS_ERRATA_10GMAC_A004
t_Error FM_MAC_ConfigSkipFman11Workaround (t_Handle h_FmMac);
#endif /* FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 */
/** @} */ /* end of FM_mac_advanced_init_grp group */
/** @} */ /* end of FM_mac_init_grp group */
/**************************************************************************//**
@Group FM_mac_runtime_control_grp FM MAC Runtime Control Unit
@Description FM MAC Runtime control unit API functions, definitions and enums.
@{
*//***************************************************************************/
/**************************************************************************//**
@Function FM_MAC_Enable
@Description Enable the MAC
@Param[in] h_FmMac A handle to a FM MAC Module.
@Param[in] mode Mode of operation (RX, TX, Both)
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_Enable(t_Handle h_FmMac, e_CommMode mode);
/**************************************************************************//**
@Function FM_MAC_Disable
@Description DISABLE the MAC
@Param[in] h_FmMac A handle to a FM MAC Module.
@Param[in] mode Define what part to Disable (RX, TX or BOTH)
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_Disable(t_Handle h_FmMac, e_CommMode mode);
/**************************************************************************//**
@Function FM_MAC_Resume
@Description Re-init the MAC after suspend
@Param[in] h_FmMac A handle to a FM MAC Module.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_Resume(t_Handle h_FmMac);
/**************************************************************************//**
@Function FM_MAC_Enable1588TimeStamp
@Description Enables the TSU operation.
@Param[in] h_Fm - Handle to the PTP as returned from the FM_MAC_PtpConfig.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_Enable1588TimeStamp(t_Handle h_Fm);
/**************************************************************************//**
@Function FM_MAC_Disable1588TimeStamp
@Description Disables the TSU operation.
@Param[in] h_Fm - Handle to the PTP as returned from the FM_MAC_PtpConfig.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_Disable1588TimeStamp(t_Handle h_Fm);
/**************************************************************************//**
@Function FM_MAC_SetTxAutoPauseFrames
@Description Enable/Disable transmission of Pause-Frames.
The routine changes the default configuration [DEFAULT_TX_PAUSE_TIME].
@Param[in] h_FmMac - A handle to a FM MAC Module.
@Param[in] pauseTime - Pause quanta value used with transmitted pause frames.
Each quanta represents a 512 bit-times; Note that '0'
as an input here will be used as disabling the
transmission of the pause-frames.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_SetTxAutoPauseFrames(t_Handle h_FmMac,
uint16_t pauseTime);
/**************************************************************************//**
@Function FM_MAC_SetTxPauseFrames
@Description Enable/Disable transmission of Pause-Frames.
The routine changes the default configuration:
pause-time - [DEFAULT_TX_PAUSE_TIME]
threshold-time - [0]
@Param[in] h_FmMac - A handle to a FM MAC Module.
@Param[in] priority - the PFC class of service; use 'FM_MAC_NO_PFC'
to indicate legacy pause support (i.e. no PFC).
@Param[in] pauseTime - Pause quanta value used with transmitted pause frames.
Each quanta represents a 512 bit-times;
Note that '0' as an input here will be used as disabling the
transmission of the pause-frames.
@Param[in] threshTime - Pause Threshold equanta value used by the MAC to retransmit pause frame.
if the situation causing a pause frame to be sent didn't finish when the timer
reached the threshold quanta, the MAC will retransmit the pause frame.
Each quanta represents a 512 bit-times.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_MAC_Init().
In order for PFC to work properly the user must configure
TNUM-aging in the tx-port it is recommended that pre-fetch and
rate limit in the tx port should be disabled;
PFC is supported only on new mEMAC; i.e. in MACs that don't have
PFC support (10G-MAC and dTSEC), user should use 'FM_MAC_NO_PFC'
in the 'priority' field.
*//***************************************************************************/
t_Error FM_MAC_SetTxPauseFrames(t_Handle h_FmMac,
uint8_t priority,
uint16_t pauseTime,
uint16_t threshTime);
/**************************************************************************//**
@Function FM_MAC_SetRxIgnorePauseFrames
@Description Enable/Disable ignoring of Pause-Frames.
@Param[in] h_FmMac - A handle to a FM MAC Module.
@Param[in] en - boolean indicates whether to ignore the incoming pause
frames or not.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_SetRxIgnorePauseFrames(t_Handle h_FmMac, bool en);
/**************************************************************************//**
@Function FM_MAC_SetWakeOnLan
@Description Enable/Disable Wake On Lan support
@Param[in] h_FmMac - A handle to a FM MAC Module.
@Param[in] en - boolean indicates whether to enable Wake On Lan
support or not.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_SetWakeOnLan(t_Handle h_FmMac, bool en);
/**************************************************************************//**
@Function FM_MAC_ResetCounters
@Description reset all statistics counters
@Param[in] h_FmMac - A handle to a FM MAC Module.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_ResetCounters(t_Handle h_FmMac);
/**************************************************************************//**
@Function FM_MAC_SetException
@Description Enable/Disable a specific Exception
@Param[in] h_FmMac - A handle to a FM MAC Module.
@Param[in] ex - Type of the desired exceptions
@Param[in] enable - TRUE to enable the specified exception, FALSE to disable it.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_SetException(t_Handle h_FmMac, e_FmMacExceptions ex, bool enable);
/**************************************************************************//**
@Function FM_MAC_SetStatistics
@Description Define Statistics level.
Where applicable, the routine also enables the MIB counters
overflow interrupt in order to keep counters accurate
and account for overflows.
This routine is relevant only for dTSEC.
@Param[in] h_FmMac - A handle to a FM MAC Module.
@Param[in] statisticsLevel - Full statistics level provides all standard counters but may
reduce performance. Partial statistics provides only special
event counters (errors etc.). If selected, regular counters (such as
byte/packet) will be invalid and will return -1.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_SetStatistics(t_Handle h_FmMac, e_FmMacStatisticsLevel statisticsLevel);
/**************************************************************************//**
@Function FM_MAC_GetStatistics
@Description get all statistics counters
@Param[in] h_FmMac - A handle to a FM MAC Module.
@Param[in] p_Statistics - Structure with statistics
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_Init().
*//***************************************************************************/
t_Error FM_MAC_GetStatistics(t_Handle h_FmMac, t_FmMacStatistics *p_Statistics);
/**************************************************************************//**
@Function FM_MAC_ModifyMacAddr
@Description Replace the main MAC Address
@Param[in] h_FmMac - A handle to a FM Module.
@Param[in] p_EnetAddr - Ethernet Mac address
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only after FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_ModifyMacAddr(t_Handle h_FmMac, t_EnetAddr *p_EnetAddr);
/**************************************************************************//**
@Function FM_MAC_AddHashMacAddr
@Description Add an Address to the hash table. This is for filter purpose only.
@Param[in] h_FmMac - A handle to a FM Module.
@Param[in] p_EnetAddr - Ethernet Mac address
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_MAC_Init(). It is a filter only address.
@Cautions Some address need to be filterd out in upper FM blocks.
*//***************************************************************************/
t_Error FM_MAC_AddHashMacAddr(t_Handle h_FmMac, t_EnetAddr *p_EnetAddr);
/**************************************************************************//**
@Function FM_MAC_RemoveHashMacAddr
@Description Delete an Address to the hash table. This is for filter purpose only.
@Param[in] h_FmMac - A handle to a FM Module.
@Param[in] p_EnetAddr - Ethernet Mac address
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_RemoveHashMacAddr(t_Handle h_FmMac, t_EnetAddr *p_EnetAddr);
/**************************************************************************//**
@Function FM_MAC_AddExactMatchMacAddr
@Description Add a unicast or multicast mac address for exact-match filtering
(8 on dTSEC, 2 for 10G-MAC)
@Param[in] h_FmMac - A handle to a FM Module.
@Param[in] p_EnetAddr - MAC Address to ADD
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only after FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_AddExactMatchMacAddr(t_Handle h_FmMac, t_EnetAddr *p_EnetAddr);
/**************************************************************************//**
@Function FM_MAC_RemovelExactMatchMacAddr
@Description Remove a uni cast or multi cast mac address.
@Param[in] h_FmMac - A handle to a FM Module.
@Param[in] p_EnetAddr - MAC Address to remove
@Return E_OK on success; Error code otherwise..
@Cautions Allowed only after FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_RemovelExactMatchMacAddr(t_Handle h_FmMac, t_EnetAddr *p_EnetAddr);
/**************************************************************************//**
@Function FM_MAC_SetPromiscuous
@Description Enable/Disable MAC Promiscuous mode for ALL mac addresses.
@Param[in] h_FmMac - A handle to a FM MAC Module.
@Param[in] enable - TRUE to enable or FALSE to disable.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only after FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_SetPromiscuous(t_Handle h_FmMac, bool enable);
/**************************************************************************//**
@Function FM_MAC_AdjustLink
@Description Adjusts the Ethernet link with new speed/duplex setup.
This routine is relevant for dTSEC and mEMAC.
In case of mEMAC, this routine is also used for manual
re-configuration of RGMII speed and duplex mode for
RGMII PHYs not supporting in-band status information
to MAC.
@Param[in] h_FmMac - A handle to a FM Module.
@Param[in] speed - Ethernet speed.
@Param[in] fullDuplex - TRUE for full-duplex mode;
FALSE for half-duplex mode.
@Return E_OK on success; Error code otherwise.
*//***************************************************************************/
t_Error FM_MAC_AdjustLink(t_Handle h_FmMac, e_EnetSpeed speed, bool fullDuplex);
/**************************************************************************//**
@Function FM_MAC_RestartAutoneg
@Description Restarts the auto-negotiation process.
When auto-negotiation process is invoked under traffic the
auto-negotiation process between the internal SGMII PHY and the
external PHY does not always complete successfully. Calling this
function will restart the auto-negotiation process that will end
successfully. It is recommended to call this function after issuing
auto-negotiation restart command to the Eth Phy.
This routine is relevant only for dTSEC.
@Param[in] h_FmMac - A handle to a FM Module.
@Return E_OK on success; Error code otherwise.
*//***************************************************************************/
t_Error FM_MAC_RestartAutoneg(t_Handle h_FmMac);
/**************************************************************************//**
@Function FM_MAC_GetId
@Description Return the MAC ID
@Param[in] h_FmMac - A handle to a FM Module.
@Param[out] p_MacId - MAC ID of device
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only after FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_GetId(t_Handle h_FmMac, uint32_t *p_MacId);
/**************************************************************************//**
@Function FM_MAC_GetVesrion
@Description Return Mac HW chip version
@Param[in] h_FmMac - A handle to a FM Module.
@Param[out] p_MacVresion - Mac version as defined by the chip
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only after FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_GetVesrion(t_Handle h_FmMac, uint32_t *p_MacVresion);
/**************************************************************************//**
@Function FM_MAC_MII_WritePhyReg
@Description Write data into Phy Register
@Param[in] h_FmMac - A handle to a FM Module.
@Param[in] phyAddr - Phy Address on the MII bus
@Param[in] reg - Register Number.
@Param[in] data - Data to write.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only after FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_MII_WritePhyReg(t_Handle h_FmMac, uint8_t phyAddr, uint8_t reg, uint16_t data);
/**************************************************************************//**
@Function FM_MAC_MII_ReadPhyReg
@Description Read data from Phy Register
@Param[in] h_FmMac - A handle to a FM Module.
@Param[in] phyAddr - Phy Address on the MII bus
@Param[in] reg - Register Number.
@Param[out] p_Data - Data from PHY.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only after FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_MII_ReadPhyReg(t_Handle h_FmMac, uint8_t phyAddr, uint8_t reg, uint16_t *p_Data);
#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0))
/**************************************************************************//**
@Function FM_MAC_DumpRegs
@Description Dump internal registers
@Param[in] h_FmMac - A handle to a FM Module.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only after FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_DumpRegs(t_Handle h_FmMac);
#endif /* (defined(DEBUG_ERRORS) && ... */
/** @} */ /* end of FM_mac_runtime_control_grp group */
/** @} */ /* end of FM_mac_grp group */
/** @} */ /* end of FM_grp group */
#endif /* __FM_MAC_EXT_H */

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/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**************************************************************************//**
@File fm_muram_ext.h
@Description FM MURAM Application Programming Interface.
*//***************************************************************************/
#ifndef __FM_MURAM_EXT
#define __FM_MURAM_EXT
#include "error_ext.h"
#include "std_ext.h"
/**************************************************************************//**
@Group FM_grp Frame Manager API
@Description FM API functions, definitions and enums
@{
*//***************************************************************************/
/**************************************************************************//**
@Group FM_muram_grp FM MURAM
@Description FM MURAM API functions, definitions and enums
@{
*//***************************************************************************/
/**************************************************************************//**
@Group FM_muram_init_grp FM MURAM Initialization Unit
@Description FM MURAM initialization API functions, definitions and enums
@{
*//***************************************************************************/
/**************************************************************************//**
@Function FM_MURAM_ConfigAndInit
@Description Creates partition in the MURAM.
The routine returns a handle (descriptor) to the MURAM partition.
This descriptor must be passed as first parameter to all other
FM-MURAM function calls.
No actual initialization or configuration of FM_MURAM hardware is
done by this routine.
@Param[in] baseAddress - Pointer to base of memory mapped FM-MURAM.
@Param[in] size - Size of the FM-MURAM partition.
@Return Handle to FM-MURAM object, or NULL for Failure.
*//***************************************************************************/
t_Handle FM_MURAM_ConfigAndInit(uintptr_t baseAddress, uint32_t size);
/**************************************************************************//**
@Function FM_MURAM_Free
@Description Frees all resources that were assigned to FM-MURAM module.
Calling this routine invalidates the descriptor.
@Param[in] h_FmMuram - FM-MURAM module descriptor.
@Return E_OK on success; Error code otherwise.
*//***************************************************************************/
t_Error FM_MURAM_Free(t_Handle h_FmMuram);
/** @} */ /* end of FM_muram_init_grp group */
/**************************************************************************//**
@Group FM_muram_ctrl_grp FM MURAM Control Unit
@Description FM MURAM control API functions, definitions and enums
@{
*//***************************************************************************/
/**************************************************************************//**
@Function FM_MURAM_AllocMem
@Description Allocate some memory from FM-MURAM partition.
@Param[in] h_FmMuram - FM-MURAM module descriptor.
@Param[in] size - size of the memory to be allocated.
@Param[in] align - Alignment of the memory.
@Return address of the allocated memory; NULL otherwise.
*//***************************************************************************/
void * FM_MURAM_AllocMem(t_Handle h_FmMuram, uint32_t size, uint32_t align);
/**************************************************************************//**
@Function FM_MURAM_AllocMemForce
@Description Allocate some specific memory from FM-MURAM partition (according
to base).
@Param[in] h_FmMuram - FM-MURAM module descriptor.
@Param[in] base - the desired base-address to be allocated.
@Param[in] size - size of the memory to be allocated.
@Return address of the allocated memory; NULL otherwise.
*//***************************************************************************/
void * FM_MURAM_AllocMemForce(t_Handle h_FmMuram, uint64_t base, uint32_t size);
/**************************************************************************//**
@Function FM_MURAM_FreeMem
@Description Free an allocated memory from FM-MURAM partition.
@Param[in] h_FmMuram - FM-MURAM module descriptor.
@Param[in] ptr - A pointer to an allocated memory.
@Return E_OK on success; Error code otherwise.
*//***************************************************************************/
t_Error FM_MURAM_FreeMem(t_Handle h_FmMuram, void *ptr);
/**************************************************************************//**
@Function FM_MURAM_GetFreeMemSize
@Description Returns the size (in bytes) of free MURAM memory.
@Param[in] h_FmMuram - FM-MURAM module descriptor.
@Return Free MURAM memory size in bytes.
*//***************************************************************************/
uint64_t FM_MURAM_GetFreeMemSize(t_Handle h_FmMuram);
/** @} */ /* end of FM_muram_ctrl_grp group */
/** @} */ /* end of FM_muram_grp group */
/** @} */ /* end of FM_grp group */
#endif /* __FM_MURAM_EXT */

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/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**************************************************************************//**
@File fm_rtc_ext.h
@Description External definitions and API for FM RTC IEEE1588 Timer Module.
@Cautions None.
*//***************************************************************************/
#ifndef __FM_RTC_EXT_H__
#define __FM_RTC_EXT_H__
#include "error_ext.h"
#include "std_ext.h"
#include "fsl_fman_rtc.h"
/**************************************************************************//**
@Group FM_grp Frame Manager API
@Description FM API functions, definitions and enums
@{
*//***************************************************************************/
/**************************************************************************//**
@Group fm_rtc_grp FM RTC
@Description FM RTC functions, definitions and enums.
@{
*//***************************************************************************/
/**************************************************************************//**
@Group fm_rtc_init_grp FM RTC Initialization Unit
@Description FM RTC initialization API.
@{
*//***************************************************************************/
/**************************************************************************//**
@Description FM RTC Alarm Polarity Options.
*//***************************************************************************/
typedef enum e_FmRtcAlarmPolarity
{
e_FM_RTC_ALARM_POLARITY_ACTIVE_HIGH = E_FMAN_RTC_ALARM_POLARITY_ACTIVE_HIGH, /**< Active-high output polarity */
e_FM_RTC_ALARM_POLARITY_ACTIVE_LOW = E_FMAN_RTC_ALARM_POLARITY_ACTIVE_LOW /**< Active-low output polarity */
} e_FmRtcAlarmPolarity;
/**************************************************************************//**
@Description FM RTC Trigger Polarity Options.
*//***************************************************************************/
typedef enum e_FmRtcTriggerPolarity
{
e_FM_RTC_TRIGGER_ON_RISING_EDGE = E_FMAN_RTC_TRIGGER_ON_RISING_EDGE, /**< Trigger on rising edge */
e_FM_RTC_TRIGGER_ON_FALLING_EDGE = E_FMAN_RTC_TRIGGER_ON_FALLING_EDGE /**< Trigger on falling edge */
} e_FmRtcTriggerPolarity;
/**************************************************************************//**
@Description IEEE1588 Timer Module FM RTC Optional Clock Sources.
*//***************************************************************************/
typedef enum e_FmSrcClock
{
e_FM_RTC_SOURCE_CLOCK_EXTERNAL = E_FMAN_RTC_SOURCE_CLOCK_EXTERNAL, /**< external high precision timer reference clock */
e_FM_RTC_SOURCE_CLOCK_SYSTEM = E_FMAN_RTC_SOURCE_CLOCK_SYSTEM, /**< MAC system clock */
e_FM_RTC_SOURCE_CLOCK_OSCILATOR = E_FMAN_RTC_SOURCE_CLOCK_OSCILATOR /**< RTC clock oscilator */
}e_FmSrcClk;
/**************************************************************************//**
@Description FM RTC configuration parameters structure.
This structure should be passed to FM_RTC_Config().
*//***************************************************************************/
typedef struct t_FmRtcParams
{
t_Handle h_Fm; /**< FM Handle*/
uintptr_t baseAddress; /**< Base address of FM RTC registers */
t_Handle h_App; /**< A handle to an application layer object; This handle will
be passed by the driver upon calling the above callbacks */
} t_FmRtcParams;
/**************************************************************************//**
@Function FM_RTC_Config
@Description Configures the FM RTC module according to user's parameters.
The driver assigns default values to some FM RTC parameters.
These parameters can be overwritten using the advanced
configuration routines.
@Param[in] p_FmRtcParam - FM RTC configuration parameters.
@Return Handle to the new FM RTC object; NULL pointer on failure.
@Cautions None
*//***************************************************************************/
t_Handle FM_RTC_Config(t_FmRtcParams *p_FmRtcParam);
/**************************************************************************//**
@Function FM_RTC_Init
@Description Initializes the FM RTC driver and hardware.
@Param[in] h_FmRtc - Handle to FM RTC object.
@Return E_OK on success; Error code otherwise.
@Cautions h_FmRtc must have been previously created using FM_RTC_Config().
*//***************************************************************************/
t_Error FM_RTC_Init(t_Handle h_FmRtc);
/**************************************************************************//**
@Function FM_RTC_Free
@Description Frees the FM RTC object and all allocated resources.
@Param[in] h_FmRtc - Handle to FM RTC object.
@Return E_OK on success; Error code otherwise.
@Cautions h_FmRtc must have been previously created using FM_RTC_Config().
*//***************************************************************************/
t_Error FM_RTC_Free(t_Handle h_FmRtc);
/**************************************************************************//**
@Group fm_rtc_adv_config_grp FM RTC Advanced Configuration Unit
@Description FM RTC advanced configuration functions.
@{
*//***************************************************************************/
/**************************************************************************//**
@Function FM_RTC_ConfigPeriod
@Description Configures the period of the timestamp if different than
default [DEFAULT_clockPeriod].
@Param[in] h_FmRtc - Handle to FM RTC object.
@Param[in] period - Period in nano-seconds.
@Return E_OK on success; Error code otherwise.
@Cautions h_FmRtc must have been previously created using FM_RTC_Config().
*//***************************************************************************/
t_Error FM_RTC_ConfigPeriod(t_Handle h_FmRtc, uint32_t period);
/**************************************************************************//**
@Function FM_RTC_ConfigSourceClock
@Description Configures the source clock of the RTC.
@Param[in] h_FmRtc - Handle to FM RTC object.
@Param[in] srcClk - Source clock selection.
@Param[in] freqInMhz - the source-clock frequency (in MHz).
@Return E_OK on success; Error code otherwise.
@Cautions h_FmRtc must have been previously created using FM_RTC_Config().
*//***************************************************************************/
t_Error FM_RTC_ConfigSourceClock(t_Handle h_FmRtc,
e_FmSrcClk srcClk,
uint32_t freqInMhz);
/**************************************************************************//**
@Function FM_RTC_ConfigPulseRealignment
@Description Configures the RTC to automatic FIPER pulse realignment in
response to timer adjustments [DEFAULT_pulseRealign]
In this mode, the RTC clock is identical to the source clock.
This feature can be useful when the system contains an external
RTC with inherent frequency compensation.
@Param[in] h_FmRtc - Handle to FM RTC object.
@Param[in] enable - TRUE to enable automatic realignment.
@Return E_OK on success; Error code otherwise.
@Cautions h_FmRtc must have been previously created using FM_RTC_Config().
*//***************************************************************************/
t_Error FM_RTC_ConfigPulseRealignment(t_Handle h_FmRtc, bool enable);
/**************************************************************************//**
@Function FM_RTC_ConfigFrequencyBypass
@Description Configures the RTC to bypass the frequency compensation
mechanism. [DEFAULT_bypass]
In this mode, the RTC clock is identical to the source clock.
This feature can be useful when the system contains an external
RTC with inherent frequency compensation.
@Param[in] h_FmRtc - Handle to FM RTC object.
@Param[in] enabled - TRUE to bypass frequency compensation;
FALSE otherwise.
@Return E_OK on success; Error code otherwise.
@Cautions h_FmRtc must have been previously created using FM_RTC_Config().
*//***************************************************************************/
t_Error FM_RTC_ConfigFrequencyBypass(t_Handle h_FmRtc, bool enabled);
/**************************************************************************//**
@Function FM_RTC_ConfigInvertedInputClockPhase
@Description Configures the RTC to invert the source clock phase on input.
[DEFAULT_invertInputClkPhase]
@Param[in] h_FmRtc - Handle to FM RTC object.
@Param[in] inverted - TRUE to invert the source clock phase on input.
FALSE otherwise.
@Return E_OK on success; Error code otherwise.
@Cautions h_FmRtc must have been previously created using FM_RTC_Config().
*//***************************************************************************/
t_Error FM_RTC_ConfigInvertedInputClockPhase(t_Handle h_FmRtc, bool inverted);
/**************************************************************************//**
@Function FM_RTC_ConfigInvertedOutputClockPhase
@Description Configures the RTC to invert the output clock phase.
[DEFAULT_invertOutputClkPhase]
@Param[in] h_FmRtc - Handle to FM RTC object.
@Param[in] inverted - TRUE to invert the output clock phase.
FALSE otherwise.
@Return E_OK on success; Error code otherwise.
@Cautions h_FmRtc must have been previously created using FM_RTC_Config().
*//***************************************************************************/
t_Error FM_RTC_ConfigInvertedOutputClockPhase(t_Handle h_FmRtc, bool inverted);
/**************************************************************************//**
@Function FM_RTC_ConfigOutputClockDivisor
@Description Configures the divisor for generating the output clock from
the RTC clock. [DEFAULT_outputClockDivisor]
@Param[in] h_FmRtc - Handle to FM RTC object.
@Param[in] divisor - Divisor for generation of the output clock.
@Return E_OK on success; Error code otherwise.
@Cautions h_FmRtc must have been previously created using FM_RTC_Config().
*//***************************************************************************/
t_Error FM_RTC_ConfigOutputClockDivisor(t_Handle h_FmRtc, uint16_t divisor);
/**************************************************************************//**
@Function FM_RTC_ConfigAlarmPolarity
@Description Configures the polarity (active-high/active-low) of a specific
alarm signal. [DEFAULT_alarmPolarity]
@Param[in] h_FmRtc - Handle to FM RTC object.
@Param[in] alarmId - Alarm ID.
@Param[in] alarmPolarity - Alarm polarity.
@Return E_OK on success; Error code otherwise.
@Cautions h_FmRtc must have been previously created using FM_RTC_Config().
*//***************************************************************************/
t_Error FM_RTC_ConfigAlarmPolarity(t_Handle h_FmRtc,
uint8_t alarmId,
e_FmRtcAlarmPolarity alarmPolarity);
/**************************************************************************//**
@Function FM_RTC_ConfigExternalTriggerPolarity
@Description Configures the polarity (rising/falling edge) of a specific
external trigger signal. [DEFAULT_triggerPolarity]
@Param[in] h_FmRtc - Handle to FM RTC object.
@Param[in] triggerId - Trigger ID.
@Param[in] triggerPolarity - Trigger polarity.
@Return E_OK on success; Error code otherwise.
@Cautions h_FmRtc must have been previously created using FM_RTC_Config().
*//***************************************************************************/
t_Error FM_RTC_ConfigExternalTriggerPolarity(t_Handle h_FmRtc,
uint8_t triggerId,
e_FmRtcTriggerPolarity triggerPolarity);
/** @} */ /* end of fm_rtc_adv_config_grp */
/** @} */ /* end of fm_rtc_init_grp */
/**************************************************************************//**
@Group fm_rtc_control_grp FM RTC Control Unit
@Description FM RTC runtime control API.
@{
*//***************************************************************************/
/**************************************************************************//**
@Function t_FmRtcExceptionsCallback
@Description Exceptions user callback routine, used for RTC different mechanisms.
@Param[in] h_App - User's application descriptor.
@Param[in] id - source id.
*//***************************************************************************/
typedef void (t_FmRtcExceptionsCallback) ( t_Handle h_App, uint8_t id);
/**************************************************************************//**
@Description FM RTC alarm parameters.
*//***************************************************************************/
typedef struct t_FmRtcAlarmParams {
uint8_t alarmId; /**< 0 or 1 */
uint64_t alarmTime; /**< In nanoseconds, the time when the alarm
should go off - must be a multiple of
the RTC period */
t_FmRtcExceptionsCallback *f_AlarmCallback; /**< This routine will be called when RTC
reaches alarmTime */
bool clearOnExpiration; /**< TRUE to turn off the alarm once expired. */
} t_FmRtcAlarmParams;
/**************************************************************************//**
@Description FM RTC Periodic Pulse parameters.
*//***************************************************************************/
typedef struct t_FmRtcPeriodicPulseParams {
uint8_t periodicPulseId; /**< 0 or 1 */
uint64_t periodicPulsePeriod; /**< In Nanoseconds. Must be
a multiple of the RTC period */
t_FmRtcExceptionsCallback *f_PeriodicPulseCallback; /**< This routine will be called every
periodicPulsePeriod. */
} t_FmRtcPeriodicPulseParams;
/**************************************************************************//**
@Description FM RTC Periodic Pulse parameters.
*//***************************************************************************/
typedef struct t_FmRtcExternalTriggerParams {
uint8_t externalTriggerId; /**< 0 or 1 */
bool usePulseAsInput; /**< Use the pulse interrupt instead of
an external signal */
t_FmRtcExceptionsCallback *f_ExternalTriggerCallback; /**< This routine will be called every
periodicPulsePeriod. */
} t_FmRtcExternalTriggerParams;
/**************************************************************************//**
@Function FM_RTC_Enable
@Description Enable the RTC (time count is started).
The user can select to resume the time count from previous
point, or to restart the time count.
@Param[in] h_FmRtc - Handle to FM RTC object.
@Param[in] resetClock - Restart the time count from zero.
@Return E_OK on success; Error code otherwise.
@Cautions h_FmRtc must have been previously initialized using FM_RTC_Init().
*//***************************************************************************/
t_Error FM_RTC_Enable(t_Handle h_FmRtc, bool resetClock);
/**************************************************************************//**
@Function FM_RTC_Disable
@Description Disables the RTC (time count is stopped).
@Param[in] h_FmRtc - Handle to FM RTC object.
@Return E_OK on success; Error code otherwise.
@Cautions h_FmRtc must have been previously initialized using FM_RTC_Init().
*//***************************************************************************/
t_Error FM_RTC_Disable(t_Handle h_FmRtc);
/**************************************************************************//**
@Function FM_RTC_SetClockOffset
@Description Sets the clock offset (usually relative to another clock).
The user can pass a negative offset value.
@Param[in] h_FmRtc - Handle to FM RTC object.
@Param[in] offset - New clock offset (in nanoseconds).
@Return E_OK on success; Error code otherwise.
@Cautions h_FmRtc must have been previously initialized using FM_RTC_Init().
*//***************************************************************************/
t_Error FM_RTC_SetClockOffset(t_Handle h_FmRtc, int64_t offset);
/**************************************************************************//**
@Function FM_RTC_SetAlarm
@Description Schedules an alarm event to a given RTC time.
@Param[in] h_FmRtc - Handle to FM RTC object.
@Param[in] p_FmRtcAlarmParams - Alarm parameters.
@Return E_OK on success; Error code otherwise.
@Cautions h_FmRtc must have been previously initialized using FM_RTC_Init().
Must be called only prior to FM_RTC_Enable().
*//***************************************************************************/
t_Error FM_RTC_SetAlarm(t_Handle h_FmRtc, t_FmRtcAlarmParams *p_FmRtcAlarmParams);
/**************************************************************************//**
@Function FM_RTC_SetPeriodicPulse
@Description Sets a periodic pulse.
@Param[in] h_FmRtc - Handle to FM RTC object.
@Param[in] p_FmRtcPeriodicPulseParams - Periodic pulse parameters.
@Return E_OK on success; Error code otherwise.
@Cautions h_FmRtc must have been previously initialized using FM_RTC_Init().
Must be called only prior to FM_RTC_Enable().
*//***************************************************************************/
t_Error FM_RTC_SetPeriodicPulse(t_Handle h_FmRtc, t_FmRtcPeriodicPulseParams *p_FmRtcPeriodicPulseParams);
/**************************************************************************//**
@Function FM_RTC_ClearPeriodicPulse
@Description Clears a periodic pulse.
@Param[in] h_FmRtc - Handle to FM RTC object.
@Param[in] periodicPulseId - Periodic pulse id.
@Return E_OK on success; Error code otherwise.
@Cautions h_FmRtc must have been previously initialized using FM_RTC_Init().
*//***************************************************************************/
t_Error FM_RTC_ClearPeriodicPulse(t_Handle h_FmRtc, uint8_t periodicPulseId);
/**************************************************************************//**
@Function FM_RTC_SetExternalTrigger
@Description Sets an external trigger indication and define a callback
routine to be called on such event.
@Param[in] h_FmRtc - Handle to FM RTC object.
@Param[in] p_FmRtcExternalTriggerParams - External Trigger parameters.
@Return E_OK on success; Error code otherwise.
@Cautions h_FmRtc must have been previously initialized using FM_RTC_Init().
*//***************************************************************************/
t_Error FM_RTC_SetExternalTrigger(t_Handle h_FmRtc, t_FmRtcExternalTriggerParams *p_FmRtcExternalTriggerParams);
/**************************************************************************//**
@Function FM_RTC_ClearExternalTrigger
@Description Clears external trigger indication.
@Param[in] h_FmRtc - Handle to FM RTC object.
@Param[in] id - External Trigger id.
@Return E_OK on success; Error code otherwise.
@Cautions h_FmRtc must have been previously initialized using FM_RTC_Init().
*//***************************************************************************/
t_Error FM_RTC_ClearExternalTrigger(t_Handle h_FmRtc, uint8_t id);
/**************************************************************************//**
@Function FM_RTC_GetExternalTriggerTimeStamp
@Description Reads the External Trigger TimeStamp.
@Param[in] h_FmRtc - Handle to FM RTC object.
@Param[in] triggerId - External Trigger id.
@Param[out] p_TimeStamp - External Trigger timestamp (in nanoseconds).
@Return E_OK on success; Error code otherwise.
@Cautions h_FmRtc must have been previously initialized using FM_RTC_Init().
*//***************************************************************************/
t_Error FM_RTC_GetExternalTriggerTimeStamp(t_Handle h_FmRtc,
uint8_t triggerId,
uint64_t *p_TimeStamp);
/**************************************************************************//**
@Function FM_RTC_GetCurrentTime
@Description Returns the current RTC time.
@Param[in] h_FmRtc - Handle to FM RTC object.
@Param[out] p_Ts - returned time stamp (in nanoseconds).
@Return E_OK on success; Error code otherwise.
@Cautions h_FmRtc must have been previously initialized using FM_RTC_Init().
*//***************************************************************************/
t_Error FM_RTC_GetCurrentTime(t_Handle h_FmRtc, uint64_t *p_Ts);
/**************************************************************************//**
@Function FM_RTC_SetCurrentTime
@Description Sets the current RTC time.
@Param[in] h_FmRtc - Handle to FM RTC object.
@Param[in] ts - The new time stamp (in nanoseconds).
@Return E_OK on success; Error code otherwise.
@Cautions h_FmRtc must have been previously initialized using FM_RTC_Init().
*//***************************************************************************/
t_Error FM_RTC_SetCurrentTime(t_Handle h_FmRtc, uint64_t ts);
/**************************************************************************//**
@Function FM_RTC_GetFreqCompensation
@Description Retrieves the frequency compensation value
@Param[in] h_FmRtc - Handle to FM RTC object.
@Param[out] p_Compensation - A pointer to the returned value of compensation.
@Return E_OK on success; Error code otherwise.
@Cautions h_FmRtc must have been previously initialized using FM_RTC_Init().
*//***************************************************************************/
t_Error FM_RTC_GetFreqCompensation(t_Handle h_FmRtc, uint32_t *p_Compensation);
/**************************************************************************//**
@Function FM_RTC_SetFreqCompensation
@Description Sets a new frequency compensation value.
@Param[in] h_FmRtc - Handle to FM RTC object.
@Param[in] freqCompensation - The new frequency compensation value to set.
@Return E_OK on success; Error code otherwise.
@Cautions h_FmRtc must have been previously initialized using FM_RTC_Init().
*//***************************************************************************/
t_Error FM_RTC_SetFreqCompensation(t_Handle h_FmRtc, uint32_t freqCompensation);
#ifdef CONFIG_PTP_1588_CLOCK_DPAA
/**************************************************************************//**
*@Function FM_RTC_EnableInterrupt
*
*@Description Enable interrupt of FM RTC.
*
*@Param[in] h_FmRtc - Handle to FM RTC object.
*@Param[in] events - Interrupt events.
*
*@Return E_OK on success; Error code otherwise.
*//***************************************************************************/
t_Error FM_RTC_EnableInterrupt(t_Handle h_FmRtc, uint32_t events);
/**************************************************************************//**
*@Function FM_RTC_DisableInterrupt
*
*@Description Disable interrupt of FM RTC.
*
*@Param[in] h_FmRtc - Handle to FM RTC object.
*@Param[in] events - Interrupt events.
*
*@Return E_OK on success; Error code otherwise.
*//***************************************************************************/
t_Error FM_RTC_DisableInterrupt(t_Handle h_FmRtc, uint32_t events);
#endif
#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0))
/**************************************************************************//**
@Function FM_RTC_DumpRegs
@Description Dumps all FM registers
@Param[in] h_FmRtc A handle to an FM RTC Module.
@Return E_OK on success;
@Cautions Allowed only FM_Init().
*//***************************************************************************/
t_Error FM_RTC_DumpRegs(t_Handle h_FmRtc);
#endif /* (defined(DEBUG_ERRORS) && ... */
/** @} */ /* end of fm_rtc_control_grp */
/** @} */ /* end of fm_rtc_grp */
/** @} */ /* end of FM_grp group */
#endif /* __FM_RTC_EXT_H__ */

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@ -0,0 +1,411 @@
/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**************************************************************************//**
@File fm_vsp_ext.h
@Description FM Virtual Storage-Profile ...
*//***************************************************************************/
#ifndef __FM_VSP_EXT_H
#define __FM_VSP_EXT_H
#include "std_ext.h"
#include "error_ext.h"
#include "string_ext.h"
#include "debug_ext.h"
#include "fm_ext.h"
/**************************************************************************//**
@Group FM_grp Frame Manager API
@Description FM API functions, definitions and enums
@{
*//***************************************************************************/
/**************************************************************************//**
@Group FM_VSP_grp FM Virtual-Storage-Profile
@Description FM Virtual-Storage-Profile API
@{
*//***************************************************************************/
/**************************************************************************//**
@Group FM_VSP_init_grp FM VSP Initialization Unit
@Description FM VSP initialization API.
@{
*//***************************************************************************/
/**************************************************************************//**
@Description Virtual Storage Profile
*//***************************************************************************/
typedef struct t_FmVspParams {
t_Handle h_Fm; /**< A handle to the FM object this VSP related to */
t_FmExtPools extBufPools; /**< Which external buffer pools are used
(up to FM_PORT_MAX_NUM_OF_EXT_POOLS), and their sizes.
parameter associated with Rx / OP port */
uint16_t liodnOffset; /**< VSP's LIODN offset */
struct {
e_FmPortType portType; /**< Port type */
uint8_t portId; /**< Port Id - relative to type */
} portParams;
uint8_t relativeProfileId; /**< VSP Id - relative to VSP's range
defined in relevant FM object */
} t_FmVspParams;
/**************************************************************************//**
@Function FM_VSP_Config
@Description Creates descriptor for the FM VSP module.
The routine returns a handle (descriptor) to the FM VSP object.
This descriptor must be passed as first parameter to all other
FM VSP function calls.
No actual initialization or configuration of FM hardware is
done by this routine.
@Param[in] p_FmVspParams Pointer to data structure of parameters
@Retval Handle to FM VSP object, or NULL for Failure.
*//***************************************************************************/
t_Handle FM_VSP_Config(t_FmVspParams *p_FmVspParams);
/**************************************************************************//**
@Function FM_VSP_Init
@Description Initializes the FM VSP module
@Param[in] h_FmVsp - FM VSP module descriptor
@Return E_OK on success; Error code otherwise.
*//***************************************************************************/
t_Error FM_VSP_Init(t_Handle h_FmVsp);
/**************************************************************************//**
@Function FM_VSP_Free
@Description Frees all resources that were assigned to FM VSP module.
Calling this routine invalidates the descriptor.
@Param[in] h_FmVsp - FM VSP module descriptor
@Return E_OK on success; Error code otherwise.
*//***************************************************************************/
t_Error FM_VSP_Free(t_Handle h_FmVsp);
/**************************************************************************//**
@Group FM_VSP_adv_config_grp FM VSP Advanced Configuration Unit
@Description FM VSP advanced configuration functions.
@{
*//***************************************************************************/
/**************************************************************************//**
@Function FM_VSP_ConfigBufferPrefixContent
@Description Defines the structure, size and content of the application buffer.
The prefix will
In VSPs defined for Tx ports, if 'passPrsResult', the application
should set a value to their offsets in the prefix of
the FM will save the first 'privDataSize', than,
depending on 'passPrsResult' and 'passTimeStamp', copy parse result
and timeStamp, and the packet itself (in this order), to the
application buffer, and to offset.
Calling this routine changes the buffer margins definitions
in the internal driver data base from its default
configuration: Data size: [DEFAULT_FM_SP_bufferPrefixContent_privDataSize]
Pass Parser result: [DEFAULT_FM_SP_bufferPrefixContent_passPrsResult].
Pass timestamp: [DEFAULT_FM_SP_bufferPrefixContent_passTimeStamp].
@Param[in] h_FmVsp A handle to a FM VSP module.
@Param[in,out] p_FmBufferPrefixContent A structure of parameters describing the
structure of the buffer.
Out parameter: Start margin - offset
of data from start of external buffer.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_VSP_Config() and before FM_VSP_Init().
*//***************************************************************************/
t_Error FM_VSP_ConfigBufferPrefixContent(t_Handle h_FmVsp,
t_FmBufferPrefixContent *p_FmBufferPrefixContent);
/**************************************************************************//**
@Function FM_VSP_ConfigDmaSwapData
@Description Calling this routine changes the DMA swap data parameter
in the internal driver data base from its default
configuration [DEFAULT_FM_SP_dmaSwapData]
@Param[in] h_FmVsp A handle to a FM VSP module.
@Param[in] swapData New selection
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_VSP_Config() and before FM_VSP_Init().
*//***************************************************************************/
t_Error FM_VSP_ConfigDmaSwapData(t_Handle h_FmVsp, e_FmDmaSwapOption swapData);
/**************************************************************************//**
@Function FM_VSP_ConfigDmaIcCacheAttr
@Description Calling this routine changes the internal context cache
attribute parameter in the internal driver data base
from its default configuration [DEFAULT_FM_SP_dmaIntContextCacheAttr]
@Param[in] h_FmVsp A handle to a FM VSP module.
@Param[in] intContextCacheAttr New selection
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_VSP_Config() and before FM_VSP_Init().
*//***************************************************************************/
t_Error FM_VSP_ConfigDmaIcCacheAttr(t_Handle h_FmVsp,
e_FmDmaCacheOption intContextCacheAttr);
/**************************************************************************//**
@Function FM_VSP_ConfigDmaHdrAttr
@Description Calling this routine changes the header cache
attribute parameter in the internal driver data base
from its default configuration [DEFAULT_FM_SP_dmaHeaderCacheAttr]
@Param[in] h_FmVsp A handle to a FM VSP module.
@Param[in] headerCacheAttr New selection
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_VSP_Config() and before FM_VSP_Init().
*//***************************************************************************/
t_Error FM_VSP_ConfigDmaHdrAttr(t_Handle h_FmVsp, e_FmDmaCacheOption headerCacheAttr);
/**************************************************************************//**
@Function FM_VSP_ConfigDmaScatterGatherAttr
@Description Calling this routine changes the scatter gather cache
attribute parameter in the internal driver data base
from its default configuration [DEFAULT_FM_SP_dmaScatterGatherCacheAttr]
@Param[in] h_FmVsp A handle to a FM VSP module.
@Param[in] scatterGatherCacheAttr New selection
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_VSP_Config() and before FM_VSP_Init().
*//***************************************************************************/
t_Error FM_VSP_ConfigDmaScatterGatherAttr(t_Handle h_FmVsp,
e_FmDmaCacheOption scatterGatherCacheAttr);
/**************************************************************************//**
@Function FM_VSP_ConfigDmaWriteOptimize
@Description Calling this routine changes the write optimization
parameter in the internal driver data base
from its default configuration: optimize = [DEFAULT_FM_SP_dmaWriteOptimize]
@Param[in] h_FmVsp A handle to a FM VSP module.
@Param[in] optimize TRUE to enable optimization, FALSE for normal operation
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_VSP_Config() and before FM_VSP_Init().
*//***************************************************************************/
t_Error FM_VSP_ConfigDmaWriteOptimize(t_Handle h_FmVsp, bool optimize);
/**************************************************************************//**
@Function FM_VSP_ConfigNoScatherGather
@Description Calling this routine changes the possibility to receive S/G frame
in the internal driver data base
from its default configuration: optimize = [DEFAULT_FM_SP_noScatherGather]
@Param[in] h_FmVsp A handle to a FM VSP module.
@Param[in] noScatherGather TRUE to operate without scatter/gather capability.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_VSP_Config() and before FM_VSP_Init().
*//***************************************************************************/
t_Error FM_VSP_ConfigNoScatherGather(t_Handle h_FmVsp, bool noScatherGather);
/**************************************************************************//**
@Function FM_VSP_ConfigPoolDepletion
@Description Calling this routine enables pause frame generation depending on the
depletion status of BM pools. It also defines the conditions to activate
this functionality. By default, this functionality is disabled.
@Param[in] h_FmVsp A handle to a FM VSP module.
@Param[in] p_BufPoolDepletion A structure of pool depletion parameters
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_VSP_Config() and before FM_VSP_Init().
*//***************************************************************************/
t_Error FM_VSP_ConfigPoolDepletion(t_Handle h_FmVsp, t_FmBufPoolDepletion *p_BufPoolDepletion);
/**************************************************************************//**
@Function FM_VSP_ConfigBackupPools
@Description Calling this routine allows the configuration of some of the BM pools
defined for this port as backup pools.
A pool configured to be a backup pool will be used only if all other
enabled non-backup pools are depleted.
@Param[in] h_FmVsp A handle to a FM VSP module.
@Param[in] p_BackupBmPools An array of pool id's. All pools specified here will
be defined as backup pools.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_VSP_Config() and before FM_VSP_Init().
*//***************************************************************************/
t_Error FM_VSP_ConfigBackupPools(t_Handle h_FmVsp, t_FmBackupBmPools *p_BackupBmPools);
/** @} */ /* end of FM_VSP_adv_config_grp group */
/** @} */ /* end of FM_VSP_init_grp group */
/**************************************************************************//**
@Group FM_VSP_control_grp FM VSP Control Unit
@Description FM VSP runtime control API.
@{
*//***************************************************************************/
/**************************************************************************//**
@Function FM_VSP_GetBufferDataOffset
@Description Relevant for Rx ports.
Returns the data offset from the beginning of the data buffer
@Param[in] h_FmVsp - FM PORT module descriptor
@Return data offset.
@Cautions Allowed only following FM_VSP_Init().
*//***************************************************************************/
uint32_t FM_VSP_GetBufferDataOffset(t_Handle h_FmVsp);
/**************************************************************************//**
@Function FM_VSP_GetBufferICInfo
@Description Returns the Internal Context offset from the beginning of the data buffer
@Param[in] h_FmVsp - FM PORT module descriptor
@Param[in] p_Data - A pointer to the data buffer.
@Return Internal context info pointer on success, NULL if 'allOtherInfo' was not
configured for this port.
@Cautions Allowed only following FM_VSP_Init().
*//***************************************************************************/
uint8_t * FM_VSP_GetBufferICInfo(t_Handle h_FmVsp, char *p_Data);
/**************************************************************************//**
@Function FM_VSP_GetBufferPrsResult
@Description Returns the pointer to the parse result in the data buffer.
In Rx ports this is relevant after reception, if parse
result is configured to be part of the data passed to the
application. For non Rx ports it may be used to get the pointer
of the area in the buffer where parse result should be
initialized - if so configured.
See FM_VSP_ConfigBufferPrefixContent for data buffer prefix
configuration.
@Param[in] h_FmVsp - FM PORT module descriptor
@Param[in] p_Data - A pointer to the data buffer.
@Return Parse result pointer on success, NULL if parse result was not
configured for this port.
@Cautions Allowed only following FM_VSP_Init().
*//***************************************************************************/
t_FmPrsResult * FM_VSP_GetBufferPrsResult(t_Handle h_FmVsp, char *p_Data);
/**************************************************************************//**
@Function FM_VSP_GetBufferTimeStamp
@Description Returns the time stamp in the data buffer.
Relevant for Rx ports for getting the buffer time stamp.
See FM_VSP_ConfigBufferPrefixContent for data buffer prefix
configuration.
@Param[in] h_FmVsp - FM PORT module descriptor
@Param[in] p_Data - A pointer to the data buffer.
@Return A pointer to the hash result on success, NULL otherwise.
@Cautions Allowed only following FM_VSP_Init().
*//***************************************************************************/
uint64_t * FM_VSP_GetBufferTimeStamp(t_Handle h_FmVsp, char *p_Data);
/**************************************************************************//**
@Function FM_VSP_GetBufferHashResult
@Description Given a data buffer, on the condition that hash result was defined
as a part of the buffer content (see FM_VSP_ConfigBufferPrefixContent)
this routine will return the pointer to the hash result location in the
buffer prefix.
@Param[in] h_FmVsp - FM PORT module descriptor
@Param[in] p_Data - A pointer to the data buffer.
@Return A pointer to the hash result on success, NULL otherwise.
@Cautions Allowed only following FM_VSP_Init().
*//***************************************************************************/
uint8_t * FM_VSP_GetBufferHashResult(t_Handle h_FmVsp, char *p_Data);
/** @} */ /* end of FM_VSP_control_grp group */
/** @} */ /* end of FM_VSP_grp group */
/** @} */ /* end of FM_grp group */
#endif /* __FM_VSP_EXT_H */

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/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __MII_ACC_EXT_H
#define __MII_ACC_EXT_H
/**************************************************************************//**
@Function MII_ReadPhyReg
@Description This routine is called to read a specified PHY
register value.
@Param[in] h_MiiAccess - Handle to MII configuration access registers
@Param[in] phyAddr - PHY address (0-31).
@Param[in] reg - PHY register to read
@Param[out] p_Data - Gets the register value.
@Return Always zero (success).
*//***************************************************************************/
int MII_ReadPhyReg(t_Handle h_MiiAccess,
uint8_t phyAddr,
uint8_t reg,
uint16_t *p_Data);
/**************************************************************************//**
@Function MII_WritePhyReg
@Description This routine is called to write data to a specified PHY
register.
@Param[in] h_MiiAccess - Handle to MII configuration access registers
@Param[in] phyAddr - PHY address (0-31).
@Param[in] reg - PHY register to write
@Param[in] data - Data to write in register.
@Return Always zero (success).
*//***************************************************************************/
int MII_WritePhyReg(t_Handle h_MiiAccess,
uint8_t phyAddr,
uint8_t reg,
uint16_t data);
#endif /* __MII_ACC_EXT_H */

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/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**************************************************************************//**
@File core_ext.h
@Description Generic interface to basic core operations.
The system integrator must ensure that this interface is
mapped to a specific core implementation, by including the
appropriate header file.
*//***************************************************************************/
#ifndef __CORE_EXT_H
#define __CORE_EXT_H
#ifdef CONFIG_FMAN_ARM
#include "arm_ext.h"
#include <linux/smp.h>
#else
#ifdef NCSW_PPC_CORE
#include "ppc_ext.h"
#elif defined(NCSW_VXWORKS)
#include "core_vxw_ext.h"
#else
#error "Core is not defined!"
#endif /* NCSW_CORE */
#if (!defined(CORE_IS_LITTLE_ENDIAN) && !defined(CORE_IS_BIG_ENDIAN))
#error "Must define core as little-endian or big-endian!"
#endif /* (!defined(CORE_IS_LITTLE_ENDIAN) && ... */
#ifndef CORE_CACHELINE_SIZE
#error "Must define the core cache-line size!"
#endif /* !CORE_CACHELINE_SIZE */
#endif /* CONFIG_FMAN_ARM */
/**************************************************************************//**
@Function CORE_GetId
@Description Returns the core ID in the system.
@Return Core ID.
*//***************************************************************************/
uint32_t CORE_GetId(void);
/**************************************************************************//**
@Function CORE_MemoryBarrier
@Description This routine will cause the core to stop executing any commands
until all previous memory read/write commands are completely out
of the core's pipeline.
@Return None.
*//***************************************************************************/
void CORE_MemoryBarrier(void);
#define fsl_mem_core_barrier() CORE_MemoryBarrier()
#endif /* __CORE_EXT_H */

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/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**************************************************************************//**
@File arm_ext.h
@Description Core API for ARM cores
These routines must be implemented by each specific PowerPC
core driver.
*//***************************************************************************/
#ifndef __ARM_EXT_H
#define __ARM_EXT_H
#include "part_ext.h"
#define CORE_IS_LITTLE_ENDIAN
static __inline__ void CORE_MemoryBarrier(void)
{
mb();
}
#endif /* __PPC_EXT_H */

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/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**************************************************************************//**
@File e500v2_ext.h
@Description E500 external definitions prototypes
This file is not included by the E500
source file as it is an assembly file. It is used
only for prototypes exposure, for inclusion
by user and other modules.
*//***************************************************************************/
#ifndef __E500V2_EXT_H
#define __E500V2_EXT_H
#include "std_ext.h"
/* Layer 1 Cache Manipulations
*==============================
* Should not be called directly by the user.
*/
void L1DCache_Invalidate (void);
void L1ICache_Invalidate(void);
void L1DCache_Enable(void);
void L1ICache_Enable(void);
void L1DCache_Disable(void);
void L1ICache_Disable(void);
void L1DCache_Flush(void);
void L1ICache_Flush(void);
uint32_t L1ICache_IsEnabled(void);
uint32_t L1DCache_IsEnabled(void);
/*
*
*/
uint32_t L1DCache_LineLock(uint32_t addr);
uint32_t L1ICache_LineLock(uint32_t addr);
void L1Cache_BroadCastEnable(void);
void L1Cache_BroadCastDisable(void);
#define CORE_DCacheEnable E500_DCacheEnable
#define CORE_ICacheEnable E500_ICacheEnable
#define CORE_DCacheDisable E500_DCacheDisable
#define CORE_ICacheDisable E500_ICacheDisable
#define CORE_GetId E500_GetId
#define CORE_TestAndSet E500_TestAndSet
#define CORE_MemoryBarrier E500_MemoryBarrier
#define CORE_InstructionSync E500_InstructionSync
#define CORE_SetDozeMode E500_SetDozeMode
#define CORE_SetNapMode E500_SetNapMode
#define CORE_SetSleepMode E500_SetSleepMode
#define CORE_SetJogMode E500_SetJogMode
#define CORE_SetDeepSleepMode E500_SetDeepSleepMode
#define CORE_RecoverDozeMode E500_RecoverDozeMode
#define CORE_RecoverNapMode E500_RecoverNapMode
#define CORE_RecoverSleepMode E500_RecoverSleepMode
#define CORE_RecoverJogMode E500_RecoverJogMode
void E500_SetDozeMode(void);
void E500_SetNapMode(void);
void E500_SetSleepMode(void);
void E500_SetJogMode(void);
t_Error E500_SetDeepSleepMode(uint32_t bptrAddress);
void E500_RecoverDozeMode(void);
void E500_RecoverNapMode(void);
void E500_RecoverSleepMode(void);
void E500_RecoverJogMode(void);
/**************************************************************************//**
@Group E500_id E500 Application Programming Interface
@Description E500 API functions, definitions and enums
@{
*//***************************************************************************/
/**************************************************************************//**
@Group E500_init_grp E500 Initialization Unit
@Description E500 initialization unit API functions, definitions and enums
@{
*//***************************************************************************/
/**************************************************************************//**
@Function E500_DCacheEnable
@Description Enables the data cache for memory pages that are
not cache inhibited.
@Return None.
*//***************************************************************************/
void E500_DCacheEnable(void);
/**************************************************************************//**
@Function E500_ICacheEnable
@Description Enables the instruction cache for memory pages that are
not cache inhibited.
@Return None.
*//***************************************************************************/
void E500_ICacheEnable(void);
/**************************************************************************//**
@Function E500_DCacheDisable
@Description Disables the data cache.
@Return None.
*//***************************************************************************/
void E500_DCacheDisable(void);
/**************************************************************************//**
@Function E500_ICacheDisable
@Description Disables the instruction cache.
@Return None.
*//***************************************************************************/
void E500_ICacheDisable(void);
/**************************************************************************//**
@Function E500_DCacheFlush
@Description Flushes the data cache
@Return None.
*//***************************************************************************/
void E500_DCacheFlush(void);
/**************************************************************************//**
@Function E500_ICacheFlush
@Description Flushes the instruction cache.
@Return None.
*//***************************************************************************/
void E500_ICacheFlush(void);
/**************************************************************************//**
@Function E500_DCacheSetStashId
@Description Set Stash Id for data cache
@Param[in] stashId the stash id to be set.
@Return None.
*//***************************************************************************/
void E500_DCacheSetStashId(uint8_t stashId);
/**************************************************************************//**
@Description E500mc L2 Cache Operation Mode
*//***************************************************************************/
typedef enum e_E500mcL2CacheMode
{
e_L2_CACHE_MODE_DATA_ONLY = 0x00000001, /**< Cache data only */
e_L2_CACHE_MODE_INST_ONLY = 0x00000002, /**< Cache instructions only */
e_L2_CACHE_MODE_DATA_AND_INST = 0x00000003 /**< Cache data and instructions */
} e_E500mcL2CacheMode;
#if defined(CORE_E500MC) || defined(CORE_E5500)
/**************************************************************************//**
@Function E500_L2CacheEnable
@Description Enables the cache for memory pages that are not cache inhibited.
@param[in] mode - L2 cache mode: data only, instruction only or instruction and data.
@Return None.
@Cautions This routine must be call only ONCE for both caches. I.e. it is
not possible to call this routine for i-cache and than to call
again for d-cache; The second call will override the first one.
*//***************************************************************************/
void E500_L2CacheEnable(e_E500mcL2CacheMode mode);
/**************************************************************************//**
@Function E500_L2CacheDisable
@Description Disables the cache (data instruction or both).
@Return None.
*//***************************************************************************/
void E500_L2CacheDisable(void);
/**************************************************************************//**
@Function E500_L2CacheFlush
@Description Flushes the cache.
@Return None.
*//***************************************************************************/
void E500_L2CacheFlush(void);
/**************************************************************************//**
@Function E500_L2SetStashId
@Description Set Stash Id
@Param[in] stashId the stash id to be set.
@Return None.
*//***************************************************************************/
void E500_L2SetStashId(uint8_t stashId);
#endif /* defined(CORE_E500MC) || defined(CORE_E5500) */
#ifdef CORE_E6500
/**************************************************************************//**
@Function E6500_L2CacheEnable
@Description Enables the cache for memory pages that are not cache inhibited.
@param[in] mode - L2 cache mode: support data & instruction only.
@Return None.
@Cautions This routine must be call only ONCE for both caches. I.e. it is
not possible to call this routine for i-cache and than to call
again for d-cache; The second call will override the first one.
*//***************************************************************************/
void E6500_L2CacheEnable(uintptr_t clusterBase);
/**************************************************************************//**
@Function E6500_L2CacheDisable
@Description Disables the cache (data instruction or both).
@Return None.
*//***************************************************************************/
void E6500_L2CacheDisable(uintptr_t clusterBase);
/**************************************************************************//**
@Function E6500_L2CacheFlush
@Description Flushes the cache.
@Return None.
*//***************************************************************************/
void E6500_L2CacheFlush(uintptr_t clusterBase);
/**************************************************************************//**
@Function E6500_L2SetStashId
@Description Set Stash Id
@Param[in] stashId the stash id to be set.
@Return None.
*//***************************************************************************/
void E6500_L2SetStashId(uintptr_t clusterBase, uint8_t stashId);
/**************************************************************************//**
@Function E6500_GetCcsrBase
@Description Obtain SoC CCSR base address
@Param[in] None.
@Return Physical CCSR base address.
*//***************************************************************************/
physAddress_t E6500_GetCcsrBase(void);
#endif /* CORE_E6500 */
/**************************************************************************//**
@Function E500_AddressBusStreamingEnable
@Description Enables address bus streaming on the CCB.
This setting, along with the ECM streaming configuration
parameters, enables address bus streaming on the CCB.
@Return None.
*//***************************************************************************/
void E500_AddressBusStreamingEnable(void);
/**************************************************************************//**
@Function E500_AddressBusStreamingDisable
@Description Disables address bus streaming on the CCB.
@Return None.
*//***************************************************************************/
void E500_AddressBusStreamingDisable(void);
/**************************************************************************//**
@Function E500_AddressBroadcastEnable
@Description Enables address broadcast.
The e500 broadcasts cache management instructions (dcbst, dcblc
(CT = 1), icblc (CT = 1), dcbf, dcbi, mbar, msync, tlbsync, icbi)
based on ABE. ABE must be set to allow management of external
L2 caches.
@Return None.
*//***************************************************************************/
void E500_AddressBroadcastEnable(void);
/**************************************************************************//**
@Function E500_AddressBroadcastDisable
@Description Disables address broadcast.
The e500 broadcasts cache management instructions (dcbst, dcblc
(CT = 1), icblc (CT = 1), dcbf, dcbi, mbar, msync, tlbsync, icbi)
based on ABE. ABE must be set to allow management of external
L2 caches.
@Return None.
*//***************************************************************************/
void E500_AddressBroadcastDisable(void);
/**************************************************************************//**
@Function E500_IsTaskletSupported
@Description Checks if tasklets are supported by the e500 interrupt handler.
@Retval TRUE - Tasklets are supported.
@Retval FALSE - Tasklets are not supported.
*//***************************************************************************/
bool E500_IsTaskletSupported(void);
void E500_EnableTimeBase(void);
void E500_DisableTimeBase(void);
uint64_t E500_GetTimeBaseTime(void);
void E500_GenericIntrInit(void);
t_Error E500_SetIntr(int ppcIntrSrc,
void (* Isr)(t_Handle handle),
t_Handle handle);
t_Error E500_ClearIntr(int ppcIntrSrc);
/**************************************************************************//**
@Function E500_GenericIntrHandler
@Description This is the general e500 interrupt handler.
It is called by the main assembly interrupt handler
when an exception occurs and no other function has been
assigned to this exception.
@Param intrEntry - (In) The exception interrupt vector entry.
*//***************************************************************************/
void E500_GenericIntrHandler(uint32_t intrEntry);
/**************************************************************************//**
@Function CriticalIntr
@Description This is the specific critical e500 interrupt handler.
It is called by the main assembly interrupt handler
when an critical interrupt.
@Param intrEntry - (In) The exception interrupt vector entry.
*//***************************************************************************/
void CriticalIntr(uint32_t intrEntry);
/**************************************************************************//**
@Function E500_GetId
@Description Returns the core ID in the system.
@Return Core ID.
*//***************************************************************************/
uint32_t E500_GetId(void);
/**************************************************************************//**
@Function E500_TestAndSet
@Description This routine tries to atomically test-and-set an integer
in memory to a non-zero value.
The memory will be set only if it is tested as zero, in which
case the routine returns the new non-zero value; otherwise the
routine returns zero.
@Param[in] p - pointer to a volatile int in memory, on which test-and-set
operation should be made.
@Retval Zero - Operation failed - memory was already set.
@Retval Non-zero - Operation succeeded - memory has been set.
*//***************************************************************************/
int E500_TestAndSet(volatile int *p);
/**************************************************************************//**
@Function E500_MemoryBarrier
@Description This routine will cause the core to stop executing any commands
until all previous memory read/write commands are completely out
of the core's pipeline.
@Return None.
*//***************************************************************************/
static __inline__ void E500_MemoryBarrier(void)
{
#ifndef CORE_E500V2
__asm__ ("mbar 1");
#else /* CORE_E500V2 */
/**** ERRATA WORK AROUND START ****/
/* ERRATA num: CPU1 */
/* Description: "mbar MO = 1" instruction fails to order caching-inhibited
guarded loads and stores. */
/* "msync" instruction is used instead */
__asm__ ("msync");
/**** ERRATA WORK AROUND END ****/
#endif /* CORE_E500V2 */
}
/**************************************************************************//**
@Function E500_InstructionSync
@Description This routine will cause the core to wait for previous instructions
(including any interrupts they generate) to complete before the
synchronization command executes, which purges all instructions
from the processor's pipeline and refetches the next instruction.
@Return None.
*//***************************************************************************/
static __inline__ void E500_InstructionSync(void)
{
__asm__ ("isync");
}
/** @} */ /* end of E500_init_grp group */
/** @} */ /* end of E500_grp group */
#endif /* __E500V2_EXT_H */

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/*
* Copyright 2008-2012 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**************************************************************************//**
@File ppc_ext.h
@Description Core API for PowerPC cores
These routines must be implemented by each specific PowerPC
core driver.
*//***************************************************************************/
#ifndef __PPC_EXT_H
#define __PPC_EXT_H
#include "part_ext.h"
#define CORE_IS_BIG_ENDIAN
#if defined(CORE_E300) || defined(CORE_E500V2)
#define CORE_CACHELINE_SIZE 32
#elif defined(CORE_E500MC) || defined(CORE_E5500) || defined(CORE_E6500)
#define CORE_CACHELINE_SIZE 64
#else
#error "Core not defined!"
#endif /* defined(CORE_E300) || ... */
/**************************************************************************//**
@Function CORE_TestAndSet
@Description This routine tries to atomically test-and-set an integer
in memory to a non-zero value.
The memory will be set only if it is tested as zero, in which
case the routine returns the new non-zero value; otherwise the
routine returns zero.
@Param[in] p - pointer to a volatile int in memory, on which test-and-set
operation should be made.
@Retval Zero - Operation failed - memory was already set.
@Retval Non-zero - Operation succeeded - memory has been set.
*//***************************************************************************/
int CORE_TestAndSet(volatile int *p);
/**************************************************************************//**
@Function CORE_InstructionSync
@Description This routine will cause the core to wait for previous instructions
(including any interrupts they generate) to complete before the
synchronization command executes, which purges all instructions
from the processor's pipeline and refetches the next instruction.
@Return None.
*//***************************************************************************/
void CORE_InstructionSync(void);
/**************************************************************************//**
@Function CORE_DCacheEnable
@Description Enables the data cache for memory pages that are
not cache inhibited.
@Return None.
*//***************************************************************************/
void CORE_DCacheEnable(void);
/**************************************************************************//**
@Function CORE_ICacheEnable
@Description Enables the instruction cache for memory pages that are
not cache inhibited.
@Return None.
*//***************************************************************************/
void CORE_ICacheEnable(void);
/**************************************************************************//**
@Function CORE_DCacheDisable
@Description Disables the data cache.
@Return None.
*//***************************************************************************/
void CORE_DCacheDisable(void);
/**************************************************************************//**
@Function CORE_ICacheDisable
@Description Disables the instruction cache.
@Return None.
*//***************************************************************************/
void CORE_ICacheDisable(void);
#if defined(CORE_E300)
#include "e300_ext.h"
#elif defined(CORE_E500V2) || defined(CORE_E500MC) || defined(CORE_E5500) || defined(CORE_E6500)
#include "e500v2_ext.h"
#if !defined(NCSW_LINUX)
#include "e500v2_asm_ext.h"
#endif
#else
#error "Core not defined!"
#endif
#endif /* __PPC_EXT_H */

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