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drm/amd/display: add Cursor Degamma logic for DCN2 

[Why]
We need to have the ability to to tell us set degamma on the cursor.

[How]
Pass a flag down to register programming that tells us if the
current surface format needs cursor degamma.

Signed-off-by: Bayan Zabihiyan <bayan.zabihiyan@amd.com>
Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Bayan Zabihiyan 2019-07-26 11:10:11 -04:00 committed by Alex Deucher
parent c0358809d4
commit 5e1613e21f
7 changed files with 15 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/drm/amd/display/dc/dc_hw_types.h
View File

@ -516,7 +516,8 @@ union dc_cursor_attribute_flags {
uint32_t INVERT_PIXEL_DATA:1;
uint32_t ZERO_EXPANSION:1;
uint32_t MIN_MAX_INVERT:1;
uint32_t RESERVED:25;
uint32_t ENABLE_CURSOR_DEGAMMA:1;
uint32_t RESERVED:24;
} bits;
uint32_t value;
};

3
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
View File

@ -426,8 +426,9 @@ void dpp1_cnv_setup (
void dpp1_set_cursor_attributes(
struct dpp *dpp_base,
enum dc_cursor_color_format color_format)
struct dc_cursor_attributes *cursor_attributes)
{
enum dc_cursor_color_format color_format = cursor_attributes->color_format;
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
REG_UPDATE_2(CURSOR0_CONTROL,

2
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
View File

@ -1368,7 +1368,7 @@ enum dcn10_input_csc_select {
void dpp1_set_cursor_attributes(
struct dpp *dpp_base,
enum dc_cursor_color_format color_format);
struct dc_cursor_attributes *cursor_attributes);
void dpp1_set_cursor_position(
struct dpp *dpp_base,

2
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
View File

@ -2987,7 +2987,7 @@ static void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes(
pipe_ctx->plane_res.hubp, attributes);
pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes(
pipe_ctx->plane_res.dpp, attributes->color_format);
pipe_ctx->plane_res.dpp, attributes);
}
static void dcn10_set_cursor_sdr_white_level(struct pipe_ctx *pipe_ctx)

10
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
View File

@ -342,14 +342,18 @@ void dpp2_cnv_set_alpha_keyer(
void dpp2_set_cursor_attributes(
struct dpp *dpp_base,
enum dc_cursor_color_format color_format)
struct dc_cursor_attributes *cursor_attributes)
{
enum dc_cursor_color_format color_format = cursor_attributes->color_format;
struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
int cur_rom_en = 0;
if (color_format == CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA ||
color_format == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA)
cur_rom_en = 1;
color_format == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA) {
if (cursor_attributes->attribute_flags.bits.ENABLE_CURSOR_DEGAMMA) {
cur_rom_en = 1;
}
}
REG_UPDATE_3(CURSOR0_CONTROL,
CUR0_MODE, color_format,

2
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h
View File

@ -676,7 +676,7 @@ void dscl2_calc_lb_num_partitions(
void dpp2_set_cursor_attributes(
struct dpp *dpp_base,
enum dc_cursor_color_format color_format);
struct dc_cursor_attributes *cursor_attributes);
void dpp2_dummy_program_input_lut(
struct dpp *dpp_base,

2
drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
View File

@ -201,7 +201,7 @@ struct dpp_funcs {
void (*set_cursor_attributes)(
struct dpp *dpp_base,
enum dc_cursor_color_format color_format);
struct dc_cursor_attributes *cursor_attributes);
void (*set_cursor_position)(
struct dpp *dpp_base,