ARM: dts: qcom-apq8064: fix gic_irq_domain_translate warnings
Remove the usage of IRQ_TYPE_NONE to fix loud warnings from
patch (83a86fbb5b "irqchip/gic: Loudly complain about
the use of IRQ_TYPE_NONE").
Signed-off-by: Thierry Escande <thierry.escande@linaro.org>
Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org>
Tested-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This commit is contained in:
Thierry Escande
Andy Gross
parent
c715909b61
commit
5dba0480a8
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@ -444,7 +444,7 @@
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compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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reg = <0x12450000 0x100>,
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<0x12400000 0x03>;
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interrupts = <0 193 0x0>;
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interrupts = <0 193 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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@ -456,7 +456,7 @@
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pinctrl-1 = <&i2c1_pins_sleep>;
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pinctrl-names = "default", "sleep";
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reg = <0x12460000 0x1000>;
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interrupts = <0 194 IRQ_TYPE_NONE>;
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interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
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clock-names = "core", "iface";
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#address-cells = <1>;
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@ -485,7 +485,7 @@
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pinctrl-0 = <&i2c2_pins>;
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pinctrl-1 = <&i2c2_pins_sleep>;
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pinctrl-names = "default", "sleep";
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interrupts = <0 196 IRQ_TYPE_NONE>;
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interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
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clock-names = "core", "iface";
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#address-cells = <1>;
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@ -510,7 +510,7 @@
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pinctrl-1 = <&i2c3_pins_sleep>;
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pinctrl-names = "default", "sleep";
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reg = <0x16280000 0x1000>;
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interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
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interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GSBI3_QUP_CLK>,
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<&gcc GSBI3_H_CLK>;
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clock-names = "core", "iface";
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@ -537,7 +537,7 @@
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pinctrl-1 = <&i2c4_pins_sleep>;
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pinctrl-names = "default", "sleep";
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reg = <0x16380000 0x1000>;
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interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
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interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GSBI4_QUP_CLK>,
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<&gcc GSBI4_H_CLK>;
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clock-names = "core", "iface";
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@ -560,7 +560,7 @@
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compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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reg = <0x1a240000 0x100>,
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<0x1a200000 0x03>;
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interrupts = <0 154 0x0>;
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interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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@ -569,7 +569,7 @@
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gsbi5_spi: spi@1a280000 {
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compatible = "qcom,spi-qup-v1.1.1";
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reg = <0x1a280000 0x1000>;
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interrupts = <0 155 0>;
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interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-0 = <&spi5_default>;
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pinctrl-1 = <&spi5_sleep>;
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pinctrl-names = "default", "sleep";
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@ -596,7 +596,7 @@
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compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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reg = <0x16540000 0x100>,
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<0x16500000 0x03>;
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interrupts = <0 156 0x0>;
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interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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@ -608,7 +608,7 @@
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pinctrl-1 = <&i2c6_pins_sleep>;
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pinctrl-names = "default", "sleep";
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reg = <0x16580000 0x1000>;
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interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>;
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interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GSBI6_QUP_CLK>,
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<&gcc GSBI6_H_CLK>;
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clock-names = "core", "iface";
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@ -632,7 +632,7 @@
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compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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reg = <0x16640000 0x1000>,
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<0x16600000 0x1000>;
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interrupts = <0 158 0x0>;
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interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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@ -644,7 +644,7 @@
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pinctrl-1 = <&i2c7_pins_sleep>;
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pinctrl-names = "default", "sleep";
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reg = <0x16680000 0x1000>;
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interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
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interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GSBI7_QUP_CLK>,
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<&gcc GSBI7_H_CLK>;
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clock-names = "core", "iface";
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@ -1060,7 +1060,7 @@
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compatible = "qcom,apq8064-ahci", "generic-ahci";
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status = "disabled";
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reg = <0x29000000 0x180>;
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interrupts = <GIC_SPI 209 IRQ_TYPE_NONE>;
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interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc SFAB_SATA_S_H_CLK>,
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<&gcc SATA_H_CLK>,
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@ -1086,7 +1086,7 @@
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sdcc1bam:dma@12402000{
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compatible = "qcom,bam-v1.3.0";
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reg = <0x12402000 0x8000>;
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interrupts = <0 98 0>;
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interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc SDC1_H_CLK>;
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clock-names = "bam_clk";
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#dma-cells = <1>;
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@ -1096,7 +1096,7 @@
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sdcc3bam:dma@12182000{
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compatible = "qcom,bam-v1.3.0";
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reg = <0x12182000 0x8000>;
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interrupts = <0 96 0>;
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interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc SDC3_H_CLK>;
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clock-names = "bam_clk";
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#dma-cells = <1>;
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@ -1106,7 +1106,7 @@
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sdcc4bam:dma@121c2000{
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compatible = "qcom,bam-v1.3.0";
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reg = <0x121c2000 0x8000>;
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interrupts = <0 95 0>;
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interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc SDC4_H_CLK>;
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clock-names = "bam_clk";
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#dma-cells = <1>;
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@ -1185,7 +1185,7 @@
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compatible = "qcom,adreno-3xx";
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reg = <0x04300000 0x20000>;
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reg-names = "kgsl_3d0_reg_memory";
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interrupts = <GIC_SPI 80 0>;
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interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "kgsl_3d0_irq";
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clock-names =
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"core_clk",
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@ -1285,7 +1285,7 @@
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label = "MDSS DSI CTRL->0";
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 82 0>;
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interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x04700000 0x200>;
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reg-names = "dsi_ctrl";
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@ -1354,8 +1354,8 @@
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<&mmcc MDP_AXI_CLK>;
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reg = <0x07500000 0x100000>;
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interrupts =
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<GIC_SPI 63 0>,
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<GIC_SPI 64 0>;
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<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
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qcom,ncb = <2>;
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};
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@ -1370,8 +1370,8 @@
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<&mmcc MDP_AXI_CLK>;
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reg = <0x07600000 0x100000>;
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interrupts =
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<GIC_SPI 61 0>,
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<GIC_SPI 62 0>;
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<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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qcom,ncb = <2>;
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};
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@ -1386,8 +1386,8 @@
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<&mmcc GFX3D_AXI_CLK>;
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reg = <0x07c00000 0x100000>;
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interrupts =
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<GIC_SPI 69 0>,
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<GIC_SPI 70 0>;
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<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
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qcom,ncb = <3>;
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};
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@ -1402,8 +1402,8 @@
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<&mmcc GFX3D_AXI_CLK>;
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reg = <0x07d00000 0x100000>;
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interrupts =
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<GIC_SPI 210 0>,
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<GIC_SPI 211 0>;
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<GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
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qcom,ncb = <3>;
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};
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@ -1422,7 +1422,7 @@
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#size-cells = <2>;
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ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */
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0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
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interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
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interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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