arm64: tegra: Add ACONNECT, ADMA and AGIC nodes
Add device tree nodes for the ACONNECT, ADMA and AGIC devices on Tegra186 and Tegra194. Signed-off-by: Sameer Pujar <spujar@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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@ -70,6 +70,75 @@
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snps,rxpbl = <8>;
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};
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aconnect {
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compatible = "nvidia,tegra186-aconnect",
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"nvidia,tegra210-aconnect";
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clocks = <&bpmp TEGRA186_CLK_APE>,
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<&bpmp TEGRA186_CLK_APB2APE>;
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clock-names = "ape", "apb2ape";
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power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x02900000 0x0 0x02900000 0x200000>;
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status = "disabled";
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dma-controller@2930000 {
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compatible = "nvidia,tegra186-adma";
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reg = <0x02930000 0x20000>;
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interrupt-parent = <&agic>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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clocks = <&bpmp TEGRA186_CLK_AHUB>;
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clock-names = "d_audio";
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status = "disabled";
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};
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agic: interrupt-controller@2a40000 {
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compatible = "nvidia,tegra186-agic",
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"nvidia,tegra210-agic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x02a41000 0x1000>,
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<0x02a42000 0x2000>;
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interrupts = <GIC_SPI 145
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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clocks = <&bpmp TEGRA186_CLK_APE>;
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clock-names = "clk";
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status = "disabled";
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};
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};
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memory-controller@2c00000 {
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compatible = "nvidia,tegra186-mc";
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reg = <0x0 0x02c00000 0x0 0xb0000>;
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@ -59,6 +59,77 @@
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snps,rxpbl = <8>;
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};
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aconnect {
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compatible = "nvidia,tegra194-aconnect",
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"nvidia,tegra210-aconnect";
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clocks = <&bpmp TEGRA194_CLK_APE>,
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<&bpmp TEGRA194_CLK_APB2APE>;
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clock-names = "ape", "apb2ape";
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power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x02900000 0x02900000 0x200000>;
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status = "disabled";
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dma-controller@2930000 {
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compatible = "nvidia,tegra194-adma",
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"nvidia,tegra186-adma";
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reg = <0x02930000 0x20000>;
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interrupt-parent = <&agic>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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clocks = <&bpmp TEGRA194_CLK_AHUB>;
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clock-names = "d_audio";
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status = "disabled";
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};
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agic: interrupt-controller@2a40000 {
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compatible = "nvidia,tegra194-agic",
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"nvidia,tegra210-agic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x02a41000 0x1000>,
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<0x02a42000 0x2000>;
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interrupts = <GIC_SPI 145
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(GIC_CPU_MASK_SIMPLE(4) |
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IRQ_TYPE_LEVEL_HIGH)>;
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clocks = <&bpmp TEGRA194_CLK_APE>;
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clock-names = "clk";
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status = "disabled";
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};
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};
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uarta: serial@3100000 {
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compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
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reg = <0x03100000 0x40>;
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