ARM: at91: pm: Add ULP1 mode support
In the ULP1 mode, in order to achieve the lowest power consumption with the system in retention mode and be able to resume on the wake up events, all the clocks are shut off, inclusive the embedded 12MHz RC oscillator, and the number of wake up sources is limited as well. When the wake up event is asserted, the embedded 12MHz RC oscillator restarts automatically. The ULP1 (Ultra Low-power mode 1) is introduced by SAMA5D2. The previous size of pm_suspend.o was 2148 bytes. With the addition of ULP1 mode the new size of pm_suspend.o raised at 2456 bytes. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com> [claudiu.beznea@microchip.com: aligned with 4.18-rc1] Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
This commit is contained in:
Wenyou Yang
Alexandre Belloni
parent
514e2a294a
commit
5b56c182ed
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@ -42,6 +42,7 @@ extern void at91_pinctrl_gpio_resume(void);
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static const match_table_t pm_modes __initconst = {
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{ AT91_PM_STANDBY, "standby" },
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{ AT91_PM_ULP0, "ulp0" },
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{ AT91_PM_ULP1, "ulp1" },
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{ AT91_PM_BACKUP, "backup" },
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{ -1, NULL },
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};
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@ -23,7 +23,8 @@
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#define AT91_PM_STANDBY 0x00
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#define AT91_PM_ULP0 0x01
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#define AT91_PM_BACKUP 0x02
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#define AT91_PM_ULP1 0x02
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#define AT91_PM_BACKUP 0x03
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#ifndef __ASSEMBLY__
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struct at91_pm_data {
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@ -41,6 +41,15 @@ tmp2 .req r5
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beq 1b
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.endm
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/*
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* Wait for main oscillator selection is done
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*/
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.macro wait_moscsels
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1: ldr tmp1, [pmc, #AT91_PMC_SR]
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tst tmp1, #AT91_PMC_MOSCSELS
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beq 1b
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.endm
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/*
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* Wait until PLLA has locked.
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*/
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@ -112,19 +121,20 @@ ENTRY(at91_pm_suspend_in_sram)
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bl at91_sramc_self_refresh
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ldr r0, .pm_mode
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cmp r0, #AT91_PM_ULP0
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beq ulp0_mode
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cmp r0, #AT91_PM_STANDBY
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beq standby
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cmp r0, #AT91_PM_BACKUP
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beq backup_mode
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bl at91_ulp_mode
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b exit_suspend
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standby:
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/* Wait for interrupt */
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ldr pmc, .pmc_base
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at91_cpu_idle
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b exit_suspend
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ulp0_mode:
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bl at91_ulp0_mode
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b exit_suspend
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backup_mode:
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bl at91_backup_mode
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b exit_suspend
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@ -151,7 +161,102 @@ ENTRY(at91_backup_mode)
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str tmp1, [r0, #0]
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ENDPROC(at91_backup_mode)
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ENTRY(at91_ulp0_mode)
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.macro at91_pm_ulp0_mode
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ldr pmc, .pmc_base
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/* Turn off the crystal oscillator */
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ldr tmp1, [pmc, #AT91_CKGR_MOR]
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bic tmp1, tmp1, #AT91_PMC_MOSCEN
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orr tmp1, tmp1, #AT91_PMC_KEY
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str tmp1, [pmc, #AT91_CKGR_MOR]
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/* Wait for interrupt */
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at91_cpu_idle
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/* Turn on the crystal oscillator */
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ldr tmp1, [pmc, #AT91_CKGR_MOR]
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orr tmp1, tmp1, #AT91_PMC_MOSCEN
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orr tmp1, tmp1, #AT91_PMC_KEY
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str tmp1, [pmc, #AT91_CKGR_MOR]
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wait_moscrdy
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.endm
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/**
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* Note: This procedure only applies on the platform which uses
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* the external crystal oscillator as a main clock source.
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*/
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.macro at91_pm_ulp1_mode
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ldr pmc, .pmc_base
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/* Switch the main clock source to 12-MHz RC oscillator */
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ldr tmp1, [pmc, #AT91_CKGR_MOR]
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bic tmp1, tmp1, #AT91_PMC_MOSCSEL
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bic tmp1, tmp1, #AT91_PMC_KEY_MASK
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orr tmp1, tmp1, #AT91_PMC_KEY
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str tmp1, [pmc, #AT91_CKGR_MOR]
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wait_moscsels
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/* Disable the crystal oscillator */
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ldr tmp1, [pmc, #AT91_CKGR_MOR]
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bic tmp1, tmp1, #AT91_PMC_MOSCEN
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bic tmp1, tmp1, #AT91_PMC_KEY_MASK
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orr tmp1, tmp1, #AT91_PMC_KEY
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str tmp1, [pmc, #AT91_CKGR_MOR]
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/* Switch the master clock source to main clock */
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ldr tmp1, [pmc, #AT91_PMC_MCKR]
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bic tmp1, tmp1, #AT91_PMC_CSS
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orr tmp1, tmp1, #AT91_PMC_CSS_MAIN
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str tmp1, [pmc, #AT91_PMC_MCKR]
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wait_mckrdy
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/* Enter the ULP1 mode by set WAITMODE bit in CKGR_MOR */
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ldr tmp1, [pmc, #AT91_CKGR_MOR]
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orr tmp1, tmp1, #AT91_PMC_WAITMODE
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bic tmp1, tmp1, #AT91_PMC_KEY_MASK
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orr tmp1, tmp1, #AT91_PMC_KEY
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str tmp1, [pmc, #AT91_CKGR_MOR]
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wait_mckrdy
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/* Enable the crystal oscillator */
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ldr tmp1, [pmc, #AT91_CKGR_MOR]
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orr tmp1, tmp1, #AT91_PMC_MOSCEN
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bic tmp1, tmp1, #AT91_PMC_KEY_MASK
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orr tmp1, tmp1, #AT91_PMC_KEY
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str tmp1, [pmc, #AT91_CKGR_MOR]
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wait_moscrdy
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/* Switch the master clock source to slow clock */
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ldr tmp1, [pmc, #AT91_PMC_MCKR]
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bic tmp1, tmp1, #AT91_PMC_CSS
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str tmp1, [pmc, #AT91_PMC_MCKR]
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wait_mckrdy
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/* Switch main clock source to crystal oscillator */
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ldr tmp1, [pmc, #AT91_CKGR_MOR]
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orr tmp1, tmp1, #AT91_PMC_MOSCSEL
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bic tmp1, tmp1, #AT91_PMC_KEY_MASK
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orr tmp1, tmp1, #AT91_PMC_KEY
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str tmp1, [pmc, #AT91_CKGR_MOR]
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wait_moscsels
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/* Switch the master clock source to main clock */
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ldr tmp1, [pmc, #AT91_PMC_MCKR]
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bic tmp1, tmp1, #AT91_PMC_CSS
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orr tmp1, tmp1, #AT91_PMC_CSS_MAIN
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str tmp1, [pmc, #AT91_PMC_MCKR]
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wait_mckrdy
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.endm
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ENTRY(at91_ulp_mode)
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ldr pmc, .pmc_base
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/* Save Master clock setting */
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@ -174,22 +279,19 @@ ENTRY(at91_ulp0_mode)
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orr tmp1, tmp1, #(1 << 29) /* bit 29 always set */
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str tmp1, [pmc, #AT91_CKGR_PLLAR]
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/* Turn off the main oscillator */
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ldr tmp1, [pmc, #AT91_CKGR_MOR]
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bic tmp1, tmp1, #AT91_PMC_MOSCEN
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orr tmp1, tmp1, #AT91_PMC_KEY
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str tmp1, [pmc, #AT91_CKGR_MOR]
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ldr r0, .pm_mode
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cmp r0, #AT91_PM_ULP1
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beq ulp1_mode
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/* Wait for interrupt */
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at91_cpu_idle
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at91_pm_ulp0_mode
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b ulp_exit
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/* Turn on the main oscillator */
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ldr tmp1, [pmc, #AT91_CKGR_MOR]
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orr tmp1, tmp1, #AT91_PMC_MOSCEN
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orr tmp1, tmp1, #AT91_PMC_KEY
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str tmp1, [pmc, #AT91_CKGR_MOR]
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ulp1_mode:
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at91_pm_ulp1_mode
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b ulp_exit
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wait_moscrdy
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ulp_exit:
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ldr pmc, .pmc_base
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/* Restore PLLA setting */
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ldr tmp1, .saved_pllar
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@ -212,7 +314,7 @@ ENTRY(at91_ulp0_mode)
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wait_mckrdy
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mov pc, lr
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ENDPROC(at91_ulp0_mode)
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ENDPROC(at91_ulp_mode)
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/*
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* void at91_sramc_self_refresh(unsigned int is_active)
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@ -47,8 +47,10 @@
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#define AT91_CKGR_MOR 0x20 /* Main Oscillator Register [not on SAM9RL] */
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#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
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#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass */
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#define AT91_PMC_WAITMODE (1 << 2) /* Wait Mode Command */
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#define AT91_PMC_MOSCRCEN (1 << 3) /* Main On-Chip RC Oscillator Enable [some SAM9] */
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#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
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#define AT91_PMC_KEY_MASK (0xff << 16)
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#define AT91_PMC_KEY (0x37 << 16) /* MOR Writing Key */
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#define AT91_PMC_MOSCSEL (1 << 24) /* Main Oscillator Selection [some SAM9] */
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#define AT91_PMC_CFDEN (1 << 25) /* Clock Failure Detector Enable [some SAM9] */
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