mirror of
https://github.com/brain-hackers/linux-brain.git
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ARM: DT updates for v4.6
These are all the updates to device tree files for 32-bit platforms,
plus a couple of related 64-bit updates:
New SoC support:
- Allwinner A83T
- Axis Artpec-6 SoC
- Mediatek MT7623 SoC
- TI Keystone K2G SoC
- ST Microelectronics stm32f469
New board or machine support:
- ARM Juno R2
- Buffalo Linkstation LS-QVL and LS-GL
- Cubietruck plus
- D-Link DIR-885L
- DT support for ARM RealView PB1176 and PB11MPCore
- Google Nexus 7
- Homlet v2
- Itead Ibox
- Lamobo R1
- LG Optimus Black
- Logicpd dm3730
- Raspberry Pi Model A
Other changes include
- Lots of updates for Qualcomm APQ8064, MSM8974 and others
- Improved support for Nokia N900 and other OMAP machines
- Common clk support for lpc32xx
- HDLCD display on ARM
- Improved stm32f429 support
- Improved Renesas device support, r8a779x and others
- Lots of Rockchip updates
- Samsung cleanups
- ADC support for Atmel SAMA5D2
- BCM2835 (Raspberry Pi) improvements
- Broadcom Northstar Plus enhancements
- OMAP GPMC rework
- Several improvements for Atmel SAMA5D2 / Xplained
- Global change to remove inofficial "arm,amba-bus" compatible string
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM DT updates from Arnd Bergmann:
"These are all the updates to device tree files for 32-bit platforms,
plus a couple of related 64-bit updates:
New SoC support:
- Allwinner A83T
- Axis Artpec-6 SoC
- Mediatek MT7623 SoC
- TI Keystone K2G SoC
- ST Microelectronics stm32f469
New board or machine support:
- ARM Juno R2
- Buffalo Linkstation LS-QVL and LS-GL
- Cubietruck plus
- D-Link DIR-885L
- DT support for ARM RealView PB1176 and PB11MPCore
- Google Nexus 7
- Homlet v2
- Itead Ibox
- Lamobo R1
- LG Optimus Black
- Logicpd dm3730
- Raspberry Pi Model A
Other changes include
- Lots of updates for Qualcomm APQ8064, MSM8974 and others
- Improved support for Nokia N900 and other OMAP machines
- Common clk support for lpc32xx
- HDLCD display on ARM
- Improved stm32f429 support
- Improved Renesas device support, r8a779x and others
- Lots of Rockchip updates
- Samsung cleanups
- ADC support for Atmel SAMA5D2
- BCM2835 (Raspberry Pi) improvements
- Broadcom Northstar Plus enhancements
- OMAP GPMC rework
- Several improvements for Atmel SAMA5D2 / Xplained
- Global change to remove inofficial "arm,amba-bus" compatible
string"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (350 commits)
ARM, ARM64: dts: drop "arm,amba-bus" in favor of "simple-bus"
ARM: dts: artpec: dual-license on artpec6.dtsi
ARM: dts: ux500: add synaptics RMI4 for Ux500 TVK DT
arm64: dts: juno/vexpress: fix node name unit-address presence warnings
arm64: dts: foundation-v8: add SBSA Generic Watchdog device node
ARM: dts: at91: sama5d2 Xplained: add leds node
ARM: dts: at91: sama5d2 Xplained: add user push button
ARM: dts: at91: sama5d2 Xplained: set pin muxing for usb gadget and usb host
ARM: dts: stm32f429: Enable Ethernet on Eval board
ARM: dts: omap3-sniper: TWL4030 keypad support
Revert "ARM: dts: DRA7: Add dt nodes for PWMSS"
ARM: dts: dm814x: dra62x: Disable wait pin monitoring for NAND
ARM: dts: dm814x: dra62x: Fix NAND device nodes
ARM: dts: stm32f429: Add Ethernet support
ARM: dts: stm32f429: Add system config bank node
ARM: dts: at91: sama5d2: add nand0 and nfc0 nodes
ARM: dts: at91: sama5d2: add dma properties to UART nodes
ARM: dts: at91: sama5d2 Xplained: Correct the macb irq pinctrl node
ARM: dts: exynos: Don't overheat the Odroid XU3-Lite on high load
ARM: dts: exynos: Add cooling levels for Exynos5422/5800 CPUs
...
This commit is contained in:
Linus Torvalds
commit
5a6b7e53d0
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@ -182,6 +182,7 @@ described under the RS1 memory mapping.
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Required properties (in root node):
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compatible = "arm,juno"; /* For Juno r0 board */
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compatible = "arm,juno-r1"; /* For Juno r1 board */
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compatible = "arm,juno-r2"; /* For Juno r2 board */
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Required nodes:
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The description for the board must include:
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|
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29
Documentation/devicetree/bindings/arm/axis.txt
Normal file
29
Documentation/devicetree/bindings/arm/axis.txt
Normal file
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@ -0,0 +1,29 @@
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Axis Communications AB
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ARTPEC series SoC Device Tree Bindings
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ARTPEC-6 ARM SoC
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================
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Required root node properties:
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- compatible = "axis,artpec6";
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ARTPEC-6 System Controller
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--------------------------
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The ARTPEC-6 has a system controller with mixed functions controlling DMA, PCIe
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and resets.
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Required properties:
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- compatible: "axis,artpec6-syscon", "syscon"
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- reg: Address and length of the register bank.
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Example:
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syscon {
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compatible = "axis,artpec6-syscon", "syscon";
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reg = <0xf8000000 0x48>;
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};
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ARTPEC-6 Development board:
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---------------------------
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Required root node properties:
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- compatible = "axis,artpec6-dev-board", "axis,artpec6";
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@ -178,6 +178,7 @@ nodes to be present and contain the properties described below.
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"marvell,sheeva-v5"
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"nvidia,tegra132-denver"
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"qcom,krait"
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"qcom,kryo"
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"qcom,scorpion"
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- enable-method
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Value type: <stringlist>
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|
|
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@ -22,6 +22,8 @@ SoCs:
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compatible = "ti,k2l", "ti,keystone"
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- Keystone 2 Edison
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compatible = "ti,k2e", "ti,keystone"
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- K2G
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compatible = "ti,k2g", "ti,keystone"
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Boards:
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- Keystone 2 Hawking/Kepler EVM
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@ -32,3 +34,6 @@ Boards:
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- Keystone 2 Edison EVM
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compatible = "ti,k2e-evm", "ti,k2e", "ti,keystone"
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- K2G EVM
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compatible = "ti,k2g-evm", "ti,k2g", "ti-keystone"
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|
|
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@ -19,9 +19,12 @@ SoC. Currently known SoC compatibles are:
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And in addition, the compatible shall be extended with the specific
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board. Currently known boards are:
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"buffalo,linkstation-lsqvl"
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"buffalo,linkstation-lsvl"
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"buffalo,linkstation-lswsxl"
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"buffalo,linkstation-lswxl"
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"buffalo,linkstation-lswvl"
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"buffalo,lschlv2"
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"buffalo,lswvl"
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"buffalo,lswxl"
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"buffalo,lsxhl"
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"buffalo,lsxl"
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"cloudengines,pogo02"
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|
|
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@ -11,6 +11,7 @@ compatible: Must contain one of
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"mediatek,mt6589"
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"mediatek,mt6592"
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"mediatek,mt6795"
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"mediatek,mt7623"
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"mediatek,mt8127"
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"mediatek,mt8135"
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"mediatek,mt8173"
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@ -33,6 +34,9 @@ Supported boards:
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- Evaluation board for MT6795(Helio X10):
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Required root node properties:
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- compatible = "mediatek,mt6795-evb", "mediatek,mt6795";
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- Evaluation board for MT7623:
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Required root node properties:
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- compatible = "mediatek,mt7623-evb", "mediatek,mt7623";
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- MTK mt8127 tablet moose EVB:
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Required root node properties:
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- compatible = "mediatek,mt8127-moose", "mediatek,mt8127";
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|
|
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@ -155,7 +155,7 @@ Boards:
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compatible = "compulab,am437x-sbc-t43", "compulab,am437x-cm-t43", "ti,am4372", "ti,am43"
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- AM43x EPOS EVM
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compatible = "ti,am43x-epos-evm", "ti,am4372", "ti,am43"
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compatible = "ti,am43x-epos-evm", "ti,am43", "ti,am438x"
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- AM437x GP EVM
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compatible = "ti,am437x-gp-evm", "ti,am4372", "ti,am43"
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|
|
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51
Documentation/devicetree/bindings/arm/qcom.txt
Normal file
51
Documentation/devicetree/bindings/arm/qcom.txt
Normal file
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@ -0,0 +1,51 @@
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QCOM device tree bindings
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-------------------------
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Some qcom based bootloaders identify the dtb blob based on a set of
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device properties like SoC and platform and revisions of those components.
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To support this scheme, we encode this information into the board compatible
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string.
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Each board must specify a top-level board compatible string with the following
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format:
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compatible = "qcom,<SoC>[-<soc_version>][-<foundry_id>]-<board>[/<subtype>][-<board_version>]"
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The 'SoC' and 'board' elements are required. All other elements are optional.
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The 'SoC' element must be one of the following strings:
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apq8016
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apq8074
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apq8084
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apq8096
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msm8916
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msm8974
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msm8996
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The 'board' element must be one of the following strings:
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cdp
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liquid
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dragonboard
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mtp
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sbc
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The 'soc_version' and 'board_version' elements take the form of v<Major>.<Minor>
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where the minor number may be omitted when it's zero, i.e. v1.0 is the same
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as v1. If all versions of the 'board_version' elements match, then a
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wildcard '*' should be used, e.g. 'v*'.
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The 'foundry_id' and 'subtype' elements are one or more digits from 0 to 9.
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|
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Examples:
|
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"qcom,msm8916-v1-cdp-pm8916-v2.1"
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A CDP board with an msm8916 SoC, version 1 paired with a pm8916 PMIC of version
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2.1.
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"qcom,apq8074-v2.0-2-dragonboard/1-v0.1"
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A dragonboard board v0.1 of subtype 1 with an apq8074 SoC version 2, made in
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foundry 2.
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79
Documentation/devicetree/bindings/display/arm,hdlcd.txt
Normal file
79
Documentation/devicetree/bindings/display/arm,hdlcd.txt
Normal file
|
|
@ -0,0 +1,79 @@
|
|||
ARM HDLCD
|
||||
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This is a display controller found on several development platforms produced
|
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by ARM Ltd and in more modern of its' Fast Models. The HDLCD is an RGB
|
||||
streamer that reads the data from a framebuffer and sends it to a single
|
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digital encoder (DVI or HDMI).
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|
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Required properties:
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- compatible: "arm,hdlcd"
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- reg: Physical base address and length of the controller's registers.
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- interrupts: One interrupt used by the display controller to notify the
|
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interrupt controller when any of the interrupt sources programmed in
|
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the interrupt mask register have activated.
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- clocks: A list of phandle + clock-specifier pairs, one for each
|
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entry in 'clock-names'.
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- clock-names: A list of clock names. For HDLCD it should contain:
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- "pxlclk" for the clock feeding the output PLL of the controller.
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Required sub-nodes:
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- port: The HDLCD connection to an encoder chip. The connection is modeled
|
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using the OF graph bindings specified in
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Documentation/devicetree/bindings/graph.txt.
|
||||
|
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Optional properties:
|
||||
- memory-region: phandle to a node describing memory (see
|
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Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt) to be
|
||||
used for the framebuffer; if not present, the framebuffer may be located
|
||||
anywhere in memory.
|
||||
|
||||
|
||||
Example:
|
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/ {
|
||||
...
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||||
|
||||
hdlcd@2b000000 {
|
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compatible = "arm,hdlcd";
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reg = <0 0x2b000000 0 0x1000>;
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interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&oscclk5>;
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clock-names = "pxlclk";
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port {
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hdlcd_output: endpoint@0 {
|
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remote-endpoint = <&hdmi_enc_input>;
|
||||
};
|
||||
};
|
||||
};
|
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|
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/* HDMI encoder on I2C bus */
|
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i2c@7ffa0000 {
|
||||
....
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hdmi-transmitter@70 {
|
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compatible = ".....";
|
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reg = <0x70>;
|
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port@0 {
|
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hdmi_enc_input: endpoint {
|
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remote-endpoint = <&hdlcd_output>;
|
||||
};
|
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|
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hdmi_enc_output: endpoint {
|
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remote-endpoint = <&hdmi_1_port>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
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hdmi1: connector@1 {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
port {
|
||||
hdmi_1_port: endpoint {
|
||||
remote-endpoint = <&hdmi_enc_output>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
};
|
||||
|
|
@ -13,6 +13,8 @@ Required Properties:
|
|||
- "rockchip,rk2928-dw-mshc": for Rockchip RK2928 and following,
|
||||
before RK3288
|
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- "rockchip,rk3288-dw-mshc": for Rockchip RK3288
|
||||
- "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3036
|
||||
- "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3368
|
||||
|
||||
Optional Properties:
|
||||
* clocks: from common clock binding: if ciu_drive and ciu_sample are
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@ information.
|
|||
Required properties:
|
||||
- compatible: should contain the platform identifier such as:
|
||||
"fsl,ls1021a-pcie", "snps,dw-pcie"
|
||||
"fsl,ls2080a-pcie", "snps,dw-pcie"
|
||||
"fsl,ls2080a-pcie", "fsl,ls2085a-pcie", "snps,dw-pcie"
|
||||
- reg: base addresses and lengths of the PCIe controller
|
||||
- interrupts: A list of interrupt outputs of the controller. Must contain an
|
||||
entry for each entry in the interrupt-names property.
|
||||
|
|
|
|||
|
|
@ -91,6 +91,9 @@ mpp60 60 gpio, dev(ale1), uart1(rxd), sata0(prsnt), pcie(rstout),
|
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mpp61 61 gpo, dev(we1), uart1(txd), audio(lrclk)
|
||||
mpp62 62 gpio, dev(a2), uart1(cts), tdm(drx), pcie(clkreq0),
|
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audio(mclk), uart0(cts)
|
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mpp63 63 gpo, spi0(sck), tclk
|
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mpp63 63 gpio, spi0(sck), tclk
|
||||
mpp64 64 gpio, spi0(miso), spi0(cs1)
|
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mpp65 65 gpio, spi0(mosi), spi0(cs2)
|
||||
|
||||
Note: According to the datasheet mpp63 is a gpo but there is at least
|
||||
one example of a gpio usage on the board D-Link DNS-327L
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@ Required properties:
|
|||
* "mediatek,mt6582-uart" for MT6582 compatible UARTS
|
||||
* "mediatek,mt6589-uart" for MT6589 compatible UARTS
|
||||
* "mediatek,mt6795-uart" for MT6795 compatible UARTS
|
||||
* "mediatek,mt7623-uart" for MT7623 compatible UARTS
|
||||
* "mediatek,mt8127-uart" for MT8127 compatible UARTS
|
||||
* "mediatek,mt8135-uart" for MT8135 compatible UARTS
|
||||
* "mediatek,mt8173-uart" for MT8173 compatible UARTS
|
||||
|
|
|
|||
|
|
@ -6,6 +6,7 @@ Required properties:
|
|||
* "mediatek,mt2701-timer" for MT2701 compatible timers
|
||||
* "mediatek,mt6580-timer" for MT6580 compatible timers
|
||||
* "mediatek,mt6589-timer" for MT6589 compatible timers
|
||||
* "mediatek,mt7623-timer" for MT7623 compatible timers
|
||||
* "mediatek,mt8127-timer" for MT8127 compatible timers
|
||||
* "mediatek,mt8135-timer" for MT8135 compatible timers
|
||||
* "mediatek,mt8173-timer" for MT8173 compatible timers
|
||||
|
|
|
|||
|
|
@ -2,6 +2,8 @@ ifeq ($(CONFIG_OF),y)
|
|||
|
||||
dtb-$(CONFIG_ARCH_ALPINE) += \
|
||||
alpine-db.dtb
|
||||
dtb-$(CONFIG_MACH_ARTPEC6) += \
|
||||
artpec6-devboard.dtb
|
||||
dtb-$(CONFIG_MACH_ASM9260) += \
|
||||
alphascale-asm9260-devkit.dtb
|
||||
# Keep at91 dtb files sorted alphabetically for each SoC
|
||||
|
|
@ -60,6 +62,7 @@ dtb-$(CONFIG_ARCH_AXXIA) += \
|
|||
axm5516-amarillo.dtb
|
||||
dtb-$(CONFIG_ARCH_BCM2835) += \
|
||||
bcm2835-rpi-b.dtb \
|
||||
bcm2835-rpi-a.dtb \
|
||||
bcm2835-rpi-b-rev2.dtb \
|
||||
bcm2835-rpi-b-plus.dtb \
|
||||
bcm2835-rpi-a-plus.dtb \
|
||||
|
|
@ -79,6 +82,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
|
|||
bcm4709-buffalo-wxr-1900dhp.dtb \
|
||||
bcm4709-netgear-r7000.dtb \
|
||||
bcm4709-netgear-r8000.dtb \
|
||||
bcm47094-dlink-dir-885l.dtb \
|
||||
bcm94708.dtb \
|
||||
bcm94709.dtb \
|
||||
bcm953012k.dtb
|
||||
|
|
@ -156,7 +160,8 @@ dtb-$(CONFIG_ARCH_INTEGRATOR) += \
|
|||
dtb-$(CONFIG_ARCH_KEYSTONE) += \
|
||||
k2hk-evm.dtb \
|
||||
k2l-evm.dtb \
|
||||
k2e-evm.dtb
|
||||
k2e-evm.dtb \
|
||||
keystone-k2g-evm.dtb
|
||||
dtb-$(CONFIG_MACH_KIRKWOOD) += \
|
||||
kirkwood-b3.dtb \
|
||||
kirkwood-blackarmor-nas220.dtb \
|
||||
|
|
@ -189,9 +194,12 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += \
|
|||
kirkwood-is2.dtb \
|
||||
kirkwood-km_kirkwood.dtb \
|
||||
kirkwood-laplug.dtb \
|
||||
kirkwood-linkstation-lsqvl.dtb \
|
||||
kirkwood-linkstation-lsvl.dtb \
|
||||
kirkwood-linkstation-lswsxl.dtb \
|
||||
kirkwood-linkstation-lswvl.dtb \
|
||||
kirkwood-linkstation-lswxl.dtb \
|
||||
kirkwood-lschlv2.dtb \
|
||||
kirkwood-lswvl.dtb \
|
||||
kirkwood-lswxl.dtb \
|
||||
kirkwood-lsxhl.dtb \
|
||||
kirkwood-mplcec4.dtb \
|
||||
kirkwood-mv88f6281gtw-ge.dtb \
|
||||
|
|
@ -460,6 +468,7 @@ dtb-$(CONFIG_ARCH_OMAP3) += \
|
|||
omap3-sbc-t3517.dtb \
|
||||
omap3-sbc-t3530.dtb \
|
||||
omap3-sbc-t3730.dtb \
|
||||
omap3-sniper.dtb \
|
||||
omap3-thunder.dtb \
|
||||
omap3-zoom3.dtb
|
||||
dtb-$(CONFIG_SOC_TI81XX) += \
|
||||
|
|
@ -514,6 +523,7 @@ dtb-$(CONFIG_SOC_DRA7XX) += \
|
|||
dtb-$(CONFIG_ARCH_ORION5X) += \
|
||||
orion5x-lacie-d2-network.dtb \
|
||||
orion5x-lacie-ethernet-disk-mini-v2.dtb \
|
||||
orion5x-linkstation-lsgl.dtb \
|
||||
orion5x-linkstation-lswtgl.dtb \
|
||||
orion5x-lswsgl.dtb \
|
||||
orion5x-maxtor-shared-storage-2.dtb \
|
||||
|
|
@ -524,6 +534,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
|
|||
qcom-apq8064-cm-qs600.dtb \
|
||||
qcom-apq8064-ifc6410.dtb \
|
||||
qcom-apq8064-sony-xperia-yuga.dtb \
|
||||
qcom-apq8064-asus-nexus7-flo.dtb \
|
||||
qcom-apq8074-dragonboard.dtb \
|
||||
qcom-apq8084-ifc6540.dtb \
|
||||
qcom-apq8084-mtp.dtb \
|
||||
|
|
@ -611,6 +622,7 @@ dtb-$(CONFIG_ARCH_STI) += \
|
|||
stih418-b2199.dtb
|
||||
dtb-$(CONFIG_ARCH_STM32)+= \
|
||||
stm32f429-disco.dtb \
|
||||
stm32f469-disco.dtb \
|
||||
stm32429i-eval.dtb
|
||||
dtb-$(CONFIG_MACH_SUN4I) += \
|
||||
sun4i-a10-a1000.dtb \
|
||||
|
|
@ -666,8 +678,10 @@ dtb-$(CONFIG_MACH_SUN7I) += \
|
|||
sun7i-a20-cubieboard2.dtb \
|
||||
sun7i-a20-cubietruck.dtb \
|
||||
sun7i-a20-hummingbird.dtb \
|
||||
sun7i-a20-itead-ibox.dtb \
|
||||
sun7i-a20-i12-tvbox.dtb \
|
||||
sun7i-a20-icnova-swac.dtb \
|
||||
sun7i-a20-lamobo-r1.dtb \
|
||||
sun7i-a20-m3.dtb \
|
||||
sun7i-a20-mk808c.dtb \
|
||||
sun7i-a20-olimex-som-evb.dtb \
|
||||
|
|
@ -691,6 +705,8 @@ dtb-$(CONFIG_MACH_SUN8I) += \
|
|||
sun8i-a33-ippo-q8h-v1.2.dtb \
|
||||
sun8i-a33-q8-tablet.dtb \
|
||||
sun8i-a33-sinlinx-sina33.dtb \
|
||||
sun8i-a83t-allwinner-h8homlet-v2.dtb \
|
||||
sun8i-a83t-cubietruck-plus.dtb \
|
||||
sun8i-h3-orangepi-plus.dtb
|
||||
dtb-$(CONFIG_MACH_SUN9I) += \
|
||||
sun9i-a80-optimus.dtb \
|
||||
|
|
@ -809,6 +825,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
|
|||
mt6580-evbp1.dtb \
|
||||
mt6589-aquaris5.dtb \
|
||||
mt6592-evb.dtb \
|
||||
mt7623-evb.dtb \
|
||||
mt8127-moose.dtb \
|
||||
mt8135-evbp1.dtb
|
||||
dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
|
||||
|
|
|
|||
|
|
@ -155,6 +155,16 @@
|
|||
ranges = <0x02000000 0x0 0xfe000000 0x0 0xfe000000 0x0 0x1000000>;
|
||||
|
||||
bus-range = <0x00 0x00>;
|
||||
msi-parent = <&msix>;
|
||||
};
|
||||
|
||||
msix: msix@fbe00000 {
|
||||
compatible = "al,alpine-msix";
|
||||
reg = <0x0 0xfbe00000 0x0 0x100000>;
|
||||
interrupt-controller;
|
||||
msi-controller;
|
||||
al,msi-base-spi = <96>;
|
||||
al,msi-num-spis = <64>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -236,7 +236,11 @@
|
|||
status = "okay";
|
||||
|
||||
nand@0,0 {
|
||||
reg = <0 0 0>; /* CS0, offset 0 */
|
||||
compatible = "ti,omap2-nand";
|
||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||
interrupt-parent = <&gpmc>;
|
||||
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||
nand-bus-width = <8>;
|
||||
ti,nand-ecc-opt = "bch8";
|
||||
ti,nand-xfer-type = "polled";
|
||||
|
|
@ -257,12 +261,9 @@
|
|||
gpmc,access-ns = <64>;
|
||||
gpmc,rd-cycle-ns = <82>;
|
||||
gpmc,wr-cycle-ns = <82>;
|
||||
gpmc,wait-on-read = "true";
|
||||
gpmc,wait-on-write = "true";
|
||||
gpmc,bus-turnaround-ns = <0>;
|
||||
gpmc,cycle2cycle-delay-ns = <0>;
|
||||
gpmc,clk-activation-ns = <0>;
|
||||
gpmc,wait-monitoring-ns = <0>;
|
||||
gpmc,wr-access-ns = <40>;
|
||||
gpmc,wr-data-mux-bus-ns = <0>;
|
||||
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@
|
|||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#include "am33xx.dtsi"
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/ {
|
||||
model = "Grinn AM335x ChiliSOM";
|
||||
|
|
@ -208,7 +209,11 @@
|
|||
pinctrl-0 = <&nandflash_pins>;
|
||||
ranges = <0 0 0x08000000 0x01000000>; /* CS0 0 @addr 0x08000000, size 0x01000000 */
|
||||
nand@0,0 {
|
||||
compatible = "ti,omap2-nand";
|
||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||
interrupt-parent = <&gpmc>;
|
||||
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||
ti,nand-ecc-opt = "bch8";
|
||||
ti,elm-id = <&elm>;
|
||||
nand-bus-width = <8>;
|
||||
|
|
@ -227,12 +232,9 @@
|
|||
gpmc,access-ns = <64>;
|
||||
gpmc,rd-cycle-ns = <82>;
|
||||
gpmc,wr-cycle-ns = <82>;
|
||||
gpmc,wait-on-read = "true";
|
||||
gpmc,wait-on-write = "true";
|
||||
gpmc,bus-turnaround-ns = <0>;
|
||||
gpmc,cycle2cycle-delay-ns = <0>;
|
||||
gpmc,clk-activation-ns = <0>;
|
||||
gpmc,wait-monitoring-ns = <0>;
|
||||
gpmc,wr-access-ns = <40>;
|
||||
gpmc,wr-data-mux-bus-ns = <0>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include "am33xx.dtsi"
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/ {
|
||||
model = "CompuLab CM-T335";
|
||||
|
|
@ -40,12 +41,51 @@
|
|||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
/* Regulator for WiFi */
|
||||
vwlan_fixed: fixedregulator@2 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vwlan_fixed";
|
||||
gpio = <&gpio0 20 GPIO_ACTIVE_HIGH>; /* gpio0_20 */
|
||||
enable-active-high;
|
||||
regulator-boot-off;
|
||||
};
|
||||
|
||||
backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&ecap0 0 50000 0>;
|
||||
brightness-levels = <0 51 53 56 62 75 101 152 255>;
|
||||
default-brightness-level = <8>;
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "cm-t335";
|
||||
|
||||
simple-audio-card,widgets =
|
||||
"Microphone", "Mic Jack",
|
||||
"Line", "Line In",
|
||||
"Headphone", "Headphone Jack";
|
||||
|
||||
simple-audio-card,routing =
|
||||
"Headphone Jack", "LHPOUT",
|
||||
"Headphone Jack", "RHPOUT",
|
||||
"LLINEIN", "Line In",
|
||||
"RLINEIN", "Line In",
|
||||
"MICIN", "Mic Jack";
|
||||
|
||||
simple-audio-card,format = "i2s";
|
||||
simple-audio-card,bitclock-master = <&sound_master>;
|
||||
simple-audio-card,frame-master = <&sound_master>;
|
||||
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&mcasp1>;
|
||||
};
|
||||
|
||||
sound_master: simple-audio-card,codec {
|
||||
sound-dai = <&tlv320aic23>;
|
||||
system-clock-frequency = <12000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&am33xx_pinmux {
|
||||
|
|
@ -134,6 +174,24 @@
|
|||
>;
|
||||
};
|
||||
|
||||
dcan0_pins: pinmux_dcan0_pins {
|
||||
pinctrl-single,pins = <
|
||||
/* uart1_ctsn.dcan0_tx */
|
||||
AM33XX_IOPAD(0x978, PIN_OUTPUT | MUX_MODE2)
|
||||
/* uart1_rtsn.dcan0_rx */
|
||||
AM33XX_IOPAD(0x97C, PIN_INPUT | MUX_MODE2)
|
||||
>;
|
||||
};
|
||||
|
||||
dcan1_pins: pinmux_dcan1_pins {
|
||||
pinctrl-single,pins = <
|
||||
/* uart1_rxd.dcan1_tx */
|
||||
AM33XX_IOPAD(0x980, PIN_OUTPUT | MUX_MODE2)
|
||||
/* uart1_txd.dcan1_rx */
|
||||
AM33XX_IOPAD(0x984, PIN_INPUT | MUX_MODE2)
|
||||
>;
|
||||
};
|
||||
|
||||
ecap0_pins: pinmux_ecap0_pins {
|
||||
pinctrl-single,pins = <
|
||||
/* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
|
||||
|
|
@ -223,6 +281,21 @@
|
|||
>;
|
||||
};
|
||||
|
||||
spi0_pins: pinmux_spi0_pins {
|
||||
pinctrl-single,pins = <
|
||||
/* spi0_sclk.spi0_sclk */
|
||||
AM33XX_IOPAD(0x950, PIN_INPUT | MUX_MODE0)
|
||||
/* spi0_d0.spi0_d0 */
|
||||
AM33XX_IOPAD(0x954, PIN_OUTPUT_PULLUP | MUX_MODE0)
|
||||
/* spi0_d1.spi0_d1 */
|
||||
AM33XX_IOPAD(0x958, PIN_INPUT | MUX_MODE0)
|
||||
/* spi0_cs0.spi0_cs0 */
|
||||
AM33XX_IOPAD(0x95C, PIN_OUTPUT | MUX_MODE0)
|
||||
/* spi0_cs1.spi0_cs1 */
|
||||
AM33XX_IOPAD(0x960, PIN_OUTPUT | MUX_MODE0)
|
||||
>;
|
||||
};
|
||||
|
||||
/* wl1271 bluetooth */
|
||||
bluetooth_pins: pinmux_bluetooth_pins {
|
||||
pinctrl-single,pins = <
|
||||
|
|
@ -230,6 +303,30 @@
|
|||
AM33XX_IOPAD(0x9b0, PIN_OUTPUT_PULLUP | MUX_MODE7)
|
||||
>;
|
||||
};
|
||||
|
||||
/* TLV320AIC23B codec */
|
||||
mcasp1_pins: pinmux_mcasp1_pins {
|
||||
pinctrl-single,pins = <
|
||||
/* MII1_CRS.mcasp1_aclkx */
|
||||
AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4)
|
||||
/* MII1_RX_ER.mcasp1_fsx */
|
||||
AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4)
|
||||
/* MII1_COL.mcasp1_axr2 */
|
||||
AM33XX_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE4)
|
||||
/* RMII1_REF_CLK.mcasp1_axr3 */
|
||||
AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4)
|
||||
>;
|
||||
};
|
||||
|
||||
/* wl1271 WiFi */
|
||||
wifi_pins: pinmux_wifi_pins {
|
||||
pinctrl-single,pins = <
|
||||
/* EMU1.gpio3_8 - WiFi IRQ */
|
||||
AM33XX_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE7)
|
||||
/* XDMA_EVENT_INTR1.gpio0_20 - WiFi enable */
|
||||
AM33XX_IOPAD(0x9b4, PIN_OUTPUT | MUX_MODE7)
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
|
|
@ -264,6 +361,13 @@ status = "okay";
|
|||
compatible = "emmicro,em3027";
|
||||
reg = <0x56>;
|
||||
};
|
||||
/* Audio codec */
|
||||
tlv320aic23: codec@1a {
|
||||
compatible = "ti,tlv320aic23";
|
||||
reg = <0x1a>;
|
||||
#sound-dai-cells= <0>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&usb {
|
||||
|
|
@ -302,7 +406,11 @@ status = "okay";
|
|||
pinctrl-0 = <&nandflash_pins>;
|
||||
ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
|
||||
nand@0,0 {
|
||||
reg = <0 0 0>; /* CS0, offset 0 */
|
||||
compatible = "ti,omap2-nand";
|
||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||
interrupt-parent = <&gpmc>;
|
||||
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||
ti,nand-ecc-opt = "bch8";
|
||||
ti,elm-id = <&elm>;
|
||||
nand-bus-width = <8>;
|
||||
|
|
@ -321,12 +429,9 @@ status = "okay";
|
|||
gpmc,access-ns = <64>;
|
||||
gpmc,rd-cycle-ns = <82>;
|
||||
gpmc,wr-cycle-ns = <82>;
|
||||
gpmc,wait-on-read = "true";
|
||||
gpmc,wait-on-write = "true";
|
||||
gpmc,bus-turnaround-ns = <0>;
|
||||
gpmc,cycle2cycle-delay-ns = <0>;
|
||||
gpmc,clk-activation-ns = <0>;
|
||||
gpmc,wait-monitoring-ns = <0>;
|
||||
gpmc,wr-access-ns = <40>;
|
||||
gpmc,wr-data-mux-bus-ns = <0>;
|
||||
/* MTD partition table */
|
||||
|
|
@ -394,3 +499,70 @@ status = "okay";
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc1_pins>;
|
||||
};
|
||||
|
||||
&dcan0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&dcan0_pins>;
|
||||
};
|
||||
|
||||
&dcan1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&dcan1_pins>;
|
||||
};
|
||||
|
||||
/* Touschscreen and analog digital converter */
|
||||
&tscadc {
|
||||
status = "okay";
|
||||
tsc {
|
||||
ti,wires = <4>;
|
||||
ti,x-plate-resistance = <200>;
|
||||
ti,coordinate-readouts = <5>;
|
||||
ti,wire-config = <0x01 0x10 0x23 0x32>;
|
||||
ti,charge-delay = <0x400>;
|
||||
};
|
||||
|
||||
adc {
|
||||
ti,adc-channels = <4 5 6 7>;
|
||||
};
|
||||
};
|
||||
|
||||
/* CPU audio */
|
||||
&mcasp1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcasp1_pins>;
|
||||
|
||||
op-mode = <0>; /* MCASP_IIS_MODE */
|
||||
tdm-slots = <2>;
|
||||
/* 16 serializers */
|
||||
num-serializer = <16>;
|
||||
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
|
||||
0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0
|
||||
>;
|
||||
tx-num-evt = <1>;
|
||||
rx-num-evt = <1>;
|
||||
|
||||
#sound-dai-cells= <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi0_pins>;
|
||||
ti,pindir-d0-out-d1-in = <1>;
|
||||
/* WLS1271 WiFi */
|
||||
wlcore: wlcore@1 {
|
||||
compatible = "ti,wl1271";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wifi_pins>;
|
||||
reg = <1>;
|
||||
spi-max-frequency = <48000000>;
|
||||
clock-xtal;
|
||||
ref-clock-frequency = <38400000>;
|
||||
interrupt-parent = <&gpio3>;
|
||||
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
vwlan-supply = <&vwlan_fixed>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -519,7 +519,11 @@
|
|||
pinctrl-0 = <&nandflash_pins_s0>;
|
||||
ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */
|
||||
nand@0,0 {
|
||||
compatible = "ti,omap2-nand";
|
||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||
interrupt-parent = <&gpmc>;
|
||||
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||
ti,nand-ecc-opt = "bch8";
|
||||
ti,elm-id = <&elm>;
|
||||
nand-bus-width = <8>;
|
||||
|
|
@ -538,12 +542,9 @@
|
|||
gpmc,access-ns = <64>;
|
||||
gpmc,rd-cycle-ns = <82>;
|
||||
gpmc,wr-cycle-ns = <82>;
|
||||
gpmc,wait-on-read = "true";
|
||||
gpmc,wait-on-write = "true";
|
||||
gpmc,bus-turnaround-ns = <0>;
|
||||
gpmc,cycle2cycle-delay-ns = <0>;
|
||||
gpmc,clk-activation-ns = <0>;
|
||||
gpmc,wait-monitoring-ns = <0>;
|
||||
gpmc,wr-access-ns = <40>;
|
||||
gpmc,wr-data-mux-bus-ns = <0>;
|
||||
/* MTD partition table */
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include "am33xx.dtsi"
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/ {
|
||||
cpus {
|
||||
|
|
@ -129,7 +130,11 @@
|
|||
ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */
|
||||
|
||||
nand@0,0 {
|
||||
compatible = "ti,omap2-nand";
|
||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||
interrupt-parent = <&gpmc>;
|
||||
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||
nand-bus-width = <8>;
|
||||
ti,nand-ecc-opt = "bch8";
|
||||
gpmc,device-width = <1>;
|
||||
|
|
@ -147,12 +152,9 @@
|
|||
gpmc,access-ns = <64>;
|
||||
gpmc,rd-cycle-ns = <82>;
|
||||
gpmc,wr-cycle-ns = <82>;
|
||||
gpmc,wait-on-read = "true";
|
||||
gpmc,wait-on-write = "true";
|
||||
gpmc,bus-turnaround-ns = <0>;
|
||||
gpmc,cycle2cycle-delay-ns = <0>;
|
||||
gpmc,clk-activation-ns = <0>;
|
||||
gpmc,wait-monitoring-ns = <0>;
|
||||
gpmc,wr-access-ns = <40>;
|
||||
gpmc,wr-data-mux-bus-ns = <0>;
|
||||
|
||||
|
|
|
|||
|
|
@ -8,6 +8,7 @@
|
|||
*/
|
||||
|
||||
#include "am33xx.dtsi"
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/ {
|
||||
model = "Phytec AM335x phyCORE";
|
||||
|
|
@ -165,7 +166,11 @@
|
|||
pinctrl-0 = <&nandflash_pins>;
|
||||
ranges = <0 0 0x08000000 0x1000000>; /* CS0: NAND */
|
||||
nandflash: nand@0,0 {
|
||||
compatible = "ti,omap2-nand";
|
||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||
interrupt-parent = <&gpmc>;
|
||||
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||
nand-bus-width = <8>;
|
||||
ti,nand-ecc-opt = "bch8";
|
||||
gpmc,device-nand = "true";
|
||||
|
|
@ -184,13 +189,10 @@
|
|||
gpmc,access-ns = <30>;
|
||||
gpmc,rd-cycle-ns = <30>;
|
||||
gpmc,wr-cycle-ns = <30>;
|
||||
gpmc,wait-on-read = "true";
|
||||
gpmc,wait-on-write = "true";
|
||||
gpmc,bus-turnaround-ns = <0>;
|
||||
gpmc,cycle2cycle-delay-ns = <50>;
|
||||
gpmc,cycle2cycle-diffcsen;
|
||||
gpmc,clk-activation-ns = <0>;
|
||||
gpmc,wait-monitoring-ns = <0>;
|
||||
gpmc,wr-access-ns = <30>;
|
||||
gpmc,wr-data-mux-bus-ns = <0>;
|
||||
|
||||
|
|
|
|||
|
|
@ -19,6 +19,10 @@
|
|||
};
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart0;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
|
|
@ -63,12 +67,28 @@
|
|||
default-brightness-level = <6>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* audio external oscillator */
|
||||
tlv320aic3x_mclk: oscillator@0 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24576000>; /* 24.576MHz */
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "ti,da830-evm-audio";
|
||||
ti,model = "AM335x-SL50";
|
||||
ti,audio-codec = <&audio_codec>;
|
||||
ti,mcasp-controller = <&mcasp0>;
|
||||
ti,codec-clock-rate = <12000000>;
|
||||
|
||||
clocks = <&tlv320aic3x_mclk>;
|
||||
clock-names = "mclk";
|
||||
|
||||
ti,audio-routing =
|
||||
"Headphone Jack", "HPLOUT",
|
||||
"Headphone Jack", "HPROUT",
|
||||
|
|
@ -226,7 +246,7 @@
|
|||
AM33XX_IOPAD(0x994, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_fsx.mcasp0_fsx */
|
||||
AM33XX_IOPAD(0x990, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_aclkx.mcasp0_aclkx */
|
||||
AM33XX_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr0.mcasp0_axr0 */
|
||||
AM33XX_IOPAD(0x99c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/
|
||||
AM33XX_IOPAD(0x99c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2 */
|
||||
>;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -866,6 +866,8 @@
|
|||
gpmc,num-waitpins = <2>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -894,21 +894,11 @@
|
|||
gpmc,num-waitpins = <2>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
am43xx_control_usb2phy1: control-phy@44e10620 {
|
||||
compatible = "ti,control-phy-usb2-am437";
|
||||
reg = <0x44e10620 0x4>;
|
||||
reg-names = "power";
|
||||
};
|
||||
|
||||
am43xx_control_usb2phy2: control-phy@0x44e10628 {
|
||||
compatible = "ti,control-phy-usb2-am437";
|
||||
reg = <0x44e10628 0x4>;
|
||||
reg-names = "power";
|
||||
};
|
||||
|
||||
ocp2scp0: ocp2scp@483a8000 {
|
||||
compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
|
||||
#address-cells = <1>;
|
||||
|
|
@ -919,7 +909,7 @@
|
|||
usb2_phy1: phy@483a8000 {
|
||||
compatible = "ti,am437x-usb2";
|
||||
reg = <0x483a8000 0x8000>;
|
||||
ctrl-module = <&am43xx_control_usb2phy1>;
|
||||
syscon-phy-power = <&scm_conf 0x620>;
|
||||
clocks = <&usb_phy0_always_on_clk32k>,
|
||||
<&usb_otg_ss0_refclk960m>;
|
||||
clock-names = "wkupclk", "refclk";
|
||||
|
|
@ -938,7 +928,7 @@
|
|||
usb2_phy2: phy@483e8000 {
|
||||
compatible = "ti,am437x-usb2";
|
||||
reg = <0x483e8000 0x8000>;
|
||||
ctrl-module = <&am43xx_control_usb2phy2>;
|
||||
syscon-phy-power = <&scm_conf 0x628>;
|
||||
clocks = <&usb_phy1_always_on_clk32k>,
|
||||
<&usb_otg_ss1_refclk960m>;
|
||||
clock-names = "wkupclk", "refclk";
|
||||
|
|
|
|||
|
|
@ -146,7 +146,11 @@
|
|||
pinctrl-0 = <&nand_flash_x8>;
|
||||
ranges = <0 0 0x08000000 0x1000000>;
|
||||
nand@0,0 {
|
||||
reg = <0 0 0>;
|
||||
compatible = "ti,omap2-nand";
|
||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||
interrupt-parent = <&gpmc>;
|
||||
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||
ti,nand-ecc-opt = "bch8";
|
||||
ti,elm-id = <&elm>;
|
||||
|
||||
|
|
@ -166,17 +170,12 @@
|
|||
gpmc,access-ns = <64>;
|
||||
gpmc,rd-cycle-ns = <82>;
|
||||
gpmc,wr-cycle-ns = <82>;
|
||||
gpmc,wait-on-read = "true";
|
||||
gpmc,wait-on-write = "true";
|
||||
gpmc,bus-turnaround-ns = <0>;
|
||||
gpmc,cycle2cycle-delay-ns = <0>;
|
||||
gpmc,clk-activation-ns = <0>;
|
||||
gpmc,wait-monitoring-ns = <0>;
|
||||
gpmc,wr-access-ns = <40>;
|
||||
gpmc,wr-data-mux-bus-ns = <0>;
|
||||
|
||||
gpmc,wait-pin = <0>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
/* MTD partition table */
|
||||
|
|
|
|||
|
|
@ -810,9 +810,13 @@
|
|||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&nand_flash_x8>;
|
||||
ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
|
||||
ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */
|
||||
nand@0,0 {
|
||||
compatible = "ti,omap2-nand";
|
||||
reg = <0 0 4>; /* device IO registers */
|
||||
interrupt-parent = <&gpmc>;
|
||||
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||
ti,nand-ecc-opt = "bch16";
|
||||
ti,elm-id = <&elm>;
|
||||
nand-bus-width = <8>;
|
||||
|
|
@ -831,11 +835,9 @@
|
|||
gpmc,access-ns = <30>;
|
||||
gpmc,rd-cycle-ns = <40>;
|
||||
gpmc,wr-cycle-ns = <40>;
|
||||
gpmc,wait-pin = <0>;
|
||||
gpmc,bus-turnaround-ns = <0>;
|
||||
gpmc,cycle2cycle-delay-ns = <0>;
|
||||
gpmc,clk-activation-ns = <0>;
|
||||
gpmc,wait-monitoring-ns = <0>;
|
||||
gpmc,wr-access-ns = <40>;
|
||||
gpmc,wr-data-mux-bus-ns = <0>;
|
||||
/* MTD partition table */
|
||||
|
|
|
|||
|
|
@ -18,7 +18,7 @@
|
|||
|
||||
/ {
|
||||
model = "TI AM43x EPOS EVM";
|
||||
compatible = "ti,am43x-epos-evm","ti,am4372","ti,am43";
|
||||
compatible = "ti,am43x-epos-evm","ti,am438x","ti,am43";
|
||||
|
||||
aliases {
|
||||
display0 = &lcd0;
|
||||
|
|
@ -561,9 +561,13 @@
|
|||
status = "okay"; /* Disable QSPI when enabling GPMC (NAND) */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&nand_flash_x8>;
|
||||
ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */
|
||||
ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */
|
||||
nand@0,0 {
|
||||
compatible = "ti,omap2-nand";
|
||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||
interrupt-parent = <&gpmc>;
|
||||
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||
ti,nand-ecc-opt = "bch16";
|
||||
ti,elm-id = <&elm>;
|
||||
nand-bus-width = <8>;
|
||||
|
|
@ -582,11 +586,9 @@
|
|||
gpmc,access-ns = <30>; /* tCEA + 4*/
|
||||
gpmc,rd-cycle-ns = <40>;
|
||||
gpmc,wr-cycle-ns = <40>;
|
||||
gpmc,wait-pin = <0>;
|
||||
gpmc,bus-turnaround-ns = <0>;
|
||||
gpmc,cycle2cycle-delay-ns = <0>;
|
||||
gpmc,clk-activation-ns = <0>;
|
||||
gpmc,wait-monitoring-ns = <0>;
|
||||
gpmc,wr-access-ns = <40>;
|
||||
gpmc,wr-data-mux-bus-ns = <0>;
|
||||
/* MTD partition table */
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@
|
|||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x80000000>;
|
||||
reg = <0x0 0x80000000 0x0 0x80000000>;
|
||||
};
|
||||
|
||||
vdd_3v3: fixedregulator-vdd_3v3 {
|
||||
|
|
@ -592,6 +592,11 @@
|
|||
DRVDD-supply = <&vdd_3v3>;
|
||||
DVDD-supply = <&aic_dvdd>;
|
||||
};
|
||||
|
||||
eeprom: eeprom@50 {
|
||||
compatible = "at,24c32";
|
||||
reg = <0x50>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@
|
|||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x20000000>; /* 512 MB - minimal configuration */
|
||||
reg = <0x0 0x80000000 0x0 0x20000000>; /* 512 MB - minimal configuration */
|
||||
};
|
||||
|
||||
leds {
|
||||
|
|
|
|||
|
|
@ -53,6 +53,14 @@
|
|||
regulator-boot-on;
|
||||
};
|
||||
|
||||
veth: fixedregulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "veth";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
xtal24mhz: xtal24mhz@24M {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
|
|
@ -106,6 +114,53 @@
|
|||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
flash@30000000 {
|
||||
compatible = "arm,versatile-flash", "cfi-flash";
|
||||
reg = <0x30000000 0x4000000>;
|
||||
bank-width = <4>;
|
||||
};
|
||||
|
||||
fpga_flash@38000000 {
|
||||
compatible = "arm,versatile-flash", "cfi-flash";
|
||||
reg = <0x38000000 0x800000>;
|
||||
bank-width = <4>;
|
||||
};
|
||||
|
||||
/*
|
||||
* The "secure flash" contains things like the boot
|
||||
* monitor so we don't want people to accidentally
|
||||
* screw this up. Mark the device tree node disabled
|
||||
* by default.
|
||||
*/
|
||||
secflash@3c000000 {
|
||||
compatible = "arm,versatile-flash", "cfi-flash";
|
||||
reg = <0x3c000000 0x4000000>;
|
||||
bank-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* SMSC 9118 ethernet with PHY and EEPROM */
|
||||
ethernet@3a000000 {
|
||||
compatible = "smsc,lan9118", "smsc,lan9115";
|
||||
reg = <0x3a000000 0x10000>;
|
||||
interrupt-parent = <&intc_fpga1176>;
|
||||
interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
phy-mode = "mii";
|
||||
reg-io-width = <4>;
|
||||
smsc,irq-active-high;
|
||||
smsc,irq-push-pull;
|
||||
vdd33a-supply = <&veth>;
|
||||
vddvario-supply = <&veth>;
|
||||
};
|
||||
|
||||
usb@3b000000 {
|
||||
compatible = "nxp,usb-isp1761";
|
||||
reg = <0x3b000000 0x20000>;
|
||||
interrupt-parent = <&intc_fpga1176>;
|
||||
interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
port1-otg;
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -176,6 +231,41 @@
|
|||
label = "versatile:7";
|
||||
default-state = "off";
|
||||
};
|
||||
oscclk0: osc0@0c {
|
||||
compatible = "arm,syscon-icst307";
|
||||
#clock-cells = <0>;
|
||||
lock-offset = <0x20>;
|
||||
vco-offset = <0x0C>;
|
||||
clocks = <&xtal24mhz>;
|
||||
};
|
||||
oscclk1: osc1@10 {
|
||||
compatible = "arm,syscon-icst307";
|
||||
#clock-cells = <0>;
|
||||
lock-offset = <0x20>;
|
||||
vco-offset = <0x10>;
|
||||
clocks = <&xtal24mhz>;
|
||||
};
|
||||
oscclk2: osc2@14 {
|
||||
compatible = "arm,syscon-icst307";
|
||||
#clock-cells = <0>;
|
||||
lock-offset = <0x20>;
|
||||
vco-offset = <0x14>;
|
||||
clocks = <&xtal24mhz>;
|
||||
};
|
||||
oscclk3: osc3@18 {
|
||||
compatible = "arm,syscon-icst307";
|
||||
#clock-cells = <0>;
|
||||
lock-offset = <0x20>;
|
||||
vco-offset = <0x18>;
|
||||
clocks = <&xtal24mhz>;
|
||||
};
|
||||
oscclk4: osc4@1c {
|
||||
compatible = "arm,syscon-icst307";
|
||||
#clock-cells = <0>;
|
||||
lock-offset = <0x20>;
|
||||
vco-offset = <0x1c>;
|
||||
clocks = <&xtal24mhz>;
|
||||
};
|
||||
};
|
||||
|
||||
/* Primary DevChip GIC synthesized with the CPU */
|
||||
|
|
@ -297,6 +387,13 @@
|
|||
clocks = <&uartclk>, <&pclk>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
/* Direct-mapped development chip ROM */
|
||||
pb1176_rom@10200000 {
|
||||
compatible = "direct-mapped";
|
||||
reg = <0x10200000 0x4000>;
|
||||
bank-width = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
/* These peripherals are inside the FPGA rather than the DevChip */
|
||||
|
|
@ -306,6 +403,27 @@
|
|||
compatible = "simple-bus";
|
||||
ranges;
|
||||
|
||||
i2c0: i2c@10002000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "arm,versatile-i2c";
|
||||
reg = <0x10002000 0x1000>;
|
||||
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds1338";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
fpga_aaci: aaci@10004000 {
|
||||
compatible = "arm,pl041", "arm,primecell";
|
||||
reg = <0x10004000 0x1000>;
|
||||
interrupt-parent = <&intc_fpga1176>;
|
||||
interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&pclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
fpga_mci: mmcsd@10005000 {
|
||||
compatible = "arm,pl18x", "arm,primecell";
|
||||
reg = <0x10005000 0x1000>;
|
||||
|
|
|
|||
|
|
@ -230,14 +230,14 @@
|
|||
|
||||
flash0@40000000 {
|
||||
/* 2 * 32MiB NOR Flash memory */
|
||||
compatible = "arm,vexpress-flash", "cfi-flash";
|
||||
compatible = "arm,versatile-flash", "cfi-flash";
|
||||
reg = <0x40000000 0x04000000>;
|
||||
bank-width = <4>;
|
||||
};
|
||||
|
||||
flash1@44000000 {
|
||||
// 2 * 32MiB NOR Flash memory
|
||||
compatible = "arm,vexpress-flash", "cfi-flash";
|
||||
compatible = "arm,versatile-flash", "cfi-flash";
|
||||
reg = <0x44000000 0x04000000>;
|
||||
bank-width = <4>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -168,6 +168,33 @@
|
|||
spi-max-frequency = <50000000>;
|
||||
};
|
||||
};
|
||||
|
||||
nand@d0000 {
|
||||
status = "okay";
|
||||
num-cs = <1>;
|
||||
marvell,nand-keep-config;
|
||||
marvell,nand-enable-arbiter;
|
||||
nand-on-flash-bbt;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "U-Boot";
|
||||
reg = <0 0x800000>;
|
||||
};
|
||||
partition@800000 {
|
||||
label = "Linux";
|
||||
reg = <0x800000 0x800000>;
|
||||
};
|
||||
partition@1000000 {
|
||||
label = "Filesystem";
|
||||
reg = <0x1000000 0x3f000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
|
|
|
|||
|
|
@ -200,7 +200,7 @@
|
|||
&pinctrl {
|
||||
pwr_led_pin: pwr-led-pin {
|
||||
marvell,pins = "mpp63";
|
||||
marvell,function = "gpo";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
stat_led_pins: stat-led-pins {
|
||||
|
|
|
|||
|
|
@ -297,7 +297,7 @@
|
|||
|
||||
backup_led_pin: backup-led-pin {
|
||||
marvell,pins = "mpp63";
|
||||
marvell,function = "gpo";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
power_led_pin: power-led-pin {
|
||||
|
|
|
|||
|
|
@ -339,7 +339,7 @@
|
|||
|
||||
fan_ctrl_high_pin: fan-ctrl-high-pin {
|
||||
marvell,pins = "mpp63";
|
||||
marvell,function = "gpo";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
fan_alarm_pin: fan-alarm-pin {
|
||||
|
|
|
|||
|
|
@ -529,7 +529,7 @@
|
|||
};
|
||||
|
||||
sata@a0000 {
|
||||
compatible = "marvell,orion-sata";
|
||||
compatible = "marvell,armada-370-sata";
|
||||
reg = <0xa0000 0x5000>;
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gateclk 14>, <&gateclk 20>;
|
||||
|
|
|
|||
|
|
@ -135,6 +135,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
/* CON3 */
|
||||
ethernet@30000 {
|
||||
status = "okay";
|
||||
phy = <&phy2>;
|
||||
|
|
@ -144,6 +145,7 @@
|
|||
bm,pool-short = <3>;
|
||||
};
|
||||
|
||||
/* CON2 */
|
||||
ethernet@34000 {
|
||||
status = "okay";
|
||||
phy = <&phy1>;
|
||||
|
|
@ -153,6 +155,7 @@
|
|||
bm,pool-short = <3>;
|
||||
};
|
||||
|
||||
/* CON4 */
|
||||
ethernet@70000 {
|
||||
pinctrl-names = "default";
|
||||
|
||||
|
|
|
|||
|
|
@ -44,8 +44,8 @@
|
|||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada 385 GP";
|
||||
compatible = "marvell,a385-gp", "marvell,armada388", "marvell,armada380";
|
||||
model = "Marvell Armada 388 DB-88F6820-GP";
|
||||
compatible = "marvell,a388-gp", "marvell,armada388", "marvell,armada380";
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
|
|
@ -240,13 +240,13 @@
|
|||
|
||||
/* CON5 */
|
||||
usb3@f0000 {
|
||||
vcc-supply = <®_usb2_1_vbus>;
|
||||
usb-phy = <&usb2_1_phy>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* CON7 */
|
||||
usb3@f8000 {
|
||||
vcc-supply = <®_usb3_vbus>;
|
||||
usb-phy = <&usb3_phy>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
|
@ -288,13 +288,22 @@
|
|||
};
|
||||
};
|
||||
|
||||
usb2_1_phy: usb2_1_phy {
|
||||
compatible = "usb-nop-xceiv";
|
||||
vcc-supply = <®_usb2_1_vbus>;
|
||||
};
|
||||
|
||||
usb3_phy: usb3_phy {
|
||||
compatible = "usb-nop-xceiv";
|
||||
vcc-supply = <®_usb3_vbus>;
|
||||
};
|
||||
|
||||
reg_usb3_vbus: usb3-vbus {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "usb3-vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
gpio = <&expander1 15 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
|
|
@ -314,7 +323,6 @@
|
|||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
gpio = <&expander0 4 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
|
|
@ -324,7 +332,7 @@
|
|||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
gpio = <&expander0 2 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
|
|
@ -333,7 +341,6 @@
|
|||
regulator-name = "v5.0-sata0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <®_sata0>;
|
||||
};
|
||||
|
||||
|
|
@ -342,7 +349,6 @@
|
|||
regulator-name = "v12.0-sata0";
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <®_sata0>;
|
||||
};
|
||||
|
||||
|
|
@ -352,7 +358,7 @@
|
|||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
gpio = <&expander0 3 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
|
|
@ -361,7 +367,6 @@
|
|||
regulator-name = "v5.0-sata1";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <®_sata1>;
|
||||
};
|
||||
|
||||
|
|
@ -370,7 +375,6 @@
|
|||
regulator-name = "v12.0-sata1";
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <®_sata1>;
|
||||
};
|
||||
|
||||
|
|
@ -378,7 +382,7 @@
|
|||
compatible = "regulator-fixed";
|
||||
regulator-name = "pwr_en_sata2";
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
gpio = <&expander0 11 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
|
|
@ -387,7 +391,6 @@
|
|||
regulator-name = "v5.0-sata2";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <®_sata2>;
|
||||
};
|
||||
|
||||
|
|
@ -396,7 +399,6 @@
|
|||
regulator-name = "v12.0-sata2";
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <®_sata2>;
|
||||
};
|
||||
|
||||
|
|
@ -404,7 +406,7 @@
|
|||
compatible = "regulator-fixed";
|
||||
regulator-name = "pwr_en_sata3";
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
gpio = <&expander0 12 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
|
|
@ -413,7 +415,6 @@
|
|||
regulator-name = "v5.0-sata3";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <®_sata3>;
|
||||
};
|
||||
|
||||
|
|
@ -422,7 +423,6 @@
|
|||
regulator-name = "v12.0-sata3";
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <®_sata3>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -429,6 +429,27 @@
|
|||
reg = <0x22000 0x1000>;
|
||||
};
|
||||
|
||||
/*
|
||||
* As a special exception to the "order by
|
||||
* register address" rule, the eth0 node is
|
||||
* placed here to ensure that it gets
|
||||
* registered as the first interface, since
|
||||
* the network subsystem doesn't allow naming
|
||||
* interfaces using DT aliases. Without this,
|
||||
* the ordering of interfaces is different
|
||||
* from the one used in U-Boot and the
|
||||
* labeling of interfaces on the boards, which
|
||||
* is very confusing for users.
|
||||
*/
|
||||
eth0: ethernet@70000 {
|
||||
compatible = "marvell,armada-370-neta";
|
||||
reg = <0x70000 0x4000>;
|
||||
interrupts-extended = <&mpic 8>;
|
||||
clocks = <&gateclk 4>;
|
||||
tx-csum-limit = <9800>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
eth1: ethernet@30000 {
|
||||
compatible = "marvell,armada-370-neta";
|
||||
reg = <0x30000 0x4000>;
|
||||
|
|
@ -493,15 +514,6 @@
|
|||
};
|
||||
};
|
||||
|
||||
eth0: ethernet@70000 {
|
||||
compatible = "marvell,armada-370-neta";
|
||||
reg = <0x70000 0x4000>;
|
||||
interrupts-extended = <&mpic 8>;
|
||||
clocks = <&gateclk 4>;
|
||||
tx-csum-limit = <9800>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mdio: mdio@72004 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
|
|||
|
|
@ -242,6 +242,34 @@
|
|||
spi-max-frequency = <20000000>;
|
||||
};
|
||||
};
|
||||
|
||||
nand@d0000 {
|
||||
status = "okay";
|
||||
num-cs = <1>;
|
||||
marvell,nand-keep-config;
|
||||
marvell,nand-enable-arbiter;
|
||||
nand-on-flash-bbt;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "U-Boot";
|
||||
reg = <0 0x800000>;
|
||||
};
|
||||
partition@800000 {
|
||||
label = "Linux";
|
||||
reg = <0x800000 0x800000>;
|
||||
};
|
||||
partition@1000000 {
|
||||
label = "Filesystem";
|
||||
reg = <0x1000000 0x3f000000>;
|
||||
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
bm-bppi {
|
||||
|
|
|
|||
64
arch/arm/boot/dts/artpec6-devboard.dts
Normal file
64
arch/arm/boot/dts/artpec6-devboard.dts
Normal file
|
|
@ -0,0 +1,64 @@
|
|||
/*
|
||||
* Axis ARTPEC-6 development board.
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "artpec6.dtsi"
|
||||
|
||||
/ {
|
||||
model = "ARTPEC-6 development board";
|
||||
compatible = "axis,artpec6-dev-board", "axis,artpec6";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
serial2 = &uart2;
|
||||
serial3 = &uart3;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial3:115200n8";
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x10000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ðernet {
|
||||
status = "okay";
|
||||
|
||||
phy-handle = <&phy1>;
|
||||
phy-mode = "gmii";
|
||||
|
||||
mdio {
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
phy1: phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
device_type = "ethernet-phy";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
270
arch/arm/boot/dts/artpec6.dtsi
Normal file
270
arch/arm/boot/dts/artpec6.dtsi
Normal file
|
|
@ -0,0 +1,270 @@
|
|||
/*
|
||||
* Device Tree Source for the Axis ARTPEC-6 SoC
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "axis,artpec6";
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <0>;
|
||||
next-level-cache = <&pl310>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <1>;
|
||||
next-level-cache = <&pl310>;
|
||||
};
|
||||
};
|
||||
|
||||
syscon {
|
||||
compatible = "axis,artpec6-syscon", "syscon";
|
||||
reg = <0xf8000000 0x48>;
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-0.2", "arm,psci";
|
||||
method = "smc";
|
||||
psci_version = <0x84000000>;
|
||||
cpu_on = <0x84000003>;
|
||||
system_reset = <0x84000009>;
|
||||
};
|
||||
|
||||
scu@faf00000 {
|
||||
compatible = "arm,cortex-a9-scu";
|
||||
reg = <0xfaf00000 0x58>;
|
||||
};
|
||||
|
||||
/* Main external clock driving CPU and peripherals */
|
||||
ext_clk: ext_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <50000000>;
|
||||
};
|
||||
|
||||
/* PLL1 is used by CPU and some peripherals */
|
||||
pll1_clk: pll1_clk@f8000000 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "axis,artpec6-pll1-clock";
|
||||
reg = <0xf8000000 4>;
|
||||
clocks = <&ext_clk>;
|
||||
};
|
||||
|
||||
cpu_clk: cpu_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-div = <1>;
|
||||
clock-mult = <1>;
|
||||
clocks = <&pll1_clk>;
|
||||
clock-output-names = "cpu_clk";
|
||||
};
|
||||
|
||||
cpu_clkdiv2: cpu_clkdiv2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-div = <2>;
|
||||
clock-mult = <1>;
|
||||
clocks = <&cpu_clk>;
|
||||
};
|
||||
|
||||
cpu_clkdiv4: cpu_clkdiv4 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-div = <4>;
|
||||
clock-mult = <1>;
|
||||
clocks = <&cpu_clk>;
|
||||
};
|
||||
|
||||
apb_pclk: apb_pclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-div = <8>;
|
||||
clock-mult = <1>;
|
||||
clocks = <&cpu_clk>;
|
||||
clock-output-names = "apb_pclk";
|
||||
};
|
||||
|
||||
/* PLL2 is used by a number of peripherals, including UDL */
|
||||
pll2: pll2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-div = <1>;
|
||||
clock-mult = <24>;
|
||||
clocks = <&ext_clk>;
|
||||
};
|
||||
|
||||
/* PLL2DIV2 is used by the Fractional Clock Divider, for i2s */
|
||||
pll2div2: pll2div2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-div = <2>;
|
||||
clock-mult = <1>;
|
||||
clocks = <&pll2>;
|
||||
};
|
||||
|
||||
pll2div12: pll2div12 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-div = <12>;
|
||||
clock-mult = <1>;
|
||||
clocks = <&pll2>;
|
||||
};
|
||||
|
||||
pll2div24: pll2div24 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-div = <24>;
|
||||
clock-mult = <1>;
|
||||
clocks = <&pll2>;
|
||||
clock-output-names = "uart_clk";
|
||||
};
|
||||
|
||||
|
||||
gtimer@faf00200 {
|
||||
compatible = "arm,cortex-a9-global-timer";
|
||||
reg = <0xfaf00200 0x20>;
|
||||
interrupts = <GIC_PPI 11 0xf01>;
|
||||
clocks = <&cpu_clkdiv2>;
|
||||
};
|
||||
|
||||
timer@faf00600 {
|
||||
compatible = "arm,cortex-a9-twd-timer";
|
||||
reg = <0xfaf00600 0x20>;
|
||||
interrupts = <GIC_PPI 13 0xf04>;
|
||||
clocks = <&cpu_clkdiv2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
intc: interrupt-controller@faf01000 {
|
||||
interrupt-controller;
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
reg = < 0xfaf01000 0x1000 >, < 0xfaf00100 0x0100 >;
|
||||
};
|
||||
|
||||
pl310: cache-controller@faf10000 {
|
||||
compatible = "arm,pl310-cache";
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
reg = <0xfaf10000 0x1000>;
|
||||
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
arm,data-latency = <1 1 1>;
|
||||
arm,tag-latency = <1 1 1>;
|
||||
arm,filter-ranges = <0x0 0x80000000>;
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a9-pmu";
|
||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&intc>;
|
||||
};
|
||||
|
||||
amba@0 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x1>;
|
||||
interrupt-parent = <&intc>;
|
||||
ranges;
|
||||
dma-ranges = <0x80000000 0x00000000 0x40000000>;
|
||||
dma-coherent;
|
||||
|
||||
ethernet: ethernet@f8010000 {
|
||||
clock-names = "phy_ref_clk", "apb_pclk";
|
||||
clocks = <&ext_clk>, <&apb_pclk>;
|
||||
compatible = "snps,dwc-qos-ethernet-4.10";
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0xf8010000 0x4000>;
|
||||
|
||||
snps,write-requests = <2>;
|
||||
snps,read-requests = <16>;
|
||||
snps,txpbl = <8>;
|
||||
snps,rxpbl = <2>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart0: serial@f8036000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0xf8036000 0x1000>;
|
||||
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&pll2div24>, <&apb_pclk>;
|
||||
clock-names = "uart_clk", "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
uart1: serial@f8037000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0xf8037000 0x1000>;
|
||||
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&pll2div24>, <&apb_pclk>;
|
||||
clock-names = "uart_clk", "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
uart2: serial@f8038000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0xf8038000 0x1000>;
|
||||
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&pll2div24>, <&apb_pclk>;
|
||||
clock-names = "uart_clk", "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
uart3: serial@f8039000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0xf8039000 0x1000>;
|
||||
interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&pll2div24>, <&apb_pclk>;
|
||||
clock-names = "uart_clk", "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -46,6 +46,7 @@
|
|||
#include "sama5d2.dtsi"
|
||||
#include "sama5d2-pinfunc.h"
|
||||
#include <dt-bindings/mfd/atmel-flexcom.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "Atmel SAMA5D2 Xplained";
|
||||
|
|
@ -71,11 +72,20 @@
|
|||
|
||||
ahb {
|
||||
usb0: gadget@00300000 {
|
||||
atmel,vbus-gpio = <&pioA 31 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usba_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb1: ohci@00400000 {
|
||||
num-ports = <3>;
|
||||
atmel,vbus-gpio = <0 /* &pioA 41 GPIO_ACTIVE_HIGH */
|
||||
&pioA 42 GPIO_ACTIVE_HIGH
|
||||
0
|
||||
>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb_default>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
@ -267,7 +277,29 @@
|
|||
};
|
||||
};
|
||||
|
||||
adc: adc@fc030000 {
|
||||
vddana-supply = <&vdd_3v3_lp_reg>;
|
||||
vref-supply = <&vdd_3v3_lp_reg>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_adc_default>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pinctrl@fc038000 {
|
||||
/*
|
||||
* There is no real pinmux for ADC, if the pin
|
||||
* is not requested by another peripheral then
|
||||
* the muxing is done when channel is enabled.
|
||||
* Requesting pins for ADC is GPIO is
|
||||
* encouraged to prevent conflicts and to
|
||||
* disable bias in order to be in the same
|
||||
* state when the pin is not muxed to the adc.
|
||||
*/
|
||||
pinctrl_adc_default: adc_default {
|
||||
pinmux = <PIN_PD23__GPIO>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pinctrl_flx0_default: flx0_default {
|
||||
pinmux = <PIN_PB28__FLEXCOM0_IO0>,
|
||||
<PIN_PB29__FLEXCOM0_IO1>;
|
||||
|
|
@ -292,6 +324,18 @@
|
|||
bias-disable;
|
||||
};
|
||||
|
||||
pinctrl_key_gpio_default: key_gpio_default {
|
||||
pinmux = <PIN_PB9__GPIO>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
pinctrl_led_gpio_default: led_gpio_default {
|
||||
pinmux = <PIN_PB0__GPIO>,
|
||||
<PIN_PB5__GPIO>,
|
||||
<PIN_PB6__GPIO>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
pinctrl_macb0_default: macb0_default {
|
||||
pinmux = <PIN_PB14__GTXCK>,
|
||||
<PIN_PB15__GTXEN>,
|
||||
|
|
@ -308,6 +352,7 @@
|
|||
|
||||
pinctrl_macb0_phy_irq: macb0_phy_irq {
|
||||
pinmux = <PIN_PC9__GPIO>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pinctrl_pdmic_default: pdmic_default {
|
||||
|
|
@ -375,7 +420,54 @@
|
|||
<PIN_PB12__UTXD3>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pinctrl_usb_default: usb_default {
|
||||
pinmux = <PIN_PB10__GPIO>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pinctrl_usba_vbus: usba_vbus {
|
||||
pinmux = <PIN_PA31__GPIO>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gpio_keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_key_gpio_default>;
|
||||
|
||||
bp1 {
|
||||
label = "PB_USER";
|
||||
gpios = <&pioA 41 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <0x104>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_led_gpio_default>;
|
||||
status = "okay";
|
||||
|
||||
red {
|
||||
label = "red";
|
||||
gpios = <&pioA 38 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
green {
|
||||
label = "green";
|
||||
gpios = <&pioA 37 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
blue {
|
||||
label = "blue";
|
||||
gpios = <&pioA 32 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -107,7 +107,7 @@
|
|||
};
|
||||
|
||||
amba {
|
||||
compatible = "arm,amba-bus";
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
|
|
|||
|
|
@ -121,4 +121,13 @@ clocks {
|
|||
clocks = <&osc>;
|
||||
clock-output-names = "keypad", "adc/touch", "pwm";
|
||||
};
|
||||
|
||||
audiopll: audiopll {
|
||||
#clock-cells = <1>;
|
||||
compatible = "brcm,cygnus-audiopll";
|
||||
reg = <0x180aeb00 0x68>;
|
||||
clocks = <&osc>;
|
||||
clock-output-names = "audiopll", "ch0_audio",
|
||||
"ch1_audio", "ch2_audio";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -45,14 +45,14 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
next-level-cache = <&L2>;
|
||||
reg = <0x0>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
next-level-cache = <&L2>;
|
||||
|
|
@ -62,24 +62,19 @@
|
|||
};
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a9-pmu";
|
||||
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&cpu0>, <&cpu1>;
|
||||
};
|
||||
|
||||
mpcore {
|
||||
compatible = "simple-bus";
|
||||
ranges = <0x00000000 0x19000000 0x00023000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
next-level-cache = <&L2>;
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
a9pll: arm_clk@00000 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "brcm,nsp-armpll";
|
||||
|
|
@ -169,6 +164,18 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
gpioa: gpio@0020 {
|
||||
compatible = "brcm,nsp-gpio-a";
|
||||
reg = <0x0020 0x70>,
|
||||
<0x3f1c4 0x1c>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
ngpios = <32>;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-ranges = <&pinctrl 0 0 32>;
|
||||
};
|
||||
|
||||
uart0: serial@0300 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0x0300 0x100>;
|
||||
|
|
@ -185,78 +192,6 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie0: pcie@12000 {
|
||||
compatible = "brcm,iproc-pcie";
|
||||
reg = <0x12000 0x1000>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_NONE>;
|
||||
|
||||
linux,pci-domain = <0>;
|
||||
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
|
||||
/* Note: The HW does not support I/O resources. So,
|
||||
* only the memory resource range is being specified.
|
||||
*/
|
||||
ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie1: pcie@13000 {
|
||||
compatible = "brcm,iproc-pcie";
|
||||
reg = <0x13000 0x1000>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 137 IRQ_TYPE_NONE>;
|
||||
|
||||
linux,pci-domain = <1>;
|
||||
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
|
||||
/* Note: The HW does not support I/O resources. So,
|
||||
* only the memory resource range is being specified.
|
||||
*/
|
||||
ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie2: pcie@14000 {
|
||||
compatible = "brcm,iproc-pcie";
|
||||
reg = <0x14000 0x1000>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 143 IRQ_TYPE_NONE>;
|
||||
|
||||
linux,pci-domain = <2>;
|
||||
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
|
||||
/* Note: The HW does not support I/O resources. So,
|
||||
* only the memory resource range is being specified.
|
||||
*/
|
||||
ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
nand: nand@26000 {
|
||||
compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
|
||||
reg = <0x026000 0x600>,
|
||||
|
|
@ -271,6 +206,24 @@
|
|||
brcm,nand-has-wp;
|
||||
};
|
||||
|
||||
ccbtimer0: timer@34000 {
|
||||
compatible = "arm,sp804";
|
||||
reg = <0x34000 0x1000>;
|
||||
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&iprocslow>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
ccbtimer1: timer@35000 {
|
||||
compatible = "arm,sp804";
|
||||
reg = <0x35000 0x1000>;
|
||||
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&iprocslow>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
i2c0: i2c@38000 {
|
||||
compatible = "brcm,iproc-i2c";
|
||||
reg = <0x38000 0x50>;
|
||||
|
|
@ -280,6 +233,14 @@
|
|||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
watchdog@39000 {
|
||||
compatible = "arm,sp805", "arm,primecell";
|
||||
reg = <0x39000 0x1000>;
|
||||
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&iprocslow>, <&iprocslow>;
|
||||
clock-names = "wdogclk", "apb_pclk";
|
||||
};
|
||||
|
||||
lcpll0: lcpll0@3f100 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "brcm,nsp-lcpll0";
|
||||
|
|
@ -306,4 +267,76 @@
|
|||
<0x3f408 0x04>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie0: pcie@18012000 {
|
||||
compatible = "brcm,iproc-pcie";
|
||||
reg = <0x18012000 0x1000>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_NONE>;
|
||||
|
||||
linux,pci-domain = <0>;
|
||||
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
|
||||
/* Note: The HW does not support I/O resources. So,
|
||||
* only the memory resource range is being specified.
|
||||
*/
|
||||
ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie1: pcie@18013000 {
|
||||
compatible = "brcm,iproc-pcie";
|
||||
reg = <0x18013000 0x1000>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 137 IRQ_TYPE_NONE>;
|
||||
|
||||
linux,pci-domain = <1>;
|
||||
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
|
||||
/* Note: The HW does not support I/O resources. So,
|
||||
* only the memory resource range is being specified.
|
||||
*/
|
||||
ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie2: pcie@18014000 {
|
||||
compatible = "brcm,iproc-pcie";
|
||||
reg = <0x18014000 0x1000>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 143 IRQ_TYPE_NONE>;
|
||||
|
||||
linux,pci-domain = <2>;
|
||||
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
|
||||
/* Note: The HW does not support I/O resources. So,
|
||||
* only the memory resource range is being specified.
|
||||
*/
|
||||
ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
24
arch/arm/boot/dts/bcm2835-rpi-a.dts
Normal file
24
arch/arm/boot/dts/bcm2835-rpi-a.dts
Normal file
|
|
@ -0,0 +1,24 @@
|
|||
/dts-v1/;
|
||||
#include "bcm2835.dtsi"
|
||||
#include "bcm2835-rpi.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "raspberrypi,model-a", "brcm,bcm2835";
|
||||
model = "Raspberry Pi Model A";
|
||||
|
||||
leds {
|
||||
act {
|
||||
gpios = <&gpio 16 1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gpio {
|
||||
pinctrl-0 = <&gpioout &alt0 &i2s_alt2 &alt3>;
|
||||
|
||||
/* I2S interface */
|
||||
i2s_alt2: i2s_alt2 {
|
||||
brcm,pins = <28 29 30 31>;
|
||||
brcm,function = <BCM2835_FSEL_ALT2>;
|
||||
};
|
||||
};
|
||||
|
|
@ -1,3 +1,5 @@
|
|||
#include <dt-bindings/power/raspberrypi-power.h>
|
||||
|
||||
/ {
|
||||
memory {
|
||||
reg = <0 0x10000000>;
|
||||
|
|
@ -18,6 +20,12 @@
|
|||
compatible = "raspberrypi,bcm2835-firmware";
|
||||
mboxes = <&mailbox>;
|
||||
};
|
||||
|
||||
power: power {
|
||||
compatible = "raspberrypi,bcm2835-power";
|
||||
firmware = <&firmware>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -58,3 +66,11 @@
|
|||
status = "okay";
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
&pwm {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb {
|
||||
power-domains = <&power RPI_POWER_DOMAIN_USB>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
#include <dt-bindings/pinctrl/bcm2835.h>
|
||||
#include <dt-bindings/clock/bcm2835.h>
|
||||
#include <dt-bindings/clock/bcm2835-aux.h>
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
/* This include file covers the common peripherals and configuration between
|
||||
|
|
@ -111,7 +112,7 @@
|
|||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
uart0: uart@7e201000 {
|
||||
uart0: serial@7e201000 {
|
||||
compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
|
||||
reg = <0x7e201000 0x1000>;
|
||||
interrupts = <2 25>;
|
||||
|
|
@ -159,6 +160,44 @@
|
|||
clocks = <&clocks BCM2835_CLOCK_VPU>;
|
||||
};
|
||||
|
||||
uart1: serial@7e215040 {
|
||||
compatible = "brcm,bcm2835-aux-uart";
|
||||
reg = <0x7e215040 0x40>;
|
||||
interrupts = <1 29>;
|
||||
clocks = <&aux BCM2835_AUX_CLOCK_UART>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi1: spi@7e215080 {
|
||||
compatible = "brcm,bcm2835-aux-spi";
|
||||
reg = <0x7e215080 0x40>;
|
||||
interrupts = <1 29>;
|
||||
clocks = <&aux BCM2835_AUX_CLOCK_SPI1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi2: spi@7e2150c0 {
|
||||
compatible = "brcm,bcm2835-aux-spi";
|
||||
reg = <0x7e2150c0 0x40>;
|
||||
interrupts = <1 29>;
|
||||
clocks = <&aux BCM2835_AUX_CLOCK_SPI2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm: pwm@7e20c000 {
|
||||
compatible = "brcm,bcm2835-pwm";
|
||||
reg = <0x7e20c000 0x28>;
|
||||
clocks = <&clocks BCM2835_CLOCK_PWM>;
|
||||
assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
|
||||
assigned-clock-rates = <10000000>;
|
||||
#pwm-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhci: sdhci@7e300000 {
|
||||
compatible = "brcm,bcm2835-sdhci";
|
||||
reg = <0x7e300000 0x100>;
|
||||
|
|
@ -187,7 +226,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
usb@7e980000 {
|
||||
usb: usb@7e980000 {
|
||||
compatible = "brcm,bcm2835-usb";
|
||||
reg = <0x7e980000 0x10000>;
|
||||
interrupts = <1 9>;
|
||||
|
|
|
|||
111
arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts
Normal file
111
arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts
Normal file
|
|
@ -0,0 +1,111 @@
|
|||
/*
|
||||
* Broadcom BCM470X / BCM5301X ARM platform code.
|
||||
* DTS for D-Link DIR-885L
|
||||
*
|
||||
* Copyright (C) 2016 Rafał Miłecki <zajec5@gmail.com>
|
||||
*
|
||||
* Licensed under the GNU/GPL. See COPYING for details.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "bcm4708.dtsi"
|
||||
#include "bcm5301x-nand-cs0-bch8.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "dlink,dir-885l", "brcm,bcm47094", "brcm,bcm4708";
|
||||
model = "D-Link DIR-885L";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200";
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x00000000 0x08000000>;
|
||||
};
|
||||
|
||||
nand: nand@18028000 {
|
||||
nandcs@0 {
|
||||
partition@0 {
|
||||
label = "firmware";
|
||||
reg = <0x00000000 0x08000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
power-white {
|
||||
label = "bcm53xx:white:power";
|
||||
gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "default-on";
|
||||
};
|
||||
|
||||
wan-white {
|
||||
label = "bcm53xx:white:wan";
|
||||
gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "default-off";
|
||||
};
|
||||
|
||||
power-amber {
|
||||
label = "bcm53xx:amber:power";
|
||||
gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "default-off";
|
||||
};
|
||||
|
||||
wan-amber {
|
||||
label = "bcm53xx:amber:wan";
|
||||
gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "default-off";
|
||||
};
|
||||
|
||||
usb3-white {
|
||||
label = "bcm53xx:white:usb3";
|
||||
gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "default-off";
|
||||
};
|
||||
|
||||
2ghz {
|
||||
label = "bcm53xx:white:2ghz";
|
||||
gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "default-off";
|
||||
};
|
||||
|
||||
5ghz {
|
||||
label = "bcm53xx:white:5ghz";
|
||||
gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "default-off";
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
wps {
|
||||
label = "WPS";
|
||||
linux,code = <KEY_WPS_BUTTON>;
|
||||
gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
/* Switch: router / extender */
|
||||
extender {
|
||||
label = "Extender";
|
||||
linux,code = <BTN_0>;
|
||||
gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
restart {
|
||||
label = "Reset";
|
||||
linux,code = <KEY_RESTART>;
|
||||
gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
clock-frequency = <125000000>;
|
||||
};
|
||||
|
|
@ -55,6 +55,7 @@
|
|||
MATRIX_KEY(0x03, 0x04, KEY_F5)
|
||||
MATRIX_KEY(0x03, 0x06, KEY_6)
|
||||
MATRIX_KEY(0x03, 0x08, KEY_MINUS)
|
||||
MATRIX_KEY(0x03, 0x09, KEY_F13)
|
||||
MATRIX_KEY(0x03, 0x0b, KEY_BACKSLASH)
|
||||
MATRIX_KEY(0x03, 0x0c, KEY_MUHENKAN)
|
||||
|
||||
|
|
|
|||
|
|
@ -6,6 +6,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include "dm814x.dtsi"
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/ {
|
||||
model = "DM8148 EVM";
|
||||
|
|
@ -35,6 +36,63 @@
|
|||
phy-mode = "rgmii";
|
||||
};
|
||||
|
||||
&gpmc {
|
||||
ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */
|
||||
|
||||
nand@0,0 {
|
||||
compatible = "ti,omap2-nand";
|
||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||
interrupt-parent = <&gpmc>;
|
||||
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||
linux,mtd-name= "micron,mt29f2g16aadwp";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ti,nand-ecc-opt = "bch8";
|
||||
nand-bus-width = <16>;
|
||||
gpmc,device-width = <2>;
|
||||
gpmc,sync-clk-ps = <0>;
|
||||
gpmc,cs-on-ns = <0>;
|
||||
gpmc,cs-rd-off-ns = <44>;
|
||||
gpmc,cs-wr-off-ns = <44>;
|
||||
gpmc,adv-on-ns = <6>;
|
||||
gpmc,adv-rd-off-ns = <34>;
|
||||
gpmc,adv-wr-off-ns = <44>;
|
||||
gpmc,we-on-ns = <0>;
|
||||
gpmc,we-off-ns = <40>;
|
||||
gpmc,oe-on-ns = <0>;
|
||||
gpmc,oe-off-ns = <54>;
|
||||
gpmc,access-ns = <64>;
|
||||
gpmc,rd-cycle-ns = <82>;
|
||||
gpmc,wr-cycle-ns = <82>;
|
||||
gpmc,bus-turnaround-ns = <0>;
|
||||
gpmc,cycle2cycle-delay-ns = <0>;
|
||||
gpmc,clk-activation-ns = <0>;
|
||||
gpmc,wr-access-ns = <40>;
|
||||
gpmc,wr-data-mux-bus-ns = <0>;
|
||||
partition@0 {
|
||||
label = "X-Loader";
|
||||
reg = <0 0x80000>;
|
||||
};
|
||||
partition@0x80000 {
|
||||
label = "U-Boot";
|
||||
reg = <0x80000 0x1c0000>;
|
||||
};
|
||||
partition@0x1c0000 {
|
||||
label = "Environment";
|
||||
reg = <0x240000 0x40000>;
|
||||
};
|
||||
partition@0x280000 {
|
||||
label = "Kernel";
|
||||
reg = <0x280000 0x500000>;
|
||||
};
|
||||
partition@0x780000 {
|
||||
label = "Filesystem";
|
||||
reg = <0x780000 0xf880000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mmc2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sd1_pins>;
|
||||
|
|
|
|||
|
|
@ -41,11 +41,11 @@
|
|||
reg = <0x0040>;
|
||||
};
|
||||
|
||||
/* Optional auxosc, 20 - 30 MHz range, assume 27 MHz by default */
|
||||
/* Optional auxosc, 20 - 30 MHz range, assume 22.5729 MHz by default */
|
||||
auxosc_ck: auxosc_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <27000000>;
|
||||
clock-frequency = <22572900>;
|
||||
};
|
||||
|
||||
/* Optional 32768Hz crystal or clock on RTCOSC pins */
|
||||
|
|
|
|||
|
|
@ -305,6 +305,13 @@
|
|||
reg = <0x60000 0x1000>;
|
||||
};
|
||||
|
||||
rtc: rtc@c0000 {
|
||||
compatible = "ti,am3352-rtc", "ti,da830-rtc";
|
||||
reg = <0xc0000 0x1000>;
|
||||
interrupts = <75 76>;
|
||||
ti,hwmods = "rtc";
|
||||
};
|
||||
|
||||
mmc2: mmc@1d8000 {
|
||||
compatible = "ti,omap4-hsmmc";
|
||||
ti,hwmods = "mmc2";
|
||||
|
|
@ -548,6 +555,20 @@
|
|||
reg-names = "gmii-sel";
|
||||
};
|
||||
};
|
||||
|
||||
gpmc: gpmc@50000000 {
|
||||
compatible = "ti,am3352-gpmc";
|
||||
ti,hwmods = "gpmc";
|
||||
ti,no-idle-on-init;
|
||||
reg = <0x50000000 0x2000>;
|
||||
interrupts = <100>;
|
||||
gpmc,num-cs = <7>;
|
||||
gpmc,num-waitpins = <2>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -6,6 +6,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include "dm816x.dtsi"
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/ {
|
||||
model = "DM8168 EVM";
|
||||
|
|
@ -85,8 +86,12 @@
|
|||
ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */
|
||||
|
||||
nand@0,0 {
|
||||
compatible = "ti,omap2-nand";
|
||||
linux,mtd-name= "micron,mt29f2g16aadwp";
|
||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||
interrupt-parent = <&gpmc>;
|
||||
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ti,nand-ecc-opt = "bch8";
|
||||
|
|
@ -106,12 +111,9 @@
|
|||
gpmc,access-ns = <64>;
|
||||
gpmc,rd-cycle-ns = <82>;
|
||||
gpmc,wr-cycle-ns = <82>;
|
||||
gpmc,wait-on-read = "true";
|
||||
gpmc,wait-on-write = "true";
|
||||
gpmc,bus-turnaround-ns = <0>;
|
||||
gpmc,cycle2cycle-delay-ns = <0>;
|
||||
gpmc,clk-activation-ns = <0>;
|
||||
gpmc,wait-monitoring-ns = <0>;
|
||||
gpmc,wr-access-ns = <40>;
|
||||
gpmc,wr-data-mux-bus-ns = <0>;
|
||||
partition@0 {
|
||||
|
|
|
|||
|
|
@ -183,6 +183,8 @@
|
|||
dma-names = "rxtx";
|
||||
gpmc,num-cs = <6>;
|
||||
gpmc,num-waitpins = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
i2c1: i2c@48028000 {
|
||||
|
|
@ -214,6 +216,13 @@
|
|||
reg = <0x48200000 0x1000>;
|
||||
};
|
||||
|
||||
rtc: rtc@480c0000 {
|
||||
compatible = "ti,am3352-rtc", "ti,da830-rtc";
|
||||
reg = <0x480c0000 0x1000>;
|
||||
interrupts = <75 76>;
|
||||
ti,hwmods = "rtc";
|
||||
};
|
||||
|
||||
mailbox: mailbox@480c8000 {
|
||||
compatible = "ti,omap4-mailbox";
|
||||
reg = <0x480c8000 0x2000>;
|
||||
|
|
|
|||
|
|
@ -6,6 +6,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include "dra62x.dtsi"
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/ {
|
||||
model = "DRA62x J5 Eco EVM";
|
||||
|
|
@ -35,6 +36,63 @@
|
|||
phy-mode = "rgmii";
|
||||
};
|
||||
|
||||
&gpmc {
|
||||
ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */
|
||||
|
||||
nand@0,0 {
|
||||
compatible = "ti,omap2-nand";
|
||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||
interrupt-parent = <&gpmc>;
|
||||
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||
linux,mtd-name= "micron,mt29f2g16aadwp";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ti,nand-ecc-opt = "bch8";
|
||||
nand-bus-width = <16>;
|
||||
gpmc,device-width = <2>;
|
||||
gpmc,sync-clk-ps = <0>;
|
||||
gpmc,cs-on-ns = <0>;
|
||||
gpmc,cs-rd-off-ns = <44>;
|
||||
gpmc,cs-wr-off-ns = <44>;
|
||||
gpmc,adv-on-ns = <6>;
|
||||
gpmc,adv-rd-off-ns = <34>;
|
||||
gpmc,adv-wr-off-ns = <44>;
|
||||
gpmc,we-on-ns = <0>;
|
||||
gpmc,we-off-ns = <40>;
|
||||
gpmc,oe-on-ns = <0>;
|
||||
gpmc,oe-off-ns = <54>;
|
||||
gpmc,access-ns = <64>;
|
||||
gpmc,rd-cycle-ns = <82>;
|
||||
gpmc,wr-cycle-ns = <82>;
|
||||
gpmc,bus-turnaround-ns = <0>;
|
||||
gpmc,cycle2cycle-delay-ns = <0>;
|
||||
gpmc,clk-activation-ns = <0>;
|
||||
gpmc,wr-access-ns = <40>;
|
||||
gpmc,wr-data-mux-bus-ns = <0>;
|
||||
partition@0 {
|
||||
label = "X-Loader";
|
||||
reg = <0 0x80000>;
|
||||
};
|
||||
partition@0x80000 {
|
||||
label = "U-Boot";
|
||||
reg = <0x80000 0x1c0000>;
|
||||
};
|
||||
partition@0x1c0000 {
|
||||
label = "Environment";
|
||||
reg = <0x240000 0x40000>;
|
||||
};
|
||||
partition@0x280000 {
|
||||
label = "Kernel";
|
||||
reg = <0x280000 0x500000>;
|
||||
};
|
||||
partition@0x780000 {
|
||||
label = "Filesystem";
|
||||
reg = <0x780000 0xf880000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mmc2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sd1_pins>;
|
||||
|
|
|
|||
27
arch/arm/boot/dts/dra7-dspeve-thermal.dtsi
Normal file
27
arch/arm/boot/dts/dra7-dspeve-thermal.dtsi
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
/*
|
||||
* Device Tree Source for DRA7x SoC DSPEVE thermal
|
||||
*
|
||||
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
|
||||
dspeve_thermal: dspeve_thermal {
|
||||
polling-delay-passive = <250>; /* milliseconds */
|
||||
polling-delay = <500>; /* milliseconds */
|
||||
|
||||
/* sensor ID */
|
||||
thermal-sensors = <&bandgap 3>;
|
||||
|
||||
trips {
|
||||
dspeve_crit: dspeve_crit {
|
||||
temperature = <125000>; /* milliCelsius */
|
||||
hysteresis = <2000>; /* milliCelsius */
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -18,7 +18,7 @@
|
|||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x60000000>; /* 1536 MB */
|
||||
reg = <0x0 0x80000000 0x0 0x60000000>; /* 1536 MB */
|
||||
};
|
||||
|
||||
evm_3v3_sd: fixedregulator-sd {
|
||||
|
|
@ -741,9 +741,13 @@
|
|||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&nand_flash_x16>;
|
||||
ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
|
||||
ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */
|
||||
nand@0,0 {
|
||||
compatible = "ti,omap2-nand";
|
||||
reg = <0 0 4>; /* device IO registers */
|
||||
interrupt-parent = <&gpmc>;
|
||||
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||
ti,nand-ecc-opt = "bch8";
|
||||
ti,elm-id = <&elm>;
|
||||
nand-bus-width = <16>;
|
||||
|
|
@ -766,7 +770,6 @@
|
|||
gpmc,bus-turnaround-ns = <0>;
|
||||
gpmc,cycle2cycle-delay-ns = <0>;
|
||||
gpmc,clk-activation-ns = <0>;
|
||||
gpmc,wait-monitoring-ns = <0>;
|
||||
gpmc,wr-data-mux-bus-ns = <0>;
|
||||
/* MTD partition table */
|
||||
/* All SPL-* partitions are sized to minimal length
|
||||
|
|
|
|||
27
arch/arm/boot/dts/dra7-iva-thermal.dtsi
Normal file
27
arch/arm/boot/dts/dra7-iva-thermal.dtsi
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
/*
|
||||
* Device Tree Source for DRA7x SoC IVA thermal
|
||||
*
|
||||
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
|
||||
iva_thermal: iva_thermal {
|
||||
polling-delay-passive = <250>; /* milliseconds */
|
||||
polling-delay = <500>; /* milliseconds */
|
||||
|
||||
/* sensor ID */
|
||||
thermal-sensors = <&bandgap 4>;
|
||||
|
||||
trips {
|
||||
iva_crit: iva_crit {
|
||||
temperature = <125000>; /* milliCelsius */
|
||||
hysteresis = <2000>; /* milliCelsius */
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -15,8 +15,8 @@
|
|||
#define MAX_SOURCES 400
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
compatible = "ti,dra7xx";
|
||||
interrupt-parent = <&crossbar_mpu>;
|
||||
|
|
@ -57,10 +57,10 @@
|
|||
compatible = "arm,cortex-a15-gic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
reg = <0x48211000 0x1000>,
|
||||
<0x48212000 0x1000>,
|
||||
<0x48214000 0x2000>,
|
||||
<0x48216000 0x2000>;
|
||||
reg = <0x0 0x48211000 0x0 0x1000>,
|
||||
<0x0 0x48212000 0x0 0x1000>,
|
||||
<0x0 0x48214000 0x0 0x2000>,
|
||||
<0x0 0x48216000 0x0 0x2000>;
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
interrupt-parent = <&gic>;
|
||||
};
|
||||
|
|
@ -69,7 +69,7 @@
|
|||
compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
reg = <0x48281000 0x1000>;
|
||||
reg = <0x0 0x48281000 0x0 0x1000>;
|
||||
interrupt-parent = <&gic>;
|
||||
};
|
||||
|
||||
|
|
@ -96,10 +96,10 @@
|
|||
compatible = "ti,dra7-l3-noc", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
ranges = <0x0 0x0 0x0 0xc0000000>;
|
||||
ti,hwmods = "l3_main_1", "l3_main_2";
|
||||
reg = <0x44000000 0x1000000>,
|
||||
<0x45000000 0x1000>;
|
||||
reg = <0x0 0x44000000 0x0 0x1000000>,
|
||||
<0x0 0x45000000 0x0 0x1000>;
|
||||
interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
|
|
@ -156,6 +156,11 @@
|
|||
compatible = "syscon";
|
||||
reg = <0x1c04 0x0020>;
|
||||
};
|
||||
|
||||
scm_conf_pcie: scm_conf@1c24 {
|
||||
compatible = "syscon";
|
||||
reg = <0x1c24 0x0024>;
|
||||
};
|
||||
};
|
||||
|
||||
cm_core_aon: cm_core_aon@5000 {
|
||||
|
|
@ -1168,14 +1173,6 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
omap_control_sata: control-phy@4a002374 {
|
||||
compatible = "ti,control-phy-pipe3";
|
||||
reg = <0x4a002374 0x4>;
|
||||
reg-names = "power";
|
||||
clocks = <&sys_clkin1>;
|
||||
clock-names = "sysclk";
|
||||
};
|
||||
|
||||
/* OCP2SCP3 */
|
||||
ocp2scp@4a090000 {
|
||||
compatible = "ti,omap-ocp2scp";
|
||||
|
|
@ -1190,7 +1187,7 @@
|
|||
<0x4A096400 0x64>, /* phy_tx */
|
||||
<0x4A096800 0x40>; /* pll_ctrl */
|
||||
reg-names = "phy_rx", "phy_tx", "pll_ctrl";
|
||||
ctrl-module = <&omap_control_sata>;
|
||||
syscon-phy-power = <&scm_conf 0x374>;
|
||||
clocks = <&sys_clkin1>, <&sata_ref_clk>;
|
||||
clock-names = "sysclk", "refclk";
|
||||
syscon-pllreset = <&scm_conf 0x3fc>;
|
||||
|
|
@ -1202,16 +1199,18 @@
|
|||
reg = <0x4a094000 0x80>, /* phy_rx */
|
||||
<0x4a094400 0x64>; /* phy_tx */
|
||||
reg-names = "phy_rx", "phy_tx";
|
||||
ctrl-module = <&omap_control_pcie1phy>;
|
||||
syscon-phy-power = <&scm_conf_pcie 0x1c>;
|
||||
syscon-pcs = <&scm_conf_pcie 0x10>;
|
||||
clocks = <&dpll_pcie_ref_ck>,
|
||||
<&dpll_pcie_ref_m2ldo_ck>,
|
||||
<&optfclk_pciephy1_32khz>,
|
||||
<&optfclk_pciephy1_clk>,
|
||||
<&optfclk_pciephy1_div_clk>,
|
||||
<&optfclk_pciephy_div>;
|
||||
<&optfclk_pciephy_div>,
|
||||
<&sys_clkin1>;
|
||||
clock-names = "dpll_ref", "dpll_ref_m2",
|
||||
"wkupclk", "refclk",
|
||||
"div-clk", "phy-div";
|
||||
"div-clk", "phy-div", "sysclk";
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
|
|
@ -1220,16 +1219,18 @@
|
|||
reg = <0x4a095000 0x80>, /* phy_rx */
|
||||
<0x4a095400 0x64>; /* phy_tx */
|
||||
reg-names = "phy_rx", "phy_tx";
|
||||
ctrl-module = <&omap_control_pcie2phy>;
|
||||
syscon-phy-power = <&scm_conf_pcie 0x20>;
|
||||
syscon-pcs = <&scm_conf_pcie 0x10>;
|
||||
clocks = <&dpll_pcie_ref_ck>,
|
||||
<&dpll_pcie_ref_m2ldo_ck>,
|
||||
<&optfclk_pciephy2_32khz>,
|
||||
<&optfclk_pciephy2_clk>,
|
||||
<&optfclk_pciephy2_div_clk>,
|
||||
<&optfclk_pciephy_div>;
|
||||
<&optfclk_pciephy_div>,
|
||||
<&sys_clkin1>;
|
||||
clock-names = "dpll_ref", "dpll_ref_m2",
|
||||
"wkupclk", "refclk",
|
||||
"div-clk", "phy-div";
|
||||
"div-clk", "phy-div", "sysclk";
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -1245,23 +1246,6 @@
|
|||
ti,hwmods = "sata";
|
||||
};
|
||||
|
||||
omap_control_pcie1phy: control-phy@0x4a003c40 {
|
||||
compatible = "ti,control-phy-pcie";
|
||||
reg = <0x4a003c40 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
|
||||
reg-names = "power", "control_sma", "pcie_pcs";
|
||||
clocks = <&sys_clkin1>;
|
||||
clock-names = "sysclk";
|
||||
};
|
||||
|
||||
omap_control_pcie2phy: control-pcie@0x4a003c44 {
|
||||
compatible = "ti,control-phy-pcie";
|
||||
reg = <0x4a003c44 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
|
||||
reg-names = "power", "control_sma", "pcie_pcs";
|
||||
clocks = <&sys_clkin1>;
|
||||
clock-names = "sysclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rtc: rtc@48838000 {
|
||||
compatible = "ti,am3352-rtc";
|
||||
reg = <0x48838000 0x100>;
|
||||
|
|
@ -1271,24 +1255,6 @@
|
|||
clocks = <&sys_32k_ck>;
|
||||
};
|
||||
|
||||
omap_control_usb2phy1: control-phy@4a002300 {
|
||||
compatible = "ti,control-phy-usb2";
|
||||
reg = <0x4a002300 0x4>;
|
||||
reg-names = "power";
|
||||
};
|
||||
|
||||
omap_control_usb3phy1: control-phy@4a002370 {
|
||||
compatible = "ti,control-phy-pipe3";
|
||||
reg = <0x4a002370 0x4>;
|
||||
reg-names = "power";
|
||||
};
|
||||
|
||||
omap_control_usb2phy2: control-phy@0x4a002e74 {
|
||||
compatible = "ti,control-phy-usb2-dra7";
|
||||
reg = <0x4a002e74 0x4>;
|
||||
reg-names = "power";
|
||||
};
|
||||
|
||||
/* OCP2SCP1 */
|
||||
ocp2scp@4a080000 {
|
||||
compatible = "ti,omap-ocp2scp";
|
||||
|
|
@ -1301,7 +1267,7 @@
|
|||
usb2_phy1: phy@4a084000 {
|
||||
compatible = "ti,omap-usb2";
|
||||
reg = <0x4a084000 0x400>;
|
||||
ctrl-module = <&omap_control_usb2phy1>;
|
||||
syscon-phy-power = <&scm_conf 0x300>;
|
||||
clocks = <&usb_phy1_always_on_clk32k>,
|
||||
<&usb_otg_ss1_refclk960m>;
|
||||
clock-names = "wkupclk",
|
||||
|
|
@ -1310,9 +1276,10 @@
|
|||
};
|
||||
|
||||
usb2_phy2: phy@4a085000 {
|
||||
compatible = "ti,omap-usb2";
|
||||
compatible = "ti,dra7x-usb2-phy2",
|
||||
"ti,omap-usb2";
|
||||
reg = <0x4a085000 0x400>;
|
||||
ctrl-module = <&omap_control_usb2phy2>;
|
||||
syscon-phy-power = <&scm_conf 0xe74>;
|
||||
clocks = <&usb_phy2_always_on_clk32k>,
|
||||
<&usb_otg_ss2_refclk960m>;
|
||||
clock-names = "wkupclk",
|
||||
|
|
@ -1326,7 +1293,7 @@
|
|||
<0x4a084800 0x64>,
|
||||
<0x4a084c00 0x40>;
|
||||
reg-names = "phy_rx", "phy_tx", "pll_ctrl";
|
||||
ctrl-module = <&omap_control_usb3phy1>;
|
||||
syscon-phy-power = <&scm_conf 0x370>;
|
||||
clocks = <&usb_phy3_always_on_clk32k>,
|
||||
<&sys_clkin1>,
|
||||
<&usb_otg_ss1_refclk960m>;
|
||||
|
|
@ -1357,7 +1324,6 @@
|
|||
"otg";
|
||||
phys = <&usb2_phy1>, <&usb3_phy1>;
|
||||
phy-names = "usb2-phy", "usb3-phy";
|
||||
tx-fifo-resize;
|
||||
maximum-speed = "super-speed";
|
||||
dr_mode = "otg";
|
||||
snps,dis_u3_susphy_quirk;
|
||||
|
|
@ -1385,7 +1351,6 @@
|
|||
"otg";
|
||||
phys = <&usb2_phy2>;
|
||||
phy-names = "usb2-phy";
|
||||
tx-fifo-resize;
|
||||
maximum-speed = "high-speed";
|
||||
dr_mode = "otg";
|
||||
snps,dis_u3_susphy_quirk;
|
||||
|
|
@ -1413,7 +1378,6 @@
|
|||
interrupt-names = "peripheral",
|
||||
"host",
|
||||
"otg";
|
||||
tx-fifo-resize;
|
||||
maximum-speed = "high-speed";
|
||||
dr_mode = "otg";
|
||||
snps,dis_u3_susphy_quirk;
|
||||
|
|
@ -1438,6 +1402,8 @@
|
|||
gpmc,num-waitpins = <2>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1613,6 +1579,8 @@
|
|||
#include "omap4-cpu-thermal.dtsi"
|
||||
#include "omap5-gpu-thermal.dtsi"
|
||||
#include "omap5-core-thermal.dtsi"
|
||||
#include "dra7-dspeve-thermal.dtsi"
|
||||
#include "dra7-iva-thermal.dtsi"
|
||||
};
|
||||
|
||||
};
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@
|
|||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x40000000>; /* 1024 MB */
|
||||
reg = <0x0 0x80000000 0x0 0x40000000>; /* 1024 MB */
|
||||
};
|
||||
|
||||
aliases {
|
||||
|
|
@ -492,13 +492,17 @@
|
|||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&nand_default>;
|
||||
ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
|
||||
ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */
|
||||
nand@0,0 {
|
||||
/* To use NAND, DIP switch SW5 must be set like so:
|
||||
* SW5.1 (NAND_SELn) = ON (LOW)
|
||||
* SW5.9 (GPMC_WPN) = OFF (HIGH)
|
||||
*/
|
||||
compatible = "ti,omap2-nand";
|
||||
reg = <0 0 4>; /* device IO registers */
|
||||
interrupt-parent = <&gpmc>;
|
||||
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||
ti,nand-ecc-opt = "bch8";
|
||||
ti,elm-id = <&elm>;
|
||||
nand-bus-width = <16>;
|
||||
|
|
@ -521,7 +525,6 @@
|
|||
gpmc,bus-turnaround-ns = <0>;
|
||||
gpmc,cycle2cycle-delay-ns = <0>;
|
||||
gpmc,clk-activation-ns = <0>;
|
||||
gpmc,wait-monitoring-ns = <0>;
|
||||
gpmc,wr-data-mux-bus-ns = <0>;
|
||||
/* MTD partition table */
|
||||
/* All SPL-* partitions are sized to minimal length
|
||||
|
|
|
|||
|
|
@ -76,7 +76,6 @@
|
|||
interrupt-names = "peripheral",
|
||||
"host",
|
||||
"otg";
|
||||
tx-fifo-resize;
|
||||
maximum-speed = "high-speed";
|
||||
dr_mode = "otg";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -2146,4 +2146,28 @@
|
|||
ti,bit-shift = <0>;
|
||||
reg = <0x558>;
|
||||
};
|
||||
|
||||
ehrpwm0_tbclk: ehrpwm0_tbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&l4_root_clk_div>;
|
||||
ti,bit-shift = <20>;
|
||||
reg = <0x0558>;
|
||||
};
|
||||
|
||||
ehrpwm1_tbclk: ehrpwm1_tbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&l4_root_clk_div>;
|
||||
ti,bit-shift = <21>;
|
||||
reg = <0x0558>;
|
||||
};
|
||||
|
||||
ehrpwm2_tbclk: ehrpwm2_tbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&l4_root_clk_div>;
|
||||
ti,bit-shift = <22>;
|
||||
reg = <0x0558>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@
|
|||
*/
|
||||
|
||||
#include "skeleton.dtsi"
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/ {
|
||||
|
|
@ -53,8 +54,8 @@
|
|||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a9-pmu";
|
||||
interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 121 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
clocks@e0110000 {
|
||||
|
|
@ -158,7 +159,7 @@
|
|||
timer@e0180000 {
|
||||
compatible = "renesas,em-sti";
|
||||
reg = <0xe0180000 0x54>;
|
||||
interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&sti_sclk>;
|
||||
clock-names = "sclk";
|
||||
};
|
||||
|
|
@ -166,7 +167,7 @@
|
|||
uart0: serial@e1020000 {
|
||||
compatible = "renesas,em-uart";
|
||||
reg = <0xe1020000 0x38>;
|
||||
interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&usia_u0_sclk>;
|
||||
clock-names = "sclk";
|
||||
};
|
||||
|
|
@ -174,7 +175,7 @@
|
|||
uart1: serial@e1030000 {
|
||||
compatible = "renesas,em-uart";
|
||||
reg = <0xe1030000 0x38>;
|
||||
interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&usib_u1_sclk>;
|
||||
clock-names = "sclk";
|
||||
};
|
||||
|
|
@ -182,7 +183,7 @@
|
|||
uart2: serial@e1040000 {
|
||||
compatible = "renesas,em-uart";
|
||||
reg = <0xe1040000 0x38>;
|
||||
interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&usib_u2_sclk>;
|
||||
clock-names = "sclk";
|
||||
};
|
||||
|
|
@ -190,7 +191,7 @@
|
|||
uart3: serial@e1050000 {
|
||||
compatible = "renesas,em-uart";
|
||||
reg = <0xe1050000 0x38>;
|
||||
interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&usib_u3_sclk>;
|
||||
clock-names = "sclk";
|
||||
};
|
||||
|
|
@ -203,8 +204,8 @@
|
|||
gpio0: gpio@e0050000 {
|
||||
compatible = "renesas,em-gio";
|
||||
reg = <0xe0050000 0x2c>, <0xe0050040 0x20>;
|
||||
interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 68 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 0 32>;
|
||||
#gpio-cells = <2>;
|
||||
|
|
@ -215,8 +216,8 @@
|
|||
gpio1: gpio@e0050080 {
|
||||
compatible = "renesas,em-gio";
|
||||
reg = <0xe0050080 0x2c>, <0xe00500c0 0x20>;
|
||||
interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 70 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 32 32>;
|
||||
#gpio-cells = <2>;
|
||||
|
|
@ -227,8 +228,8 @@
|
|||
gpio2: gpio@e0050100 {
|
||||
compatible = "renesas,em-gio";
|
||||
reg = <0xe0050100 0x2c>, <0xe0050140 0x20>;
|
||||
interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 72 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 64 32>;
|
||||
#gpio-cells = <2>;
|
||||
|
|
@ -239,8 +240,8 @@
|
|||
gpio3: gpio@e0050180 {
|
||||
compatible = "renesas,em-gio";
|
||||
reg = <0xe0050180 0x2c>, <0xe00501c0 0x20>;
|
||||
interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 74 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 96 32>;
|
||||
#gpio-cells = <2>;
|
||||
|
|
@ -251,8 +252,8 @@
|
|||
gpio4: gpio@e0050200 {
|
||||
compatible = "renesas,em-gio";
|
||||
reg = <0xe0050200 0x2c>, <0xe0050240 0x20>;
|
||||
interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 76 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 128 31>;
|
||||
#gpio-cells = <2>;
|
||||
|
|
@ -266,7 +267,7 @@
|
|||
#size-cells = <0>;
|
||||
compatible = "renesas,iic-emev2";
|
||||
reg = <0xe0070000 0x28>;
|
||||
interrupts = <0 32 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&iic0_sclk>;
|
||||
clock-names = "sclk";
|
||||
status = "disabled";
|
||||
|
|
@ -277,7 +278,7 @@
|
|||
#size-cells = <0>;
|
||||
compatible = "renesas,iic-emev2";
|
||||
reg = <0xe10a0000 0x28>;
|
||||
interrupts = <0 33 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupts = <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&iic1_sclk>;
|
||||
clock-names = "sclk";
|
||||
status = "disabled";
|
||||
|
|
|
|||
27
arch/arm/boot/dts/exynos-syscon-restart.dtsi
Normal file
27
arch/arm/boot/dts/exynos-syscon-restart.dtsi
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
/*
|
||||
* Samsung's Exynos SoC syscon reboot/poweroff nodes common definition.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/ {
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
|
||||
poweroff: syscon-poweroff {
|
||||
compatible = "syscon-poweroff";
|
||||
regmap = <&pmu_system_controller>;
|
||||
offset = <0x330C>; /* PS_HOLD_CONTROL */
|
||||
mask = <0x5200>; /* reset value */
|
||||
};
|
||||
|
||||
reboot: syscon-reboot {
|
||||
compatible = "syscon-reboot";
|
||||
regmap = <&pmu_system_controller>;
|
||||
offset = <0x0400>; /* SWRESET */
|
||||
mask = <0x1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -43,7 +43,7 @@
|
|||
linux,code = <KEY_POWER>;
|
||||
label = "power key";
|
||||
debounce-interval = <10>;
|
||||
gpio-key,wakeup;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -67,7 +67,7 @@
|
|||
interrupt-parent = <&gpx1>;
|
||||
interrupts = <5 0>;
|
||||
reg = <0x25>;
|
||||
wakeup;
|
||||
wakeup-source;
|
||||
|
||||
muic: max77836-muic {
|
||||
compatible = "maxim,max77836-muic";
|
||||
|
|
@ -185,7 +185,7 @@
|
|||
interrupt-parent = <&gpx0>;
|
||||
interrupts = <7 0>;
|
||||
reg = <0x66>;
|
||||
wakeup;
|
||||
wakeup-source;
|
||||
|
||||
s2mps14_osc: clocks {
|
||||
compatible = "samsung,s2mps14-clk";
|
||||
|
|
|
|||
|
|
@ -43,7 +43,7 @@
|
|||
linux,code = <KEY_POWER>;
|
||||
label = "power key";
|
||||
debounce-interval = <10>;
|
||||
gpio-key,wakeup;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -58,7 +58,7 @@
|
|||
interrupt-parent = <&gpx1>;
|
||||
interrupts = <5 0>;
|
||||
reg = <0x25>;
|
||||
wakeup;
|
||||
wakeup-source;
|
||||
|
||||
muic: max77836-muic {
|
||||
compatible = "maxim,max77836-muic";
|
||||
|
|
@ -246,7 +246,7 @@
|
|||
interrupt-parent = <&gpx0>;
|
||||
interrupts = <7 0>;
|
||||
reg = <0x66>;
|
||||
wakeup;
|
||||
wakeup-source;
|
||||
|
||||
s2mps14_osc: clocks {
|
||||
compatible = "samsung,s2mps14-clk";
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@
|
|||
|
||||
#include "skeleton.dtsi"
|
||||
#include "exynos4-cpu-thermal.dtsi"
|
||||
#include "exynos-syscon-restart.dtsi"
|
||||
#include <dt-bindings/clock/exynos3250.h>
|
||||
|
||||
/ {
|
||||
|
|
@ -152,20 +153,6 @@
|
|||
interrupt-parent = <&gic>;
|
||||
};
|
||||
|
||||
poweroff: syscon-poweroff {
|
||||
compatible = "syscon-poweroff";
|
||||
regmap = <&pmu_system_controller>;
|
||||
offset = <0x330C>; /* PS_HOLD_CONTROL */
|
||||
mask = <0x5200>; /* Reset value */
|
||||
};
|
||||
|
||||
reboot: syscon-reboot {
|
||||
compatible = "syscon-reboot";
|
||||
regmap = <&pmu_system_controller>;
|
||||
offset = <0x0400>; /* SWRESET */
|
||||
mask = <0x1>;
|
||||
};
|
||||
|
||||
mipi_phy: video-phy@10020710 {
|
||||
compatible = "samsung,s5pv210-mipi-video-phy";
|
||||
#phy-cells = <1>;
|
||||
|
|
@ -381,7 +368,7 @@
|
|||
};
|
||||
|
||||
amba {
|
||||
compatible = "arm,amba-bus";
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
|
|
|||
|
|
@ -22,6 +22,7 @@
|
|||
#include <dt-bindings/clock/exynos4.h>
|
||||
#include <dt-bindings/clock/exynos-audss-clk.h>
|
||||
#include "skeleton.dtsi"
|
||||
#include "exynos-syscon-restart.dtsi"
|
||||
|
||||
/ {
|
||||
interrupt-parent = <&gic>;
|
||||
|
|
@ -76,6 +77,11 @@
|
|||
reg = <0x10000000 0x100>;
|
||||
};
|
||||
|
||||
sromc@12570000 {
|
||||
compatible = "samsung,exynos-srom";
|
||||
reg = <0x12570000 0x14>;
|
||||
};
|
||||
|
||||
mipi_phy: video-phy@10020710 {
|
||||
compatible = "samsung,s5pv210-mipi-video-phy";
|
||||
#phy-cells = <1>;
|
||||
|
|
@ -158,20 +164,6 @@
|
|||
interrupt-parent = <&gic>;
|
||||
};
|
||||
|
||||
poweroff: syscon-poweroff {
|
||||
compatible = "syscon-poweroff";
|
||||
regmap = <&pmu_system_controller>;
|
||||
offset = <0x330C>; /* PS_HOLD_CONTROL */
|
||||
mask = <0x5200>; /* reset value */
|
||||
};
|
||||
|
||||
reboot: syscon-reboot {
|
||||
compatible = "syscon-reboot";
|
||||
regmap = <&pmu_system_controller>;
|
||||
offset = <0x0400>; /* SWRESET */
|
||||
mask = <0x1>;
|
||||
};
|
||||
|
||||
dsi_0: dsi@11C80000 {
|
||||
compatible = "samsung,exynos4210-mipi-dsi";
|
||||
reg = <0x11C80000 0x10000>;
|
||||
|
|
@ -661,7 +653,7 @@
|
|||
amba {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "arm,amba-bus";
|
||||
compatible = "simple-bus";
|
||||
interrupt-parent = <&gic>;
|
||||
ranges;
|
||||
|
||||
|
|
|
|||
|
|
@ -60,35 +60,35 @@
|
|||
label = "Up";
|
||||
gpios = <&gpx2 0 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_UP>;
|
||||
gpio-key,wakeup;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
down {
|
||||
label = "Down";
|
||||
gpios = <&gpx2 1 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_DOWN>;
|
||||
gpio-key,wakeup;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
back {
|
||||
label = "Back";
|
||||
gpios = <&gpx1 7 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_BACK>;
|
||||
gpio-key,wakeup;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
home {
|
||||
label = "Home";
|
||||
gpios = <&gpx1 6 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_HOME>;
|
||||
gpio-key,wakeup;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
menu {
|
||||
label = "Menu";
|
||||
gpios = <&gpx1 5 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_MENU>;
|
||||
gpio-key,wakeup;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -66,7 +66,7 @@
|
|||
samsung,keypad-num-rows = <2>;
|
||||
samsung,keypad-num-columns = <8>;
|
||||
linux,keypad-no-autorepeat;
|
||||
linux,keypad-wakeup;
|
||||
wakeup-source;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&keypad_rows &keypad_cols>;
|
||||
status = "okay";
|
||||
|
|
|
|||
|
|
@ -112,7 +112,7 @@
|
|||
linux,code = <116>;
|
||||
label = "power";
|
||||
debounce-interval = <10>;
|
||||
gpio-key,wakeup;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
ok-key {
|
||||
|
|
|
|||
|
|
@ -92,7 +92,7 @@
|
|||
linux,code = <171>;
|
||||
label = "config";
|
||||
debounce-interval = <1>;
|
||||
gpio-key,wakeup;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
camera-key {
|
||||
|
|
@ -107,7 +107,7 @@
|
|||
linux,code = <116>;
|
||||
label = "power";
|
||||
debounce-interval = <1>;
|
||||
gpio-key,wakeup;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
ok-key {
|
||||
|
|
|
|||
|
|
@ -35,7 +35,7 @@
|
|||
linux,code = <KEY_POWER>;
|
||||
label = "power key";
|
||||
debounce-interval = <10>;
|
||||
gpio-key,wakeup;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -48,7 +48,7 @@
|
|||
linux,code = <KEY_HOME>;
|
||||
label = "home key";
|
||||
debounce-interval = <10>;
|
||||
gpio-key,wakeup;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -423,7 +423,7 @@
|
|||
samsung,keypad-num-rows = <3>;
|
||||
samsung,keypad-num-columns = <2>;
|
||||
linux,keypad-no-autorepeat;
|
||||
linux,keypad-wakeup;
|
||||
wakeup-source;
|
||||
pinctrl-0 = <&keypad_rows &keypad_cols>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
|
|
|||
|
|
@ -45,7 +45,7 @@
|
|||
samsung,keypad-num-rows = <3>;
|
||||
samsung,keypad-num-columns = <8>;
|
||||
linux,keypad-no-autorepeat;
|
||||
linux,keypad-wakeup;
|
||||
wakeup-source;
|
||||
pinctrl-0 = <&keypad_rows &keypad_cols>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
|
|
|||
|
|
@ -119,7 +119,7 @@
|
|||
linux,code = <116>;
|
||||
label = "power";
|
||||
debounce-interval = <10>;
|
||||
gpio-key,wakeup;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
key-ok {
|
||||
|
|
@ -127,7 +127,7 @@
|
|||
linux,code = <139>;
|
||||
label = "ok";
|
||||
debounce-inteval = <10>;
|
||||
gpio-key,wakeup;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -380,7 +380,7 @@
|
|||
};
|
||||
|
||||
amba {
|
||||
compatible = "arm,amba-bus";
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-parent = <&gic>;
|
||||
|
|
|
|||
|
|
@ -14,6 +14,7 @@
|
|||
*/
|
||||
|
||||
#include "skeleton.dtsi"
|
||||
#include "exynos-syscon-restart.dtsi"
|
||||
|
||||
/ {
|
||||
interrupt-parent = <&gic>;
|
||||
|
|
@ -30,6 +31,11 @@
|
|||
reg = <0x10000000 0x100>;
|
||||
};
|
||||
|
||||
sromc@12250000 {
|
||||
compatible = "samsung,exynos-srom";
|
||||
reg = <0x12250000 0x14>;
|
||||
};
|
||||
|
||||
combiner: interrupt-controller@10440000 {
|
||||
compatible = "samsung,exynos4210-combiner";
|
||||
#interrupt-cells = <2>;
|
||||
|
|
@ -88,20 +94,6 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
poweroff: syscon-poweroff {
|
||||
compatible = "syscon-poweroff";
|
||||
regmap = <&pmu_system_controller>;
|
||||
offset = <0x330C>; /* PS_HOLD_CONTROL */
|
||||
mask = <0x5200>; /* reset value */
|
||||
};
|
||||
|
||||
reboot: syscon-reboot {
|
||||
compatible = "syscon-reboot";
|
||||
regmap = <&pmu_system_controller>;
|
||||
offset = <0x0400>; /* SWRESET */
|
||||
mask = <0x1>;
|
||||
};
|
||||
|
||||
fimd: fimd@14400000 {
|
||||
compatible = "samsung,exynos5250-fimd";
|
||||
interrupt-parent = <&combiner>;
|
||||
|
|
|
|||
|
|
@ -34,42 +34,42 @@
|
|||
label = "SW-TACT2";
|
||||
gpios = <&gpx1 4 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_MENU>;
|
||||
gpio-key,wakeup;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
home {
|
||||
label = "SW-TACT3";
|
||||
gpios = <&gpx1 5 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_HOME>;
|
||||
gpio-key,wakeup;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
up {
|
||||
label = "SW-TACT4";
|
||||
gpios = <&gpx1 6 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_UP>;
|
||||
gpio-key,wakeup;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
down {
|
||||
label = "SW-TACT5";
|
||||
gpios = <&gpx1 7 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_DOWN>;
|
||||
gpio-key,wakeup;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
back {
|
||||
label = "SW-TACT6";
|
||||
gpios = <&gpx2 0 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_BACK>;
|
||||
gpio-key,wakeup;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
wakeup {
|
||||
label = "SW-TACT7";
|
||||
gpios = <&gpx2 1 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_WAKEUP>;
|
||||
gpio-key,wakeup;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -37,7 +37,7 @@
|
|||
label = "Power";
|
||||
gpios = <&gpx1 3 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_POWER>;
|
||||
gpio-key,wakeup;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
lid-switch {
|
||||
|
|
@ -46,7 +46,7 @@
|
|||
linux,input-type = <5>; /* EV_SW */
|
||||
linux,code = <0>; /* SW_LID */
|
||||
debounce-interval = <1>;
|
||||
gpio-key,wakeup;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -37,7 +37,7 @@
|
|||
label = "Power";
|
||||
gpios = <&gpx1 3 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_POWER>;
|
||||
gpio-key,wakeup;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
lid-switch {
|
||||
|
|
@ -46,7 +46,7 @@
|
|||
linux,input-type = <5>; /* EV_SW */
|
||||
linux,code = <0>; /* SW_LID */
|
||||
debounce-interval = <1>;
|
||||
gpio-key,wakeup;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -674,7 +674,7 @@
|
|||
amba {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "arm,amba-bus";
|
||||
compatible = "simple-bus";
|
||||
interrupt-parent = <&gic>;
|
||||
ranges;
|
||||
|
||||
|
|
@ -807,7 +807,7 @@
|
|||
|
||||
sss@10830000 {
|
||||
compatible = "samsung,exynos4210-secss";
|
||||
reg = <0x10830000 0x10000>;
|
||||
reg = <0x10830000 0x300>;
|
||||
interrupts = <0 112 0>;
|
||||
clocks = <&clock CLK_SSS>;
|
||||
clock-names = "secss";
|
||||
|
|
|
|||
406
arch/arm/boot/dts/exynos5410-pinctrl.dtsi
Normal file
406
arch/arm/boot/dts/exynos5410-pinctrl.dtsi
Normal file
|
|
@ -0,0 +1,406 @@
|
|||
/*
|
||||
* Exynos5410 SoC pin-mux and pin-config device tree source
|
||||
*
|
||||
* Copyright (c) 2013 Hardkernel Co., Ltd.
|
||||
* http://www.hardkernel.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
&pinctrl_0 {
|
||||
gpa0: gpa0 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpa1: gpa1 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpa2: gpa2 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpb0: gpb0 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpb1: gpb1 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpb2: gpb2 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpb3: gpb3 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpc0: gpc0 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpc3: gpc3 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpc1: gpc1 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpc2: gpc2 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpm5: gpm5 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpd1: gpd1 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpe0: gpe0 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpe1: gpe1 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpf0: gpf0 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpf1: gpf1 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpg0: gpg0 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpg1: gpg1 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpg2: gpg2 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gph0: gph0 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gph1: gph1 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpm7: gpm7 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpy0: gpy0 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpy1: gpy1 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpy2: gpy2 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpy3: gpy3 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpy4: gpy4 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpy5: gpy5 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpy6: gpy6 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpy7: gpy7 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpx0: gpx0 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&combiner>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <23 0>,
|
||||
<24 0>,
|
||||
<25 0>,
|
||||
<25 1>,
|
||||
<26 0>,
|
||||
<26 1>,
|
||||
<27 0>,
|
||||
<27 1>;
|
||||
};
|
||||
|
||||
gpx1: gpx1 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&combiner>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <28 0>,
|
||||
<28 1>,
|
||||
<29 0>,
|
||||
<29 1>,
|
||||
<30 0>,
|
||||
<30 1>,
|
||||
<31 0>,
|
||||
<31 1>;
|
||||
};
|
||||
|
||||
gpx2: gpx2 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpx3: gpx3 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl_1 {
|
||||
gpj0: gpj0 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpj1: gpj1 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpj2: gpj2 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpj3: gpj3 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpj4: gpj4 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpk0: gpk0 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpk1: gpk1 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpk2: gpk2 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpk3: gpk3 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl_2 {
|
||||
gpv0: gpv0 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpv1: gpv1 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpv2: gpv2 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpv3: gpv3 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpv4: gpv4 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl_3 {
|
||||
gpz: gpz {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
|
@ -11,6 +11,7 @@
|
|||
|
||||
/dts-v1/;
|
||||
#include "exynos5410.dtsi"
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
/ {
|
||||
model = "Samsung SMDK5410 board based on EXYNOS5410";
|
||||
compatible = "samsung,smdk5410", "samsung,exynos5410", "samsung,exynos5";
|
||||
|
|
@ -61,6 +62,46 @@
|
|||
disable-wp;
|
||||
};
|
||||
|
||||
&pinctrl_0 {
|
||||
srom_ctl: srom-ctl {
|
||||
samsung,pins = "gpy0-3", "gpy0-4", "gpy0-5",
|
||||
"gpy1-0", "gpy1-1", "gpy1-2", "gpy1-3";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
|
||||
srom_ebi: srom-ebi {
|
||||
samsung,pins = "gpy3-0", "gpy3-1", "gpy3-2", "gpy3-3",
|
||||
"gpy3-4", "gpy3-5", "gpy3-6", "gpy3-7",
|
||||
"gpy5-0", "gpy5-1", "gpy5-2", "gpy5-3",
|
||||
"gpy5-4", "gpy5-5", "gpy5-6", "gpy5-7",
|
||||
"gpy6-0", "gpy6-1", "gpy6-2", "gpy6-3",
|
||||
"gpy6-4", "gpy6-5", "gpy6-6", "gpy6-7";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&sromc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&srom_ctl>, <&srom_ebi>;
|
||||
|
||||
ethernet@3,0 {
|
||||
compatible = "smsc,lan9115";
|
||||
reg = <3 0 0x10000>;
|
||||
phy-mode = "mii";
|
||||
interrupt-parent = <&gpx0>;
|
||||
interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
|
||||
reg-io-width = <2>;
|
||||
smsc,irq-push-pull;
|
||||
smsc,force-internal-phy;
|
||||
|
||||
samsung,srom-page-mode = <1>;
|
||||
samsung,srom-timing = <9 12 1 9 1 1>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -14,6 +14,7 @@
|
|||
*/
|
||||
|
||||
#include "skeleton.dtsi"
|
||||
#include "exynos-syscon-restart.dtsi"
|
||||
#include <dt-bindings/clock/exynos5410.h>
|
||||
|
||||
/ {
|
||||
|
|
@ -21,6 +22,10 @@
|
|||
interrupt-parent = <&gic>;
|
||||
|
||||
aliases {
|
||||
pinctrl0 = &pinctrl_0;
|
||||
pinctrl1 = &pinctrl_1;
|
||||
pinctrl2 = &pinctrl_2;
|
||||
pinctrl3 = &pinctrl_3;
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
serial2 = &uart2;
|
||||
|
|
@ -97,25 +102,22 @@
|
|||
reg = <0x10000000 0x100>;
|
||||
};
|
||||
|
||||
sromc: sromc@12250000 {
|
||||
compatible = "samsung,exynos-srom";
|
||||
reg = <0x12250000 0x14>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0x04000000 0x20000
|
||||
1 0 0x05000000 0x20000
|
||||
2 0 0x06000000 0x20000
|
||||
3 0 0x07000000 0x20000>;
|
||||
};
|
||||
|
||||
pmu_system_controller: system-controller@10040000 {
|
||||
compatible = "samsung,exynos5410-pmu", "syscon";
|
||||
reg = <0x10040000 0x5000>;
|
||||
};
|
||||
|
||||
poweroff: syscon-poweroff {
|
||||
compatible = "syscon-poweroff";
|
||||
regmap = <&pmu_system_controller>;
|
||||
offset = <0x330C>; /* PS_HOLD_CONTROL */
|
||||
mask = <0x5200>; /* reset value */
|
||||
};
|
||||
|
||||
reboot: syscon-reboot {
|
||||
compatible = "syscon-reboot";
|
||||
regmap = <&pmu_system_controller>;
|
||||
offset = <0x0400>; /* SWRESET */
|
||||
mask = <0x1>;
|
||||
};
|
||||
|
||||
mct: mct@101C0000 {
|
||||
compatible = "samsung,exynos4210-mct";
|
||||
reg = <0x101C0000 0xB00>;
|
||||
|
|
@ -205,6 +207,36 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
pinctrl_0: pinctrl@13400000 {
|
||||
compatible = "samsung,exynos5410-pinctrl";
|
||||
reg = <0x13400000 0x1000>;
|
||||
interrupts = <0 45 0>;
|
||||
|
||||
wakeup-interrupt-controller {
|
||||
compatible = "samsung,exynos4210-wakeup-eint";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 32 0>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_1: pinctrl@14000000 {
|
||||
compatible = "samsung,exynos5410-pinctrl";
|
||||
reg = <0x14000000 0x1000>;
|
||||
interrupts = <0 46 0>;
|
||||
};
|
||||
|
||||
pinctrl_2: pinctrl@10d10000 {
|
||||
compatible = "samsung,exynos5410-pinctrl";
|
||||
reg = <0x10d10000 0x1000>;
|
||||
interrupts = <0 50 0>;
|
||||
};
|
||||
|
||||
pinctrl_3: pinctrl@03860000 {
|
||||
compatible = "samsung,exynos5410-pinctrl";
|
||||
reg = <0x03860000 0x1000>;
|
||||
interrupts = <0 47 0>;
|
||||
};
|
||||
|
||||
uart0: serial@12C00000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x12C00000 0x100>;
|
||||
|
|
@ -233,3 +265,5 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
#include "exynos5410-pinctrl.dtsi"
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@
|
|||
|
||||
/dts-v1/;
|
||||
#include "exynos5420.dtsi"
|
||||
#include "exynos5420-cpus.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
|
@ -47,11 +48,19 @@
|
|||
label = "SW-TACT1";
|
||||
gpios = <&gpx2 7 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_WAKEUP>;
|
||||
gpio-key,wakeup;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <&buck2_reg>;
|
||||
};
|
||||
|
||||
&cpu4 {
|
||||
cpu-supply = <&buck6_reg>;
|
||||
};
|
||||
|
||||
&usbdrd_dwc3_1 {
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
|
|
|||
126
arch/arm/boot/dts/exynos5420-cpus.dtsi
Normal file
126
arch/arm/boot/dts/exynos5420-cpus.dtsi
Normal file
|
|
@ -0,0 +1,126 @@
|
|||
/*
|
||||
* SAMSUNG EXYNOS5420 SoC cpu device tree source
|
||||
*
|
||||
* Copyright (c) 2015 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* This file provides desired ordering for Exynos5420 and Exynos5800
|
||||
* boards: CPU[0123] being the A15.
|
||||
*
|
||||
* The Exynos5420, 5422 and 5800 actually share the same CPU configuration
|
||||
* but particular boards choose different booting order.
|
||||
*
|
||||
* Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
|
||||
* booting cluster (big or LITTLE) is chosen by IROM code by reading
|
||||
* the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
|
||||
* from the LITTLE: Cortex-A7.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/ {
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x0>;
|
||||
clocks = <&clock CLK_ARM_CLK>;
|
||||
clock-frequency = <1800000000>;
|
||||
cci-control-port = <&cci_control1>;
|
||||
operating-points-v2 = <&cluster_a15_opp_table>;
|
||||
cooling-min-level = <0>;
|
||||
cooling-max-level = <11>;
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x1>;
|
||||
clock-frequency = <1800000000>;
|
||||
cci-control-port = <&cci_control1>;
|
||||
operating-points-v2 = <&cluster_a15_opp_table>;
|
||||
cooling-min-level = <0>;
|
||||
cooling-max-level = <11>;
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
};
|
||||
|
||||
cpu2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x2>;
|
||||
clock-frequency = <1800000000>;
|
||||
cci-control-port = <&cci_control1>;
|
||||
operating-points-v2 = <&cluster_a15_opp_table>;
|
||||
cooling-min-level = <0>;
|
||||
cooling-max-level = <11>;
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
};
|
||||
|
||||
cpu3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x3>;
|
||||
clock-frequency = <1800000000>;
|
||||
cci-control-port = <&cci_control1>;
|
||||
operating-points-v2 = <&cluster_a15_opp_table>;
|
||||
cooling-min-level = <0>;
|
||||
cooling-max-level = <11>;
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
};
|
||||
|
||||
cpu4: cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x100>;
|
||||
clocks = <&clock CLK_KFC_CLK>;
|
||||
clock-frequency = <1000000000>;
|
||||
cci-control-port = <&cci_control0>;
|
||||
operating-points-v2 = <&cluster_a7_opp_table>;
|
||||
cooling-min-level = <0>;
|
||||
cooling-max-level = <7>;
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
};
|
||||
|
||||
cpu5: cpu@101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x101>;
|
||||
clock-frequency = <1000000000>;
|
||||
cci-control-port = <&cci_control0>;
|
||||
operating-points-v2 = <&cluster_a7_opp_table>;
|
||||
cooling-min-level = <0>;
|
||||
cooling-max-level = <7>;
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
};
|
||||
|
||||
cpu6: cpu@102 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x102>;
|
||||
clock-frequency = <1000000000>;
|
||||
cci-control-port = <&cci_control0>;
|
||||
operating-points-v2 = <&cluster_a7_opp_table>;
|
||||
cooling-min-level = <0>;
|
||||
cooling-max-level = <7>;
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
};
|
||||
|
||||
cpu7: cpu@103 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x103>;
|
||||
clock-frequency = <1000000000>;
|
||||
cci-control-port = <&cci_control0>;
|
||||
operating-points-v2 = <&cluster_a7_opp_table>;
|
||||
cooling-min-level = <0>;
|
||||
cooling-max-level = <7>;
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -15,6 +15,7 @@
|
|||
#include <dt-bindings/clock/maxim,max77802.h>
|
||||
#include <dt-bindings/regulator/maxim,max77802.h>
|
||||
#include "exynos5420.dtsi"
|
||||
#include "exynos5420-cpus.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Google Peach Pit Rev 6+";
|
||||
|
|
@ -64,7 +65,7 @@
|
|||
label = "Power";
|
||||
gpios = <&gpx1 2 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_POWER>;
|
||||
gpio-key,wakeup;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
lid-switch {
|
||||
|
|
@ -73,7 +74,7 @@
|
|||
linux,input-type = <5>; /* EV_SW */
|
||||
linux,code = <0>; /* SW_LID */
|
||||
debounce-interval = <1>;
|
||||
gpio-key,wakeup;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -143,6 +144,14 @@
|
|||
vdd-supply = <&ldo9_reg>;
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <&buck2_reg>;
|
||||
};
|
||||
|
||||
&cpu4 {
|
||||
cpu-supply = <&buck6_reg>;
|
||||
};
|
||||
|
||||
&dp {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@
|
|||
|
||||
/dts-v1/;
|
||||
#include "exynos5420.dtsi"
|
||||
#include "exynos5420-cpus.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
|
|
@ -89,6 +90,14 @@
|
|||
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <&buck2_reg>;
|
||||
};
|
||||
|
||||
&cpu4 {
|
||||
cpu-supply = <&buck6_reg>;
|
||||
};
|
||||
|
||||
&dp {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&dp_hpd>;
|
||||
|
|
|
|||
|
|
@ -50,75 +50,121 @@
|
|||
usbdrdphy1 = &usbdrd_phy1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x0>;
|
||||
clock-frequency = <1800000000>;
|
||||
cci-control-port = <&cci_control1>;
|
||||
cluster_a15_opp_table: opp_table0 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
opp@1800000000 {
|
||||
opp-hz = /bits/ 64 <1800000000>;
|
||||
opp-microvolt = <1250000>;
|
||||
clock-latency-ns = <140000>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x1>;
|
||||
clock-frequency = <1800000000>;
|
||||
cci-control-port = <&cci_control1>;
|
||||
opp@1700000000 {
|
||||
opp-hz = /bits/ 64 <1700000000>;
|
||||
opp-microvolt = <1212500>;
|
||||
clock-latency-ns = <140000>;
|
||||
};
|
||||
|
||||
cpu2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x2>;
|
||||
clock-frequency = <1800000000>;
|
||||
cci-control-port = <&cci_control1>;
|
||||
opp@1600000000 {
|
||||
opp-hz = /bits/ 64 <1600000000>;
|
||||
opp-microvolt = <1175000>;
|
||||
clock-latency-ns = <140000>;
|
||||
};
|
||||
|
||||
cpu3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x3>;
|
||||
clock-frequency = <1800000000>;
|
||||
cci-control-port = <&cci_control1>;
|
||||
opp@1500000000 {
|
||||
opp-hz = /bits/ 64 <1500000000>;
|
||||
opp-microvolt = <1137500>;
|
||||
clock-latency-ns = <140000>;
|
||||
};
|
||||
|
||||
cpu4: cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x100>;
|
||||
clock-frequency = <1000000000>;
|
||||
cci-control-port = <&cci_control0>;
|
||||
opp@1400000000 {
|
||||
opp-hz = /bits/ 64 <1400000000>;
|
||||
opp-microvolt = <1112500>;
|
||||
clock-latency-ns = <140000>;
|
||||
};
|
||||
|
||||
cpu5: cpu@101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x101>;
|
||||
clock-frequency = <1000000000>;
|
||||
cci-control-port = <&cci_control0>;
|
||||
opp@1300000000 {
|
||||
opp-hz = /bits/ 64 <1300000000>;
|
||||
opp-microvolt = <1062500>;
|
||||
clock-latency-ns = <140000>;
|
||||
};
|
||||
|
||||
cpu6: cpu@102 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x102>;
|
||||
clock-frequency = <1000000000>;
|
||||
cci-control-port = <&cci_control0>;
|
||||
opp@1200000000 {
|
||||
opp-hz = /bits/ 64 <1200000000>;
|
||||
opp-microvolt = <1037500>;
|
||||
clock-latency-ns = <140000>;
|
||||
};
|
||||
|
||||
cpu7: cpu@103 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x103>;
|
||||
clock-frequency = <1000000000>;
|
||||
cci-control-port = <&cci_control0>;
|
||||
opp@1100000000 {
|
||||
opp-hz = /bits/ 64 <1100000000>;
|
||||
opp-microvolt = <1012500>;
|
||||
clock-latency-ns = <140000>;
|
||||
};
|
||||
opp@1000000000 {
|
||||
opp-hz = /bits/ 64 <1000000000>;
|
||||
opp-microvolt = < 987500>;
|
||||
clock-latency-ns = <140000>;
|
||||
};
|
||||
opp@900000000 {
|
||||
opp-hz = /bits/ 64 <900000000>;
|
||||
opp-microvolt = < 962500>;
|
||||
clock-latency-ns = <140000>;
|
||||
};
|
||||
opp@800000000 {
|
||||
opp-hz = /bits/ 64 <800000000>;
|
||||
opp-microvolt = < 937500>;
|
||||
clock-latency-ns = <140000>;
|
||||
};
|
||||
opp@700000000 {
|
||||
opp-hz = /bits/ 64 <700000000>;
|
||||
opp-microvolt = < 912500>;
|
||||
clock-latency-ns = <140000>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster_a7_opp_table: opp_table1 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
opp@1300000000 {
|
||||
opp-hz = /bits/ 64 <1300000000>;
|
||||
opp-microvolt = <1275000>;
|
||||
clock-latency-ns = <140000>;
|
||||
};
|
||||
opp@1200000000 {
|
||||
opp-hz = /bits/ 64 <1200000000>;
|
||||
opp-microvolt = <1212500>;
|
||||
clock-latency-ns = <140000>;
|
||||
};
|
||||
opp@1100000000 {
|
||||
opp-hz = /bits/ 64 <1100000000>;
|
||||
opp-microvolt = <1162500>;
|
||||
clock-latency-ns = <140000>;
|
||||
};
|
||||
opp@1000000000 {
|
||||
opp-hz = /bits/ 64 <1000000000>;
|
||||
opp-microvolt = <1112500>;
|
||||
clock-latency-ns = <140000>;
|
||||
};
|
||||
opp@900000000 {
|
||||
opp-hz = /bits/ 64 <900000000>;
|
||||
opp-microvolt = <1062500>;
|
||||
clock-latency-ns = <140000>;
|
||||
};
|
||||
opp@800000000 {
|
||||
opp-hz = /bits/ 64 <800000000>;
|
||||
opp-microvolt = <1025000>;
|
||||
clock-latency-ns = <140000>;
|
||||
};
|
||||
opp@700000000 {
|
||||
opp-hz = /bits/ 64 <700000000>;
|
||||
opp-microvolt = <975000>;
|
||||
clock-latency-ns = <140000>;
|
||||
};
|
||||
opp@600000000 {
|
||||
opp-hz = /bits/ 64 <600000000>;
|
||||
opp-microvolt = <937500>;
|
||||
clock-latency-ns = <140000>;
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* The 'cpus' node is not present here but instead it is provided
|
||||
* by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi.
|
||||
*/
|
||||
|
||||
cci: cci@10d20000 {
|
||||
compatible = "arm,cci-400";
|
||||
#address-cells = <1>;
|
||||
|
|
@ -252,8 +298,10 @@
|
|||
compatible = "samsung,exynos4210-pd";
|
||||
reg = <0x10044000 0x20>;
|
||||
#power-domain-cells = <0>;
|
||||
clocks = <&clock CLK_GSCL0>, <&clock CLK_GSCL1>;
|
||||
clock-names = "asb0", "asb1";
|
||||
clocks = <&clock CLK_FIN_PLL>,
|
||||
<&clock CLK_MOUT_USER_ACLK300_GSCL>,
|
||||
<&clock CLK_GSCL0>, <&clock CLK_GSCL1>;
|
||||
clock-names = "oscclk", "clk0", "asb0", "asb1";
|
||||
};
|
||||
|
||||
isp_pd: power-domain@10044020 {
|
||||
|
|
@ -327,7 +375,7 @@
|
|||
amba {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "arm,amba-bus";
|
||||
compatible = "simple-bus";
|
||||
interrupt-parent = <&gic>;
|
||||
ranges;
|
||||
|
||||
|
|
@ -859,7 +907,7 @@
|
|||
|
||||
sss: sss@10830000 {
|
||||
compatible = "samsung,exynos4210-secss";
|
||||
reg = <0x10830000 0x10000>;
|
||||
reg = <0x10830000 0x300>;
|
||||
interrupts = <0 112 0>;
|
||||
clocks = <&clock CLK_SSS>;
|
||||
clock-names = "secss";
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@
|
|||
thermal-zones {
|
||||
cpu0_thermal: cpu0-thermal {
|
||||
thermal-sensors = <&tmu_cpu0 0>;
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <0>;
|
||||
trips {
|
||||
cpu_alert0: cpu-alert-0 {
|
||||
|
|
@ -39,6 +39,23 @@
|
|||
hysteresis = <0>; /* millicelsius */
|
||||
type = "critical";
|
||||
};
|
||||
/*
|
||||
* Exyunos542x support only 4 trip-points
|
||||
* so for these polling mode is required.
|
||||
* Start polling at temperature level of last
|
||||
* interrupt-driven trip: cpu_alert2
|
||||
*/
|
||||
cpu_alert3: cpu-alert-3 {
|
||||
temperature = <70000>; /* millicelsius */
|
||||
hysteresis = <10000>; /* millicelsius */
|
||||
type = "passive";
|
||||
};
|
||||
cpu_alert4: cpu-alert-4 {
|
||||
temperature = <85000>; /* millicelsius */
|
||||
hysteresis = <10000>; /* millicelsius */
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
};
|
||||
cooling-maps {
|
||||
map0 {
|
||||
|
|
@ -53,6 +70,33 @@
|
|||
trip = <&cpu_alert2>;
|
||||
cooling-device = <&fan0 2 3>;
|
||||
};
|
||||
/*
|
||||
* When reaching cpu_alert3, reduce CPU
|
||||
* by 2 steps. On Exynos5422/5800 that would
|
||||
* be: 1500 MHz and 1100 MHz.
|
||||
*/
|
||||
map3 {
|
||||
trip = <&cpu_alert3>;
|
||||
cooling-device = <&cpu0 0 2>;
|
||||
};
|
||||
map4 {
|
||||
trip = <&cpu_alert3>;
|
||||
cooling-device = <&cpu4 0 2>;
|
||||
};
|
||||
|
||||
/*
|
||||
* When reaching cpu_alert4, reduce CPU
|
||||
* further, down to 600 MHz (11 steps for big,
|
||||
* 7 steps for LITTLE).
|
||||
*/
|
||||
map5 {
|
||||
trip = <&cpu_alert4>;
|
||||
cooling-device = <&cpu0 3 7>;
|
||||
};
|
||||
map6 {
|
||||
trip = <&cpu_alert4>;
|
||||
cooling-device = <&cpu4 3 11>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -4,78 +4,122 @@
|
|||
* Copyright (c) 2015 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* The only difference between EXYNOS5422 and EXYNOS5800 is cpu ordering. The
|
||||
* EXYNOS5422 is booting from Cortex-A7 core while the EXYNOS5800 is booting
|
||||
* from Cortex-A15 core.
|
||||
* This file provides desired ordering for Exynos5422: CPU[0123] being the A7.
|
||||
*
|
||||
* EXYNOS5422 based board files can include this file to provide cpu ordering
|
||||
* which could boot a cortex-a7 from cpu0.
|
||||
* The Exynos5420, 5422 and 5800 actually share the same CPU configuration
|
||||
* but particular boards choose different booting order.
|
||||
*
|
||||
* Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
|
||||
* booting cluster (big or LITTLE) is chosen by IROM code by reading
|
||||
* the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
|
||||
* from the LITTLE: Cortex-A7.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
&cpu0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x100>;
|
||||
clock-frequency = <1000000000>;
|
||||
cci-control-port = <&cci_control0>;
|
||||
};
|
||||
/ {
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
&cpu1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x101>;
|
||||
clock-frequency = <1000000000>;
|
||||
cci-control-port = <&cci_control0>;
|
||||
};
|
||||
cpu0: cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x100>;
|
||||
clocks = <&clock CLK_KFC_CLK>;
|
||||
clock-frequency = <1000000000>;
|
||||
cci-control-port = <&cci_control0>;
|
||||
operating-points-v2 = <&cluster_a7_opp_table>;
|
||||
cooling-min-level = <0>;
|
||||
cooling-max-level = <11>;
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
};
|
||||
|
||||
&cpu2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x102>;
|
||||
clock-frequency = <1000000000>;
|
||||
cci-control-port = <&cci_control0>;
|
||||
};
|
||||
cpu1: cpu@101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x101>;
|
||||
clock-frequency = <1000000000>;
|
||||
cci-control-port = <&cci_control0>;
|
||||
operating-points-v2 = <&cluster_a7_opp_table>;
|
||||
cooling-min-level = <0>;
|
||||
cooling-max-level = <11>;
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
};
|
||||
|
||||
&cpu3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x103>;
|
||||
clock-frequency = <1000000000>;
|
||||
cci-control-port = <&cci_control0>;
|
||||
};
|
||||
cpu2: cpu@102 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x102>;
|
||||
clock-frequency = <1000000000>;
|
||||
cci-control-port = <&cci_control0>;
|
||||
operating-points-v2 = <&cluster_a7_opp_table>;
|
||||
cooling-min-level = <0>;
|
||||
cooling-max-level = <11>;
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
};
|
||||
|
||||
&cpu4 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x0>;
|
||||
clock-frequency = <1800000000>;
|
||||
cci-control-port = <&cci_control1>;
|
||||
};
|
||||
cpu3: cpu@103 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x103>;
|
||||
clock-frequency = <1000000000>;
|
||||
cci-control-port = <&cci_control0>;
|
||||
operating-points-v2 = <&cluster_a7_opp_table>;
|
||||
cooling-min-level = <0>;
|
||||
cooling-max-level = <11>;
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
};
|
||||
|
||||
&cpu5 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x1>;
|
||||
clock-frequency = <1800000000>;
|
||||
cci-control-port = <&cci_control1>;
|
||||
};
|
||||
cpu4: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
clocks = <&clock CLK_ARM_CLK>;
|
||||
reg = <0x0>;
|
||||
clock-frequency = <1800000000>;
|
||||
cci-control-port = <&cci_control1>;
|
||||
operating-points-v2 = <&cluster_a15_opp_table>;
|
||||
cooling-min-level = <0>;
|
||||
cooling-max-level = <15>;
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
};
|
||||
|
||||
&cpu6 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x2>;
|
||||
clock-frequency = <1800000000>;
|
||||
cci-control-port = <&cci_control1>;
|
||||
};
|
||||
cpu5: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x1>;
|
||||
clock-frequency = <1800000000>;
|
||||
cci-control-port = <&cci_control1>;
|
||||
operating-points-v2 = <&cluster_a15_opp_table>;
|
||||
cooling-min-level = <0>;
|
||||
cooling-max-level = <15>;
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
};
|
||||
|
||||
&cpu7 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x3>;
|
||||
clock-frequency = <1800000000>;
|
||||
cci-control-port = <&cci_control1>;
|
||||
cpu6: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x2>;
|
||||
clock-frequency = <1800000000>;
|
||||
cci-control-port = <&cci_control1>;
|
||||
operating-points-v2 = <&cluster_a15_opp_table>;
|
||||
cooling-min-level = <0>;
|
||||
cooling-max-level = <15>;
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
};
|
||||
|
||||
cpu7: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x3>;
|
||||
clock-frequency = <1800000000>;
|
||||
cci-control-port = <&cci_control1>;
|
||||
operating-points-v2 = <&cluster_a15_opp_table>;
|
||||
cooling-min-level = <0>;
|
||||
cooling-max-level = <15>;
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -67,6 +67,14 @@
|
|||
<19200000>;
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <&buck6_reg>;
|
||||
};
|
||||
|
||||
&cpu4 {
|
||||
cpu-supply = <&buck2_reg>;
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
status = "okay";
|
||||
hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>;
|
||||
|
|
|
|||
|
|
@ -200,7 +200,7 @@
|
|||
amba {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "arm,amba-bus";
|
||||
compatible = "simple-bus";
|
||||
interrupt-parent = <&gic>;
|
||||
ranges;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -15,6 +15,7 @@
|
|||
#include <dt-bindings/clock/maxim,max77802.h>
|
||||
#include <dt-bindings/regulator/maxim,max77802.h>
|
||||
#include "exynos5800.dtsi"
|
||||
#include "exynos5420-cpus.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Google Peach Pi Rev 10+";
|
||||
|
|
@ -63,7 +64,7 @@
|
|||
label = "Power";
|
||||
gpios = <&gpx1 2 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_POWER>;
|
||||
gpio-key,wakeup;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
lid-switch {
|
||||
|
|
@ -72,7 +73,7 @@
|
|||
linux,input-type = <5>; /* EV_SW */
|
||||
linux,code = <0>; /* SW_LID */
|
||||
debounce-interval = <1>;
|
||||
gpio-key,wakeup;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
};
|
||||
|
|
@ -143,6 +144,14 @@
|
|||
vdd-supply = <&ldo9_reg>;
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <&buck2_reg>;
|
||||
};
|
||||
|
||||
&cpu4 {
|
||||
cpu-supply = <&buck6_reg>;
|
||||
};
|
||||
|
||||
&dp {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user