ARM: socfpga: support suspend to ram
Add code that requests that the sdr controller go into self-refresh mode. This code is run from ocram. Suspend-to-RAM and EDAC support are mutually exclusive on SOCFPGA. If the EDAC is enabled, it will prevent the platform from going into suspend. Example of how to request to suspend to ram: $ echo enabled > \ /sys/devices/soc/ffc02000.serial0/tty/ttyS0/power/wakeup $ echo -n mem > /sys/power/state Signed-off-by: Alan Tull <atull@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Kevin Hilman <khilman@linaro.org>
This commit is contained in:
Alan Tull
Kevin Hilman
parent
45be0cdb53
commit
44fd8c7d40
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@ -1,4 +1,4 @@
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config ARCH_SOCFPGA
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menuconfig ARCH_SOCFPGA
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bool "Altera SOCFPGA family" if ARCH_MULTI_V7
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select ARCH_SUPPORTS_BIG_ENDIAN
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select ARM_AMBA
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@ -9,3 +9,11 @@ config ARCH_SOCFPGA
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select HAVE_ARM_SCU
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select HAVE_ARM_TWD if SMP
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select MFD_SYSCON
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if ARCH_SOCFPGA
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config SOCFPGA_SUSPEND
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bool "Suspend to RAM on SOCFPGA"
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help
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Select this if you want to enable Suspend-to-RAM on SOCFPGA
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platforms.
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endif
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@ -4,3 +4,4 @@
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obj-y := socfpga.o
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obj-$(CONFIG_SMP) += headsmp.o platsmp.o
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obj-$(CONFIG_SOCFPGA_SUSPEND) += pm.o self-refresh.o
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@ -1,6 +1,6 @@
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/*
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* Copyright 2012 Pavel Machek <pavel@denx.de>
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* Copyright (C) 2012 Altera Corporation
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* Copyright (C) 2012-2015 Altera Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -40,6 +40,10 @@ extern void socfpga_sysmgr_init(void);
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extern void __iomem *sys_manager_base_addr;
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extern void __iomem *rst_manager_base_addr;
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extern void __iomem *sdr_ctl_base_addr;
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u32 socfpga_sdram_self_refresh(u32 sdr_base);
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extern unsigned int socfpga_sdram_self_refresh_sz;
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extern char secondary_trampoline, secondary_trampoline_end;
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@ -0,0 +1,149 @@
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/*
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* arch/arm/mach-socfpga/pm.c
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*
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* Copyright (C) 2014-2015 Altera Corporation. All rights reserved.
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*
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* with code from pm-imx6.c
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* Copyright 2011-2014 Freescale Semiconductor, Inc.
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* Copyright 2011 Linaro Ltd.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/bitops.h>
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#include <linux/genalloc.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/of_platform.h>
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#include <linux/suspend.h>
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#include <asm/suspend.h>
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#include <asm/fncpy.h>
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#include "core.h"
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/* Pointer to function copied to ocram */
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static u32 (*socfpga_sdram_self_refresh_in_ocram)(u32 sdr_base);
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static int socfpga_setup_ocram_self_refresh(void)
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{
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struct platform_device *pdev;
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phys_addr_t ocram_pbase;
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struct device_node *np;
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struct gen_pool *ocram_pool;
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unsigned long ocram_base;
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void __iomem *suspend_ocram_base;
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int ret = 0;
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np = of_find_compatible_node(NULL, NULL, "mmio-sram");
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if (!np) {
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pr_err("%s: Unable to find mmio-sram in dtb\n", __func__);
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return -ENODEV;
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}
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pdev = of_find_device_by_node(np);
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if (!pdev) {
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pr_warn("%s: failed to find ocram device!\n", __func__);
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ret = -ENODEV;
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goto put_node;
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}
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ocram_pool = dev_get_gen_pool(&pdev->dev);
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if (!ocram_pool) {
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pr_warn("%s: ocram pool unavailable!\n", __func__);
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ret = -ENODEV;
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goto put_node;
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}
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ocram_base = gen_pool_alloc(ocram_pool, socfpga_sdram_self_refresh_sz);
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if (!ocram_base) {
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pr_warn("%s: unable to alloc ocram!\n", __func__);
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ret = -ENOMEM;
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goto put_node;
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}
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ocram_pbase = gen_pool_virt_to_phys(ocram_pool, ocram_base);
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suspend_ocram_base = __arm_ioremap_exec(ocram_pbase,
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socfpga_sdram_self_refresh_sz,
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false);
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if (!suspend_ocram_base) {
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pr_warn("%s: __arm_ioremap_exec failed!\n", __func__);
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ret = -ENOMEM;
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goto put_node;
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}
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/* Copy the code that puts DDR in self refresh to ocram */
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socfpga_sdram_self_refresh_in_ocram =
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(void *)fncpy(suspend_ocram_base,
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&socfpga_sdram_self_refresh,
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socfpga_sdram_self_refresh_sz);
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WARN(!socfpga_sdram_self_refresh_in_ocram,
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"could not copy function to ocram");
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if (!socfpga_sdram_self_refresh_in_ocram)
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ret = -EFAULT;
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put_node:
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of_node_put(np);
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return ret;
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}
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static int socfpga_pm_suspend(unsigned long arg)
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{
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u32 ret;
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if (!sdr_ctl_base_addr)
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return -EFAULT;
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ret = socfpga_sdram_self_refresh_in_ocram((u32)sdr_ctl_base_addr);
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pr_debug("%s self-refresh loops request=%d exit=%d\n", __func__,
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ret & 0xffff, (ret >> 16) & 0xffff);
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return 0;
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}
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static int socfpga_pm_enter(suspend_state_t state)
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{
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switch (state) {
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case PM_SUSPEND_STANDBY:
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case PM_SUSPEND_MEM:
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outer_disable();
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cpu_suspend(0, socfpga_pm_suspend);
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outer_resume();
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static const struct platform_suspend_ops socfpga_pm_ops = {
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.valid = suspend_valid_only_mem,
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.enter = socfpga_pm_enter,
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};
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static int __init socfpga_pm_init(void)
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{
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int ret;
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ret = socfpga_setup_ocram_self_refresh();
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if (ret)
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return ret;
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suspend_set_ops(&socfpga_pm_ops);
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pr_info("SoCFPGA initialized for DDR self-refresh during suspend.\n");
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return 0;
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}
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arch_initcall(socfpga_pm_init);
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@ -0,0 +1,136 @@
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/*
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* Copyright (C) 2014-2015 Altera Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#define MAX_LOOP_COUNT 1000
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/* Register offset */
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#define SDR_CTRLGRP_LOWPWREQ_ADDR 0x54
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#define SDR_CTRLGRP_LOWPWRACK_ADDR 0x58
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/* Bitfield positions */
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#define SELFRSHREQ_POS 3
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#define SELFRSHREQ_MASK 0x8
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#define SELFRFSHACK_POS 1
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#define SELFRFSHACK_MASK 0x2
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/*
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* This code assumes that when the bootloader configured
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* the sdram controller for the DDR on the board it
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* configured the following fields depending on the DDR
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* vendor/configuration:
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*
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* sdr.ctrlcfg.lowpwreq.selfrfshmask
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* sdr.ctrlcfg.lowpwrtiming.clkdisablecycles
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* sdr.ctrlcfg.dramtiming4.selfrfshexit
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*/
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.arch armv7-a
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.text
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.align 3
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/*
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* socfpga_sdram_self_refresh
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*
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* r0 : sdr_ctl_base_addr
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* r1 : temp storage of return value
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* r2 : temp storage of register values
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* r3 : loop counter
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*
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* return value: lower 16 bits: loop count going into self refresh
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* upper 16 bits: loop count exiting self refresh
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*/
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ENTRY(socfpga_sdram_self_refresh)
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/* Enable dynamic clock gating in the Power Control Register. */
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mrc p15, 0, r2, c15, c0, 0
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orr r2, r2, #1
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mcr p15, 0, r2, c15, c0, 0
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/* Enable self refresh: set sdr.ctrlgrp.lowpwreq.selfrshreq = 1 */
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ldr r2, [r0, #SDR_CTRLGRP_LOWPWREQ_ADDR]
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orr r2, r2, #SELFRSHREQ_MASK
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str r2, [r0, #SDR_CTRLGRP_LOWPWREQ_ADDR]
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/* Poll until sdr.ctrlgrp.lowpwrack.selfrfshack == 1 or hit max loops */
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mov r3, #0
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while_ack_0:
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ldr r2, [r0, #SDR_CTRLGRP_LOWPWRACK_ADDR]
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and r2, r2, #SELFRFSHACK_MASK
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cmp r2, #SELFRFSHACK_MASK
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beq ack_1
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add r3, #1
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cmp r3, #MAX_LOOP_COUNT
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bne while_ack_0
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ack_1:
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mov r1, r3
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/*
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* Execute an ISB instruction to ensure that all of the
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* CP15 register changes have been committed.
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*/
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isb
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/*
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* Execute a barrier instruction to ensure that all cache,
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* TLB and branch predictor maintenance operations issued
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* by any CPU in the cluster have completed.
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*/
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dsb
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dmb
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wfi
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/* Disable self-refresh: set sdr.ctrlgrp.lowpwreq.selfrshreq = 0 */
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ldr r2, [r0, #SDR_CTRLGRP_LOWPWREQ_ADDR]
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bic r2, r2, #SELFRSHREQ_MASK
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str r2, [r0, #SDR_CTRLGRP_LOWPWREQ_ADDR]
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/* Poll until sdr.ctrlgrp.lowpwrack.selfrfshack == 0 or hit max loops */
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mov r3, #0
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while_ack_1:
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ldr r2, [r0, #SDR_CTRLGRP_LOWPWRACK_ADDR]
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and r2, r2, #SELFRFSHACK_MASK
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cmp r2, #SELFRFSHACK_MASK
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bne ack_0
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add r3, #1
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cmp r3, #MAX_LOOP_COUNT
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bne while_ack_1
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ack_0:
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/*
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* Prepare return value:
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* Shift loop count for exiting self refresh into upper 16 bits.
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* Leave loop count for requesting self refresh in lower 16 bits.
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*/
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mov r3, r3, lsl #16
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add r1, r1, r3
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/* Disable dynamic clock gating in the Power Control Register. */
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mrc p15, 0, r2, c15, c0, 0
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bic r2, r2, #1
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mcr p15, 0, r2, c15, c0, 0
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mov r0, r1 @ return value
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bx lr @ return
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ENDPROC(socfpga_sdram_self_refresh)
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ENTRY(socfpga_sdram_self_refresh_sz)
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.word . - socfpga_sdram_self_refresh
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@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2012 Altera Corporation
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* Copyright (C) 2012-2015 Altera Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -29,6 +29,7 @@
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void __iomem *sys_manager_base_addr;
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void __iomem *rst_manager_base_addr;
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void __iomem *sdr_ctl_base_addr;
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unsigned long socfpga_cpu1start_addr;
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void __init socfpga_sysmgr_init(void)
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@ -49,6 +50,9 @@ void __init socfpga_sysmgr_init(void)
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np = of_find_compatible_node(NULL, NULL, "altr,rst-mgr");
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rst_manager_base_addr = of_iomap(np, 0);
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np = of_find_compatible_node(NULL, NULL, "altr,sdr-ctl");
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sdr_ctl_base_addr = of_iomap(np, 0);
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}
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static void __init socfpga_init_irq(void)
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