arm64: tegra: Add display support on Tegra194
Tegra194 contains a display architecture very similar to that found on the Tegra186. One notable exception is that DSI is no longer a supported output. Instead there are four display controllers and four SORs (with a DPAUX associated to each of them) that can drive HDMI or DP. Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Thierry Reding
parent
73b551ba8f
commit
3db6d3ba08
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@ -4,6 +4,7 @@
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/mailbox/tegra186-hsp.h>
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#include <dt-bindings/reset/tegra194-reset.h>
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#include <dt-bindings/power/tegra194-powergate.h>
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/ {
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compatible = "nvidia,tegra194";
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@ -418,6 +419,340 @@
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<0x0c3a0000 0x10000>;
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reg-names = "pmc", "wake", "aotag", "scratch", "misc";
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};
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host1x@13e00000 {
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compatible = "nvidia,tegra194-host1x", "simple-bus";
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reg = <0x13e00000 0x10000>,
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<0x13e10000 0x10000>;
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reg-names = "hypervisor", "vm";
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interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA194_CLK_HOST1X>;
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clock-names = "host1x";
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resets = <&bpmp TEGRA194_RESET_HOST1X>;
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reset-names = "host1x";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x15000000 0x15000000 0x01000000>;
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display-hub@15200000 {
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compatible = "nvidia,tegra194-display", "simple-bus";
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resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>,
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<&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>,
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<&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>,
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<&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>,
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<&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>,
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<&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>,
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<&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>;
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reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
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"wgrp3", "wgrp4", "wgrp5";
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clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>,
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<&bpmp TEGRA194_CLK_NVDISPLAYHUB>;
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clock-names = "disp", "hub";
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status = "disabled";
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power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x15200000 0x15200000 0x40000>;
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display@15200000 {
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compatible = "nvidia,tegra194-dc";
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reg = <0x15200000 0x10000>;
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interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>;
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clock-names = "dc";
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resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>;
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reset-names = "dc";
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power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
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nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
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nvidia,head = <0>;
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};
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display@15210000 {
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compatible = "nvidia,tegra194-dc";
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reg = <0x15210000 0x10000>;
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interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>;
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clock-names = "dc";
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resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>;
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reset-names = "dc";
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power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>;
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nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
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nvidia,head = <1>;
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};
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display@15220000 {
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compatible = "nvidia,tegra194-dc";
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reg = <0x15220000 0x10000>;
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interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>;
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clock-names = "dc";
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resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>;
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reset-names = "dc";
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power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
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nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
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nvidia,head = <2>;
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};
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display@15230000 {
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compatible = "nvidia,tegra194-dc";
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reg = <0x15230000 0x10000>;
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interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>;
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clock-names = "dc";
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resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>;
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reset-names = "dc";
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power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
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nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
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nvidia,head = <3>;
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};
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};
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dpaux0: dpaux@155c0000 {
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compatible = "nvidia,tegra194-dpaux";
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reg = <0x155c0000 0x10000>;
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interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA194_CLK_DPAUX>,
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<&bpmp TEGRA194_CLK_PLLDP>;
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clock-names = "dpaux", "parent";
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resets = <&bpmp TEGRA194_RESET_DPAUX>;
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reset-names = "dpaux";
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status = "disabled";
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power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
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state_dpaux0_aux: pinmux-aux {
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groups = "dpaux-io";
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function = "aux";
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};
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state_dpaux0_i2c: pinmux-i2c {
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groups = "dpaux-io";
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function = "i2c";
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};
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state_dpaux0_off: pinmux-off {
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groups = "dpaux-io";
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function = "off";
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};
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i2c-bus {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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dpaux1: dpaux@155d0000 {
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compatible = "nvidia,tegra194-dpaux";
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reg = <0x155d0000 0x10000>;
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interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA194_CLK_DPAUX1>,
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<&bpmp TEGRA194_CLK_PLLDP>;
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clock-names = "dpaux", "parent";
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resets = <&bpmp TEGRA194_RESET_DPAUX1>;
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reset-names = "dpaux";
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status = "disabled";
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power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
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state_dpaux1_aux: pinmux-aux {
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groups = "dpaux-io";
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function = "aux";
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};
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state_dpaux1_i2c: pinmux-i2c {
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groups = "dpaux-io";
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function = "i2c";
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};
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state_dpaux1_off: pinmux-off {
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groups = "dpaux-io";
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function = "off";
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};
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i2c-bus {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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dpaux2: dpaux@155e0000 {
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compatible = "nvidia,tegra194-dpaux";
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reg = <0x155e0000 0x10000>;
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interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA194_CLK_DPAUX2>,
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<&bpmp TEGRA194_CLK_PLLDP>;
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clock-names = "dpaux", "parent";
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resets = <&bpmp TEGRA194_RESET_DPAUX2>;
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reset-names = "dpaux";
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status = "disabled";
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power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
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state_dpaux2_aux: pinmux-aux {
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groups = "dpaux-io";
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function = "aux";
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};
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state_dpaux2_i2c: pinmux-i2c {
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groups = "dpaux-io";
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function = "i2c";
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};
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state_dpaux2_off: pinmux-off {
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groups = "dpaux-io";
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function = "off";
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};
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i2c-bus {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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dpaux3: dpaux@155f0000 {
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compatible = "nvidia,tegra194-dpaux";
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reg = <0x155f0000 0x10000>;
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interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA194_CLK_DPAUX3>,
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<&bpmp TEGRA194_CLK_PLLDP>;
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clock-names = "dpaux", "parent";
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resets = <&bpmp TEGRA194_RESET_DPAUX3>;
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reset-names = "dpaux";
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status = "disabled";
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power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
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state_dpaux3_aux: pinmux-aux {
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groups = "dpaux-io";
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function = "aux";
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};
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state_dpaux3_i2c: pinmux-i2c {
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groups = "dpaux-io";
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function = "i2c";
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};
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state_dpaux3_off: pinmux-off {
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groups = "dpaux-io";
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function = "off";
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};
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i2c-bus {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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sor0: sor@15b00000 {
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compatible = "nvidia,tegra194-sor";
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reg = <0x15b00000 0x40000>;
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interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA194_CLK_SOR0_REF>,
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<&bpmp TEGRA194_CLK_SOR0_OUT>,
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<&bpmp TEGRA194_CLK_PLLD>,
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<&bpmp TEGRA194_CLK_PLLDP>,
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<&bpmp TEGRA194_CLK_SOR_SAFE>,
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<&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>;
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clock-names = "sor", "out", "parent", "dp", "safe",
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"pad";
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resets = <&bpmp TEGRA194_RESET_SOR0>;
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reset-names = "sor";
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pinctrl-0 = <&state_dpaux0_aux>;
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pinctrl-1 = <&state_dpaux0_i2c>;
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pinctrl-2 = <&state_dpaux0_off>;
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pinctrl-names = "aux", "i2c", "off";
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status = "disabled";
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power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
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nvidia,interface = <0>;
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};
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sor1: sor@15b40000 {
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compatible = "nvidia,tegra194-sor";
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reg = <0x155c0000 0x40000>;
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interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA194_CLK_SOR1_REF>,
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<&bpmp TEGRA194_CLK_SOR1_OUT>,
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<&bpmp TEGRA194_CLK_PLLD2>,
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<&bpmp TEGRA194_CLK_PLLDP>,
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<&bpmp TEGRA194_CLK_SOR_SAFE>,
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<&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>;
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clock-names = "sor", "out", "parent", "dp", "safe",
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"pad";
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resets = <&bpmp TEGRA194_RESET_SOR1>;
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reset-names = "sor";
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pinctrl-0 = <&state_dpaux1_aux>;
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pinctrl-1 = <&state_dpaux1_i2c>;
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pinctrl-2 = <&state_dpaux1_off>;
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pinctrl-names = "aux", "i2c", "off";
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status = "disabled";
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power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
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nvidia,interface = <1>;
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};
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sor2: sor@15b80000 {
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compatible = "nvidia,tegra194-sor";
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reg = <0x15b80000 0x40000>;
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interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA194_CLK_SOR2_REF>,
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<&bpmp TEGRA194_CLK_SOR2_OUT>,
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<&bpmp TEGRA194_CLK_PLLD3>,
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<&bpmp TEGRA194_CLK_PLLDP>,
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<&bpmp TEGRA194_CLK_SOR_SAFE>,
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<&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>;
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clock-names = "sor", "out", "parent", "dp", "safe",
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"pad";
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resets = <&bpmp TEGRA194_RESET_SOR2>;
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reset-names = "sor";
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pinctrl-0 = <&state_dpaux2_aux>;
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pinctrl-1 = <&state_dpaux2_i2c>;
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pinctrl-2 = <&state_dpaux2_off>;
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pinctrl-names = "aux", "i2c", "off";
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status = "disabled";
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power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
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nvidia,interface = <2>;
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};
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sor3: sor@15bc0000 {
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compatible = "nvidia,tegra194-sor";
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reg = <0x15bc0000 0x40000>;
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interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA194_CLK_SOR3_REF>,
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<&bpmp TEGRA194_CLK_SOR3_OUT>,
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<&bpmp TEGRA194_CLK_PLLD4>,
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<&bpmp TEGRA194_CLK_PLLDP>,
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<&bpmp TEGRA194_CLK_SOR_SAFE>,
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<&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>;
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clock-names = "sor", "out", "parent", "dp", "safe",
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"pad";
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resets = <&bpmp TEGRA194_RESET_SOR3>;
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reset-names = "sor";
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pinctrl-0 = <&state_dpaux3_aux>;
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pinctrl-1 = <&state_dpaux3_i2c>;
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pinctrl-2 = <&state_dpaux3_off>;
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pinctrl-names = "aux", "i2c", "off";
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status = "disabled";
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power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
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nvidia,interface = <3>;
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};
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};
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};
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sysram@40000000 {
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