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Merge remote-tracking branch 'origin/display/nwl-dsi' into display/next
* origin/display/nwl-dsi: (14 commits) drm/bridge: nwl-dsi Correct the DSI init sequence drm/bridge: nwl-dsi: Fix find_panel_or_bridge drm/bridge: nwl-dsi: Add support for 8QM and 8QXP drm/bridge: nwl-dsi: Add support for component framework phy: imx8-mipi-dphy: Add support for 8QM and 8QXP ...
This commit is contained in:
commit
356e74dcf7
161
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml
Normal file
161
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml
Normal file
|
@ -0,0 +1,161 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/bridge/nwl-dsi.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
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||||
|
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title: Northwest Logic MIPI-DSI controller on i.MX SoCs
|
||||
|
||||
maintainers:
|
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- Guido Gúnther <agx@sigxcpu.org>
|
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- Robert Chiras <robert.chiras@nxp.com>
|
||||
|
||||
description: |
|
||||
NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi bridge for
|
||||
the SOCs NWL MIPI-DSI host controller.
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||||
|
||||
properties:
|
||||
compatible:
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const: fsl,imx8mq-nwl-dsi
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
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- description: DSI core clock
|
||||
- description: RX_ESC clock (used in escape mode)
|
||||
- description: TX_ESC clock (used in escape mode)
|
||||
- description: PHY_REF clock
|
||||
- description: VIDEO_PLL clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: core
|
||||
- const: rx_esc
|
||||
- const: tx_esc
|
||||
- const: phy_ref
|
||||
- const: video_pll
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||||
|
||||
mux-controls:
|
||||
description:
|
||||
mux controller node to use for operating the input mux
|
||||
|
||||
phys:
|
||||
maxItems: 1
|
||||
description:
|
||||
A phandle to the phy module representing the DPHY
|
||||
|
||||
phy-names:
|
||||
items:
|
||||
- const: dphy
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
description:
|
||||
A phandle to the power domain
|
||||
|
||||
resets:
|
||||
description:
|
||||
phandles to the reset controller
|
||||
items:
|
||||
- description: dsi byte reset line
|
||||
- description: dsi dpi reset line
|
||||
- description: dsi esc reset line
|
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- description: dsi pclk reset line
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: byte
|
||||
- const: dpi
|
||||
- const: esc
|
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- const: pclk
|
||||
|
||||
ports:
|
||||
type: object
|
||||
description:
|
||||
A node containing DSI input & output port nodes with endpoint
|
||||
definitions as documented in
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||||
Documentation/devicetree/bindings/graph.txt.
|
||||
|
||||
port@0:
|
||||
type: object
|
||||
description:
|
||||
Input port node to receive pixel data from the
|
||||
display controller
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|
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port@1:
|
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type: object
|
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description:
|
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DSI output port node to the panel or the next bridge
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in the chain
|
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|
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fsl,clock-drop-level:
|
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description:
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Specifies the level at wich the crtc_clock should be dropped
|
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|
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patternProperties:
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"^panel@[0-9]+$": true
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|
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required:
|
||||
- clock-names
|
||||
- clocks
|
||||
- compatible
|
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- interrupts
|
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- mux-controls
|
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- phy-names
|
||||
- phys
|
||||
- ports
|
||||
- reg
|
||||
- reset-names
|
||||
- resets
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
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mipi_dsi: mipi_dsi@30a00000 {
|
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx8mq-nwl-dsi";
|
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reg = <0x30A00000 0x300>;
|
||||
clocks = <&clk 163>, <&clk 244>, <&clk 245>, <&clk 164>;
|
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clock-names = "core", "rx_esc", "tx_esc", "phy_ref";
|
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interrupts = <0 34 4>;
|
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mux-controls = <&mux 0>;
|
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power-domains = <&pgc_mipi>;
|
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resets = <&src 0>, <&src 1>, <&src 2>, <&src 3>;
|
||||
reset-names = "byte", "dpi", "esc", "pclk";
|
||||
phys = <&dphy>;
|
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phy-names = "dphy";
|
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|
||||
panel@0 {
|
||||
compatible = "rocktech,jh057n00900";
|
||||
reg = <0>;
|
||||
port@0 {
|
||||
panel_in: endpoint {
|
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remote-endpoint = <&mipi_dsi_out>;
|
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};
|
||||
};
|
||||
};
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
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mipi_dsi_in: endpoint {
|
||||
remote-endpoint = <&lcdif_mipi_dsi>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
mipi_dsi_out: endpoint {
|
||||
remote-endpoint = <&panel_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
|
@ -163,6 +163,8 @@ source "drivers/gpu/drm/bridge/analogix/Kconfig"
|
|||
|
||||
source "drivers/gpu/drm/bridge/adv7511/Kconfig"
|
||||
|
||||
source "drivers/gpu/drm/bridge/nwl-dsi/Kconfig"
|
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|
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source "drivers/gpu/drm/bridge/cadence/Kconfig"
|
||||
|
||||
source "drivers/gpu/drm/bridge/synopsys/Kconfig"
|
||||
|
|
|
@ -16,6 +16,7 @@ obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/
|
|||
obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/
|
||||
obj-$(CONFIG_DRM_TI_SN65DSI86) += ti-sn65dsi86.o
|
||||
obj-$(CONFIG_DRM_TI_TFP410) += ti-tfp410.o
|
||||
obj-$(CONFIG_DRM_NWL_MIPI_DSI) += nwl-dsi/
|
||||
obj-y += cadence/
|
||||
obj-y += synopsys/
|
||||
obj-$(CONFIG_DRM_ITE_IT6263) += it6263.o
|
||||
|
|
16
drivers/gpu/drm/bridge/nwl-dsi/Kconfig
Normal file
16
drivers/gpu/drm/bridge/nwl-dsi/Kconfig
Normal file
|
@ -0,0 +1,16 @@
|
|||
config DRM_NWL_MIPI_DSI
|
||||
tristate "Support for Northwest Logic MIPI DSI Host controller"
|
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depends on DRM
|
||||
depends on COMMON_CLK
|
||||
depends on OF && HAS_IOMEM
|
||||
select DRM_KMS_HELPER
|
||||
select DRM_MIPI_DSI
|
||||
select DRM_PANEL_BRIDGE
|
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select GENERIC_PHY_MIPI_DPHY
|
||||
select MFD_SYSCON
|
||||
select MULTIPLEXER
|
||||
select REGMAP_MMIO
|
||||
help
|
||||
This enables the Northwest Logic MIPI DSI Host controller as
|
||||
for example found on NXP's i.MX8 Processors.
|
||||
|
4
drivers/gpu/drm/bridge/nwl-dsi/Makefile
Normal file
4
drivers/gpu/drm/bridge/nwl-dsi/Makefile
Normal file
|
@ -0,0 +1,4 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
nwl-mipi-dsi-y := nwl-drv.o nwl-dsi.o
|
||||
obj-$(CONFIG_DRM_NWL_MIPI_DSI) += nwl-mipi-dsi.o
|
||||
header-test-y += nwl-drv.h nwl-dsi.h
|
1244
drivers/gpu/drm/bridge/nwl-dsi/nwl-drv.c
Normal file
1244
drivers/gpu/drm/bridge/nwl-dsi/nwl-drv.c
Normal file
File diff suppressed because it is too large
Load Diff
97
drivers/gpu/drm/bridge/nwl-dsi/nwl-drv.h
Normal file
97
drivers/gpu/drm/bridge/nwl-dsi/nwl-drv.h
Normal file
|
@ -0,0 +1,97 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* NWL MIPI DSI host driver
|
||||
*
|
||||
* Copyright (C) 2017 NXP
|
||||
* Copyright (C) 2019 Purism SPC
|
||||
*/
|
||||
|
||||
#ifndef __NWL_DRV_H__
|
||||
#define __NWL_DRV_H__
|
||||
|
||||
#include <linux/mux/consumer.h>
|
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#include <linux/phy/phy.h>
|
||||
|
||||
#include <drm/drm_bridge.h>
|
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#include <drm/drm_mipi_dsi.h>
|
||||
|
||||
struct nwl_dsi_platform_data;
|
||||
|
||||
/* i.MX8 NWL quirks */
|
||||
/* i.MX8MQ errata E11418 */
|
||||
#define E11418_HS_MODE_QUIRK BIT(0)
|
||||
/* Skip DSI bits in SRC on disable to avoid blank display on enable */
|
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#define SRC_RESET_QUIRK BIT(1)
|
||||
|
||||
/* * DPI color coding */
|
||||
#define NWL_DSI_DPI_16_BIT_565_PACKED 0
|
||||
#define NWL_DSI_DPI_16_BIT_565_ALIGNED 1
|
||||
#define NWL_DSI_DPI_16_BIT_565_SHIFTED 2
|
||||
#define NWL_DSI_DPI_18_BIT_PACKED 3
|
||||
#define NWL_DSI_DPI_18_BIT_ALIGNED 4
|
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#define NWL_DSI_DPI_24_BIT 5
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||||
|
||||
#define NWL_DSI_MAX_PLATFORM_CLOCKS 2
|
||||
struct nwl_dsi_plat_clk_config {
|
||||
const char *id;
|
||||
struct clk *clk;
|
||||
bool present;
|
||||
};
|
||||
|
||||
struct mode_config {
|
||||
int clock;
|
||||
int crtc_clock;
|
||||
unsigned int lanes;
|
||||
unsigned long bitclock;
|
||||
unsigned long phy_rates[3];
|
||||
unsigned long pll_rates[3];
|
||||
int phy_rate_idx;
|
||||
struct list_head list;
|
||||
};
|
||||
|
||||
struct nwl_dsi {
|
||||
struct drm_encoder encoder;
|
||||
struct drm_bridge bridge;
|
||||
struct mipi_dsi_host dsi_host;
|
||||
struct drm_bridge *panel_bridge;
|
||||
struct device *dev;
|
||||
struct phy *phy;
|
||||
union phy_configure_opts phy_cfg;
|
||||
unsigned int quirks;
|
||||
unsigned int instance;
|
||||
|
||||
struct regmap *regmap;
|
||||
struct regmap *csr;
|
||||
int irq;
|
||||
struct reset_control *rst_byte;
|
||||
struct reset_control *rst_esc;
|
||||
struct reset_control *rst_dpi;
|
||||
struct reset_control *rst_pclk;
|
||||
struct mux_control *mux;
|
||||
|
||||
/* DSI clocks */
|
||||
struct clk *phy_ref_clk;
|
||||
struct clk *rx_esc_clk;
|
||||
struct clk *tx_esc_clk;
|
||||
struct clk *pll_clk;
|
||||
struct clk *lcdif_clk;
|
||||
/* Platform dependent clocks */
|
||||
struct nwl_dsi_plat_clk_config clk_config[NWL_DSI_MAX_PLATFORM_CLOCKS];
|
||||
|
||||
struct list_head valid_modes;
|
||||
/* dsi lanes */
|
||||
u32 lanes;
|
||||
u32 clk_drop_lvl;
|
||||
enum mipi_dsi_pixel_format format;
|
||||
struct drm_display_mode mode;
|
||||
unsigned long dsi_mode_flags;
|
||||
|
||||
struct nwl_dsi_transfer *xfer;
|
||||
|
||||
const struct nwl_dsi_platform_data *pdata;
|
||||
|
||||
bool use_dcss;
|
||||
};
|
||||
|
||||
#endif /* __NWL_DRV_H__ */
|
684
drivers/gpu/drm/bridge/nwl-dsi/nwl-dsi.c
Normal file
684
drivers/gpu/drm/bridge/nwl-dsi/nwl-dsi.c
Normal file
|
@ -0,0 +1,684 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* NWL MIPI DSI host driver
|
||||
*
|
||||
* Copyright (C) 2017 NXP
|
||||
* Copyright (C) 2019 Purism SPC
|
||||
*/
|
||||
|
||||
#include <linux/bitfield.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/time64.h>
|
||||
|
||||
#include <video/mipi_display.h>
|
||||
#include <video/videomode.h>
|
||||
|
||||
#include <drm/drm_atomic_helper.h>
|
||||
#include <drm/drm_crtc_helper.h>
|
||||
#include <drm/drm_of.h>
|
||||
#include <drm/drm_panel.h>
|
||||
#include <drm/drm_print.h>
|
||||
|
||||
#include "nwl-drv.h"
|
||||
#include "nwl-dsi.h"
|
||||
|
||||
#define NWL_DSI_MIPI_FIFO_TIMEOUT msecs_to_jiffies(500)
|
||||
|
||||
/*
|
||||
* PKT_CONTROL format:
|
||||
* [15: 0] - word count
|
||||
* [17:16] - virtual channel
|
||||
* [23:18] - data type
|
||||
* [24] - LP or HS select (0 - LP, 1 - HS)
|
||||
* [25] - perform BTA after packet is sent
|
||||
* [26] - perform BTA only, no packet tx
|
||||
*/
|
||||
#define NWL_DSI_WC(x) FIELD_PREP(GENMASK(15, 0), (x))
|
||||
#define NWL_DSI_TX_VC(x) FIELD_PREP(GENMASK(17, 16), (x))
|
||||
#define NWL_DSI_TX_DT(x) FIELD_PREP(GENMASK(23, 18), (x))
|
||||
#define NWL_DSI_HS_SEL(x) FIELD_PREP(GENMASK(24, 24), (x))
|
||||
#define NWL_DSI_BTA_TX(x) FIELD_PREP(GENMASK(25, 25), (x))
|
||||
#define NWL_DSI_BTA_NO_TX(x) FIELD_PREP(GENMASK(26, 26), (x))
|
||||
|
||||
/*
|
||||
* RX_PKT_HEADER format:
|
||||
* [15: 0] - word count
|
||||
* [21:16] - data type
|
||||
* [23:22] - virtual channel
|
||||
*/
|
||||
#define NWL_DSI_RX_DT(x) FIELD_GET(GENMASK(21, 16), (x))
|
||||
#define NWL_DSI_RX_VC(x) FIELD_GET(GENMASK(23, 22), (x))
|
||||
|
||||
/* DSI Video mode */
|
||||
#define NWL_DSI_VM_BURST_MODE_WITH_SYNC_PULSES 0
|
||||
#define NWL_DSI_VM_NON_BURST_MODE_WITH_SYNC_EVENTS BIT(0)
|
||||
#define NWL_DSI_VM_BURST_MODE BIT(1)
|
||||
|
||||
/* * DPI color coding */
|
||||
#define NWL_DSI_DPI_16_BIT_565_PACKED 0
|
||||
#define NWL_DSI_DPI_16_BIT_565_ALIGNED 1
|
||||
#define NWL_DSI_DPI_16_BIT_565_SHIFTED 2
|
||||
#define NWL_DSI_DPI_18_BIT_PACKED 3
|
||||
#define NWL_DSI_DPI_18_BIT_ALIGNED 4
|
||||
#define NWL_DSI_DPI_24_BIT 5
|
||||
|
||||
/* * DPI Pixel format */
|
||||
#define NWL_DSI_PIXEL_FORMAT_16 0
|
||||
#define NWL_DSI_PIXEL_FORMAT_18 BIT(0)
|
||||
#define NWL_DSI_PIXEL_FORMAT_18L BIT(1)
|
||||
#define NWL_DSI_PIXEL_FORMAT_24 (BIT(0) | BIT(1))
|
||||
|
||||
enum transfer_direction {
|
||||
DSI_PACKET_SEND,
|
||||
DSI_PACKET_RECEIVE,
|
||||
};
|
||||
|
||||
struct nwl_dsi_transfer {
|
||||
const struct mipi_dsi_msg *msg;
|
||||
struct mipi_dsi_packet packet;
|
||||
struct completion completed;
|
||||
|
||||
int status; /* status of transmission */
|
||||
enum transfer_direction direction;
|
||||
bool need_bta;
|
||||
u8 cmd;
|
||||
u16 rx_word_count;
|
||||
size_t tx_len; /* in bytes */
|
||||
size_t rx_len; /* in bytes */
|
||||
};
|
||||
|
||||
static int nwl_dsi_write(struct nwl_dsi *dsi, unsigned int reg, u32 val)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = regmap_write(dsi->regmap, reg, val);
|
||||
if (ret < 0)
|
||||
DRM_DEV_ERROR(dsi->dev,
|
||||
"Failed to write NWL DSI reg 0x%x: %d\n", reg,
|
||||
ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static u32 nwl_dsi_read(struct nwl_dsi *dsi, u32 reg)
|
||||
{
|
||||
unsigned int val;
|
||||
int ret;
|
||||
|
||||
ret = regmap_read(dsi->regmap, reg, &val);
|
||||
if (ret < 0)
|
||||
DRM_DEV_ERROR(dsi->dev, "Failed to read NWL DSI reg 0x%x: %d\n",
|
||||
reg, ret);
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
static u32 nwl_dsi_get_dpi_pixel_format(enum mipi_dsi_pixel_format format)
|
||||
{
|
||||
switch (format) {
|
||||
case MIPI_DSI_FMT_RGB565:
|
||||
return NWL_DSI_PIXEL_FORMAT_16;
|
||||
case MIPI_DSI_FMT_RGB666:
|
||||
return NWL_DSI_PIXEL_FORMAT_18L;
|
||||
case MIPI_DSI_FMT_RGB666_PACKED:
|
||||
return NWL_DSI_PIXEL_FORMAT_18;
|
||||
case MIPI_DSI_FMT_RGB888:
|
||||
return NWL_DSI_PIXEL_FORMAT_24;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
#define PSEC_PER_SEC 1000000000000LL
|
||||
/*
|
||||
* ps2bc - Picoseconds to byte clock cycles
|
||||
*/
|
||||
static u32 ps2bc(struct nwl_dsi *dsi, unsigned long long ps)
|
||||
{
|
||||
int bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
|
||||
|
||||
return DIV_ROUND_UP(ps * dsi->mode.clock * 1000 * bpp,
|
||||
dsi->lanes * 8 * PSEC_PER_SEC);
|
||||
}
|
||||
|
||||
/*
|
||||
* ui2bc - UI time periods to byte clock cycles
|
||||
*/
|
||||
static u32 ui2bc(struct nwl_dsi *dsi, unsigned long long ui)
|
||||
{
|
||||
int bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
|
||||
|
||||
return DIV_ROUND_UP(ui * dsi->lanes, dsi->mode.clock * 1000 * bpp);
|
||||
}
|
||||
|
||||
/*
|
||||
* us2bc - micro seconds to lp clock cycles
|
||||
*/
|
||||
static u32 us2lp(u32 lp_clk_rate, unsigned long us)
|
||||
{
|
||||
return DIV_ROUND_UP(us * lp_clk_rate, USEC_PER_SEC);
|
||||
}
|
||||
|
||||
static int nwl_dsi_config_host(struct nwl_dsi *dsi)
|
||||
{
|
||||
u32 cycles;
|
||||
struct phy_configure_opts_mipi_dphy *cfg = &dsi->phy_cfg.mipi_dphy;
|
||||
|
||||
if (dsi->lanes < 1 || dsi->lanes > 4)
|
||||
return -EINVAL;
|
||||
|
||||
DRM_DEV_DEBUG_DRIVER(dsi->dev, "DSI Lanes %d\n", dsi->lanes);
|
||||
nwl_dsi_write(dsi, NWL_DSI_CFG_NUM_LANES, dsi->lanes - 1);
|
||||
|
||||
if (dsi->dsi_mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) {
|
||||
nwl_dsi_write(dsi, NWL_DSI_CFG_NONCONTINUOUS_CLK, 0x01);
|
||||
nwl_dsi_write(dsi, NWL_DSI_CFG_AUTOINSERT_EOTP, 0x01);
|
||||
} else {
|
||||
nwl_dsi_write(dsi, NWL_DSI_CFG_NONCONTINUOUS_CLK, 0x00);
|
||||
nwl_dsi_write(dsi, NWL_DSI_CFG_AUTOINSERT_EOTP, 0x00);
|
||||
}
|
||||
|
||||
/* values in byte clock cycles */
|
||||
cycles = ui2bc(dsi, cfg->clk_pre);
|
||||
DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_t_pre: 0x%x\n", cycles);
|
||||
nwl_dsi_write(dsi, NWL_DSI_CFG_T_PRE, cycles);
|
||||
cycles = ps2bc(dsi, cfg->lpx + cfg->clk_prepare + cfg->clk_zero);
|
||||
DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_tx_gap (pre): 0x%x\n", cycles);
|
||||
cycles += ui2bc(dsi, cfg->clk_pre);
|
||||
DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_tx_gap: 0x%x\n", cycles);
|
||||
nwl_dsi_write(dsi, NWL_DSI_CFG_T_POST, cycles);
|
||||
cycles = ps2bc(dsi, cfg->hs_exit);
|
||||
DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_tx_gap: 0x%x\n", cycles);
|
||||
nwl_dsi_write(dsi, NWL_DSI_CFG_TX_GAP, cycles);
|
||||
|
||||
nwl_dsi_write(dsi, NWL_DSI_CFG_EXTRA_CMDS_AFTER_EOTP, 0x01);
|
||||
nwl_dsi_write(dsi, NWL_DSI_CFG_HTX_TO_COUNT, 0x00);
|
||||
nwl_dsi_write(dsi, NWL_DSI_CFG_LRX_H_TO_COUNT, 0x00);
|
||||
nwl_dsi_write(dsi, NWL_DSI_CFG_BTA_H_TO_COUNT, 0x00);
|
||||
/* In LP clock cycles */
|
||||
cycles = us2lp(cfg->lp_clk_rate, cfg->wakeup);
|
||||
DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_twakeup: 0x%x\n", cycles);
|
||||
nwl_dsi_write(dsi, NWL_DSI_CFG_TWAKEUP, cycles);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int nwl_dsi_config_dpi(struct nwl_dsi *dsi)
|
||||
{
|
||||
u32 color_format, mode;
|
||||
bool burst_mode;
|
||||
int hfront_porch, hback_porch, vfront_porch, vback_porch;
|
||||
int hsync_len, vsync_len;
|
||||
|
||||
hfront_porch = dsi->mode.hsync_start - dsi->mode.hdisplay;
|
||||
hsync_len = dsi->mode.hsync_end - dsi->mode.hsync_start;
|
||||
hback_porch = dsi->mode.htotal - dsi->mode.hsync_end;
|
||||
|
||||
vfront_porch = dsi->mode.vsync_start - dsi->mode.vdisplay;
|
||||
vsync_len = dsi->mode.vsync_end - dsi->mode.vsync_start;
|
||||
vback_porch = dsi->mode.vtotal - dsi->mode.vsync_end;
|
||||
|
||||
DRM_DEV_DEBUG_DRIVER(dsi->dev, "hfront_porch = %d\n", hfront_porch);
|
||||
DRM_DEV_DEBUG_DRIVER(dsi->dev, "hback_porch = %d\n", hback_porch);
|
||||
DRM_DEV_DEBUG_DRIVER(dsi->dev, "hsync_len = %d\n", hsync_len);
|
||||
DRM_DEV_DEBUG_DRIVER(dsi->dev, "hdisplay = %d\n", dsi->mode.hdisplay);
|
||||
DRM_DEV_DEBUG_DRIVER(dsi->dev, "vfront_porch = %d\n", vfront_porch);
|
||||
DRM_DEV_DEBUG_DRIVER(dsi->dev, "vback_porch = %d\n", vback_porch);
|
||||
DRM_DEV_DEBUG_DRIVER(dsi->dev, "vsync_len = %d\n", vsync_len);
|
||||
DRM_DEV_DEBUG_DRIVER(dsi->dev, "vactive = %d\n", dsi->mode.vdisplay);
|
||||
DRM_DEV_DEBUG_DRIVER(dsi->dev, "clock = %d kHz\n", dsi->mode.clock);
|
||||
|
||||
color_format = nwl_dsi_get_dpi_pixel_format(dsi->format);
|
||||
if (color_format < 0) {
|
||||
DRM_DEV_ERROR(dsi->dev, "Invalid color format 0x%x\n",
|
||||
dsi->format);
|
||||
return color_format;
|
||||
}
|
||||
DRM_DEV_DEBUG_DRIVER(dsi->dev, "pixel fmt = %d\n", dsi->format);
|
||||
|
||||
nwl_dsi_write(dsi, NWL_DSI_INTERFACE_COLOR_CODING, NWL_DSI_DPI_24_BIT);
|
||||
nwl_dsi_write(dsi, NWL_DSI_PIXEL_FORMAT, color_format);
|
||||
/*
|
||||
* Adjusting input polarity based on the video mode results in
|
||||
* a black screen so always pick active low:
|
||||
*/
|
||||
nwl_dsi_write(dsi, NWL_DSI_VSYNC_POLARITY,
|
||||
NWL_DSI_VSYNC_POLARITY_ACTIVE_LOW);
|
||||
nwl_dsi_write(dsi, NWL_DSI_HSYNC_POLARITY,
|
||||
NWL_DSI_HSYNC_POLARITY_ACTIVE_LOW);
|
||||
|
||||
burst_mode = (dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_BURST) &&
|
||||
!(dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE);
|
||||
|
||||
if (burst_mode) {
|
||||
nwl_dsi_write(dsi, NWL_DSI_VIDEO_MODE, NWL_DSI_VM_BURST_MODE);
|
||||
nwl_dsi_write(dsi, NWL_DSI_PIXEL_FIFO_SEND_LEVEL, 256);
|
||||
} else {
|
||||
mode = ((dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) ?
|
||||
NWL_DSI_VM_BURST_MODE_WITH_SYNC_PULSES :
|
||||
NWL_DSI_VM_NON_BURST_MODE_WITH_SYNC_EVENTS);
|
||||
nwl_dsi_write(dsi, NWL_DSI_VIDEO_MODE, mode);
|
||||
nwl_dsi_write(dsi, NWL_DSI_PIXEL_FIFO_SEND_LEVEL,
|
||||
dsi->mode.hdisplay);
|
||||
}
|
||||
|
||||
nwl_dsi_write(dsi, NWL_DSI_HFP, hfront_porch);
|
||||
nwl_dsi_write(dsi, NWL_DSI_HBP, hback_porch);
|
||||
nwl_dsi_write(dsi, NWL_DSI_HSA, hsync_len);
|
||||
|
||||
nwl_dsi_write(dsi, NWL_DSI_ENABLE_MULT_PKTS, 0x0);
|
||||
nwl_dsi_write(dsi, NWL_DSI_BLLP_MODE, 0x1);
|
||||
nwl_dsi_write(dsi, NWL_DSI_ENABLE_MULT_PKTS, 0x0);
|
||||
nwl_dsi_write(dsi, NWL_DSI_USE_NULL_PKT_BLLP, 0x0);
|
||||
nwl_dsi_write(dsi, NWL_DSI_VC, 0x0);
|
||||
|
||||
nwl_dsi_write(dsi, NWL_DSI_PIXEL_PAYLOAD_SIZE, dsi->mode.hdisplay);
|
||||
nwl_dsi_write(dsi, NWL_DSI_VACTIVE, dsi->mode.vdisplay - 1);
|
||||
nwl_dsi_write(dsi, NWL_DSI_VBP, vback_porch);
|
||||
nwl_dsi_write(dsi, NWL_DSI_VFP, vfront_porch);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void nwl_dsi_init_interrupts(struct nwl_dsi *dsi)
|
||||
{
|
||||
u32 irq_enable;
|
||||
|
||||
nwl_dsi_write(dsi, NWL_DSI_IRQ_MASK, 0xffffffff);
|
||||
nwl_dsi_write(dsi, NWL_DSI_IRQ_MASK2, 0x7);
|
||||
|
||||
irq_enable = ~(u32)(NWL_DSI_TX_PKT_DONE_MASK |
|
||||
NWL_DSI_RX_PKT_HDR_RCVD_MASK |
|
||||
NWL_DSI_TX_FIFO_OVFLW_MASK |
|
||||
NWL_DSI_HS_TX_TIMEOUT_MASK);
|
||||
|
||||
nwl_dsi_write(dsi, NWL_DSI_IRQ_MASK, irq_enable);
|
||||
}
|
||||
|
||||
static int nwl_dsi_host_attach(struct mipi_dsi_host *dsi_host,
|
||||
struct mipi_dsi_device *device)
|
||||
{
|
||||
struct nwl_dsi *dsi = container_of(dsi_host, struct nwl_dsi, dsi_host);
|
||||
struct device *dev = dsi->dev;
|
||||
|
||||
DRM_DEV_INFO(dev, "lanes=%u, format=0x%x flags=0x%lx\n", device->lanes,
|
||||
device->format, device->mode_flags);
|
||||
|
||||
if (device->lanes < 1 || device->lanes > 4)
|
||||
return -EINVAL;
|
||||
|
||||
dsi->lanes = device->lanes;
|
||||
dsi->format = device->format;
|
||||
dsi->dsi_mode_flags = device->mode_flags;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int nwl_dsi_host_detach(struct mipi_dsi_host *dsi_host,
|
||||
struct mipi_dsi_device *device)
|
||||
{
|
||||
struct nwl_dsi *dsi = container_of(dsi_host, struct nwl_dsi, dsi_host);
|
||||
|
||||
dsi->lanes = 0;
|
||||
dsi->format = 0;
|
||||
dsi->dsi_mode_flags = 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static bool nwl_dsi_read_packet(struct nwl_dsi *dsi, u32 status)
|
||||
{
|
||||
struct device *dev = dsi->dev;
|
||||
struct nwl_dsi_transfer *xfer = dsi->xfer;
|
||||
u8 *payload = xfer->msg->rx_buf;
|
||||
u32 val;
|
||||
u16 word_count;
|
||||
u8 channel;
|
||||
u8 data_type;
|
||||
|
||||
xfer->status = 0;
|
||||
|
||||
if (xfer->rx_word_count == 0) {
|
||||
if (!(status & NWL_DSI_RX_PKT_HDR_RCVD))
|
||||
return false;
|
||||
/* Get the RX header and parse it */
|
||||
val = nwl_dsi_read(dsi, NWL_DSI_RX_PKT_HEADER);
|
||||
word_count = NWL_DSI_WC(val);
|
||||
channel = NWL_DSI_RX_VC(val);
|
||||
data_type = NWL_DSI_RX_DT(val);
|
||||
|
||||
if (channel != xfer->msg->channel) {
|
||||
DRM_DEV_ERROR(dev,
|
||||
"[%02X] Channel mismatch (%u != %u)\n",
|
||||
xfer->cmd, channel, xfer->msg->channel);
|
||||
return true;
|
||||
}
|
||||
|
||||
switch (data_type) {
|
||||
case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
|
||||
/* Fall through */
|
||||
case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
|
||||
if (xfer->msg->rx_len > 1) {
|
||||
/* read second byte */
|
||||
payload[1] = word_count >> 8;
|
||||
++xfer->rx_len;
|
||||
}
|
||||
/* Fall through */
|
||||
case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
|
||||
/* Fall through */
|
||||
case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
|
||||
if (xfer->msg->rx_len > 0) {
|
||||
/* read first byte */
|
||||
payload[0] = word_count & 0xff;
|
||||
++xfer->rx_len;
|
||||
}
|
||||
xfer->status = xfer->rx_len;
|
||||
return true;
|
||||
case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
|
||||
word_count &= 0xff;
|
||||
DRM_DEV_ERROR(dev, "[%02X] DSI error report: 0x%02x\n",
|
||||
xfer->cmd, word_count);
|
||||
xfer->status = -EPROTO;
|
||||
return true;
|
||||
}
|
||||
|
||||
if (word_count > xfer->msg->rx_len) {
|
||||
DRM_DEV_ERROR(
|
||||
dev,
|
||||
"[%02X] Receive buffer too small: %lu (< %u)\n",
|
||||
xfer->cmd, xfer->msg->rx_len, word_count);
|
||||
return true;
|
||||
}
|
||||
|
||||
xfer->rx_word_count = word_count;
|
||||
} else {
|
||||
/* Set word_count from previous header read */
|
||||
word_count = xfer->rx_word_count;
|
||||
}
|
||||
|
||||
/* If RX payload is not yet received, wait for it */
|
||||
if (!(status & NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD))
|
||||
return false;
|
||||
|
||||
/* Read the RX payload */
|
||||
while (word_count >= 4) {
|
||||
val = nwl_dsi_read(dsi, NWL_DSI_RX_PAYLOAD);
|
||||
payload[0] = (val >> 0) & 0xff;
|
||||
payload[1] = (val >> 8) & 0xff;
|
||||
payload[2] = (val >> 16) & 0xff;
|
||||
payload[3] = (val >> 24) & 0xff;
|
||||
payload += 4;
|
||||
xfer->rx_len += 4;
|
||||
word_count -= 4;
|
||||
}
|
||||
|
||||
if (word_count > 0) {
|
||||
val = nwl_dsi_read(dsi, NWL_DSI_RX_PAYLOAD);
|
||||
switch (word_count) {
|
||||
case 3:
|
||||
payload[2] = (val >> 16) & 0xff;
|
||||
++xfer->rx_len;
|
||||
/* Fall through */
|
||||
case 2:
|
||||
payload[1] = (val >> 8) & 0xff;
|
||||
++xfer->rx_len;
|
||||
/* Fall through */
|
||||
case 1:
|
||||
payload[0] = (val >> 0) & 0xff;
|
||||
++xfer->rx_len;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
xfer->status = xfer->rx_len;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static void nwl_dsi_finish_transmission(struct nwl_dsi *dsi, u32 status)
|
||||
{
|
||||
struct nwl_dsi_transfer *xfer = dsi->xfer;
|
||||
bool end_packet = false;
|
||||
|
||||
if (!xfer)
|
||||
return;
|
||||
|
||||
if (status & NWL_DSI_TX_FIFO_OVFLW) {
|
||||
DRM_DEV_ERROR_RATELIMITED(dsi->dev, "tx fifo overflow\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if (status & NWL_DSI_HS_TX_TIMEOUT) {
|
||||
DRM_DEV_ERROR_RATELIMITED(dsi->dev, "HS tx timeout\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if (xfer->direction == DSI_PACKET_SEND &&
|
||||
status & NWL_DSI_TX_PKT_DONE) {
|
||||
xfer->status = xfer->tx_len;
|
||||
end_packet = true;
|
||||
} else if (status & NWL_DSI_DPHY_DIRECTION &&
|
||||
((status & (NWL_DSI_RX_PKT_HDR_RCVD |
|
||||
NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD)))) {
|
||||
end_packet = nwl_dsi_read_packet(dsi, status);
|
||||
}
|
||||
|
||||
if (end_packet)
|
||||
complete(&xfer->completed);
|
||||
}
|
||||
|
||||
static void nwl_dsi_begin_transmission(struct nwl_dsi *dsi)
|
||||
{
|
||||
struct nwl_dsi_transfer *xfer = dsi->xfer;
|
||||
struct mipi_dsi_packet *pkt = &xfer->packet;
|
||||
const u8 *payload;
|
||||
size_t length;
|
||||
u16 word_count;
|
||||
u8 hs_mode;
|
||||
u32 val;
|
||||
u32 hs_workaround = 0;
|
||||
|
||||
/* Send the payload, if any */
|
||||
length = pkt->payload_length;
|
||||
payload = pkt->payload;
|
||||
|
||||
while (length >= 4) {
|
||||
val = *(u32 *)payload;
|
||||
hs_workaround |= !(val & 0xFFFF00);
|
||||
nwl_dsi_write(dsi, NWL_DSI_TX_PAYLOAD, val);
|
||||
payload += 4;
|
||||
length -= 4;
|
||||
}
|
||||
/* Send the rest of the payload */
|
||||
val = 0;
|
||||
switch (length) {
|
||||
case 3:
|
||||
val |= payload[2] << 16;
|
||||
/* Fall through */
|
||||
case 2:
|
||||
val |= payload[1] << 8;
|
||||
hs_workaround |= !(val & 0xFFFF00);
|
||||
/* Fall through */
|
||||
case 1:
|
||||
val |= payload[0];
|
||||
nwl_dsi_write(dsi, NWL_DSI_TX_PAYLOAD, val);
|
||||
break;
|
||||
}
|
||||
xfer->tx_len = pkt->payload_length;
|
||||
|
||||
/*
|
||||
* Send the header
|
||||
* header[0] = Virtual Channel + Data Type
|
||||
* header[1] = Word Count LSB (LP) or first param (SP)
|
||||
* header[2] = Word Count MSB (LP) or second param (SP)
|
||||
*/
|
||||
word_count = pkt->header[1] | (pkt->header[2] << 8);
|
||||
if (hs_workaround && (dsi->quirks & E11418_HS_MODE_QUIRK)) {
|
||||
DRM_DEV_DEBUG_DRIVER(dsi->dev,
|
||||
"Using hs mode workaround for cmd 0x%x\n",
|
||||
xfer->cmd);
|
||||
hs_mode = 1;
|
||||
} else {
|
||||
hs_mode = (xfer->msg->flags & MIPI_DSI_MSG_USE_LPM) ? 0 : 1;
|
||||
}
|
||||
val = NWL_DSI_WC(word_count) | NWL_DSI_TX_VC(xfer->msg->channel) |
|
||||
NWL_DSI_TX_DT(xfer->msg->type) | NWL_DSI_HS_SEL(hs_mode) |
|
||||
NWL_DSI_BTA_TX(xfer->need_bta);
|
||||
nwl_dsi_write(dsi, NWL_DSI_PKT_CONTROL, val);
|
||||
|
||||
/* Send packet command */
|
||||
nwl_dsi_write(dsi, NWL_DSI_SEND_PACKET, 0x1);
|
||||
}
|
||||
|
||||
static ssize_t nwl_dsi_host_transfer(struct mipi_dsi_host *dsi_host,
|
||||
const struct mipi_dsi_msg *msg)
|
||||
{
|
||||
struct nwl_dsi *dsi = container_of(dsi_host, struct nwl_dsi, dsi_host);
|
||||
struct nwl_dsi_transfer xfer;
|
||||
ssize_t ret = 0;
|
||||
|
||||
/* Create packet to be sent */
|
||||
dsi->xfer = &xfer;
|
||||
ret = mipi_dsi_create_packet(&xfer.packet, msg);
|
||||
if (ret < 0) {
|
||||
dsi->xfer = NULL;
|
||||
return ret;
|
||||
}
|
||||
|
||||
if ((msg->type & MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM ||
|
||||
msg->type & MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM ||
|
||||
msg->type & MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM ||
|
||||
msg->type & MIPI_DSI_DCS_READ) &&
|
||||
msg->rx_len > 0 && msg->rx_buf != NULL)
|
||||
xfer.direction = DSI_PACKET_RECEIVE;
|
||||
else
|
||||
xfer.direction = DSI_PACKET_SEND;
|
||||
|
||||
xfer.need_bta = (xfer.direction == DSI_PACKET_RECEIVE);
|
||||
xfer.need_bta |= (msg->flags & MIPI_DSI_MSG_REQ_ACK) ? 1 : 0;
|
||||
xfer.msg = msg;
|
||||
xfer.status = -ETIMEDOUT;
|
||||
xfer.rx_word_count = 0;
|
||||
xfer.rx_len = 0;
|
||||
xfer.cmd = 0x00;
|
||||
if (msg->tx_len > 0)
|
||||
xfer.cmd = ((u8 *)(msg->tx_buf))[0];
|
||||
init_completion(&xfer.completed);
|
||||
|
||||
ret = clk_prepare_enable(dsi->rx_esc_clk);
|
||||
if (ret < 0) {
|
||||
DRM_DEV_ERROR(dsi->dev, "Failed to enable rx_esc clk: %zd\n",
|
||||
ret);
|
||||
return ret;
|
||||
}
|
||||
DRM_DEV_DEBUG_DRIVER(dsi->dev, "Enabled rx_esc clk @%lu Hz\n",
|
||||
clk_get_rate(dsi->rx_esc_clk));
|
||||
|
||||
/* Initiate the DSI packet transmision */
|
||||
nwl_dsi_begin_transmission(dsi);
|
||||
|
||||
if (!wait_for_completion_timeout(&xfer.completed,
|
||||
NWL_DSI_MIPI_FIFO_TIMEOUT)) {
|
||||
DRM_DEV_ERROR(dsi_host->dev, "[%02X] DSI transfer timed out\n",
|
||||
xfer.cmd);
|
||||
ret = -ETIMEDOUT;
|
||||
} else {
|
||||
ret = xfer.status;
|
||||
}
|
||||
|
||||
clk_disable_unprepare(dsi->rx_esc_clk);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
const struct mipi_dsi_host_ops nwl_dsi_host_ops = {
|
||||
.attach = nwl_dsi_host_attach,
|
||||
.detach = nwl_dsi_host_detach,
|
||||
.transfer = nwl_dsi_host_transfer,
|
||||
};
|
||||
|
||||
irqreturn_t nwl_dsi_irq_handler(int irq, void *data)
|
||||
{
|
||||
u32 irq_status;
|
||||
struct nwl_dsi *dsi = data;
|
||||
|
||||
irq_status = nwl_dsi_read(dsi, NWL_DSI_IRQ_STATUS);
|
||||
|
||||
if (irq_status & NWL_DSI_TX_PKT_DONE ||
|
||||
irq_status & NWL_DSI_RX_PKT_HDR_RCVD ||
|
||||
irq_status & NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD)
|
||||
nwl_dsi_finish_transmission(dsi, irq_status);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
int nwl_dsi_enable(struct nwl_dsi *dsi)
|
||||
{
|
||||
struct device *dev = dsi->dev;
|
||||
union phy_configure_opts *phy_cfg = &dsi->phy_cfg;
|
||||
int ret;
|
||||
|
||||
if (!dsi->lanes) {
|
||||
DRM_DEV_ERROR(dev, "Need DSI lanes: %d\n", dsi->lanes);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = phy_init(dsi->phy);
|
||||
if (ret < 0) {
|
||||
DRM_DEV_ERROR(dev, "Failed to init DSI phy: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = phy_configure(dsi->phy, phy_cfg);
|
||||
if (ret < 0) {
|
||||
DRM_DEV_ERROR(dev, "Failed to configure DSI phy: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(dsi->tx_esc_clk);
|
||||
if (ret < 0) {
|
||||
DRM_DEV_ERROR(dsi->dev, "Failed to enable tx_esc clk: %d\n",
|
||||
ret);
|
||||
return ret;
|
||||
}
|
||||
DRM_DEV_DEBUG_DRIVER(dsi->dev, "Enabled tx_esc clk @%lu Hz\n",
|
||||
clk_get_rate(dsi->tx_esc_clk));
|
||||
|
||||
ret = nwl_dsi_config_host(dsi);
|
||||
if (ret < 0) {
|
||||
DRM_DEV_ERROR(dev, "Failed to set up DSI: %d", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = nwl_dsi_config_dpi(dsi);
|
||||
if (ret < 0) {
|
||||
DRM_DEV_ERROR(dev, "Failed to set up DPI: %d", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = phy_power_on(dsi->phy);
|
||||
if (ret < 0) {
|
||||
DRM_DEV_ERROR(dev, "Failed to power on DPHY (%d)\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
nwl_dsi_init_interrupts(dsi);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int nwl_dsi_disable(struct nwl_dsi *dsi)
|
||||
{
|
||||
struct device *dev = dsi->dev;
|
||||
|
||||
DRM_DEV_DEBUG_DRIVER(dev, "Disabling clocks and phy\n");
|
||||
|
||||
phy_power_off(dsi->phy);
|
||||
phy_exit(dsi->phy);
|
||||
|
||||
/* Disabling the clock before the phy breaks enabling dsi again */
|
||||
clk_disable_unprepare(dsi->tx_esc_clk);
|
||||
|
||||
return 0;
|
||||
}
|
112
drivers/gpu/drm/bridge/nwl-dsi/nwl-dsi.h
Normal file
112
drivers/gpu/drm/bridge/nwl-dsi/nwl-dsi.h
Normal file
|
@ -0,0 +1,112 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* NWL MIPI DSI host driver
|
||||
*
|
||||
* Copyright (C) 2017 NXP
|
||||
* Copyright (C) 2019 Purism SPC
|
||||
*/
|
||||
#ifndef __NWL_DSI_H__
|
||||
#define __NWL_DSI_H__
|
||||
|
||||
#include <linux/irqreturn.h>
|
||||
|
||||
#include <drm/drm_mipi_dsi.h>
|
||||
|
||||
#include "nwl-drv.h"
|
||||
|
||||
/* DSI HOST registers */
|
||||
#define NWL_DSI_CFG_NUM_LANES 0x0
|
||||
#define NWL_DSI_CFG_NONCONTINUOUS_CLK 0x4
|
||||
#define NWL_DSI_CFG_T_PRE 0x8
|
||||
#define NWL_DSI_CFG_T_POST 0xc
|
||||
#define NWL_DSI_CFG_TX_GAP 0x10
|
||||
#define NWL_DSI_CFG_AUTOINSERT_EOTP 0x14
|
||||
#define NWL_DSI_CFG_EXTRA_CMDS_AFTER_EOTP 0x18
|
||||
#define NWL_DSI_CFG_HTX_TO_COUNT 0x1c
|
||||
#define NWL_DSI_CFG_LRX_H_TO_COUNT 0x20
|
||||
#define NWL_DSI_CFG_BTA_H_TO_COUNT 0x24
|
||||
#define NWL_DSI_CFG_TWAKEUP 0x28
|
||||
#define NWL_DSI_CFG_STATUS_OUT 0x2c
|
||||
#define NWL_DSI_RX_ERROR_STATUS 0x30
|
||||
|
||||
/* DSI DPI registers */
|
||||
#define NWL_DSI_PIXEL_PAYLOAD_SIZE 0x200
|
||||
#define NWL_DSI_PIXEL_FIFO_SEND_LEVEL 0x204
|
||||
#define NWL_DSI_INTERFACE_COLOR_CODING 0x208
|
||||
#define NWL_DSI_PIXEL_FORMAT 0x20c
|
||||
#define NWL_DSI_VSYNC_POLARITY 0x210
|
||||
#define NWL_DSI_VSYNC_POLARITY_ACTIVE_LOW 0
|
||||
#define NWL_DSI_VSYNC_POLARITY_ACTIVE_HIGH BIT(1)
|
||||
|
||||
#define NWL_DSI_HSYNC_POLARITY 0x214
|
||||
#define NWL_DSI_HSYNC_POLARITY_ACTIVE_LOW 0
|
||||
#define NWL_DSI_HSYNC_POLARITY_ACTIVE_HIGH BIT(1)
|
||||
|
||||
#define NWL_DSI_VIDEO_MODE 0x218
|
||||
#define NWL_DSI_HFP 0x21c
|
||||
#define NWL_DSI_HBP 0x220
|
||||
#define NWL_DSI_HSA 0x224
|
||||
#define NWL_DSI_ENABLE_MULT_PKTS 0x228
|
||||
#define NWL_DSI_VBP 0x22c
|
||||
#define NWL_DSI_VFP 0x230
|
||||
#define NWL_DSI_BLLP_MODE 0x234
|
||||
#define NWL_DSI_USE_NULL_PKT_BLLP 0x238
|
||||
#define NWL_DSI_VACTIVE 0x23c
|
||||
#define NWL_DSI_VC 0x240
|
||||
|
||||
/* DSI APB PKT control */
|
||||
#define NWL_DSI_TX_PAYLOAD 0x280
|
||||
#define NWL_DSI_PKT_CONTROL 0x284
|
||||
#define NWL_DSI_SEND_PACKET 0x288
|
||||
#define NWL_DSI_PKT_STATUS 0x28c
|
||||
#define NWL_DSI_PKT_FIFO_WR_LEVEL 0x290
|
||||
#define NWL_DSI_PKT_FIFO_RD_LEVEL 0x294
|
||||
#define NWL_DSI_RX_PAYLOAD 0x298
|
||||
#define NWL_DSI_RX_PKT_HEADER 0x29c
|
||||
|
||||
/* DSI IRQ handling */
|
||||
#define NWL_DSI_IRQ_STATUS 0x2a0
|
||||
#define NWL_DSI_SM_NOT_IDLE BIT(0)
|
||||
#define NWL_DSI_TX_PKT_DONE BIT(1)
|
||||
#define NWL_DSI_DPHY_DIRECTION BIT(2)
|
||||
#define NWL_DSI_TX_FIFO_OVFLW BIT(3)
|
||||
#define NWL_DSI_TX_FIFO_UDFLW BIT(4)
|
||||
#define NWL_DSI_RX_FIFO_OVFLW BIT(5)
|
||||
#define NWL_DSI_RX_FIFO_UDFLW BIT(6)
|
||||
#define NWL_DSI_RX_PKT_HDR_RCVD BIT(7)
|
||||
#define NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD BIT(8)
|
||||
#define NWL_DSI_BTA_TIMEOUT BIT(29)
|
||||
#define NWL_DSI_LP_RX_TIMEOUT BIT(30)
|
||||
#define NWL_DSI_HS_TX_TIMEOUT BIT(31)
|
||||
|
||||
#define NWL_DSI_IRQ_STATUS2 0x2a4
|
||||
#define NWL_DSI_SINGLE_BIT_ECC_ERR BIT(0)
|
||||
#define NWL_DSI_MULTI_BIT_ECC_ERR BIT(1)
|
||||
#define NWL_DSI_CRC_ERR BIT(2)
|
||||
|
||||
#define NWL_DSI_IRQ_MASK 0x2a8
|
||||
#define NWL_DSI_SM_NOT_IDLE_MASK BIT(0)
|
||||
#define NWL_DSI_TX_PKT_DONE_MASK BIT(1)
|
||||
#define NWL_DSI_DPHY_DIRECTION_MASK BIT(2)
|
||||
#define NWL_DSI_TX_FIFO_OVFLW_MASK BIT(3)
|
||||
#define NWL_DSI_TX_FIFO_UDFLW_MASK BIT(4)
|
||||
#define NWL_DSI_RX_FIFO_OVFLW_MASK BIT(5)
|
||||
#define NWL_DSI_RX_FIFO_UDFLW_MASK BIT(6)
|
||||
#define NWL_DSI_RX_PKT_HDR_RCVD_MASK BIT(7)
|
||||
#define NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD_MASK BIT(8)
|
||||
#define NWL_DSI_BTA_TIMEOUT_MASK BIT(29)
|
||||
#define NWL_DSI_LP_RX_TIMEOUT_MASK BIT(30)
|
||||
#define NWL_DSI_HS_TX_TIMEOUT_MASK BIT(31)
|
||||
|
||||
#define NWL_DSI_IRQ_MASK2 0x2ac
|
||||
#define NWL_DSI_SINGLE_BIT_ECC_ERR_MASK BIT(0)
|
||||
#define NWL_DSI_MULTI_BIT_ECC_ERR_MASK BIT(1)
|
||||
#define NWL_DSI_CRC_ERR_MASK BIT(2)
|
||||
|
||||
extern const struct mipi_dsi_host_ops nwl_dsi_host_ops;
|
||||
|
||||
irqreturn_t nwl_dsi_irq_handler(int irq, void *data);
|
||||
int nwl_dsi_enable(struct nwl_dsi *dsi);
|
||||
int nwl_dsi_disable(struct nwl_dsi *dsi);
|
||||
|
||||
#endif /* __NWL_DSI_H__ */
|
|
@ -57,6 +57,8 @@
|
|||
|
||||
enum mixel_dphy_devtype {
|
||||
MIXEL_IMX8MQ,
|
||||
MIXEL_IMX8QM,
|
||||
MIXEL_IMX8QX,
|
||||
};
|
||||
|
||||
struct mixel_dphy_devdata {
|
||||
|
@ -75,6 +77,20 @@ static const struct mixel_dphy_devdata mixel_dphy_devdata[] = {
|
|||
.reg_rxcdrp = 0x44,
|
||||
.reg_rxhs_settle = 0x48,
|
||||
},
|
||||
[MIXEL_IMX8QM] = {
|
||||
.reg_tx_rcal = 0x00,
|
||||
.reg_auto_pd_en = 0x38,
|
||||
.reg_rxlprp = 0x3c,
|
||||
.reg_rxcdrp = 0x40,
|
||||
.reg_rxhs_settle = 0x44,
|
||||
},
|
||||
[MIXEL_IMX8QX] = {
|
||||
.reg_tx_rcal = 0x00,
|
||||
.reg_auto_pd_en = 0x38,
|
||||
.reg_rxlprp = 0x3c,
|
||||
.reg_rxcdrp = 0x40,
|
||||
.reg_rxhs_settle = 0x44,
|
||||
},
|
||||
};
|
||||
|
||||
struct mixel_dphy_cfg {
|
||||
|
@ -424,6 +440,10 @@ static const struct phy_ops mixel_dphy_phy_ops = {
|
|||
static const struct of_device_id mixel_dphy_of_match[] = {
|
||||
{ .compatible = "fsl,imx8mq-mipi-dphy",
|
||||
.data = &mixel_dphy_devdata[MIXEL_IMX8MQ] },
|
||||
{ .compatible = "fsl,imx8qm-mipi-dphy",
|
||||
.data = &mixel_dphy_devdata[MIXEL_IMX8QM] },
|
||||
{ .compatible = "fsl,imx8qx-mipi-dphy",
|
||||
.data = &mixel_dphy_devdata[MIXEL_IMX8QX] },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, mixel_dphy_of_match);
|
||||
|
|
Loading…
Reference in New Issue
Block a user