MLK-24278: arm64: dts: add i.MX8DXL inmate/root dts
Add i.MX8DXL inmate/root dts. Needs to use non-m4 flash.bin and use the following command to boot the 2nd Linux: ./jailhouse cell linux imx8dxl-linux-demo.cell Image -d imx8dxl-evk-inmate.dtb -c "clk_ignore_unused console=ttyLP4,115200 earlycon=lpuart32,mmio32,0x5a060010,115200 cma=32MB root=/dev/mmcblk0p2 rootwait rw" Signed-off-by: Alice Guo <alice.guo@nxp.com>
This commit is contained in:
Alice Guo
parent
251d8ae450
commit
2e6d2985aa
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@ -142,6 +142,6 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek-dom0.dtb imx8qxp-mek-root.dtb \
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dtb-$(CONFIG_ARCH_MXC) += imx8dxl-evk.dtb imx8dxl-evk-rpmsg.dtb \
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imx8dxl-evk-enet0.dtb imx8dxl-evk-enet0-tja1100.dtb imx8dxl-evk-pcie.dtb \
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imx8dxl-evk-lpspi-slave.dtb \
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imx8dxl-ddr3-val.dtb
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imx8dxl-ddr3-val.dtb imx8dxl-evk-root.dtb imx8dxl-evk-inmate.dtb
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dtb-$(CONFIG_ARCH_S32) += s32v234-evb.dtb \
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s32v234-sbc.dtb
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@ -0,0 +1,255 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2020 NXP
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*/
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/dts-v1/;
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#include <dt-bindings/clock/imx8-clock.h>
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#include <dt-bindings/firmware/imx/rsrc.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/pinctrl/pads-imx8dxl.h>
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#include <dt-bindings/thermal/thermal.h>
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/ {
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model = "Freescale i.MX8DXL EVK";
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compatible = "fsl,imx8dxl-mek", "fsl,imx8dxl";
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interrupt-parent = <&gic>;
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#address-cells = <0x2>;
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#size-cells = <0x2>;
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aliases {
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mmc0 = &usdhc1;
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serial4 = &cm40_lpuart;
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};
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cpus {
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#address-cells = <0x2>;
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#size-cells = <0x0>;
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,armv8";
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enable-method = "psci";
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reg = <0x0 0x1>;
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clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
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};
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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scu {
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compatible = "fsl,imx-scu";
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mbox-names = "tx0", "tx1", "tx2", "tx3",
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"rx0", "rx1", "rx2", "rx3",
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"gip3";
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mboxes = <&lsio_mu2 0 0
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&lsio_mu2 0 1
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&lsio_mu2 0 2
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&lsio_mu2 0 3
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&lsio_mu2 1 0
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&lsio_mu2 1 1
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&lsio_mu2 1 2
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&lsio_mu2 1 3
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&lsio_mu2 3 3>;
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pd: imx8dxl-pd {
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compatible = "fsl,imx8dxl-scu-pd", "fsl,scu-pd";
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#power-domain-cells = <1>;
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};
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clk: clock-controller {
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compatible = "fsl,imx8dxl-clk", "fsl,scu-clk";
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#clock-cells = <2>;
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clocks = <&xtal32k &xtal24m>;
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clock-names = "xtal_32KHz", "xtal_24Mhz";
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};
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iomuxc: pinctrl {
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compatible = "fsl,imx8dxl-iomuxc";
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};
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};
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soc {
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compatible = "fsl,imx8qxp-soc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
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clock-frequency = <8333333>;
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};
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gic: interrupt-controller@51a00000 {
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compatible = "arm,gic-v3";
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reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
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<0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
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#interrupt-cells = <3>;
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interrupt-controller;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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clk_dummy: clock-dummy {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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clock-output-names = "clk_dummy";
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};
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xtal32k: clock-xtal32k {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "xtal_32KHz";
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};
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xtal24m: clock-xtal24m {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "xtal_24MHz";
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};
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pci@bf700000 {
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compatible = "pci-host-ecam-generic";
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device_type = "pci";
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bus-range = <0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &gic GIC_SPI 200 IRQ_TYPE_EDGE_RISING>,
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<0 0 0 2 &gic GIC_SPI 201 IRQ_TYPE_EDGE_RISING>,
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<0 0 0 3 &gic GIC_SPI 202 IRQ_TYPE_EDGE_RISING>,
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<0 0 0 4 &gic GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
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reg = <0x0 0xbf700000 0x0 0x00100000>;
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ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>;
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};
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/* For early console */
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serial@5a060000 {
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compatible = "fsl,imx8dxl-lpuart", "fsl,imx7ulp-lpuart";
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reg = <0x0 0x5a060000 0x0 0x1000>;
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};
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#include "imx8-ss-lsio.dtsi"
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#include "imx8-ss-adma.dtsi"
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#include "imx8-ss-conn.dtsi"
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#include "imx8-ss-cm40.dtsi"
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};
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#include "imx8dxl-ss-lsio.dtsi"
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#include "imx8dxl-ss-adma.dtsi"
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#include "imx8dxl-ss-conn.dtsi"
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&edma0 {
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status = "disabled";
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};
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&acm {
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status = "disabled";
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};
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&iomuxc {
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pinctrl_cm40_lpuart: cm40_lpuartgrp {
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fsl,pins = <
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IMX8DXL_ADC_IN2_M40_UART0_RX 0x06000020
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IMX8DXL_ADC_IN3_M40_UART0_TX 0x06000020
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
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IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
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IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
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IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
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IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
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IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
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IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
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IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
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IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
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IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
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IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
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>;
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};
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};
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&usdhc1 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc1>;
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bus-width = <8>;
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non-removable;
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status = "okay";
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};
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&lsio_mu1 {
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status = "disabled";
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};
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&lsio_mu2 {
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status = "okay";
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};
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&lsio_gpio0 {
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status = "disabled";
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};
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&lsio_gpio1 {
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status = "disabled";
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};
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&lsio_gpio2 {
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status = "disabled";
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};
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&lsio_gpio3 {
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status = "disabled";
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};
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&lsio_gpio4 {
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status = "disabled";
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};
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&lsio_gpio5 {
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status = "disabled";
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};
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&lsio_gpio6 {
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status = "disabled";
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};
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&lsio_gpio7 {
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status = "disabled";
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};
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&cm40_intmux {
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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};
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&cm40_intmux {
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status = "okay";
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};
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&cm40_lpuart {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_cm40_lpuart>;
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status = "okay";
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};
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/delete-node/ &lpuart0;
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@ -0,0 +1,100 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright NXP 2020
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*/
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#include "imx8dxl-evk.dts"
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/ {
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domu {
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/*
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* There are 5 MUs, 0A is used by root cell, 1A is used
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* by ATF, so for non-root cell, 2A/3A/4A could be used.
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* SC_R_MU_0A
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* SC_R_MU_1A
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* SC_R_MU_2A
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* SC_R_MU_3A
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* SC_R_MU_4A
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* The rsrcs and pads will be configured by uboot scu_rm cmd
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*/
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#address-cells = <1>;
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#size-cells = <0>;
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doma {
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/*
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* This is not for domu, this is just reuse
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* the method for jailhouse inmate non root cell
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* Linux.
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*/
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compatible = "xen,domu";
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/*
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* The reg property will be updated by U-Boot to
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* reflect the partition id.
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*/
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reg = <0>;
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init_on_rsrcs = <
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IMX_SC_R_MU_2A
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>;
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rsrcs = <
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IMX_SC_R_SDHC_0
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IMX_SC_R_M4_0_INTMUX
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IMX_SC_R_M4_0_UART
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IMX_SC_R_MU_2A
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>;
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pads = <
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/* emmc */
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IMX8DXL_EMMC0_CLK
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IMX8DXL_EMMC0_CMD
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IMX8DXL_EMMC0_DATA0
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IMX8DXL_EMMC0_DATA1
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IMX8DXL_EMMC0_DATA2
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IMX8DXL_EMMC0_DATA3
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IMX8DXL_EMMC0_DATA4
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IMX8DXL_EMMC0_DATA5
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IMX8DXL_EMMC0_DATA6
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IMX8DXL_EMMC0_DATA7
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IMX8DXL_EMMC0_STROBE
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/* cm40_lpuart */
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IMX8DXL_ADC_IN3
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IMX8DXL_ADC_IN2
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>;
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};
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};
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};
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&{/reserved-memory} {
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jh_reserved: jh@bfc00000 {
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no-map;
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reg = <0x0 0xbfc00000 0x0 0x400000>;
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};
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loader_reserved: loader@bfb00000 {
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no-map;
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reg = <0x0 0xbfb00000 0x0 0x00100000>;
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};
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ivshmem_reserved: ivshmem@bf900000 {
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no-map;
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reg = <0x0 0xbf900000 0x0 0x00200000>;
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};
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pci_reserved: pci@bf700000 {
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no-map;
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reg = <0x0 0xbf700000 0x0 0x00200000>;
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};
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/* Decrease if no need such big memory */
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inmate_reserved: inmate@a1700000 {
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no-map;
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reg = <0x0 0xa1700000 0x0 0x1e000000>;
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};
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};
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&usdhc1 {
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status = "disabled";
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};
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&cm40_lpuart {
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/* Let inmate linux use this for console */
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status = "disabled";
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};
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