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arm: dts: imx7d: add epdc property 

on imx7d-sdb board, epdc has pin conflict with fec2, sim, etc.
so add a separate dts file for it.

Signed-off-by: Robby Cai <robby.cai@nxp.com>
This commit is contained in:
Robby Cai 2019-08-21 08:54:43 -04:00 committed by Dong Aisheng
parent 1482c8df9a
commit 290e14eb71
4 changed files with 101 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
arch/arm/boot/dts/imx7d-sdb-epdc.dts Normal file
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@ -0,0 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
* Copyright 2019 NXP
*/
#include "imx7d-sdb.dts"
#include "imx7d-sdb-epdc.dtsi"

41
arch/arm/boot/dts/imx7d-sdb-epdc.dtsi Normal file
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@ -0,0 +1,41 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
* Copyright 2019 NXP
*/
&epdc {
status = "okay";
};
&fec1 {
status = "okay";
};
&fec2 {
status = "disabled";
};
&reg_can2_3v3 {
status = "disabled";
};
&reg_fec2_3v3 {
status = "disabled";
};
&flexcan2 {
status = "disabled";
};
&max17135 {
status = "okay";
};
&sim1 {
status = "disabled";
};
&uart5 {
status = "disabled";
};

43
arch/arm/boot/dts/imx7d-sdb.dts
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@ -205,6 +205,16 @@
};
};
&epdc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_epdc0 &pinctrl_enet2_reg>;
V3P3-supply = <&V3P3_reg>;
VCOM-supply = <&VCOM_reg>;
DISPLAY-supply = <&DISPLAY_reg>;
en-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
&epxp {
status = "okay";
};
@ -671,7 +681,38 @@
pinctrl_enet2_reg: enet2reggrp {
fsl,pins = <
MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x14
MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x80000000
>;
};
pinctrl_epdc0: epdcgrp0 {
fsl,pins = <
MX7D_PAD_EPDC_DATA00__EPDC_DATA0 0x2
MX7D_PAD_EPDC_DATA01__EPDC_DATA1 0x2
MX7D_PAD_EPDC_DATA02__EPDC_DATA2 0x2
MX7D_PAD_EPDC_DATA03__EPDC_DATA3 0x2
MX7D_PAD_EPDC_DATA04__EPDC_DATA4 0x2
MX7D_PAD_EPDC_DATA05__EPDC_DATA5 0x2
MX7D_PAD_EPDC_DATA06__EPDC_DATA6 0x2
MX7D_PAD_EPDC_DATA07__EPDC_DATA7 0x2
MX7D_PAD_EPDC_DATA08__EPDC_DATA8 0x2
MX7D_PAD_EPDC_DATA09__EPDC_DATA9 0x2
MX7D_PAD_EPDC_DATA10__EPDC_DATA10 0x2
MX7D_PAD_EPDC_DATA11__EPDC_DATA11 0x2
MX7D_PAD_EPDC_DATA12__EPDC_DATA12 0x2
MX7D_PAD_EPDC_DATA13__EPDC_DATA13 0x2
MX7D_PAD_EPDC_DATA14__EPDC_DATA14 0x2
MX7D_PAD_EPDC_DATA15__EPDC_DATA15 0x2
MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK 0x2
MX7D_PAD_EPDC_SDLE__EPDC_SDLE 0x2
MX7D_PAD_EPDC_SDOE__EPDC_SDOE 0x2
MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR 0x2
MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 0x2
MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 0x2
MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK 0x2
MX7D_PAD_EPDC_GDOE__EPDC_GDOE 0x2
MX7D_PAD_EPDC_GDRL__EPDC_GDRL 0x2
MX7D_PAD_EPDC_GDSP__EPDC_GDSP 0x2
>;
};

11
arch/arm/boot/dts/imx7d.dtsi
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@ -173,6 +173,17 @@
status = "disabled";
};
epdc: epdc@306f0000 {
compatible = "fsl,imx7d-epdc";
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x306f0000 0x10000>;
clocks = <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_EPDC_PIXEL_ROOT_CLK>;
clock-names = "epdc_axi", "epdc_pix";
epdc-ram = <&gpr 0x4 30>;
qos = <&qosc>;
status = "disabled";
};
epxp: epxp@30700000 {
compatible = "fsl,imx7d-pxp-dma";
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,