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drm/amd/display: Add CM_BYPASS via debug option

Browse Source 
[Why]
bypass CM block and MPC ogam for debug or triage use.

[How]
create a new flag cm_bypass_mode, which will set both CM_CONTROL
and MPCC_OGAM_MODE to bypass when set to 1.

Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Qingqing Zhuo 2019-06-27 19:17:23 -04:00 committed by Alex Deucher
parent a208009869
commit 290129c256
5 changed files with 22 additions and 1 deletions
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3
drivers/gpu/drm/amd/display/dc/dc.h
View File

@ -379,6 +379,9 @@ struct dc_debug_options {
*/
unsigned int force_min_dcfclk_mhz;
bool disable_timing_sync;
#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
bool cm_in_bypass;
#endif
};
struct dc_debug_data {

7
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c
View File

@ -52,7 +52,12 @@ static void dpp2_enable_cm_block(
{
struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
REG_UPDATE(CM_CONTROL, CM_BYPASS, 0);
unsigned int cm_bypass_mode = 0;
//Temp, put CM in bypass mode
if (dpp_base->ctx->dc->debug.cm_in_bypass)
cm_bypass_mode = 1;
REG_UPDATE(CM_CONTROL, CM_BYPASS, cm_bypass_mode);
}

11
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
View File

@ -368,6 +368,11 @@ void apply_DEDCN20_305_wa(
{
struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
if (mpc->ctx->dc->debug.cm_in_bypass) {
REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE, 0);
return;
}
if (mpc->ctx->dc->work_arounds.dedcn20_305_wa == false) {
/*hw fixed in new review*/
return;
@ -390,10 +395,16 @@ void mpc2_set_output_gamma(
enum dc_lut_mode next_mode;
struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
if (mpc->ctx->dc->debug.cm_in_bypass) {
REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE, 0);
return;
}
if (params == NULL) {
REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE, 0);
return;
}
current_mode = mpc20_get_ogam_current(mpc, mpcc_id);
if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)
next_mode = LUT_RAM_B;

1
drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
View File

@ -42,6 +42,7 @@ struct dpp {
#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
struct pwl_params shaper_params;
bool cm_bypass_mode;
#endif
};

1
drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
View File

@ -128,6 +128,7 @@ struct mpc {
struct mpcc mpcc_array[MAX_MPCC];
#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
struct pwl_params blender_params;
bool cm_bypass_mode;
#endif
};